[Mesa-dev] [PATCH] glsl: fix Bug 85252 - Segfault in compiler while processing ternary operator with void arguments
This is done by returning an rvalue of type void in the
ast_function_expression::hir function instead of a void expression.
This produces (in the case of the ternary) an hir with a call
to the void returning function and an assignement of a void variable
which will be optimized out (the assignement) during the optimization
pass.
This fix results in having a valid subexpression in the many
different cases where the subexpressions are functions whose
return values are void.
Thus preventing to dereference NULL in the following cases:
* binary operator
* unary operators
* ternary operator
* comparison operators (except equal and nequal operator)
Equal and nequal had to be handled as a special case because
instead of segfaulting on a forbidden syntax it was now accepting
expressions with a void return value on either (or both) side of
the expression.
Piglist tests are on the way
Signed-off-by: Renaud Gaubert ren...@lse.epita.fr
Reviewed-by: Gabriel Laskar gabr...@lse.epita.fr
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85252
---
src/glsl/ast_function.cpp | 6 +-
src/glsl/ast_to_hir.cpp | 10 +-
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/glsl/ast_function.cpp b/src/glsl/ast_function.cpp
index 92e26bf..776a754 100644
--- a/src/glsl/ast_function.cpp
+++ b/src/glsl/ast_function.cpp
@@ -1785,7 +1785,11 @@ ast_function_expression::hir(exec_list *instructions,
/* an error has already been emitted */
value = ir_rvalue::error_value(ctx);
} else {
-value = generate_call(instructions, sig, actual_parameters, state);
+value = generate_call(instructions, sig, actual_parameters, state);
+if (!value) {
+ ir_variable *const tmp = new(ctx) ir_variable(glsl_type::void_type,
void_var, ir_var_temporary);
+ value = new(ctx) ir_dereference_variable(tmp);
+}
}
return value;
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 8cb46be..00cc16c 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -1270,7 +1270,15 @@ ast_expression::do_hir(exec_list *instructions,
*applied to one operand that can make them match, in which
*case this conversion is done.
*/
- if ((!apply_implicit_conversion(op[0]-type, op[1], state)
+
+ if (op[0]-type == glsl_type::void_type || op[1]-type ==
glsl_type::void_type) {
+
+_mesa_glsl_error( loc, state, `%s': wrong operand types: no
operation
+ `%1$s' exists that takes a left-hand operand of type 'void' or a
+ right operand of type 'void', (this-oper == ast_equal) ? == :
!=);
+
+ error_emitted = true;
+ } else if ((!apply_implicit_conversion(op[0]-type, op[1], state)
!apply_implicit_conversion(op[1]-type, op[0], state))
|| (op[0]-type != op[1]-type)) {
_mesa_glsl_error( loc, state, operands of `%s' must have the same
--
2.4.5
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Re: [Mesa-dev] [PATCH 1/2] i965: Set brw-batch.emit only #ifdef DEBUG.
Even if your next patch needs more work this one alone still makes
sense:
Reviewed-by: Iago Toral Quiroga ito...@igalia.com
Iago
On Wed, 2015-07-08 at 14:00 -0700, Matt Turner wrote:
It's only used inside #ifdef DEBUG. Cuts ~1.7k of .text, and more
importantly prevents a larger code size regression in the next commit
when the .used field is replaced and calculated on demand.
text data bss dec hex filename
4945468 19515226192 5166812 4ed6dc i965_dri.so before
4943740 19515226192 5165084 4ed01c i965_dri.so after
And surround the emit and total fields with #ifdef DEBUG to prevent
such mistakes from happening again.
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 7596139..afb714b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -872,7 +872,9 @@ struct intel_batchbuffer {
/** BO for post-sync nonzero writes for gen6 workaround. */
drm_intel_bo *workaround_bo;
+#ifdef DEBUG
uint16_t emit, total;
+#endif
uint16_t used, reserved_space;
uint32_t *map;
uint32_t *cpu_map;
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index fdd07e0..f0971e9 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -134,8 +134,8 @@ intel_batchbuffer_begin(struct brw_context *brw, int n,
enum brw_gpu_ring ring)
{
intel_batchbuffer_require_space(brw, n * 4, ring);
- brw-batch.emit = brw-batch.used;
#ifdef DEBUG
+ brw-batch.emit = brw-batch.used;
brw-batch.total = n;
#endif
}
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[Mesa-dev] [HACK] i965/fs: Fix ordering of src0 alpha and oMask in the framebuffer write payload.
We were passing src0 alpha and oMask in reverse order. There seems to
be no good way to pass them in the correct order to the new-style
LOAD_PAYLOAD (how surprising) because src0 alpha is per-channel while
oMask is not. Just split src0 alpha in fixed-width registers and pass
them to LOAD_PAYLOAD as if they were part of the header as work-around
for now.
I've written a piglit test that demonstrates the problem by using
gl_SampleMask from a fragment shader with multiple color outputs [1].
[1] http://lists.freedesktop.org/archives/piglit/2015-July/016499.html
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 94d6a58..304ae74 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1535,6 +1535,19 @@ fs_visitor::emit_single_fb_write(const fs_builder bld,
length++;
}
+ if (src0_alpha.file != BAD_FILE color0.file != BAD_FILE) {
+ /* Neat, we need to chop the src0 alpha component and pass it as part of
+ * the header even though it has per-channel semantics, because the next
+ * optional field is header-like and LOAD_PAYLOAD requires all such
+ * fields to form a contiguous segment at the beginning of the message.
+ */
+ for (unsigned i = 0; i exec_size / 8; i++) {
+ setup_color_payload(sources[length], src0_alpha, 1, 8,
+ use_2nd_half || i == 1);
+ length++;
+ }
+ }
+
prog_data-uses_omask =
prog-OutputsWritten BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK);
if (prog_data-uses_omask) {
@@ -1561,19 +1574,14 @@ fs_visitor::emit_single_fb_write(const fs_builder bld,
offset(this-outputs[0], bld, 3),
1, exec_size, false);
length += 4;
- } else if (color1.file == BAD_FILE) {
- if (src0_alpha.file != BAD_FILE) {
- setup_color_payload(sources[length], src0_alpha, 1, exec_size,
false);
- length++;
- }
-
- setup_color_payload(sources[length], color0, components,
- exec_size, use_2nd_half);
- length += 4;
} else {
setup_color_payload(sources[length], color0, components,
exec_size, use_2nd_half);
length += 4;
+
+ }
+
+ if (color1.file != BAD_FILE) {
setup_color_payload(sources[length], color1, components,
exec_size, use_2nd_half);
length += 4;
--
2.4.3
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Re: [Mesa-dev] [Mesa-stable] [PATCHv2] i965/gen9: Use custom MOCS entries set up by the kernel.
Ben Widawsky b...@bwidawsk.net writes:
On Tue, Jul 07, 2015 at 10:21:28PM +0300, Francisco Jerez wrote:
Instead of relying on hardware defaults the i915 kernel driver is
going program custom MOCS tables system-wide on Gen9 hardware. The
WT entry previously used for renderbuffers had a number of problems:
It disabled caching on eLLC, it used a reserved L3 cacheability
setting, and it used to override the PTE controls making renderbuffers
always WT on LLC regardless of the kernel's setting. Instead use an
entry from the new MOCS tables with parameters: TC=LLC/eLLC, LeCC=PTE,
L3CC=WB.
The WB entry previously used for anything other than renderbuffers
has moved to a different index in the new MOCS tables but it should
have the same caching semantics as the old entry.
Even though the corresponding kernel change (drm/i915: Added
Programming of the MOCS) is in a way an ABI break it doesn't seem
necessary to check that the kernel is recent enough because the change
should only affect Gen9 which is still unreleased hardware.
v2: Update MOCS values for the new Android-incompatible tables
introduced in v7 of the kernel patch.
Cc: 10.6 mesa-sta...@lists.freedesktop.org
It'd be cool to get perf data, but certainly not a requirement here since the
requirement to change is pretty obvious, IMO (mostly, I'm just curious). I do
like having the References: in the commit for the kernel patch, but that's
just
me, and I can live with whatever.
I ran SynMark on SKL with this patch applied last Monday and didn't spot
any significant differences. Some of the benchmarks seemed to give
quite erratic results regardless. Meh...
---
src/mesa/drivers/dri/i965/brw_defines.h| 11 ++-
src/mesa/drivers/dri/i965/gen8_surface_state.c | 3 +--
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 66b9abc..8ab8d62 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -2491,12 +2491,13 @@ enum brw_wm_barycentric_interp_mode {
#define BDW_MOCS_WT 0x58
#define BDW_MOCS_PTE 0x18
-/* Skylake: MOCS is now an index into an array of 64 different configurable
- * cache settings. We still use only either write-back or write-through;
and
- * rely on the documented default values.
+/* Skylake: MOCS is now an index into an array of 62 different caching
+ * configurations programmed by the kernel.
I'd keep the '64' instead of '62' the latter is a software construct, but
whatever you like.
It's an actual hardware limitation, the last two entries are reserved by
the hardware and are neither configurable (as the previous comment said)
nor can be programmed by the kernel (as my comment would imply had I
left the 64).
*/
-#define SKL_MOCS_WB (0b001001 1)
-#define SKL_MOCS_WT (0b000101 1)
+/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
+#define SKL_MOCS_WB (2 1)
+/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
+#define SKL_MOCS_PTE (1 1)
#define MEDIA_VFE_STATE 0x7000
/* GEN7 DW2, GEN8+ DW3 */
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index bd3eb00..dfaf762 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -401,8 +401,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
irb-mt_layer : (irb-mt_layer / MAX2(mt-num_samples, 1));
GLenum gl_target =
rb-TexImage ? rb-TexImage-TexObject-Target : GL_TEXTURE_2D;
- /* FINISHME: Use PTE MOCS on Skylake. */
- uint32_t mocs = brw-gen = 9 ? SKL_MOCS_WT : BDW_MOCS_PTE;
+ uint32_t mocs = brw-gen = 9 ? SKL_MOCS_PTE : BDW_MOCS_PTE;
I don't know the policy on const really, but this is a good opportunity to
const.
Sure, why not, const is always good.
intel_miptree_used_for_rendering(mt);
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Thanks.
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Re: [Mesa-dev] [PATCH 4/4] vc4: unref old fence
On Thu, Jul 9, 2015 at 8:36 AM, Emil Velikov emil.l.veli...@gmail.com wrote:
On 9 July 2015 at 01:46, Rob Clark robdcl...@gmail.com wrote:
From: Rob Clark robcl...@freedesktop.org
Some, but not all, state trackers will explicitly unref (and set to
NULL) the previous *fence before calling pipe-flush(). So driver
should use fence_ref() which will unref the old fence if not NULL.
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/drivers/vc4/vc4_context.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/vc4/vc4_context.c
b/src/gallium/drivers/vc4/vc4_context.c
index 630f8e6..316598f 100644
--- a/src/gallium/drivers/vc4/vc4_context.c
+++ b/src/gallium/drivers/vc4/vc4_context.c
@@ -103,8 +103,10 @@ vc4_pipe_flush(struct pipe_context *pctx, struct
pipe_fence_handle **fence,
vc4_flush(pctx);
if (fence) {
+struct pipe_screen *screen = pctx-screen;
struct vc4_fence *f = vc4_fence_create(vc4-screen,
vc4-last_emit_seqno);
+screen-fence_reference(screen, fence, NULL);
The order seems to be reversed comparing to the other patches that
you've sent. Is that intentional ?
it just made the diff smaller to do it in this order... the order
doesn't really matter
BR,
-R
-Emil
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Re: [Mesa-dev] [PATCH 2/2] i965: Optimize intel_batchbuffer_emit_dword().
On 09/07/15 11:13, Chris Wilson wrote:
On Wed, Jul 08, 2015 at 05:08:11PM -0700, Matt Turner wrote:
On Wed, Jul 8, 2015 at 4:53 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
static void upload_viewport_state_pointers(struct brw_context *brw)
{
BEGIN_BATCH(4);
brw-batch.map[0] = (_3DSTATE_VIEWPORT_STATE_POINTERS 16 | (4 - 2) |
GEN6_CC_VIEWPORT_MODIFY |
GEN6_SF_VIEWPORT_MODIFY |
GEN6_CLIP_VIEWPORT_MODIFY);
brw-batch.map[1] = (brw-clip.vp_offset);
brw-batch.map[2] = (brw-sf.vp_offset);
brw-batch.map[3] = (brw-cc.vp_offset);
brw-batch.map += 4;
ADVANCE_BATCH();
}
-Chris
Ah, thanks. I see.
I'll give it another shot.
Playing a bit more, I get reasonable code generation using
uint32_t *out = BEGIN_BATCH(4);
*out++ = (_3DSTATE_VIEWPORT_STATE_POINTERS 16 | (4 - 2) |
GEN6_CC_VIEWPORT_MODIFY |
GEN6_SF_VIEWPORT_MODIFY |
GEN6_CLIP_VIEWPORT_MODIFY);
*out++ = (brw-clip.vp_offset);
*out++ = (brw-sf.vp_offset);
*out++ = (brw-cc.vp_offset);
ADVANCE_BATCH(out);
with BEGIN_BATCH(n) {
uint32_t *ptr = brw-batch.map;
brw-batch.map + =n;
return ptr;
}
That also gives a simple ADVANCE_BATCH(out) assert(out == brw-batch.map),
and works with a little fudging (out - brw-batch.base) for OUT_RELOC.
-Chris
Hey guys,
I tried Chris' patches
(http://cgit.freedesktop.org/~ickle/mesa/log/?h=brw-batch) and found the
following results:
Baseline is commit 7916e0d12968f68e3916b221798049e2ea6c2340: i965:
AMD_pinned_memory and userptr
commit 195a0598da480f9ca2c499b668b76d836b8b65ea: ptr
customer benchmark: +0.5%
Synmark Oglbatch7: -2.29%
Glxgears: +4.78%
commit 37a093052dc92a5976134658b31ff82f25a3d01e: out
customer benchmark: +2.6% (103.1% of baseline)
Synmark Oglbatch7: +2.21% (99.8% of baseline)
Glxgears: +0% (104.78% of baseline)
This is done by iterating 10 times each benchmark for every commit. So,
this looks like in average, this is a net positive! Thanks Matt and Chris!
Martin
PS: Sorry for the commit number, they are taken from my branch that gets
rid of the DRI2/3-related commits of Chris' branch.
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[Mesa-dev] [PATCH] glsl: fix Bug 85252 - Segfault in compiler while processing ternary operator with void arguments
This is done by returning an rvalue of type void in the
ast_function_expression::hir function instead of a void expression.
This produces (in the case of the ternary) an hir with a call
to the void returning function and an assignement of a void variable
which will be optimized out (the assignement) during the optimization
pass.
This fix results in having a valid subexpression in the many
different cases where the subexpressions are functions whose
return values are void.
Thus preventing to dereference NULL in the following cases:
* binary operator
* unary operators
* ternary operator
* comparison operators (except equal and nequal operator)
Equal and nequal had to be handled as a special case because
instead of segfaulting on a forbidden syntax it was now accepting
expressions with a void return value on either (or both) side of
the expression.
Piglist tests are on the way
Signed-off-by: Renaud Gaubert ren...@lse.epita.fr
Reviewed-by: Gabriel Laskar gabr...@lse.epita.fr
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85252
---
src/glsl/ast_function.cpp | 7 ++-
src/glsl/ast_to_hir.cpp | 10 +-
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/glsl/ast_function.cpp b/src/glsl/ast_function.cpp
index 92e26bf..3c2b1ea 100644
--- a/src/glsl/ast_function.cpp
+++ b/src/glsl/ast_function.cpp
@@ -1785,7 +1785,12 @@ ast_function_expression::hir(exec_list *instructions,
/* an error has already been emitted */
value = ir_rvalue::error_value(ctx);
} else {
-value = generate_call(instructions, sig, actual_parameters, state);
+value = generate_call(instructions, sig, actual_parameters, state);
+if (!value) {
+ ir_variable *const tmp = new(ctx) ir_variable(glsl_type::void_type,
void_var, ir_var_temporary);
+ value = new(ctx) ir_dereference_variable(tmp);
+ instructions-push_tail(tmp);
+}
}
return value;
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 8cb46be..00cc16c 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -1270,7 +1270,15 @@ ast_expression::do_hir(exec_list *instructions,
*applied to one operand that can make them match, in which
*case this conversion is done.
*/
- if ((!apply_implicit_conversion(op[0]-type, op[1], state)
+
+ if (op[0]-type == glsl_type::void_type || op[1]-type ==
glsl_type::void_type) {
+
+_mesa_glsl_error( loc, state, `%s': wrong operand types: no
operation
+ `%1$s' exists that takes a left-hand operand of type 'void' or a
+ right operand of type 'void', (this-oper == ast_equal) ? == :
!=);
+
+ error_emitted = true;
+ } else if ((!apply_implicit_conversion(op[0]-type, op[1], state)
!apply_implicit_conversion(op[1]-type, op[0], state))
|| (op[0]-type != op[1]-type)) {
_mesa_glsl_error( loc, state, operands of `%s' must have the same
--
2.4.5
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Re: [Mesa-dev] [RFC] loader: libudev vs sysfs vs libdrm
On 09/07/2015 15:33, Emil Velikov wrote : Yakes forgot about that one. From a quick look we can (I know it feels durty) use readlink( /sys/dev/char/$(major):$(minor)). Everything seems to be there - bus type and exact location of the device on the bus. It's limited to sysfs users, but they are more than the libudev ones (perhaps not by much). How does that sound ? Cheers, Emil The idea behind using udev for the tag was that arbitrary tag could be used, especially to identify usb devices. Ofc another solution could be used. Yours, Axel ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH shader-db] Add support for shadertoy tests
Attached script grabs shaders from shadertoy, and dumps them out as
.shader_test files which can be run through shader-db for compiler
testing.
shadertoy only gives you a fragment shader (which works based on
gl_FragCoord), so a generic vertex shader is used. And a blurb is
inserted for the pre-defined uniforms and main() function (which just
calls shadertoy mainImage() fxn).
v2: updated w/ python suggestions from Dylan
---
Note: we probably want to pick a couple shadertoy shaders and commit
them (rather than pulling down *all* shadertoy shaders, which may
change over time, etc). I can just pick a couple randomly unless
anyone has some requests. Either way, seems useful to have the script
in git in case anyone else wants to grab new/more shaders.
grab-shadertoy.py | 66 +++
1 file changed, 66 insertions(+)
create mode 100755 grab-shadertoy.py
diff --git a/grab-shadertoy.py b/grab-shadertoy.py
new file mode 100755
index 000..04db411
--- /dev/null
+++ b/grab-shadertoy.py
@@ -0,0 +1,66 @@
+#!/usr/bin/env python3
+
+
+import os, requests, textwrap
+
+url = 'https://www.shadertoy.com/api/v1/shaders'
+key = '?key=NdnKw7'
+
+header = textwrap.dedent(\
+[require]
+GLSL = 1.30
+
+[fragment shader]
+#version 130
+uniform vec3 iResolution;
+uniform float iGlobalTime;
+uniform float iChannelTime[4];
+uniform vec4 iMouse;
+uniform vec4 iDate;
+uniform float iSampleRate;
+uniform vec3 iChannelResolution[4];
+uniform sampler2D iChannel0;
+uniform sampler2D iChannel1;
+uniform sampler2D iChannel2;
+uniform sampler2D iChannel3;
+
+)
+
+footer = textwrap.dedent(\
+
+void main() { mainImage(gl_FragColor, gl_FragCoord.xy); }
+
+[vertex shader]
+#version 130
+in vec2 position;
+
+void main()
+{
+ gl_Position = vec4(position, 0.0, 1.0);
+}
+)
+
+# Get the list of shaders
+r = requests.get(url + key)
+j = r.json()
+print('Found {} shaders'.format(j['Shaders']))
+
+shader_ids = j['Results']
+for id in shader_ids:
+print('Fetching shader: {}'.format(id))
+print('url: {}/{}{}'.format(url, id, key))
+r = requests.get(url + '/' + id + key)
+j = r.json()
+s = j['Shader']
+info = s['info']
+print('Name: ' + info['name'])
+print('Description: ' + info['description'])
+if not os.path.exists('shaders/shadertoy'):
+os.makedirs('shaders/shadertoy')
+for i, p in enumerate(s['renderpass']):
+#print('Inputs: {}'.format(p['inputs']))
+#print('Outputs: {}'.format(p['outputs']))
+with open('shaders/shadertoy/{}_{}.shader_test'.format(id, i), 'w') as
fobj:
+fobj.write(header)
+fobj.write(p['code'])
+fobj.write(footer)
--
2.4.3
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Re: [Mesa-dev] [PATCH 06/78] i965/nir/vec4: Add setup of uniform variables
On Tuesday, June 30, 2015 10:04:47 AM Iago Toral wrote:
Hi Jason,
On Mon, 2015-06-29 at 16:22 -0700, Jason Ekstrand wrote:
On Fri, Jun 26, 2015 at 1:06 AM, Eduardo Lima Mitev el...@igalia.com
wrote:
From: Iago Toral Quiroga ito...@igalia.com
This is based on similar code existing in vec4_visitor. It builds the
uniform register file iterating through each uniform variable. It
also stores the index of each register at the corresponding offset
in a map. This map will later be used by load_uniform intrinsic
instructions to build the correct UNIFORM source register.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4.h | 2 +
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 115
-
2 files changed, 114 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 673df4e..6535f19 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -414,6 +414,8 @@ public:
src_reg *nir_inputs;
int *nir_outputs;
brw_reg_type *nir_output_types;
+ unsigned *nir_uniform_offset;
+ unsigned *nir_uniform_driver_location;
protected:
void emit_vertex();
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 2d457a6..40ec66f 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -106,19 +106,128 @@ vec4_visitor::nir_setup_outputs(nir_shader *shader)
void
vec4_visitor::nir_setup_uniforms(nir_shader *shader)
{
- /* @TODO: Not yet implemented */
+ uniforms = 0;
+
+ nir_uniform_offset =
+ rzalloc_array(mem_ctx, unsigned, this-uniform_array_size);
+ memset(nir_uniform_offset, 0, this-uniform_array_size *
sizeof(unsigned));
rzalloc memsets the whole thing to 0 for you, this memset is redundant.
+
+ nir_uniform_driver_location =
+ rzalloc_array(mem_ctx, unsigned, this-uniform_array_size);
+ memset(nir_uniform_driver_location, 0,
+ this-uniform_array_size * sizeof(unsigned));
Same here.
Oh, right.
+
+ if (shader_prog) {
+ foreach_list_typed(nir_variable, var, node, shader-uniforms) {
+ /* UBO's, atomics and samplers don't take up space in the
+uniform file */
+ if (var-interface_type != NULL || var-type-contains_atomic()
||
+ type_size(var-type) == 0) {
I'm curious as to why you have this extra type_size() == 0 condition.
We don't have that in the FS NIR code. What caused you to add it?
Take this piglit test for example:
bin/textureSize vs isampler1D -auto -fbo
here, 'tex' is a uniform of size 0 since type_size() returns 0 for all
sampler types. If we do not ignore these, we will try to store uniform
information for them in the various structures we have to track uniform
data, like uniform_size[] and others. The size allocated for these
arrays is computed by in the vec4_visitor constructor based on
stage_prog_data-nr_params (uniform_array_size) and that does not seem
to make room for zero-sized uniforms. Without that check we would
process more uniforms than uniform_array_size and overflow the arrays we
allocate to track uniform information. I understand that
stage_prog_data-nr_params does not track uniforms that don't use
register space, so skipping uniforms with no size seems to make sense
here.
Notice that this is done in the current vec4_visitor too, when we visit
the variable in vec4_visitor::visit(ir_variable *ir), for ir_var_uniform
there is this code:
if (ir-is_in_uniform_block() || type_size(ir-type) == 0)
return;
Oh, right. I think we handle sampler uniforms a bit differently in the
vec4 and FS backends, and I was never quite sure why...I know we've had
bugs relating to zero-sized uniforms, but I was never quite able to sort
them out.
This seems fine for now - it keeps the vec4 world doing what it's always
done.
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Re: [Mesa-dev] [PATCH] [v2] i965: Split out gen8 push constant state upload
On Thu, Jul 09, 2015 at 09:44:52AM -0700, Ben Widawsky wrote:
While implementing the workaround in the previous patch I noticed things were
starting to get a bit messy. Since gen8 works differently enough from gen7, I
thought splitting it out with be good.
While here, get rid of gen8 MOCS which does nothing and was in the wrong place
anyway.
This patch is totally optional. I'd be willing to just always use buffer #2 on
gen8+. Pre-HSW this wasn't allowed, but it looks like it's okay for gen8 too.
v2: Move inactive batch generation to the top of the function in order to make
the rest of the code easier to read.
Jenkins results (still a bunch of spurious failures, I miss Mark):
http://otc-mesa-ci.jf.intel.com/job/bwidawsk/169/
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com (v1)
---
I had a minor bug in v1 which prevented me from pushing this sooner. I'd like
to
merge this patch unless anyone has complaints?
---
src/mesa/drivers/dri/i965/brw_state.h | 6 +-
src/mesa/drivers/dri/i965/gen6_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_vs_state.c | 3 +-
src/mesa/drivers/dri/i965/gen6_wm_state.c | 3 +-
src/mesa/drivers/dri/i965/gen7_vs_state.c | 93
---
5 files changed, 68 insertions(+), 39 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 987672f..f45459d 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -368,9 +368,9 @@ brw_upload_pull_constants(struct brw_context *brw,
/* gen7_vs_state.c */
void
-gen7_upload_constant_state(struct brw_context *brw,
- const struct brw_stage_state *stage_state,
- bool active, unsigned opcode);
+brw_upload_constant_state(struct brw_context *brw,
+ const struct brw_stage_state *stage_state,
+ bool active, unsigned opcode);
#ifdef __cplusplus
}
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c
b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index eb4c586..19568b0 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -48,7 +48,7 @@ gen6_upload_gs_push_constants(struct brw_context *brw)
}
if (brw-gen = 7)
- gen7_upload_constant_state(brw, stage_state, gp, _3DSTATE_CONSTANT_GS);
+ brw_upload_constant_state(brw, stage_state, gp, _3DSTATE_CONSTANT_GS);
}
const struct brw_tracked_state gen6_gs_push_constants = {
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c
b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 35d10ef..c33607d 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -140,8 +140,7 @@ gen6_upload_vs_push_constants(struct brw_context *brw)
if (brw-gen == 7 !brw-is_haswell !brw-is_baytrail)
gen7_emit_vs_workaround_flush(brw);
- gen7_upload_constant_state(brw, stage_state, true /* active */,
- _3DSTATE_CONSTANT_VS);
+ brw_upload_constant_state(brw, stage_state, true,
_3DSTATE_CONSTANT_VS);
}
}
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c
b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index d1748ba..ced4ad6 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -50,8 +50,7 @@ gen6_upload_wm_push_constants(struct brw_context *brw)
stage_state, AUB_TRACE_WM_CONSTANTS);
if (brw-gen = 7) {
- gen7_upload_constant_state(brw, brw-wm.base, true,
- _3DSTATE_CONSTANT_PS);
+ brw_upload_constant_state(brw, brw-wm.base, true,
_3DSTATE_CONSTANT_PS);
}
}
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c
b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 4b17d06..6a51934 100644
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -29,20 +29,23 @@
#include program/prog_statevars.h
#include intel_batchbuffer.h
-
-void
-gen7_upload_constant_state(struct brw_context *brw,
+static void
+gen8_upload_constant_state(struct brw_context *brw,
const struct brw_stage_state *stage_state,
bool active, unsigned opcode)
{
- uint32_t mocs = brw-gen 8 ? GEN7_MOCS_L3 : 0;
- /* Disable if the shader stage is inactive or there are no push
constants. */
- active = active stage_state-push_const_size != 0;
+ /* FINISHME: determine if we should use mocs on gen9 */
- int dwords = brw-gen = 8 ? 11 : 7;
- BEGIN_BATCH(dwords);
- OUT_BATCH(opcode 16 | (dwords - 2));
+ BEGIN_BATCH(11);
+ OUT_BATCH(opcode 16 | (11 - 2));
+
+ if (!active) {
+ for (int i = 0; i 11; i++)
+ OUT_BATCH(0);
+
+
[Mesa-dev] [PATCH] i965/hsw: Implement end of batch workaround
From: Ben Widawsky benjamin.widaw...@intel.com
This patch can cause an infinite recursion if the previous patch titled, i965:
Track finished batch state isn't present (backporters take notice).
v2: Sent out the wrong patch originally. This patches switches the order of
flushes, doing the generic flush before the CC_STATE, and the required
workaround flush afterwards
v3: Only perform workaround for render ring
Add text to the BATCH_RESERVE comments
v4: Rebase; update citation to mention PRM and Wa name; combine two blocks.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 27 +--
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 4
2 files changed, 29 insertions(+), 2 deletions(-)
Hey Ben,
I was going to suggest a few minor changes, and then realized it'd save us both
time if I just typed them up. Here's a v4 of your patch. If it passes Jenkins,
I'd say let's push it. Thanks for remembering this!
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 969d92c..d93ee6e 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -32,6 +32,7 @@
#include intel_buffers.h
#include intel_fbo.h
#include brw_context.h
+#include brw_defines.h
#include xf86drm.h
#include i915_drm.h
@@ -206,10 +207,32 @@ brw_finish_batch(struct brw_context *brw)
*/
brw_emit_query_end(brw);
- /* We may also need to snapshot and disable OA counters. */
- if (brw-batch.ring == RENDER_RING)
+ if (brw-batch.ring == RENDER_RING) {
+ /* We may also need to snapshot and disable OA counters. */
brw_perf_monitor_finish_batch(brw);
+ if (brw-is_haswell) {
+ /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
+ * 3DSTATE_CC_STATE_POINTERS Note:
+ *
+ * SW must program 3DSTATE_CC_STATE_POINTERS command at the end of
every
+ * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS
stall.
+ *
+ * From the example in the docs, it seems to expect a regular pipe
control
+ * flush here as well. We may have done it already, but meh.
+ *
+ * See also WaAvoidRCZCounterRollover.
+ */
+ brw_emit_mi_flush(brw);
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_CC_STATE_POINTERS 16 | (2 - 2));
+ OUT_BATCH(brw-cc.state_offset | 1);
+ ADVANCE_BATCH();
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH |
+ PIPE_CONTROL_CS_STALL);
+ }
+ }
+
/* Mark that the current program cache BO has been used by the GPU.
* It will be reallocated if we need to put new programs in for the
* next batch.
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index fdd07e0..8eaedd1 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -26,6 +26,10 @@ extern C {
* - 3 DWords for MI_REPORT_PERF_COUNT itself on Gen6+. == 12 bytes.
* On Ironlake, it's 6 DWords, but we have some slack due to the lack of
* Sandybridge PIPE_CONTROL madness.
+ * - CC_STATE workaround on HSW (12 * 4 = 48 bytes)
+ * - 5 dwords for initial mi_flush
+ * - 2 dwords for CC state setup
+ * - 5 dwords for the required pipe control at the end
*/
#define BATCH_RESERVED 152
--
2.4.5
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Re: [Mesa-dev] [PATCH 04/11] dri_interface: drop __NOT_HAVE_DRM_H magic
On 07/08/2015 10:07 AM, Emil Velikov wrote: Signed-off-by: Emil Velikov emil.l.veli...@gmail.com --- include/GL/internal/dri_interface.h | 11 --- 1 file changed, 11 deletions(-) diff --git a/include/GL/internal/dri_interface.h b/include/GL/internal/dri_interface.h index c827bb6..c0545b1 100644 --- a/include/GL/internal/dri_interface.h +++ b/include/GL/internal/dri_interface.h @@ -40,20 +40,9 @@ #ifndef DRI_INTERFACE_H #define DRI_INTERFACE_H -/* For archs with no drm.h */ -#if defined(__APPLE__) || defined(__CYGWIN__) || defined(__GNU__) -#ifndef __NOT_HAVE_DRM_H -#define __NOT_HAVE_DRM_H -#endif -#endif - -#ifndef __NOT_HAVE_DRM_H Shouldn't this get changed to use HAVE_LIBDRM as in later patches? I guess drm_context_t and drm_drawable_t are ABI, so they shouldn't ever change. It does feel a little icky to redefine them when not necessary. -#include drm.h -#else typedef unsigned int drm_context_t; typedef unsigned int drm_drawable_t; typedef struct drm_clip_rect drm_clip_rect_t; -#endif /** * \name DRI interface structures ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 06/11] loader: use HAVE_LIBDRM instead of ! __NOT_HAVE_DRM_H
I can't really speak to the Android.mk or SConscript changes, but the
rest of this patch is
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
You might also see what Jeremy Huddleston Sequoia jerem...@apple.com
thinks, since most of this exists to support his platform. :)
On 07/08/2015 10:07 AM, Emil Velikov wrote:
Double negatives in English language are normally avoided, plus the
former seems cleaner and more consistent.
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/loader/Android.mk | 6 ++
src/loader/Makefile.am | 5 +
src/loader/SConscript | 2 --
src/loader/loader.c| 8
src/loader/pci_id_driver_map.c | 2 +-
5 files changed, 8 insertions(+), 15 deletions(-)
diff --git a/src/loader/Android.mk b/src/loader/Android.mk
index 92d9fd2..8690565 100644
--- a/src/loader/Android.mk
+++ b/src/loader/Android.mk
@@ -33,10 +33,8 @@ include $(CLEAR_VARS)
LOCAL_SRC_FILES := \
$(LOADER_C_FILES)
-# swrast only
-ifeq ($(MESA_GPU_DRIVERS),swrast)
-LOCAL_CFLAGS += -D__NOT_HAVE_DRM_H
-else
+ifneq ($(filter-out swrast,$(MESA_GPU_DRIVERS)),)
+LOCAL_CFLAGS += -DHAVE_LIBDRM
LOCAL_SHARED_LIBRARIES := libdrm
endif
diff --git a/src/loader/Makefile.am b/src/loader/Makefile.am
index aef1bd6..5190f7f 100644
--- a/src/loader/Makefile.am
+++ b/src/loader/Makefile.am
@@ -48,10 +48,7 @@ libloader_la_CPPFLAGS += \
endif
-if !HAVE_LIBDRM
-libloader_la_CPPFLAGS += \
- -D__NOT_HAVE_DRM_H
-else
+if HAVE_LIBDRM
libloader_la_CPPFLAGS += \
$(LIBDRM_CFLAGS)
diff --git a/src/loader/SConscript b/src/loader/SConscript
index 16d1053..d98f11e 100644
--- a/src/loader/SConscript
+++ b/src/loader/SConscript
@@ -8,8 +8,6 @@ env.Prepend(CPPPATH = [
'#include'
])
-env.Append(CPPDEFINES = ['__NOT_HAVE_DRM_H'])
-
if env['udev']:
env.PkgUseModules('UDEV')
env.Append(CPPDEFINES = ['HAVE_LIBUDEV'])
diff --git a/src/loader/loader.c b/src/loader/loader.c
index 8780587..4ed0a1f 100644
--- a/src/loader/loader.c
+++ b/src/loader/loader.c
@@ -85,7 +85,7 @@
#endif
#include loader.h
-#ifndef __NOT_HAVE_DRM_H
+#ifdef HAVE_LIBDRM
#include xf86drm.h
#endif
@@ -501,7 +501,7 @@ sysfs_get_pci_id_for_fd(int fd, int *vendor_id, int
*chip_id)
}
#endif
-#if !defined(__NOT_HAVE_DRM_H)
+#if defined(HAVE_LIBDRM)
/* for i915 */
#include i915_drm.h
/* for radeon */
@@ -584,7 +584,7 @@ loader_get_pci_id_for_fd(int fd, int *vendor_id, int
*chip_id)
if (sysfs_get_pci_id_for_fd(fd, vendor_id, chip_id))
return 1;
#endif
-#if !defined(__NOT_HAVE_DRM_H)
+#if HAVE_LIBDRM
if (drm_get_pci_id_for_fd(fd, vendor_id, chip_id))
return 1;
#endif
@@ -695,7 +695,7 @@ loader_get_driver_for_fd(int fd, unsigned driver_types)
if (!loader_get_pci_id_for_fd(fd, vendor_id, chip_id)) {
-#ifndef __NOT_HAVE_DRM_H
+#if HAVE_LIBDRM
/* fallback to drmGetVersion(): */
drmVersionPtr version = drmGetVersion(fd);
diff --git a/src/loader/pci_id_driver_map.c b/src/loader/pci_id_driver_map.c
index cb6f705..3c4657f 100644
--- a/src/loader/pci_id_driver_map.c
+++ b/src/loader/pci_id_driver_map.c
@@ -23,7 +23,7 @@
int is_nouveau_vieux(int fd);
-#ifndef __NOT_HAVE_DRM_H
+#ifdef HAVE_LIBDRM
#include xf86drm.h
#include nouveau_drm.h
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Re: [Mesa-dev] [PATCH] i965/cs: Initialize GPGPU Thread Count
On Thu, Jul 02, 2015 at 11:32:03PM -0700, Jordan Justen wrote:
On 2015-06-25 11:34:59, Ben Widawsky wrote:
On Thu, Jun 11, 2015 at 09:04:45PM -0700, Jordan Justen wrote:
+ desc[dw++] = 0;
+ const uint32_t media_threads =
+ brw-gen = 8 ?
+ SET_FIELD(threads, GEN8_MEDIA_GPGPU_THREAD_COUNT) :
+ SET_FIELD(threads, MEDIA_GPGPU_THREAD_COUNT);
+ desc[dw++] = media_threads;
What's the deal with, The maximum value for global barriers is limited by
the
number of threads in the system, or by 511, Can we add an assert?
I guess we are using a local barrier, so the maximum value is the
number of threads in a subslice for local barriers.
How about I add assert(threads = brw-max_cs_threads)? Although, in
brw_compute:brw_emit_gpgpu_walker we have a similar assertion.
-Jordan
Seems fine either way. The original mail had my r-b
BEGIN_BATCH(4);
OUT_BATCH(MEDIA_INTERFACE_DESCRIPTOR_LOAD 16 | (4 - 2));
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index f6da305..2a8f500 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -2495,6 +2495,11 @@ enum brw_wm_barycentric_interp_mode {
# define MEDIA_VFE_STATE_CURBE_ALLOC_MASK INTEL_MASK(15, 0)
#define MEDIA_INTERFACE_DESCRIPTOR_LOAD 0x7002
+/* GEN7 DW5, GEN8+ DW6 */
+# define MEDIA_GPGPU_THREAD_COUNT_SHIFT 0
+# define MEDIA_GPGPU_THREAD_COUNT_MASK INTEL_MASK(7, 0)
+# define GEN8_MEDIA_GPGPU_THREAD_COUNT_SHIFT0
+# define GEN8_MEDIA_GPGPU_THREAD_COUNT_MASK INTEL_MASK(9, 0)
#define MEDIA_STATE_FLUSH 0x7004
#define GPGPU_WALKER0x7105
/* GEN8+ DW2 */
--
2.1.4
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Re: [Mesa-dev] [PATCH 03/11] radeon: remove dri_mirror state
On 07/08/2015 10:07 AM, Emil Velikov wrote:
Most of the data stored(duplicated) was unused, and for the one that is
follow the approach set by other drivers.
This eliminates the use of legacy (dri1) types.
XXX: The radeon code is the only user of __DRIscreen::drm_version (the
only __DRIversion outside of dri1 land). Should we move it into radeon
and/or bump the min. required drm module version ?
Cc: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
I think the cleanups suggested by Michel and Emil sound like a good idea
too, FWIW.
Cc: Marek Olšák marek.ol...@amd.com
Cc: Michel Dänzer michel.daen...@amd.com
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/mesa/drivers/dri/radeon/radeon_common.c | 18 +-
src/mesa/drivers/dri/radeon/radeon_common_context.c | 7 ++-
src/mesa/drivers/dri/radeon/radeon_common_context.h | 19 +++
src/mesa/drivers/dri/radeon/radeon_texture.c| 2 +-
4 files changed, 15 insertions(+), 31 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c
b/src/mesa/drivers/dri/radeon/radeon_common.c
index 2a8bd6c9..d834d9b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -164,7 +164,7 @@ uint32_t radeonGetAge(radeonContextPtr radeon)
gp.param = RADEON_PARAM_LAST_CLEAR;
gp.value = (int *)age;
- ret = drmCommandWriteRead(radeon-dri.fd, DRM_RADEON_GETPARAM,
+ ret = drmCommandWriteRead(radeon-radeonScreen-driScreen-fd,
DRM_RADEON_GETPARAM,
gp, sizeof(gp));
if (ret) {
fprintf(stderr, %s: drmRadeonGetParam: %d\n, __func__,
@@ -358,8 +358,8 @@ void radeonDrawBuffer( struct gl_context *ctx, GLenum
mode )
* that the front-buffer has actually been allocated.
*/
if (!was_front_buffer_rendering
radeon-is_front_buffer_rendering) {
- radeon_update_renderbuffers(radeon-dri.context,
- radeon-dri.context-driDrawablePriv, GL_FALSE);
+ radeon_update_renderbuffers(radeon-driContext,
+ radeon-driContext-driDrawablePriv, GL_FALSE);
}
}
@@ -375,8 +375,8 @@ void radeonReadBuffer( struct gl_context *ctx, GLenum
mode )
|| (mode == GL_FRONT);
if (!was_front_buffer_reading
rmesa-is_front_buffer_reading) {
- radeon_update_renderbuffers(rmesa-dri.context,
-
rmesa-dri.context-driReadablePriv, GL_FALSE);
+ radeon_update_renderbuffers(rmesa-driContext,
+
rmesa-driContext-driReadablePriv, GL_FALSE);
}
}
/* nothing, until we implement h/w glRead/CopyPixels or CopyTexImage */
@@ -399,7 +399,7 @@ void radeon_window_moved(radeonContextPtr radeon)
void radeon_viewport(struct gl_context *ctx)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
- __DRIcontext *driContext = radeon-dri.context;
+ __DRIcontext *driContext = radeon-driContext;
void (*old_viewport)(struct gl_context *ctx);
if (_mesa_is_winsys_fbo(ctx-DrawBuffer)) {
@@ -693,6 +693,7 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa)
{
GLuint size;
struct drm_radeon_gem_info mminfo = { 0 };
+ int fd = rmesa-radeonScreen-driScreen-fd;
/* Initialize command buffer */
size = 256 * driQueryOptioni(rmesa-optionCache,
@@ -711,8 +712,7 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa)
Allocating %d bytes command buffer (max state is %d
bytes)\n,
size * 4, rmesa-hw.max_state_size * 4);
- rmesa-cmdbuf.csm =
- radeon_cs_manager_gem_ctor(rmesa-radeonScreen-driScreen-fd);
+ rmesa-cmdbuf.csm = radeon_cs_manager_gem_ctor(fd);
if (rmesa-cmdbuf.csm == NULL) {
/* FIXME: fatal error */
return;
@@ -725,7 +725,7 @@ void rcommonInitCmdBuf(radeonContextPtr rmesa)
(void (*)(void *))rmesa-glCtx.Driver.Flush,
rmesa-glCtx);
- if (!drmCommandWriteRead(rmesa-dri.fd, DRM_RADEON_GEM_INFO,
+ if (!drmCommandWriteRead(fd, DRM_RADEON_GEM_INFO,
mminfo, sizeof(mminfo))) {
radeon_cs_set_limit(rmesa-cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM,
mminfo.vram_visible);
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c
b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 3d0ceda..4660d98 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -162,10 +162,7 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
[Mesa-dev] [PATCH] [v3] i965: Split out gen8 push constant state upload
While implementing the workaround in the previous patch I noticed things were
starting to get a bit messy. Since gen8 works differently enough from gen7, I
thought splitting it out with be good.
While here, get rid of gen8 MOCS which does nothing and was in the wrong place
anyway.
This patch is totally optional. I'd be willing to just always use buffer #2 on
gen8+. Pre-HSW this wasn't allowed, but it looks like it's okay for gen8 too.
v2: Move inactive batch generation to the top of the function in order to make
the rest of the code easier to read.
Jenkins results (still a bunch of spurious failures, I miss Mark):
http://otc-mesa-ci.jf.intel.com/job/bwidawsk/169/
v3: v2 had a bug in that it both didn't emit the right number of dwords, and it
didn't do ADVANCE_BATCH(). I'm moderately worried that there were no failures as
a result.
http://otc-mesa-ci.jf.intel.com/job/bwidawsk/170/
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com (v1)
---
src/mesa/drivers/dri/i965/brw_state.h | 6 +-
src/mesa/drivers/dri/i965/gen6_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_vs_state.c | 3 +-
src/mesa/drivers/dri/i965/gen6_wm_state.c | 3 +-
src/mesa/drivers/dri/i965/gen7_vs_state.c | 94 +--
5 files changed, 69 insertions(+), 39 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 987672f..f45459d 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -368,9 +368,9 @@ brw_upload_pull_constants(struct brw_context *brw,
/* gen7_vs_state.c */
void
-gen7_upload_constant_state(struct brw_context *brw,
- const struct brw_stage_state *stage_state,
- bool active, unsigned opcode);
+brw_upload_constant_state(struct brw_context *brw,
+ const struct brw_stage_state *stage_state,
+ bool active, unsigned opcode);
#ifdef __cplusplus
}
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c
b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index eb4c586..19568b0 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -48,7 +48,7 @@ gen6_upload_gs_push_constants(struct brw_context *brw)
}
if (brw-gen = 7)
- gen7_upload_constant_state(brw, stage_state, gp, _3DSTATE_CONSTANT_GS);
+ brw_upload_constant_state(brw, stage_state, gp, _3DSTATE_CONSTANT_GS);
}
const struct brw_tracked_state gen6_gs_push_constants = {
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c
b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 35d10ef..c33607d 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -140,8 +140,7 @@ gen6_upload_vs_push_constants(struct brw_context *brw)
if (brw-gen == 7 !brw-is_haswell !brw-is_baytrail)
gen7_emit_vs_workaround_flush(brw);
- gen7_upload_constant_state(brw, stage_state, true /* active */,
- _3DSTATE_CONSTANT_VS);
+ brw_upload_constant_state(brw, stage_state, true, _3DSTATE_CONSTANT_VS);
}
}
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c
b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index d1748ba..ced4ad6 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -50,8 +50,7 @@ gen6_upload_wm_push_constants(struct brw_context *brw)
stage_state, AUB_TRACE_WM_CONSTANTS);
if (brw-gen = 7) {
- gen7_upload_constant_state(brw, brw-wm.base, true,
- _3DSTATE_CONSTANT_PS);
+ brw_upload_constant_state(brw, brw-wm.base, true,
_3DSTATE_CONSTANT_PS);
}
}
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c
b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 4b17d06..f8f0ad2 100644
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -29,20 +29,24 @@
#include program/prog_statevars.h
#include intel_batchbuffer.h
-
-void
-gen7_upload_constant_state(struct brw_context *brw,
+static void
+gen8_upload_constant_state(struct brw_context *brw,
const struct brw_stage_state *stage_state,
bool active, unsigned opcode)
{
- uint32_t mocs = brw-gen 8 ? GEN7_MOCS_L3 : 0;
- /* Disable if the shader stage is inactive or there are no push constants.
*/
- active = active stage_state-push_const_size != 0;
+ /* FINISHME: determine if we should use mocs on gen9 */
- int dwords = brw-gen = 8 ? 11 : 7;
- BEGIN_BATCH(dwords);
- OUT_BATCH(opcode 16 | (dwords - 2));
+ BEGIN_BATCH(11);
+ OUT_BATCH(opcode 16 | (11 - 2));
+
+ if (!active) {
+ for (int i = 0; i 10; i++)
+ OUT_BATCH(0);
+
+ ADVANCE_BATCH();
+ return;
+ }
/* Workaround for SKL+ (we use option #2 until we have a
Re: [Mesa-dev] [PATCH] glsl: use the fast hash table for ir_validate
Timothy Arceri t_arc...@yahoo.com.au writes:
---
Some of the AoA tests currently get stuck in an optimisation
loop for a long time and this was taking a large amount of time.
Its a symptom not a cause but I don't see any issue with using the faster
version.
src/glsl/ir_validate.cpp | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/src/glsl/ir_validate.cpp b/src/glsl/ir_validate.cpp
index cfe0df3..f3752bd 100644
--- a/src/glsl/ir_validate.cpp
+++ b/src/glsl/ir_validate.cpp
@@ -35,7 +35,7 @@
#include ir.h
#include ir_hierarchical_visitor.h
-#include program/hash_table.h
+#include util/hash_table.h
#include glsl_types.h
namespace {
@@ -44,8 +44,8 @@ class ir_validate : public ir_hierarchical_visitor {
public:
ir_validate()
{
- this-ht = hash_table_ctor(0, hash_table_pointer_hash,
- hash_table_pointer_compare);
+ this-ht = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
+ _mesa_key_pointer_equal);
this-current_function = NULL;
@@ -55,7 +55,7 @@ public:
~ir_validate()
{
- hash_table_dtor(this-ht);
+ _mesa_hash_table_destroy(this-ht, NULL);
}
virtual ir_visitor_status visit(ir_variable *v);
@@ -94,7 +94,7 @@ ir_validate::visit(ir_dereference_variable *ir)
abort();
}
- if (hash_table_find(ht, ir-var) == NULL) {
+ if (_mesa_hash_table_search(ht, ir-var) == NULL) {
printf(ir_dereference_variable @ %p specifies undeclared variable
`%s' @ %p\n,
(void *) ir, ir-var-name, (void *) ir-var);
@@ -730,8 +730,7 @@ ir_validate::visit(ir_variable *ir)
if (ir-name ir-is_name_ralloced())
assert(ralloc_parent(ir-name) == ir);
- hash_table_insert(ht, ir, ir);
-
+ _mesa_hash_table_insert(ht, ir, ir);
/* If a variable is an array, verify that the maximum array index is in
* bounds. There was once an error in AST-to-HIR conversion that set this
@@ -887,13 +886,13 @@ ir_validate::validate_ir(ir_instruction *ir, void *data)
{
struct hash_table *ht = (struct hash_table *) data;
- if (hash_table_find(ht, ir)) {
+ if (_mesa_hash_table_search(ht, ir)) {
printf(Instruction node present twice in ir tree:\n);
ir-print();
printf(\n);
abort();
}
- hash_table_insert(ht, ir, ir);
+ _mesa_hash_table_insert(ht, ir, ir);
}
It looks like you should use a set instead of a hash table, since you
don't need a separate data field.
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[Mesa-dev] [PATCH] mesa: Fix generation of git_sha1.h.tmp for gitlinks
Don't assume that $(top_srcdir)/.git is a directory. It may be a gitlink file [1] if $(top_srcdir) is a submodule checkout or a linked worktree [2]. [1] A gitlink is a text file that specifies the real location of the gitdir. [2] Linked worktrees are a new feature in Git 2.5. Cc: 10.6, 10.5 mesa-sta...@lists.freedesktop.org --- src/mesa/Makefile.am | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/Makefile.am b/src/mesa/Makefile.am index c86ded9..eb4a3da 100644 --- a/src/mesa/Makefile.am +++ b/src/mesa/Makefile.am @@ -38,8 +38,11 @@ gl_HEADERS = $(top_srcdir)/include/GL/*.h .PHONY: main/git_sha1.h.tmp main/git_sha1.h.tmp: + @# Don't assume that $(top_srcdir)/.git is a directory. It may be + @# a gitlink file if $(top_srcdir) is a submodule checkout or a linked + @# worktree. @touch main/git_sha1.h.tmp - @if test -d $(top_srcdir)/.git; then \ + @if test -e $(top_srcdir)/.git; then \ if which git /dev/null; then \ git --git-dir=$(top_srcdir)/.git log -n 1 --oneline | \ sed 's/^\([^ ]*\) .*/#define MESA_GIT_SHA1 git-\1/' \ -- 2.5.0.rc1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 91290] SIGSEGV glcpp/glcpp-parse.y:1077
https://bugs.freedesktop.org/show_bug.cgi?id=91290 Bug ID: 91290 Summary: SIGSEGV glcpp/glcpp-parse.y:1077 Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: All Status: NEW Keywords: have-backtrace Severity: normal Priority: medium Component: Mesa core Assignee: mesa-dev@lists.freedesktop.org Reporter: v...@freedesktop.org QA Contact: mesa-dev@lists.freedesktop.org mesa: f12302b89836a24255674a251f7a6902b4e9af7c (master 10.7.0-devel) This minimum shader triggers a null pointer dereference in the GLSL compiler. frag #define A 1 /* comment */ #define A 1 /* comment */ /frag (gdb) bt #0 _token_list_equal_ignoring_space (b=optimized out, a=optimized out) at glcpp/glcpp-parse.y:1077 #1 _macro_equal (a=0x20863a0, b=0x2086080) at glcpp/glcpp-parse.y:2112 #2 0x00498117 in _define_object_macro (parser=parser@entry=0x2082110, loc=loc@entry=0x7ffe7e7b0414, identifier=0x2086150 A, replacements=0x2086240) at glcpp/glcpp-parse.y:2141 #3 0x0049b966 in glcpp_parser_parse (parser=parser@entry=0x2082110) at glcpp/glcpp-parse.y:254 #4 0x004637f2 in glcpp_preprocess (ralloc_ctx=0x2081790, shader=0x7ffe7e7b14b0, info_log=0x20819b0, extensions=optimized out, gl_ctx=optimized out) at glcpp/pp.c:226 #5 0x00428ef4 in _mesa_glsl_compile_shader (ctx=0x7ffe7e7b1540, shader=0x2080b70, dump_ast=optimized out, dump_hir=optimized out) at glsl_parser_extras.cpp:1504 #6 0x00406345 in compile_shader (ctx=0x7ffe7e7b1540, shader=0x2080b70) at main.cpp:293 #7 0x0040437f in main (argc=2, argv=0x7ffe7e7d4528) at main.cpp:392 (gdb) frame 0 #0 _token_list_equal_ignoring_space (b=optimized out, a=optimized out) at glcpp/glcpp-parse.y:1077 1077while (node_a-token-type == SPACE) (gdb) print node_a $2 = (token_node_t *) 0x0 -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 07/19] glsl/types: add new subroutine type (v3)
7-12 inclusive are
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Thu, Jul 9, 2015 at 7:17 PM, Dave Airlie airl...@gmail.com wrote:
From: Dave Airlie airl...@redhat.com
This type will be used to store the name of subroutine types
as in subroutine void myfunc(void);
will store myfunc into a subroutine type.
This is required to the parser can identify a subroutine
type in a uniform decleration as a valid type, and also for
looking up the type later.
Also add contains_subroutine method.
v2: handle subroutine to int comparisons, needed
for lowering pass.
v3: do subroutine to int with it's own IR
operation to avoid hacking on asserts (Kayden)
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/glsl_types.cpp| 63
++
src/glsl/glsl_types.h | 19 ++
src/glsl/ir.cpp| 2 ++
src/glsl/ir.h | 1 +
src/glsl/ir_builder.cpp| 6
src/glsl/ir_builder.h | 1 +
src/glsl/ir_clone.cpp | 1 +
src/glsl/ir_validate.cpp | 4 +++
src/glsl/link_uniform_initializers.cpp | 1 +
9 files changed, 98 insertions(+)
diff --git a/src/glsl/glsl_types.cpp b/src/glsl/glsl_types.cpp
index 281ff51..1e3ebb2 100644
--- a/src/glsl/glsl_types.cpp
+++ b/src/glsl/glsl_types.cpp
@@ -32,6 +32,7 @@ mtx_t glsl_type::mutex = _MTX_INITIALIZER_NP;
hash_table *glsl_type::array_types = NULL;
hash_table *glsl_type::record_types = NULL;
hash_table *glsl_type::interface_types = NULL;
+hash_table *glsl_type::subroutine_types = NULL;
void *glsl_type::mem_ctx = NULL;
void
@@ -159,6 +160,22 @@ glsl_type::glsl_type(const glsl_struct_field *fields,
unsigned num_fields,
mtx_unlock(glsl_type::mutex);
}
+glsl_type::glsl_type(const char *subroutine_name) :
+ gl_type(0),
+ base_type(GLSL_TYPE_SUBROUTINE),
+ sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
+ sampler_type(0), interface_packing(0),
+ vector_elements(0), matrix_columns(0),
+ length(0)
+{
+ mtx_lock(glsl_type::mutex);
+
+ init_ralloc_type_ctx();
+ assert(subroutine_name != NULL);
+ this-name = ralloc_strdup(this-mem_ctx, subroutine_name);
+ this-vector_elements = 1;
+ mtx_unlock(glsl_type::mutex);
+}
bool
glsl_type::contains_sampler() const
@@ -229,6 +246,22 @@ glsl_type::contains_opaque() const {
}
}
+bool
+glsl_type::contains_subroutine() const
+{
+ if (this-is_array()) {
+ return this-fields.array-contains_subroutine();
+ } else if (this-is_record()) {
+ for (unsigned int i = 0; i this-length; i++) {
+if (this-fields.structure[i].type-contains_subroutine())
+ return true;
+ }
+ return false;
+ } else {
+ return this-is_subroutine();
+ }
+}
+
gl_texture_index
glsl_type::sampler_index() const
{
@@ -826,6 +859,34 @@ glsl_type::get_interface_instance(const
glsl_struct_field *fields,
return t;
}
+const glsl_type *
+glsl_type::get_subroutine_instance(const char *subroutine_name)
+{
+ const glsl_type key(subroutine_name);
+
+ mtx_lock(glsl_type::mutex);
+
+ if (subroutine_types == NULL) {
+ subroutine_types = hash_table_ctor(64, record_key_hash,
record_key_compare);
+ }
+
+ const glsl_type *t = (glsl_type *) hash_table_find(subroutine_types,
key);
+ if (t == NULL) {
+ mtx_unlock(glsl_type::mutex);
+ t = new glsl_type(subroutine_name);
+ mtx_lock(glsl_type::mutex);
+
+ hash_table_insert(subroutine_types, (void *) t, t);
+ }
+
+ assert(t-base_type == GLSL_TYPE_SUBROUTINE);
+ assert(strcmp(t-name, subroutine_name) == 0);
+
+ mtx_unlock(glsl_type::mutex);
+
+ return t;
+}
+
const glsl_type *
glsl_type::get_mul_type(const glsl_type *type_a, const glsl_type *type_b)
@@ -958,6 +1019,7 @@ glsl_type::component_slots() const
case GLSL_TYPE_SAMPLER:
case GLSL_TYPE_ATOMIC_UINT:
case GLSL_TYPE_VOID:
+ case GLSL_TYPE_SUBROUTINE:
case GLSL_TYPE_ERROR:
break;
}
@@ -1331,6 +1393,7 @@ glsl_type::count_attribute_slots() const
case GLSL_TYPE_IMAGE:
case GLSL_TYPE_ATOMIC_UINT:
case GLSL_TYPE_VOID:
+ case GLSL_TYPE_SUBROUTINE:
case GLSL_TYPE_ERROR:
break;
}
diff --git a/src/glsl/glsl_types.h b/src/glsl/glsl_types.h
index f54a939..0f4dc80 100644
--- a/src/glsl/glsl_types.h
+++ b/src/glsl/glsl_types.h
@@ -59,6 +59,7 @@ enum glsl_base_type {
GLSL_TYPE_INTERFACE,
GLSL_TYPE_ARRAY,
GLSL_TYPE_VOID,
+ GLSL_TYPE_SUBROUTINE,
GLSL_TYPE_ERROR
};
@@ -264,6 +265,11 @@ struct glsl_type {
const char *block_name);
/**
+* Get the instance of an subroutine type
+*/
+ static const glsl_type *get_subroutine_instance(const char
*subroutine_name);
+
+ /**
* Get the type resulting
Re: [Mesa-dev] [PATCH 1/4] radeon, r200: remove unused variable texmicrotile
Ohhh ripping out some more of my _very_ old code, how dare you :-).
Too bad some parts (fast z clear for instance) never made it past UMS
for these chips, quake3 never was as fast again ;-). I wonder how well
things actually work these days with enabled hyperz, it has some, let's
say, limitations...
Reviewed-by: Roland Scheidegger srol...@vmware.com
Am 09.07.2015 um 22:13 schrieb Emil Velikov:
Dead since at least 2009 with commit ccf7814a315(radeon: major cleanups
removing old dead codepaths.)
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/mesa/drivers/dri/r200/r200_context.c | 3 ---
src/mesa/drivers/dri/r200/r200_context.h | 1 -
src/mesa/drivers/dri/radeon/radeon_context.c | 3 ---
src/mesa/drivers/dri/radeon/radeon_context.h | 1 -
4 files changed, 8 deletions(-)
diff --git a/src/mesa/drivers/dri/r200/r200_context.c
b/src/mesa/drivers/dri/r200/r200_context.c
index fb15082..40cc50a 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -234,9 +234,6 @@ GLboolean r200CreateContext( gl_api api,
rmesa-using_hyperz = GL_TRUE;
}
- if ( sPriv-drm_version.minor = 15 )
- rmesa-texmicrotile = GL_TRUE;
-
/* Init default driver functions then plug in our R200-specific functions
* (the texture functions are especially important)
*/
diff --git a/src/mesa/drivers/dri/r200/r200_context.h
b/src/mesa/drivers/dri/r200/r200_context.h
index eb498f7..2ca1c7a 100644
--- a/src/mesa/drivers/dri/r200/r200_context.h
+++ b/src/mesa/drivers/dri/r200/r200_context.h
@@ -618,7 +618,6 @@ struct r200_context {
struct r200_swtcl_info swtcl;
GLboolean using_hyperz;
- GLboolean texmicrotile;
struct ati_fragment_shader *afs_loaded;
};
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c
b/src/mesa/drivers/dri/radeon/radeon_context.c
index d4d1935..edb154c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -199,9 +199,6 @@ r100CreateContext( gl_api api,
rmesa-using_hyperz = GL_TRUE;
}
- if ( sPriv-drm_version.minor = 15 )
- rmesa-texmicrotile = GL_TRUE;
-
/* Init default driver functions then plug in our Radeon-specific
functions
* (the texture functions are especially important)
*/
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h
b/src/mesa/drivers/dri/radeon/radeon_context.h
index 4032532..badabd9 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_context.h
@@ -426,7 +426,6 @@ struct r100_context {
struct r100_swtcl_info swtcl;
GLboolean using_hyperz;
- GLboolean texmicrotile;
/* Performance counters
*/
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Re: [Mesa-dev] [PATCH 09/11] android: dri: correctly set HAVE_LIBDRM
Emil Velikov 於 西元2015年07月09日 01:07 寫道: Set the macro if we're not building swrast alone. Cc: Chih-Wei Huang cwhu...@linux.org.tw Cc: Eric Anholt e...@anholt.net Signed-off-by: Emil Velikov emil.l.veli...@gmail.com --- src/gallium/targets/dri/Android.mk | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/gallium/targets/dri/Android.mk b/src/gallium/targets/dri/Android.mk index 5ba129b..bccc91a 100644 --- a/src/gallium/targets/dri/Android.mk +++ b/src/gallium/targets/dri/Android.mk @@ -35,17 +35,15 @@ endif LOCAL_SRC_FILES := target.c -LOCAL_CFLAGS := -DDRI_TARGET -DHAVE_LIBDRM +LOCAL_CFLAGS := -DDRI_TARGET LOCAL_SHARED_LIBRARIES := \ libdl \ libglapi \ libexpat \ -# swrast only? -ifeq ($(MESA_GPU_DRIVERS),swrast) -LOCAL_CFLAGS += -D__NOT_HAVE_DRM_H -else +ifneq ($(filter-out swrast,$(MESA_GPU_DRIVERS)),) +LOCAL_CFLAGS += -DHAVE_LIBDRM LOCAL_SHARED_LIBRARIES += libdrm endif Looks good to me. Reviewed-by: Chih-Wei Huang cwhu...@linux.org.tw ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/4] radeon, r200: allow hyperz for radeon DRM module v2
On 10.07.2015 05:13, Emil Velikov wrote:
The original code only half considered hyperz as an option. As per
previous commit major != 2 cannot occur we can simply things, and
allow users to set the option if they choose to do so.
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/mesa/drivers/dri/r200/r200_context.c | 10 ++
src/mesa/drivers/dri/radeon/radeon_context.c | 9 ++---
2 files changed, 4 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/r200/r200_context.c
b/src/mesa/drivers/dri/r200/r200_context.c
index 40cc50a..2a42ab3 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -225,14 +225,8 @@ GLboolean r200CreateContext( gl_api api,
rmesa-radeon.initialMaxAnisotropy =
driQueryOptionf(rmesa-radeon.optionCache,
def_max_anisotropy);
- if ( sPriv-drm_version.major == 1
-driQueryOptionb( rmesa-radeon.optionCache, hyperz ) ) {
- if ( sPriv-drm_version.minor 13 )
- fprintf( stderr, DRM version 1.%d too old to support HyperZ,
- disabling.\n, sPriv-drm_version.minor );
- else
- rmesa-using_hyperz = GL_TRUE;
- }
This code only set rmesa-using_hyperz = GL_TRUE if
sPriv-drm_version.major == 1. It was disabled for KMS in commit
e541845959761e9f47d14ade6b58a32db04ef7e4 (r200: Fix piglit paths test.).
+ if (driQueryOptionb( rmesa-radeon.optionCache, hyperz))
+ rmesa-using_hyperz = GL_TRUE;
This enables it again for KMS. Maybe that's okay though, especially if
the driconf option is disabled by default.
The rest of the series is
Reviewed-by: Michel Dänzer michel.daen...@amd.com
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
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Re: [Mesa-dev] [PATCH 2/2] i965: Optimize intel_batchbuffer_emit_dword().
On Wed, Jul 08, 2015 at 05:08:11PM -0700, Matt Turner wrote:
On Wed, Jul 8, 2015 at 4:53 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
static void upload_viewport_state_pointers(struct brw_context *brw)
{
BEGIN_BATCH(4);
brw-batch.map[0] = (_3DSTATE_VIEWPORT_STATE_POINTERS 16 | (4 - 2) |
GEN6_CC_VIEWPORT_MODIFY |
GEN6_SF_VIEWPORT_MODIFY |
GEN6_CLIP_VIEWPORT_MODIFY);
brw-batch.map[1] = (brw-clip.vp_offset);
brw-batch.map[2] = (brw-sf.vp_offset);
brw-batch.map[3] = (brw-cc.vp_offset);
brw-batch.map += 4;
ADVANCE_BATCH();
}
-Chris
Ah, thanks. I see.
I'll give it another shot.
Playing a bit more, I get reasonable code generation using
uint32_t *out = BEGIN_BATCH(4);
*out++ = (_3DSTATE_VIEWPORT_STATE_POINTERS 16 | (4 - 2) |
GEN6_CC_VIEWPORT_MODIFY |
GEN6_SF_VIEWPORT_MODIFY |
GEN6_CLIP_VIEWPORT_MODIFY);
*out++ = (brw-clip.vp_offset);
*out++ = (brw-sf.vp_offset);
*out++ = (brw-cc.vp_offset);
ADVANCE_BATCH(out);
with BEGIN_BATCH(n) {
uint32_t *ptr = brw-batch.map;
brw-batch.map + =n;
return ptr;
}
That also gives a simple ADVANCE_BATCH(out) assert(out == brw-batch.map),
and works with a little fudging (out - brw-batch.base) for OUT_RELOC.
-Chris
--
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[Mesa-dev] [PATCH 0/2] egl, i965: Support importing R8 and GR88 dma_bufs as textures
Teach EGL_EXT_image_dma_buf_import about DRM_FORMAT_R8 and DRM_FORMAT_GR88 in egl_dri2.c. Then add the plumbing to i965 to import R8 and GR88 dma_bufs as textures. This Mesa series shouldn't land until my kernel patch lands: To: dri-de...@freedesktop.org Subject: [PATCH] drm/fourcc: Add formats R8, RG88, GR88 Date: Wed, 8 Jul 2015 10:19:34 -0700 The Mesa patches build and run correctly, though, without the kernel patch because all the kernel patch does is define the new formats in drm_fourcc.h. I've duplicated the format definitions in egl_dri2.c so that building Mesa won't require unreleased kernel headers. This patch series lives on the tag: git://github.com/chadversary/mesa refs/tags/i965-drm-fourcc-r8-gr88-v01 I also sent patches for a Piglit test, which passes on Broadwell: Subject: [PATCH] ext_image_dma_buf: Add tests for R8 and GR88 Date: Mon, 22 Jun 2015 06:40:14 -0700 Chad Versace (2): egl: Add support for DRM_FORMAT_R8, RG88, and GR88 i965: Support importing R8 and GR88 dma_bufs include/GL/internal/dri_interface.h | 9 +++-- src/egl/drivers/dri2/egl_dri2.c | 19 +++ src/mesa/drivers/dri/i965/intel_screen.c | 6 ++ 3 files changed, 32 insertions(+), 2 deletions(-) -- 2.5.0.rc1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] egl: Add support for DRM_FORMAT_R8, RG88, and GR88
The Kodi/XBMC developers want to transcode NV12 to RGB with OpenGL shaders,
importing the two source planes through EGL_EXT_image_dma_buf_import. That
requires importing the Y plane as an R8 EGLImage and the UV plane as either an
RG88 or GR88 EGLImage.
This patch teaches the driver-independent part of EGL about the new
formats. Real driver support is left for follow-up patches.
CC: Peter Frühberger peter.fruehber...@gmail.com
Cc: Rainer Hochecker rainer.hochec...@onlinehome.de
Signed-off-by: Chad Versace chad.vers...@intel.com
---
src/egl/drivers/dri2/egl_dri2.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 65194cb..9813dd5 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -53,6 +53,22 @@
#include egl_dri2.h
#include ../util/u_atomic.h
+/* The kernel header drm_fourcc.h defines the DRM formats below. We duplicate
+ * some of the definitions here so that building Mesa won't bleeding-edge
+ * kernel headers.
+ */
+#ifndef DRM_FORMAT_R8
+#define DRM_FORMAT_R8fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
+#endif
+
+#ifndef DRM_FORMAT_RG88
+#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G
8:8 little endian */
+#endif
+
+#ifndef DRM_FORMAT_GR88
+#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R
8:8 little endian */
+#endif
+
const __DRIuseInvalidateExtension use_invalidate = {
.base = { __DRI_USE_INVALIDATE, 1 }
};
@@ -1679,6 +1695,9 @@ dri2_check_dma_buf_format(const _EGLImageAttribs *attrs)
unsigned i, plane_n;
switch (attrs-DMABufFourCC.Value) {
+ case DRM_FORMAT_R8:
+ case DRM_FORMAT_RG88:
+ case DRM_FORMAT_GR88:
case DRM_FORMAT_RGB332:
case DRM_FORMAT_BGR233:
case DRM_FORMAT_XRGB:
--
2.5.0.rc1
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[Mesa-dev] [PATCH 2/2] i965: Support importing R8 and GR88 dma_bufs
EGL_EXT_image_dma_buf_import now supports those formats.
CC: Peter Frühberger peter.fruehber...@gmail.com
Cc: Rainer Hochecker rainer.hochec...@onlinehome.de
Signed-off-by: Chad Versace chad.vers...@intel.com
---
include/GL/internal/dri_interface.h | 9 +++--
src/mesa/drivers/dri/i965/intel_screen.c | 6 ++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/include/GL/internal/dri_interface.h
b/include/GL/internal/dri_interface.h
index c827bb6..97b6972 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -1101,12 +1101,15 @@ struct __DRIdri2ExtensionRec {
/**
- * Four CC formats that matches with WL_DRM_FORMAT_* from wayland_drm.h
- * and GBM_FORMAT_* from gbm.h, used with createImageFromNames.
+ * Four CC formats that matches with WL_DRM_FORMAT_* from wayland_drm.h,
+ * GBM_FORMAT_* from gbm.h, and DRM_FORMAT_* from drm_fourcc.h. Used with
+ * createImageFromNames.
*
* \since 5
*/
+#define __DRI_IMAGE_FOURCC_R8 0x20203852
+#define __DRI_IMAGE_FOURCC_GR880x38385247
#define __DRI_IMAGE_FOURCC_RGB565 0x36314752
#define __DRI_IMAGE_FOURCC_ARGB0x34325241
#define __DRI_IMAGE_FOURCC_XRGB0x34325258
@@ -1141,6 +1144,8 @@ struct __DRIdri2ExtensionRec {
#define __DRI_IMAGE_COMPONENTS_Y_U_V 0x3003
#define __DRI_IMAGE_COMPONENTS_Y_UV0x3004
#define __DRI_IMAGE_COMPONENTS_Y_XUXV 0x3005
+#define __DRI_IMAGE_COMPONENTS_R 0x3006
+#define __DRI_IMAGE_COMPONENTS_RG 0x3007
/**
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index c0f5c92..c4e7193 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -229,6 +229,12 @@ static struct intel_image_format intel_image_formats[] = {
{ __DRI_IMAGE_FOURCC_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } },
+ { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } },
+
+ { __DRI_IMAGE_FOURCC_GR88, __DRI_IMAGE_COMPONENTS_RG, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } },
+
{ __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },
--
2.5.0.rc1
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[Mesa-dev] [Bug 90903] egl_dri2.c:dri2_load fails to load libglapi on osx
https://bugs.freedesktop.org/show_bug.cgi?id=90903 Emil Velikov emil.l.veli...@gmail.com changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #2 from Emil Velikov emil.l.veli...@gmail.com --- Pushed to master. Thanks ! -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 90249] Fails to build egl_dri2 on osx
https://bugs.freedesktop.org/show_bug.cgi?id=90249 Emil Velikov emil.l.veli...@gmail.com changed: What|Removed |Added Status|NEW |RESOLVED URL||https://www.khronos.org/bug ||zilla/show_bug.cgi?id=1356 Resolution|--- |FIXED --- Comment #3 from Emil Velikov emil.l.veli...@gmail.com --- As requested on the ML an upstream bug is opened with Khronos. Please keep us posted on the progress. Meanwhile I've pushed this to master. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glsl: fix Bug 85252 - Segfault in compiler while processing ternary operator with void arguments
On 07/07/15 21:47, Renaud Gaubert wrote:
This is done by returning an rvalue of type void in the
ast_function_expression::hir function instead of a void expression.
This produces (in the case of the ternary) an hir with a call
to the void returning function and an assignement of a void variable
which will be optimized out (the assignement) during the optimization
pass.
This fix results in having a valid subexpression in the many
different cases where the subexpressions are functions whose
return values are void.
Thus preventing to dereference NULL in the following cases:
* binary operator
* unary operators
* ternary operator
* comparison operators (except equal and nequal operator)
Equal and nequal had to be handled as a special case because
instead of segfaulting on a forbidden syntax it was now accepting
expressions with a void return value on either (or both) side of
the expression.
Piglist tests are on the way
Signed-off-by: Renaud Gaubert ren...@lse.epita.fr
Reviewed-by: Gabriel Laskar gabr...@lse.epita.fr
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85252
---
src/glsl/ast_function.cpp | 6 +-
src/glsl/ast_to_hir.cpp | 10 +-
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/glsl/ast_function.cpp b/src/glsl/ast_function.cpp
index 92e26bf..776a754 100644
--- a/src/glsl/ast_function.cpp
+++ b/src/glsl/ast_function.cpp
@@ -1785,7 +1785,11 @@ ast_function_expression::hir(exec_list *instructions,
/* an error has already been emitted */
value = ir_rvalue::error_value(ctx);
} else {
- value = generate_call(instructions, sig, actual_parameters, state);
+value = generate_call(instructions, sig, actual_parameters, state);
+if (!value) {
+ ir_variable *const tmp = new(ctx)
ir_variable(glsl_type::void_type, void_var, ir_var_temporary);
You forgot to add the ir_variable to the IR. Something like:
instructions-push_tail(tmp);
should be enough.
Sam
+ value = new(ctx) ir_dereference_variable(tmp);
+}
}
return value;
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 8cb46be..00cc16c 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -1270,7 +1270,15 @@ ast_expression::do_hir(exec_list *instructions,
*applied to one operand that can make them match, in which
*case this conversion is done.
*/
- if ((!apply_implicit_conversion(op[0]-type, op[1], state)
+
+ if (op[0]-type == glsl_type::void_type || op[1]-type ==
glsl_type::void_type) {
+
+_mesa_glsl_error( loc, state, `%s': wrong operand types: no
operation
+ `%1$s' exists that takes a left-hand operand of type 'void' or a
+ right operand of type 'void', (this-oper == ast_equal) ? == :
!=);
+
+ error_emitted = true;
+ } else if ((!apply_implicit_conversion(op[0]-type, op[1], state)
!apply_implicit_conversion(op[1]-type, op[0], state))
|| (op[0]-type != op[1]-type)) {
_mesa_glsl_error( loc, state, operands of `%s' must have the same
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[Mesa-dev] [Bug 66346] shader_query.cpp:49: error: invalid conversion from 'void*' to 'GLuint'
https://bugs.freedesktop.org/show_bug.cgi?id=66346 Emil Velikov emil.l.veli...@gmail.com changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #17 from Emil Velikov emil.l.veli...@gmail.com --- A slightly different fix has landed as below. Perhaps one day we'll either get this upstreamed with Khronos or have our build apply/revert it on demand. Not a huge deal either way :-) #ifdef __APPLE__ +#ifdef BUILDING_MESA +/* Avoid uint - void* warnings */ +typedef unsigned long GLhandleARB; +#else typedef void *GLhandleARB; +#endif -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 79706] [TRACKER] Mesa regression tracker
https://bugs.freedesktop.org/show_bug.cgi?id=79706 Bug 79706 depends on bug 66346, which changed state. Bug 66346 Summary: shader_query.cpp:49: error: invalid conversion from 'void*' to 'GLuint' https://bugs.freedesktop.org/show_bug.cgi?id=66346 What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [RFC] r600 geometry streams (and ARB_gpu_shader5 support)
This applies on top of the two patches I've sent already, and enables the geometry streams, which is the final piece missing for ARB_gpu_shader5 on evergreen and cayman. (I'll do doc update patches later) Glenn wrote most of this, I just spent some time making it work and cleaning up the code. Though I suspect it could do with more cleaning. The main thing I don't really like is we try and emit all outputs into each ring so we waste a bit of space, however it does work, though the special casing to avoid POSITION going into any other streams kinda makes me wonder if anything else needs that special casing. Dave. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 4/6] r600g/sb: add support for multiple streams to SB backend
From: Glenn Kennard glenn.kenn...@gmail.com
This adds a peephole and removes an assert that isn't
actually valid with some of the stream emit instructions.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/r600/sb/sb_bc_finalize.cpp | 2 --
src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 18 +++---
2 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
b/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
index 8c2cd14..48d56ac 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
@@ -761,8 +761,6 @@ void bc_finalizer::finalize_cf(cf_node* c) {
mask |= (1 chan);
}
- assert(reg = 0 mask);
-
if (reg = 0)
update_ngpr(reg);
diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
index 4879c03..25b0f55 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
@@ -757,10 +757,22 @@ int bc_parser::prepare_ir() {
c-bc.end_of_program = eop;
} else if (flags CF_EMIT) {
- c-flags |= NF_DONT_KILL | NF_DONT_HOIST | NF_DONT_MOVE;
+ /* quick peephole */
+ cf_node *prev = static_castcf_node *(c-prev);
+ if (c-bc.op == CF_OP_CUT_VERTEX
+ prev prev-is_valid()
+ prev-bc.op == CF_OP_EMIT_VERTEX
+ c-bc.count == prev-bc.count) {
+ prev-bc.set_op(CF_OP_EMIT_CUT_VERTEX);
+ prev-bc.end_of_program = c-bc.end_of_program;
+ c-remove();
+ }
+ else {
+ c-flags |= NF_DONT_KILL | NF_DONT_HOIST |
NF_DONT_MOVE;
-
c-src.push_back(sh-get_special_value(SV_GEOMETRY_EMIT));
-
c-dst.push_back(sh-get_special_value(SV_GEOMETRY_EMIT));
+
c-src.push_back(sh-get_special_value(SV_GEOMETRY_EMIT));
+
c-dst.push_back(sh-get_special_value(SV_GEOMETRY_EMIT));
+ }
}
}
--
2.4.3
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[Mesa-dev] [PATCH 6/6] r600g: enable ARB_gpu_shader5 on evergreen and up
From: Dave Airlie airl...@redhat.com Signed-off-by: Dave Airlie airl...@redhat.com --- src/gallium/drivers/r600/r600_pipe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index 67caa69..0db1c1c 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -299,7 +299,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_GLSL_FEATURE_LEVEL: if (family = CHIP_CEDAR) - return 330; + return 400; /* pre-evergreen geom shaders need newer kernel */ if (rscreen-b.info.drm_minor = 37) return 330; -- 2.4.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/4] ilo: unref old fence
On Thu, Jul 9, 2015 at 8:46 AM, Rob Clark robdcl...@gmail.com wrote:
From: Rob Clark robcl...@freedesktop.org
Some, but not all, state trackers will explicitly unref (and set to
NULL) the previous *fence before calling pipe-flush(). So driver
should use fence_ref() which will unref the old fence if not NULL.
Looks good. Thanks.
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/drivers/ilo/ilo_context.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/ilo/ilo_context.c
b/src/gallium/drivers/ilo/ilo_context.c
index 3d5c7b6..b9a16aa 100644
--- a/src/gallium/drivers/ilo/ilo_context.c
+++ b/src/gallium/drivers/ilo/ilo_context.c
@@ -62,6 +62,8 @@ ilo_flush(struct pipe_context *pipe,
(flags PIPE_FLUSH_END_OF_FRAME) ? frame end : user request);
if (f) {
+ struct pipe_screen *screen = pipe-screen;
+ screen-fence_reference(screen, f, NULL);
*f = ilo_screen_fence_create(pipe-screen, ilo-cp-last_submitted_bo);
}
}
--
2.4.3
--
o...@lunarg.com
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[Mesa-dev] [PATCH 1/6] r600g: add support for streams to the assembler.
From: Glenn Kennard glenn.kenn...@gmail.com
This just adds support to the assembler dumper and allows
stream instructions to be generated. Also fix up the stream
debugging to add stream info.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/r600/eg_asm.c | 1 +
src/gallium/drivers/r600/r600_asm.c| 2 ++
src/gallium/drivers/r600/r600_asm.h| 1 +
src/gallium/drivers/r600/r600_shader.c | 6 --
src/gallium/drivers/r600/sb/sb_bc_dump.cpp | 3 +++
5 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/eg_asm.c
b/src/gallium/drivers/r600/eg_asm.c
index 42e8b0b..c32d317 100644
--- a/src/gallium/drivers/r600/eg_asm.c
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -115,6 +115,7 @@ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct
r600_bytecode_cf *cf)
S_SQ_CF_WORD1_BARRIER(1) |
S_SQ_CF_WORD1_COND(cf-cond) |
S_SQ_CF_WORD1_POP_COUNT(cf-pop_count) |
+ S_SQ_CF_WORD1_COUNT(cf-count) |
S_SQ_CF_WORD1_END_OF_PROGRAM(cf-end_of_program);
}
}
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 762cc7f..40639d0 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -2029,6 +2029,8 @@ void r600_bytecode_disasm(struct r600_bytecode *bc)
fprintf(stderr, CND:%X , cf-cond);
if (cf-pop_count)
fprintf(stderr, POP:%X ,
cf-pop_count);
+ if (cf-count (cfop-flags CF_EMIT))
+ fprintf(stderr, STREAM%d , cf-count);
fprintf(stderr, \n);
}
}
diff --git a/src/gallium/drivers/r600/r600_asm.h
b/src/gallium/drivers/r600/r600_asm.h
index e37d926..b282907 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -149,6 +149,7 @@ struct r600_bytecode_cf {
unsignedid;
unsignedcond;
unsignedpop_count;
+ unsignedcount;
unsignedcf_addr; /* control flow addr */
struct r600_bytecode_kcache kcache[4];
unsignedr6xx_uses_waterfall;
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 1a72bf6..dbff313 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -93,8 +93,10 @@ static void r600_dump_streamout(struct
pipe_stream_output_info *so)
for (i = 0; i so-num_outputs; i++) {
unsigned mask = ((1 so-output[i].num_components) - 1)
so-output[i].start_component;
- fprintf(stderr, %i: MEM_STREAM0_BUF%i[%i..%i] -
OUT[%i].%s%s%s%s%s\n,
- i, so-output[i].output_buffer,
+ fprintf(stderr, %i: MEM_STREAM%d_BUF%i[%i..%i] -
OUT[%i].%s%s%s%s%s\n,
+ i,
+ so-output[i].stream,
+ so-output[i].output_buffer,
so-output[i].dst_offset, so-output[i].dst_offset +
so-output[i].num_components - 1,
so-output[i].register_index,
mask 1 ? x : ,
diff --git a/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
b/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
index 5232782..631fac2 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
@@ -182,6 +182,9 @@ void bc_dump::dump(cf_node n) {
if (n.bc.pop_count)
s POP: n.bc.pop_count;
+
+ if (n.bc.count (n.bc.op_ptr-flags CF_EMIT))
+ s STREAM n.bc.count;
}
if (!n.bc.barrier)
--
2.4.3
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[Mesa-dev] [PATCH 2/6] radeon: add streamout status 1-3 queries.
From: Glenn Kennard glenn.kenn...@gmail.com
This adds support for queries against the non-0 vertex streams.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/radeon/r600_query.c | 18 --
src/gallium/drivers/radeon/r600d_common.h | 3 +++
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_query.c
b/src/gallium/drivers/radeon/r600_query.c
index 71f4a15..9ad2452 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -54,6 +54,8 @@ struct r600_query {
uint64_t end_result;
/* Fence for GPU_FINISHED. */
struct pipe_fence_handle *fence;
+ /* For transform feedback: which stream the query is for */
+ unsigned stream;
};
@@ -157,6 +159,17 @@ static void r600_update_occlusion_query_state(struct
r600_common_context *rctx,
}
}
+static unsigned event_type_for_stream(struct r600_query *query)
+{
+ switch (query-stream) {
+ default:
+ case 0: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS;
+ case 1: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS1; /* enum values
snarfed from SI kernel sid.h */
+ case 2: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS2;
+ case 3: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS3;
+ }
+}
+
static void r600_emit_query_begin(struct r600_common_context *ctx, struct
r600_query *query)
{
struct radeon_winsys_cs *cs = ctx-rings.gfx.cs;
@@ -191,7 +204,7 @@ static void r600_emit_query_begin(struct
r600_common_context *ctx, struct r600_q
case PIPE_QUERY_SO_STATISTICS:
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
- radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) |
EVENT_INDEX(3));
+ radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) |
EVENT_INDEX(3));
radeon_emit(cs, va);
radeon_emit(cs, (va 32UL) 0xFF);
break;
@@ -248,7 +261,7 @@ static void r600_emit_query_end(struct r600_common_context
*ctx, struct r600_que
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
va += query-buffer.results_end + query-result_size/2;
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
- radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) |
EVENT_INDEX(3));
+ radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) |
EVENT_INDEX(3));
radeon_emit(cs, va);
radeon_emit(cs, (va 32UL) 0xFF);
break;
@@ -369,6 +382,7 @@ static struct pipe_query *r600_create_query(struct
pipe_context *ctx, unsigned q
/* NumPrimitivesWritten, PrimitiveStorageNeeded. */
query-result_size = 32;
query-num_cs_dw = 6;
+ query-stream = index;
break;
case PIPE_QUERY_PIPELINE_STATISTICS:
/* 11 values on EG, 8 on R600. */
diff --git a/src/gallium/drivers/radeon/r600d_common.h
b/src/gallium/drivers/radeon/r600d_common.h
index 74c8d87..5a56a54 100644
--- a/src/gallium/drivers/radeon/r600d_common.h
+++ b/src/gallium/drivers/radeon/r600d_common.h
@@ -66,6 +66,9 @@
#define PKT3_SET_SH_REG0x76 /* SI and later */
#define PKT3_SET_UCONFIG_REG 0x79 /* CIK and later */
+#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS1 0x1 /* EG and later */
+#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS2 0x2 /* EG and later */
+#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS3 0x3 /* EG and later */
#define EVENT_TYPE_PS_PARTIAL_FLUSH0x10
#define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
#define EVENT_TYPE_ZPASS_DONE 0x15
--
2.4.3
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[Mesa-dev] [PATCH 5/6] r600g: add streamout support
From: Glenn Kennard glenn.kenn...@gmail.com
This adds the main chunk of the geometry shader multiple stream
support to the r600 driver.
Glenn wrote the original pass, and I took his code and hacked
it into a working state.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c | 29 ++--
src/gallium/drivers/r600/r600_pipe.c | 2 +-
src/gallium/drivers/r600/r600_shader.c | 200 ---
src/gallium/drivers/r600/r600_shader.h | 6 +-
src/gallium/drivers/r600/r600_state.c| 6 +-
src/gallium/drivers/r600/r600_state_common.c | 7 +
6 files changed, 180 insertions(+), 70 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 4ddbc0b..788bf54 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2988,8 +2988,12 @@ void evergreen_update_gs_state(struct pipe_context *ctx,
struct r600_pipe_shader
struct r600_command_buffer *cb = shader-command_buffer;
struct r600_shader *rshader = shader-shader;
struct r600_shader *cp_shader = shader-gs_copy_shader-shader;
- unsigned gsvs_itemsize =
- (cp_shader-ring_item_size *
rshader-gs_max_out_vertices) 2;
+ unsigned gsvs_itemsizes[4] = {
+ (cp_shader-ring_item_sizes[0] *
rshader-gs_max_out_vertices) 2,
+ (cp_shader-ring_item_sizes[1] *
rshader-gs_max_out_vertices) 2,
+ (cp_shader-ring_item_sizes[2] *
rshader-gs_max_out_vertices) 2,
+ (cp_shader-ring_item_sizes[3] *
rshader-gs_max_out_vertices) 2
+ };
r600_init_command_buffer(cb, 64);
@@ -3008,21 +3012,24 @@ void evergreen_update_gs_state(struct pipe_context
*ctx, struct r600_pipe_shader
S_028B90_ENABLE(rshader-gs_num_invocations
0));
}
r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
- r600_store_value(cb, cp_shader-ring_item_size 2);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
- r600_store_value(cb, 0);
+ r600_store_value(cb, cp_shader-ring_item_sizes[0] 2);
+ r600_store_value(cb, cp_shader-ring_item_sizes[1] 2);
+ r600_store_value(cb, cp_shader-ring_item_sizes[2] 2);
+ r600_store_value(cb, cp_shader-ring_item_sizes[3] 2);
r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
- (rshader-ring_item_size) 2);
+ (rshader-ring_item_sizes[0]) 2);
r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
- gsvs_itemsize);
+ gsvs_itemsizes[0] +
+ gsvs_itemsizes[1] +
+ gsvs_itemsizes[2] +
+ gsvs_itemsizes[3]);
r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
- r600_store_value(cb, gsvs_itemsize);
- r600_store_value(cb, gsvs_itemsize);
- r600_store_value(cb, gsvs_itemsize);
+ r600_store_value(cb, gsvs_itemsizes[0]);
+ r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1]);
+ r600_store_value(cb, gsvs_itemsizes[0] + gsvs_itemsizes[1] +
gsvs_itemsizes[2]);
/* FIXME calculate these values somehow ??? */
r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 143e98e..67caa69 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -352,7 +352,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
return 16384;
case PIPE_CAP_MAX_VERTEX_STREAMS:
- return 1;
+ return family = CHIP_CEDAR ? 4 : 1;
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
return 2047;
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index dbff313..ef19706 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -311,7 +311,9 @@ struct r600_shader_ctx {
int gs_out_ring_offset;
int gs_next_vertex;
struct r600_shader *gs_for_vs;
- int gs_export_gpr_treg;
+ int gs_export_gpr_tregs[4];
+ const struct pipe_stream_output_info*gs_stream_output_info;
+ unsignedenabled_stream_buffers_mask; /*
See r600_streamout.enabled_stream_buffers_mask */
};
struct r600_shader_tgsi_instruction {
@@ -319,7 +321,7 @@ struct r600_shader_tgsi_instruction {
[Mesa-dev] [PATCH 3/6] radeon: add support for streams to the common streamout code.
From: Glenn Kennard glenn.kenn...@gmail.com
This just adds to the common radeon streamout code, support
for multiple streams.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
src/gallium/drivers/radeon/r600_streamout.c | 23 +--
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index a471426..22d940e 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -327,6 +327,7 @@ struct r600_streamout {
/* External state which comes from the vertex shader,
* it must be set explicitly when binding a shader. */
unsigned*stride_in_dw;
+ unsignedenabled_stream_buffers_mask; /* stream0
buffers0-3 in 4 LSB */
/* The state of VGT_STRMOUT_(CONFIG|EN). */
struct r600_atomenable_atom;
diff --git a/src/gallium/drivers/radeon/r600_streamout.c
b/src/gallium/drivers/radeon/r600_streamout.c
index bc8bf97..a602dac 100644
--- a/src/gallium/drivers/radeon/r600_streamout.c
+++ b/src/gallium/drivers/radeon/r600_streamout.c
@@ -195,7 +195,11 @@ static void r600_emit_streamout_begin(struct
r600_common_context *rctx, struct r
r600_write_context_reg(cs, rctx-chip_class = EVERGREEN ?
R_028B98_VGT_STRMOUT_BUFFER_CONFIG :
R_028B20_VGT_STRMOUT_BUFFER_EN,
- rctx-streamout.enabled_mask);
+ (rctx-streamout.enabled_mask |
+ (rctx-streamout.enabled_mask 4) |
+ (rctx-streamout.enabled_mask 8) |
+ (rctx-streamout.enabled_mask 12))
+
rctx-streamout.enabled_stream_buffers_mask);
for (i = 0; i rctx-streamout.num_targets; i++) {
if (!t[i])
@@ -326,11 +330,18 @@ static bool r600_get_strmout_en(struct
r600_common_context *rctx)
static void r600_emit_streamout_enable(struct r600_common_context *rctx,
struct r600_atom *atom)
{
- r600_write_context_reg(rctx-rings.gfx.cs,
- rctx-chip_class = EVERGREEN ?
- R_028B94_VGT_STRMOUT_CONFIG :
- R_028AB0_VGT_STRMOUT_EN,
-
S_028B94_STREAMOUT_0_EN(r600_get_strmout_en(rctx)));
+ unsigned reg = R_028AB0_VGT_STRMOUT_EN;
+ unsigned val = S_028B94_STREAMOUT_0_EN(r600_get_strmout_en(rctx));
+ if (rctx-chip_class = EVERGREEN) {
+ reg = R_028B94_VGT_STRMOUT_CONFIG;
+ val |=
+ S_028B94_RAST_STREAM(0) |
+ S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) |
+ S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) |
+ S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx));
+ }
+
+ r600_write_context_reg(rctx-rings.gfx.cs, reg, val);
}
static void r600_set_streamout_enable(struct r600_common_context *rctx, bool
enable)
--
2.4.3
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Re: [Mesa-dev] [PATCH 16/78] i965/nir/vec4: Implement store_output intrinsic
On 06/30/2015 06:51 PM, Jason Ekstrand wrote:
On Fri, Jun 26, 2015 at 1:06 AM, Eduardo Lima Mitev el...@igalia.com wrote:
The index into the output_reg array where to store the destination register
is
fetched from the nir_outputs map built during nir_setup_outputs stage.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 8a2d335..55d4490 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -520,10 +520,23 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr)
}
case nir_intrinsic_store_output_indirect:
+ has_indirect = true;
/* fallthrough */
- case nir_intrinsic_store_output:
- /* @TODO: Not yet implemented */
+ case nir_intrinsic_store_output: {
+ int offset = instr-const_index[0];
+ int output = nir_outputs[offset];
+
+ src = get_nir_src(instr-src[0], nir_output_types[offset]);
+ dest = dst_reg(src);
+
+ dest.writemask = brw_writemask_for_size(instr-num_components);
+
+ if (has_indirect)
+ dest.reladdr = new(mem_ctx) src_reg(get_nir_src(instr-src[1]));
+
+ output_reg[output] = dest;
I'm very confused about the amount of indirection going on here. It
seems to me that we should be setting these outputs up in
setup_outputs() rather than storring off a map from ints to other ints
and setting it up here. I didn't make this comment on the patch for
setup_outputs() because I wanted to wait to see it used before I
commented on it.
I'm guessing you did it this way because the nir_assign_var_locations
is giving you bogus values. If so, then it might be better to just
assign variable locations in setup_outputs() rather than having a
remap table. The whole point of nir_lower_io is to make IO easy for
the back-end. If you need a re-map table, then it's no longer making
it easy and we need to think more about what's going on.
--Jason
That double indirection felt bad since the beginning, but it was needed
to store the original variable's location (var-data.location). Let me
explain:
We are (re)using the plumbering in vec4_visitor to setup URB, so the
only thing we need to do is to store the out register in output_reg
map at the correct location. And that location is given by the original
location in the shader (var-data.location).
So, in this case, nir_assign_var_locations pass, which constructs
var-data.driver_location, is not useful to us, except to give us
consecutive indexes to construct the other map we have, the type map,
which is needed to carry the correct type from the original variable to
the output register.
So, before knowing that I could modify nir_lower_io, my best shot at
transferring the original variable location was to create this
nir_outputs map. Now, what I have done is to put that value in
const_index[1] of the intrinsic instruction, which was previously
unused. What do you think?
That removes the offset to offset map, but we still need the type map.
About your comment on initializing the register during setup stage, I'm
a bit confused: the register that we need to store is not available
during setup stage, because we still don't have local registers allocated.
break;
+ }
case nir_intrinsic_load_vertex_id:
unreachable(should be lowered by lower_vertex_id());
--
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Re: [Mesa-dev] [PATCH] r600g: fix sampler/ubo indexing on cayman
On Thu, 09 Jul 2015 07:37:59 +0200, Dave Airlie airl...@gmail.com wrote:
From: Dave Airlie airl...@redhat.com
Cayman needs a different method to upload the CF IDX0/1
This fixes 31 piglits when ARB_gpu_shader5 is forced on
with cayman.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/r600/eg_asm.c | 17 +++--
src/gallium/drivers/r600/eg_sq.h | 11 +++
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/r600/eg_asm.c
b/src/gallium/drivers/r600/eg_asm.c
index d04921e..c32d317 100644
--- a/src/gallium/drivers/r600/eg_asm.c
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -161,6 +161,9 @@ int egcm_load_index_reg(struct r600_bytecode *bc,
unsigned id, bool inside_alu_c
alu.op = ALU_OP1_MOVA_INT;
alu.src[0].sel = bc-index_reg[id];
alu.src[0].chan = 0;
+ if (bc-chip_class == CAYMAN)
+ alu.dst.sel = id == 0 ? CM_V_SQ_MOVA_DST_CF_IDX0 :
CM_V_SQ_MOVA_DST_CF_IDX1;
+
alu.last = 1;
r = r600_bytecode_add_alu(bc, alu);
if (r)
@@ -168,12 +171,14 @@ int egcm_load_index_reg(struct r600_bytecode *bc,
unsigned id, bool inside_alu_c
bc-ar_loaded = 0; /* clobbered */
Could split ar_loaded into 3 bits for AR/IDX0/IDX1 for cayman, however I
think it would be better to teach SB to handle sampler/ubo indexing and
keep things simple here.
- memset(alu, 0, sizeof(alu));
- alu.op = id == 0 ? ALU_OP0_SET_CF_IDX0 : ALU_OP0_SET_CF_IDX1;
- alu.last = 1;
- r = r600_bytecode_add_alu(bc, alu);
- if (r)
- return r;
+ if (bc-chip_class == EVERGREEN) {
+ memset(alu, 0, sizeof(alu));
+ alu.op = id == 0 ? ALU_OP0_SET_CF_IDX0 : ALU_OP0_SET_CF_IDX1;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(bc, alu);
+ if (r)
+ return r;
+ }
/* Must split ALU group as index only applies to following group */
if (inside_alu_clause) {
diff --git a/src/gallium/drivers/r600/eg_sq.h
b/src/gallium/drivers/r600/eg_sq.h
index b534872..10caa07 100644
--- a/src/gallium/drivers/r600/eg_sq.h
+++ b/src/gallium/drivers/r600/eg_sq.h
@@ -521,4 +521,15 @@
#define V_SQ_REL_ABSOLUTE 0
#define V_SQ_REL_RELATIVE 1
+
+/* CAYMAN has special encoding for MOVA_INT destination */
+#define CM_V_SQ_MOVA_DST_AR_X 0
+#define CM_V_SQ_MOVA_DST_CF_PC 1
+#define CM_V_SQ_MOVA_DST_CF_IDX0 2
+#define CM_V_SQ_MOVA_DST_CF_IDX1 3
+#define CM_V_SQ_MOVA_DST_CF_CLAUSE_GLOBAL_7_0 4
+#define CM_V_SQ_MOVA_DST_CF_CLAUSE_GLOBAL_15_8 5
+#define CM_V_SQ_MOVA_DST_CF_CLAUSE_GLOBAL_23_16 6
+#define CM_V_SQ_MOVA_DST_CF_CLAUSE_GLOBAL_31_24 7
Can't think of any useful cases for the cayman specific ALU global
register. Drop these four?
+
#endif
Reviewed-by: Glenn Kennard glenn.kenn...@gmail.com
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[Mesa-dev] [PATCH] r600g: move sampler/ubo index registers before temp reg
From: Dave Airlie airl...@redhat.com
temp_reg needs to be last, as we increment things
away from it, otherwise on cayman some tests were overwriting
the index regs.
Fixes 2 piglit with ARB_gpu_shader5 forced on cayman.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/r600/r600_shader.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index af7622e..1a72bf6 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1931,15 +1931,14 @@ static int r600_shader_from_tgsi(struct r600_context
*rctx,
ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
ctx.bc-ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
+ ctx.bc-index_reg[0] = ctx.bc-ar_reg + 1;
+ ctx.bc-index_reg[1] = ctx.bc-ar_reg + 2;
+
if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
- ctx.gs_export_gpr_treg = ctx.bc-ar_reg + 1;
- ctx.temp_reg = ctx.bc-ar_reg + 2;
- ctx.bc-index_reg[0] = ctx.bc-ar_reg + 3;
- ctx.bc-index_reg[1] = ctx.bc-ar_reg + 4;
+ ctx.gs_export_gpr_treg = ctx.bc-ar_reg + 3;
+ ctx.temp_reg = ctx.bc-ar_reg + 4;
} else {
- ctx.temp_reg = ctx.bc-ar_reg + 1;
- ctx.bc-index_reg[0] = ctx.bc-ar_reg + 2;
- ctx.bc-index_reg[1] = ctx.bc-ar_reg + 3;
+ ctx.temp_reg = ctx.bc-ar_reg + 3;
}
shader-max_arrays = 0;
--
2.4.3
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[Mesa-dev] [PATCH 12/19] glsl/ir: add subroutine lowering pass (v2.1)
From: Dave Airlie airl...@redhat.com
This lowers the enhanced ir_call using the lookaside table
of subroutines into an if ladder. This initially was done
at the AST level but it caused some ordering issues so a separate
pass was required.
v2: clone return value derefs.
v2.1: update for subroutine-int convert.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/Makefile.sources | 1 +
src/glsl/glsl_parser_extras.cpp | 1 +
src/glsl/ir_optimization.h | 2 +
src/glsl/lower_subroutine.cpp | 109
4 files changed, 113 insertions(+)
create mode 100644 src/glsl/lower_subroutine.cpp
diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
index d784a81..3f113c8 100644
--- a/src/glsl/Makefile.sources
+++ b/src/glsl/Makefile.sources
@@ -154,6 +154,7 @@ LIBGLSL_FILES = \
lower_packed_varyings.cpp \
lower_named_interface_blocks.cpp \
lower_packing_builtins.cpp \
+ lower_subroutine.cpp \
lower_texture_projection.cpp \
lower_variable_index_to_cond_assign.cpp \
lower_vec_index_to_cond_assign.cpp \
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index ba869f9..a2de278 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -1558,6 +1558,7 @@ _mesa_glsl_compile_shader(struct gl_context *ctx, struct
gl_shader *shader,
struct gl_shader_compiler_options *options =
ctx-Const.ShaderCompilerOptions[shader-Stage];
+ lower_subroutine(shader-ir, state);
/* Do some optimization at compile time to reduce shader IR size
* and reduce later work if the same shader is linked multiple times
*/
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index e6939f3..fef5a83 100644
--- a/src/glsl/ir_optimization.h
+++ b/src/glsl/ir_optimization.h
@@ -135,6 +135,8 @@ void optimize_dead_builtin_variables(exec_list
*instructions,
bool lower_vertex_id(gl_shader *shader);
+bool lower_subroutine(exec_list *instructions, struct _mesa_glsl_parse_state
*state);
+
ir_rvalue *
compare_index_block(exec_list *instructions, ir_variable *index,
unsigned base, unsigned components, void *mem_ctx);
diff --git a/src/glsl/lower_subroutine.cpp b/src/glsl/lower_subroutine.cpp
new file mode 100644
index 000..e5635a2
--- /dev/null
+++ b/src/glsl/lower_subroutine.cpp
@@ -0,0 +1,109 @@
+/*
+ * Copyright ?? 2015 Red Hat
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+ * \file lower_subroutine.cpp
+ *
+ * lowers subroutines to an if ladder.
+ */
+
+#include glsl_types.h
+#include glsl_parser_extras.h
+#include ir.h
+#include ir_builder.h
+
+using namespace ir_builder;
+namespace {
+
+class lower_subroutine_visitor : public ir_hierarchical_visitor {
+public:
+ lower_subroutine_visitor()
+ {
+ this-progress = false;
+ }
+
+ ir_visitor_status visit_leave(ir_call *);
+ bool progress;
+ struct _mesa_glsl_parse_state *state;
+};
+
+}
+
+bool
+lower_subroutine(exec_list *instructions, struct _mesa_glsl_parse_state *state)
+{
+ lower_subroutine_visitor v;
+ v.state = state;
+ visit_list_elements(v, instructions);
+ return v.progress;
+}
+
+ir_visitor_status
+lower_subroutine_visitor::visit_leave(ir_call *ir)
+{
+ if (!ir-sub_var)
+ return visit_continue;
+
+ void *mem_ctx = ralloc_parent(ir);
+ ir_if *last_branch = NULL;
+ ir_dereference_variable *return_deref = ir-return_deref;
+
+ for (int s = this-state-num_subroutines - 1; s = 0; s--) {
+ ir_rvalue *var;
+ ir_constant *lc = new(mem_ctx)ir_constant(s);
+ ir_function *fn = this-state-subroutines[s];
+ bool is_compat = false;
+
+ for (int i = 0; i fn-num_subroutine_types; i++) {
+ if (ir-sub_var-type-without_array() == fn-subroutine_types[i]) {
+is_compat = true;
+break;
+
[Mesa-dev] [PATCH 18/19] st/mesa: add subroutine bits (v1.1)
From: Dave Airlie airl...@redhat.com Just add support for the subroutine type to the glsl-tgsi convertor. v1.1: add subroutine to int support. Signed-off-by: Dave Airlie airl...@redhat.com --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index 25e30c7..a1dd70f 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -797,7 +797,7 @@ glsl_to_tgsi_visitor::get_opcode(ir_instruction *ir, unsigned op, case TGSI_OPCODE_##c: \ if (type == GLSL_TYPE_DOUBLE) \ op = TGSI_OPCODE_##d; \ - else if (type == GLSL_TYPE_INT) \ + else if (type == GLSL_TYPE_INT || type == GLSL_TYPE_SUBROUTINE) \ op = TGSI_OPCODE_##i; \ else if (type == GLSL_TYPE_UINT) \ op = TGSI_OPCODE_##u; \ @@ -1090,6 +1090,7 @@ type_size(const struct glsl_type *type) return size; case GLSL_TYPE_SAMPLER: case GLSL_TYPE_IMAGE: + case GLSL_TYPE_SUBROUTINE: /* Samplers take up one slot in UNIFORMS[], but they're baked in * at link time. */ @@ -1470,6 +1471,9 @@ glsl_to_tgsi_visitor::visit(ir_expression *ir) result_src = op[0]; } break; + case ir_unop_subroutine_to_int: + emit_asm(ir, TGSI_OPCODE_MOV, result_dst, op[0]); + break; case ir_unop_abs: emit_asm(ir, TGSI_OPCODE_ABS, result_dst, op[0]); break; -- 2.4.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 15/19] program_resource: add subroutine support
From: Dave Airlie airl...@redhat.com
This fleshes out the ARB_program_query support for the
APIs that ARB_shader_subroutine introduces, leaving
some TODOs for later addition.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/mesa/main/shader_query.cpp | 46 ++
1 file changed, 46 insertions(+)
diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp
index a6246a3..4fa5913 100644
--- a/src/mesa/main/shader_query.cpp
+++ b/src/mesa/main/shader_query.cpp
@@ -61,6 +61,7 @@ DECL_RESOURCE_FUNC(UBO, gl_uniform_block);
DECL_RESOURCE_FUNC(UNI, gl_uniform_storage);
DECL_RESOURCE_FUNC(ATC, gl_active_atomic_buffer);
DECL_RESOURCE_FUNC(XFB, gl_transform_feedback_varying_info);
+DECL_RESOURCE_FUNC(SUB, gl_subroutine_function);
void GLAPIENTRY
_mesa_BindAttribLocation(GLhandleARB program, GLuint index,
@@ -497,6 +498,24 @@ _mesa_program_resource_name(struct gl_program_resource
*res)
return RESOURCE_VAR(res)-name;
case GL_UNIFORM:
return RESOURCE_UNI(res)-name;
+ case GL_VERTEX_SUBROUTINE_UNIFORM:
+ case GL_GEOMETRY_SUBROUTINE_UNIFORM:
+ case GL_FRAGMENT_SUBROUTINE_UNIFORM:
+ /* TODO
+ case GL_COMPUTE_SUBROUTINE_UNIFORM:
+ case GL_TESS_CONTROL_SUBROUTINE_UNIFORM:
+ case GL_TESS_EVALUATION_SUBROUTINE_UNIFORM:
+ */
+ return RESOURCE_UNI(res)-name + 9;
+ case GL_VERTEX_SUBROUTINE:
+ case GL_GEOMETRY_SUBROUTINE:
+ case GL_FRAGMENT_SUBROUTINE:
+ /* TODO
+ case GL_COMPUTE_SUBROUTINE:
+ case GL_TESS_CONTROL_SUBROUTINE:
+ case GL_TESS_EVALUATION_SUBROUTINE:
+ */
+ return RESOURCE_SUB(res)-name;
default:
assert(!support for resource type not implemented);
}
@@ -515,6 +534,9 @@ _mesa_program_resource_array_size(struct
gl_program_resource *res)
case GL_PROGRAM_OUTPUT:
return RESOURCE_VAR(res)-data.max_array_access;
case GL_UNIFORM:
+ case GL_VERTEX_SUBROUTINE_UNIFORM:
+ case GL_GEOMETRY_SUBROUTINE_UNIFORM:
+ case GL_FRAGMENT_SUBROUTINE_UNIFORM:
return RESOURCE_UNI(res)-array_elements;
case GL_ATOMIC_COUNTER_BUFFER:
case GL_UNIFORM_BLOCK:
@@ -571,6 +593,12 @@ _mesa_program_resource_find_name(struct gl_shader_program
*shProg,
case GL_TRANSFORM_FEEDBACK_VARYING:
case GL_UNIFORM_BLOCK:
case GL_UNIFORM:
+ case GL_VERTEX_SUBROUTINE_UNIFORM:
+ case GL_GEOMETRY_SUBROUTINE_UNIFORM:
+ case GL_FRAGMENT_SUBROUTINE_UNIFORM:
+ case GL_VERTEX_SUBROUTINE:
+ case GL_GEOMETRY_SUBROUTINE:
+ case GL_FRAGMENT_SUBROUTINE:
if (strncmp(rname, name, baselen) == 0) {
/* Basename match, check if array or struct. */
if (name[baselen] == '\0' ||
@@ -651,6 +679,12 @@ _mesa_program_resource_find_index(struct gl_shader_program
*shProg,
case GL_PROGRAM_INPUT:
case GL_PROGRAM_OUTPUT:
case GL_UNIFORM:
+ case GL_VERTEX_SUBROUTINE_UNIFORM:
+ case GL_GEOMETRY_SUBROUTINE_UNIFORM:
+ case GL_FRAGMENT_SUBROUTINE_UNIFORM:
+ case GL_VERTEX_SUBROUTINE:
+ case GL_GEOMETRY_SUBROUTINE:
+ case GL_FRAGMENT_SUBROUTINE:
if (++idx == (int) index)
return res;
break;
@@ -740,6 +774,8 @@ program_resource_location(struct gl_shader_program *shProg,
{
unsigned index, offset;
int array_index = -1;
+ long offset_ret;
+ const GLchar *base_name_end;
if (res-Type == GL_PROGRAM_INPUT || res-Type == GL_PROGRAM_OUTPUT) {
array_index = array_index_of_resource(res, name);
@@ -780,6 +816,16 @@ program_resource_location(struct gl_shader_program *shProg,
/* location in remap table + array element offset */
return RESOURCE_UNI(res)-remap_location + offset;
+ case GL_VERTEX_SUBROUTINE_UNIFORM:
+ case GL_GEOMETRY_SUBROUTINE_UNIFORM:
+ case GL_FRAGMENT_SUBROUTINE_UNIFORM:
+ /* TODO
+ case GL_COMPUTE_SUBROUTINE_UNIFORM:
+ case GL_TESS_CONTROL_SUBROUTINE_UNIFORM:
+ case GL_TESS_EVALUATION_SUBROUTINE_UNIFORM:
+ */
+ offset_ret = parse_program_resource_name(name, base_name_end);
+ return
RESOURCE_UNI(res)-subroutine[_mesa_shader_stage_from_subroutine_uniform(res-Type)].index
+ ((offset_ret != -1) ? offset_ret : 0);
default:
return -1;
}
--
2.4.3
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[Mesa-dev] [PATCH 19/19] st/mesa: enable shader subroutine
From: Dave Airlie airl...@redhat.com I'm not sure if we shouldn't enable this everywhere and rip out the API checks, discuss, Signed-off-by: Dave Airlie airl...@redhat.com --- src/mesa/state_tracker/st_extensions.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/state_tracker/st_extensions.c b/src/mesa/state_tracker/st_extensions.c index b1057f3..3b828fa 100644 --- a/src/mesa/state_tracker/st_extensions.c +++ b/src/mesa/state_tracker/st_extensions.c @@ -598,6 +598,7 @@ void st_init_extensions(struct pipe_screen *screen, extensions-ARB_half_float_vertex = GL_TRUE; extensions-ARB_internalformat_query = GL_TRUE; extensions-ARB_map_buffer_range = GL_TRUE; + extensions-ARB_shader_subroutine = GL_TRUE; extensions-ARB_texture_border_clamp = GL_TRUE; /* XXX temp */ extensions-ARB_texture_cube_map = GL_TRUE; extensions-ARB_texture_env_combine = GL_TRUE; -- 2.4.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 17/19] mesa: fill out the ARB_shader_subroutine APIs
From: Dave Airlie airl...@redhat.com
This fleshes out the APIs, using the program resource
APIs where they should match.
It also sets the default values to valid subroutines.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/mesa/main/shaderapi.c | 457 +-
src/mesa/main/shaderapi.h | 3 +
2 files changed, 457 insertions(+), 3 deletions(-)
diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index 48ab217..1a46749 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -1071,6 +1071,7 @@ _mesa_use_program(struct gl_context *ctx, struct
gl_shader_program *shProg)
use_shader_program(ctx, i, shProg, ctx-Shader);
_mesa_active_program(ctx, shProg, glUseProgram);
+ _mesa_shader_program_init_subroutine_defaults(shProg);
if (ctx-Driver.UseProgram)
ctx-Driver.UseProgram(ctx, shProg);
}
@@ -1993,15 +1994,75 @@ GLint GLAPIENTRY
_mesa_GetSubroutineUniformLocation(GLuint program, GLenum shadertype,
const GLchar *name)
{
- return -1;
-}
+ GET_CURRENT_CONTEXT(ctx);
+ const char *api_name = glGetSubroutineUniformLocation;
+ struct gl_shader_program *shProg;
+ GLenum resource_type;
+ gl_shader_stage stage;
+
+ if (!ctx-Extensions.ARB_shader_subroutine) {
+ _mesa_error(ctx, GL_INVALID_OPERATION, api_name);
+ return -1;
+ }
+
+ if (!_mesa_validate_shader_target(ctx, shadertype)) {
+ _mesa_error(ctx, GL_INVALID_OPERATION, api_name);
+ return -1;
+ }
+ shProg = _mesa_lookup_shader_program_err(ctx, program, api_name);
+ if (!shProg)
+ return -1;
+
+ stage = _mesa_shader_enum_to_shader_stage(shadertype);
+ if (!shProg-_LinkedShaders[stage]) {
+ _mesa_error(ctx, GL_INVALID_OPERATION, api_name);
+ return -1;
+ }
+
+ resource_type = _mesa_shader_stage_to_subroutine_uniform(stage);
+ return _mesa_program_resource_location(shProg, resource_type, name);
+}
GLuint GLAPIENTRY
_mesa_GetSubroutineIndex(GLuint program, GLenum shadertype,
const GLchar *name)
{
- return GL_INVALID_INDEX;
+ GET_CURRENT_CONTEXT(ctx);
+ const char *api_name = glGetSubroutineIndex;
+ struct gl_shader_program *shProg;
+ struct gl_program_resource *res;
+ GLenum resource_type;
+ gl_shader_stage stage;
+
+ if (!ctx-Extensions.ARB_shader_subroutine) {
+ _mesa_error(ctx, GL_INVALID_OPERATION, api_name);
+ return -1;
+ }
+
+ if (!_mesa_validate_shader_target(ctx, shadertype)) {
+ _mesa_error(ctx, GL_INVALID_OPERATION, api_name);
+ return -1;
+ }
+
+ shProg = _mesa_lookup_shader_program_err(ctx, program, api_name);
+ if (!shProg)
+ return -1;
+
+ stage = _mesa_shader_enum_to_shader_stage(shadertype);
+ if (!shProg-_LinkedShaders[stage]) {
+ _mesa_error(ctx, GL_INVALID_OPERATION, api_name);
+ return -1;
+ }
+
+ resource_type = _mesa_shader_stage_to_subroutine(stage);
+ res = _mesa_program_resource_find_name(shProg, resource_type, name);
+ if (!res) {
+ _mesa_error(ctx, GL_INVALID_OPERATION, api_name);
+ return -1;
+ }
+
+ return _mesa_program_resource_index(shProg, res);
}
@@ -2009,6 +2070,91 @@ GLvoid GLAPIENTRY
_mesa_GetActiveSubroutineUniformiv(GLuint program, GLenum shadertype,
GLuint index, GLenum pname, GLint *values)
{
+ GET_CURRENT_CONTEXT(ctx);
+ const char *api_name = glGetActiveSubroutineUniformiv;
+ struct gl_shader_program *shProg;
+ struct gl_shader *sh;
+ gl_shader_stage stage;
+ struct gl_program_resource *res;
+ const struct gl_uniform_storage *uni;
+ GLenum resource_type;
+ int count, i, j;
+ if (!ctx-Extensions.ARB_shader_subroutine) {
+ _mesa_error(ctx, GL_INVALID_OPERATION, api_name);
+ return;
+ }
+
+ if (!_mesa_validate_shader_target(ctx, shadertype)) {
+ _mesa_error(ctx, GL_INVALID_OPERATION, api_name);
+ return;
+ }
+
+ shProg = _mesa_lookup_shader_program_err(ctx, program, api_name);
+ if (!shProg)
+ return;
+
+ stage = _mesa_shader_enum_to_shader_stage(shadertype);
+ resource_type = _mesa_shader_stage_to_subroutine_uniform(stage);
+
+ sh = shProg-_LinkedShaders[stage];
+ if (!sh) {
+ _mesa_error(ctx, GL_INVALID_OPERATION, api_name);
+ return;
+ }
+
+ switch (pname) {
+ case GL_NUM_COMPATIBLE_SUBROUTINES: {
+ res = _mesa_program_resource_find_index(shProg, resource_type, index);
+ if (res) {
+ uni = res-Data;
+ count = 0;
+ for (i = 0; i sh-NumSubroutineFunctions; i++) {
+struct gl_subroutine_function *fn = sh-SubroutineFunctions[i];
+for (j = 0; j fn-num_compat_types; j++) {
+ if (fn-types[j] == uni-type) {
+ count++;
+ break;
+ }
+}
+ }
+ values[0] = count;
+ }
+ break;
+ }
+ case GL_COMPATIBLE_SUBROUTINES: {
+ res =
[Mesa-dev] [PATCH 13/19] mesa/mtypes: add gl_subroutine_function and uniform storage to shader
From: Dave Airlie airl...@redhat.com
This adds the necessary storage for subroutine info to gl_shader.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/mesa/main/mtypes.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index a93fe94..c53bf2d 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2359,6 +2359,15 @@ struct gl_ati_fragment_shader_state
struct ati_fragment_shader *Current;
};
+/**
+ * Shader subroutine function definition
+ */
+struct gl_subroutine_function
+{
+ char *name;
+ int num_compat_types;
+ const struct glsl_type **types;
+};
/**
* A GLSL vertex or fragment shader object.
@@ -2509,6 +2518,12 @@ struct gl_shader
*/
unsigned LocalSize[3];
} Comp;
+
+ GLuint NumSubroutineUniformTypes;
+ GLuint NumSubroutineUniforms;
+ struct gl_uniform_storage **SubroutineUniformRemapTable;
+ GLuint NumSubroutineFunctions;
+ struct gl_subroutine_function *SubroutineFunctions;
};
--
2.4.3
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[Mesa-dev] [PATCH 14/19] glsl: add uniform and program resource support
From: Dave Airlie airl...@redhat.com
This adds linker support for subroutine uniforms, they
have some subtle differences from real uniforms, we also hide
them and they are given internal uniform names.
This also adds the subroutine locations and subroutine uniforms
to the program resource tracking for later use.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/ir_uniform.h | 2 +
src/glsl/link_uniforms.cpp | 56 +--
src/glsl/linker.cpp| 94 +-
3 files changed, 146 insertions(+), 6 deletions(-)
diff --git a/src/glsl/ir_uniform.h b/src/glsl/ir_uniform.h
index e1b8014..be1b38d 100644
--- a/src/glsl/ir_uniform.h
+++ b/src/glsl/ir_uniform.h
@@ -114,6 +114,8 @@ struct gl_uniform_storage {
struct gl_opaque_uniform_index image[MESA_SHADER_STAGES];
+ struct gl_opaque_uniform_index subroutine[MESA_SHADER_STAGES];
+
/**
* Storage used by the driver for the uniform
*/
diff --git a/src/glsl/link_uniforms.cpp b/src/glsl/link_uniforms.cpp
index 11ae06f..78a830a 100644
--- a/src/glsl/link_uniforms.cpp
+++ b/src/glsl/link_uniforms.cpp
@@ -47,9 +47,10 @@
static unsigned
values_for_type(const glsl_type *type)
{
- if (type-is_sampler()) {
+ if (type-is_sampler() || type-is_subroutine()) {
return 1;
- } else if (type-is_array() type-fields.array-is_sampler()) {
+ } else if (type-is_array() (type-fields.array-is_sampler() ||
+ type-fields.array-is_subroutine())) {
return type-array_size();
} else {
return type-component_slots();
@@ -284,6 +285,7 @@ public:
count_uniform_size(struct string_to_uint_map *map)
: num_active_uniforms(0), num_values(0), num_shader_samplers(0),
num_shader_images(0), num_shader_uniform_components(0),
+num_shader_subroutines(0),
is_ubo_var(false), map(map)
{
/* empty */
@@ -294,6 +296,7 @@ public:
this-num_shader_samplers = 0;
this-num_shader_images = 0;
this-num_shader_uniform_components = 0;
+ this-num_shader_subroutines = 0;
}
void process(ir_variable *var)
@@ -331,6 +334,11 @@ public:
*/
unsigned num_shader_uniform_components;
+ /**
+* Number of subroutine uniforms used
+*/
+ unsigned num_shader_subroutines;
+
bool is_ubo_var;
private:
@@ -348,7 +356,9 @@ private:
* count it for each shader target.
*/
const unsigned values = values_for_type(type);
- if (type-contains_sampler()) {
+ if (type-contains_subroutine()) {
+ this-num_shader_subroutines += values;
+ } else if (type-contains_sampler()) {
this-num_shader_samplers += values;
} else if (type-contains_image()) {
this-num_shader_images += values;
@@ -421,6 +431,7 @@ public:
this-shader_shadow_samplers = 0;
this-next_sampler = 0;
this-next_image = 0;
+ this-next_subroutine = 0;
memset(this-targets, 0, sizeof(this-targets));
}
@@ -535,6 +546,24 @@ private:
}
}
+ void handle_subroutines(const glsl_type *base_type,
+ struct gl_uniform_storage *uniform)
+ {
+ if (base_type-is_subroutine()) {
+ uniform-subroutine[shader_type].index = this-next_subroutine;
+ uniform-subroutine[shader_type].active = true;
+
+ /* Increment the subroutine index by 1 for non-arrays and by the
+ * number of array elements for arrays.
+ */
+ this-next_subroutine += MAX2(1, uniform-array_elements);
+
+ } else {
+ uniform-subroutine[shader_type].index = ~0;
+ uniform-subroutine[shader_type].active = false;
+ }
+ }
+
virtual void visit_field(const glsl_type *type, const char *name,
bool row_major)
{
@@ -588,6 +617,7 @@ private:
/* This assigns uniform indices to sampler and image uniforms. */
handle_samplers(base_type, this-uniforms[id]);
handle_images(base_type, this-uniforms[id]);
+ handle_subroutines(base_type, this-uniforms[id]);
/* If there is already storage associated with this uniform or if the
* uniform is set as builtin, it means that it was set while processing
@@ -672,6 +702,7 @@ private:
struct gl_uniform_storage *uniforms;
unsigned next_sampler;
unsigned next_image;
+ unsigned next_subroutine;
public:
union gl_constant_value *values;
@@ -952,8 +983,11 @@ link_assign_uniform_locations(struct gl_shader_program
*prog,
sh-num_samplers = uniform_size.num_shader_samplers;
sh-NumImages = uniform_size.num_shader_images;
sh-num_uniform_components = uniform_size.num_shader_uniform_components;
-
sh-num_combined_uniform_components = sh-num_uniform_components;
+ sh-NumSubroutineUniforms = uniform_size.num_shader_subroutines;
+
+ sh-SubroutineUniformRemapTable = ralloc_array(sh, struct
gl_uniform_storage *,
[Mesa-dev] [PATCH 07/19] glsl/types: add new subroutine type (v3)
From: Dave Airlie airl...@redhat.com
This type will be used to store the name of subroutine types
as in subroutine void myfunc(void);
will store myfunc into a subroutine type.
This is required to the parser can identify a subroutine
type in a uniform decleration as a valid type, and also for
looking up the type later.
Also add contains_subroutine method.
v2: handle subroutine to int comparisons, needed
for lowering pass.
v3: do subroutine to int with it's own IR
operation to avoid hacking on asserts (Kayden)
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/glsl_types.cpp| 63 ++
src/glsl/glsl_types.h | 19 ++
src/glsl/ir.cpp| 2 ++
src/glsl/ir.h | 1 +
src/glsl/ir_builder.cpp| 6
src/glsl/ir_builder.h | 1 +
src/glsl/ir_clone.cpp | 1 +
src/glsl/ir_validate.cpp | 4 +++
src/glsl/link_uniform_initializers.cpp | 1 +
9 files changed, 98 insertions(+)
diff --git a/src/glsl/glsl_types.cpp b/src/glsl/glsl_types.cpp
index 281ff51..1e3ebb2 100644
--- a/src/glsl/glsl_types.cpp
+++ b/src/glsl/glsl_types.cpp
@@ -32,6 +32,7 @@ mtx_t glsl_type::mutex = _MTX_INITIALIZER_NP;
hash_table *glsl_type::array_types = NULL;
hash_table *glsl_type::record_types = NULL;
hash_table *glsl_type::interface_types = NULL;
+hash_table *glsl_type::subroutine_types = NULL;
void *glsl_type::mem_ctx = NULL;
void
@@ -159,6 +160,22 @@ glsl_type::glsl_type(const glsl_struct_field *fields,
unsigned num_fields,
mtx_unlock(glsl_type::mutex);
}
+glsl_type::glsl_type(const char *subroutine_name) :
+ gl_type(0),
+ base_type(GLSL_TYPE_SUBROUTINE),
+ sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
+ sampler_type(0), interface_packing(0),
+ vector_elements(0), matrix_columns(0),
+ length(0)
+{
+ mtx_lock(glsl_type::mutex);
+
+ init_ralloc_type_ctx();
+ assert(subroutine_name != NULL);
+ this-name = ralloc_strdup(this-mem_ctx, subroutine_name);
+ this-vector_elements = 1;
+ mtx_unlock(glsl_type::mutex);
+}
bool
glsl_type::contains_sampler() const
@@ -229,6 +246,22 @@ glsl_type::contains_opaque() const {
}
}
+bool
+glsl_type::contains_subroutine() const
+{
+ if (this-is_array()) {
+ return this-fields.array-contains_subroutine();
+ } else if (this-is_record()) {
+ for (unsigned int i = 0; i this-length; i++) {
+if (this-fields.structure[i].type-contains_subroutine())
+ return true;
+ }
+ return false;
+ } else {
+ return this-is_subroutine();
+ }
+}
+
gl_texture_index
glsl_type::sampler_index() const
{
@@ -826,6 +859,34 @@ glsl_type::get_interface_instance(const glsl_struct_field
*fields,
return t;
}
+const glsl_type *
+glsl_type::get_subroutine_instance(const char *subroutine_name)
+{
+ const glsl_type key(subroutine_name);
+
+ mtx_lock(glsl_type::mutex);
+
+ if (subroutine_types == NULL) {
+ subroutine_types = hash_table_ctor(64, record_key_hash,
record_key_compare);
+ }
+
+ const glsl_type *t = (glsl_type *) hash_table_find(subroutine_types, key);
+ if (t == NULL) {
+ mtx_unlock(glsl_type::mutex);
+ t = new glsl_type(subroutine_name);
+ mtx_lock(glsl_type::mutex);
+
+ hash_table_insert(subroutine_types, (void *) t, t);
+ }
+
+ assert(t-base_type == GLSL_TYPE_SUBROUTINE);
+ assert(strcmp(t-name, subroutine_name) == 0);
+
+ mtx_unlock(glsl_type::mutex);
+
+ return t;
+}
+
const glsl_type *
glsl_type::get_mul_type(const glsl_type *type_a, const glsl_type *type_b)
@@ -958,6 +1019,7 @@ glsl_type::component_slots() const
case GLSL_TYPE_SAMPLER:
case GLSL_TYPE_ATOMIC_UINT:
case GLSL_TYPE_VOID:
+ case GLSL_TYPE_SUBROUTINE:
case GLSL_TYPE_ERROR:
break;
}
@@ -1331,6 +1393,7 @@ glsl_type::count_attribute_slots() const
case GLSL_TYPE_IMAGE:
case GLSL_TYPE_ATOMIC_UINT:
case GLSL_TYPE_VOID:
+ case GLSL_TYPE_SUBROUTINE:
case GLSL_TYPE_ERROR:
break;
}
diff --git a/src/glsl/glsl_types.h b/src/glsl/glsl_types.h
index f54a939..0f4dc80 100644
--- a/src/glsl/glsl_types.h
+++ b/src/glsl/glsl_types.h
@@ -59,6 +59,7 @@ enum glsl_base_type {
GLSL_TYPE_INTERFACE,
GLSL_TYPE_ARRAY,
GLSL_TYPE_VOID,
+ GLSL_TYPE_SUBROUTINE,
GLSL_TYPE_ERROR
};
@@ -264,6 +265,11 @@ struct glsl_type {
const char *block_name);
/**
+* Get the instance of an subroutine type
+*/
+ static const glsl_type *get_subroutine_instance(const char
*subroutine_name);
+
+ /**
* Get the type resulting from a multiplication of \p type_a * \p type_b
*/
static const glsl_type *get_mul_type(const glsl_type *type_a,
@@ -514,6 +520,13 @@ struct glsl_type {
/**
* Query if a type is unnamed/anonymous (named by the parser)
*/
+
+ bool is_subroutine() const
+
[Mesa-dev] ARB_shader_subroutine (again)
I've rebased this series, it's in my arb_shader_subroutine branch. I've also implemented Ken's idea for a subroutine-int conversion and put the changes into each patch that it affects. Otherwise not much different from when I last posted. Dave. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 08/19] mesa: add inline conversion functions for ARB_shader_subroutine
From: Dave Airlie airl...@redhat.com
This handles converting the shader stages to the internal
prefix along with the program resource interfaces.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/mesa/main/shaderobj.h | 84 +++
1 file changed, 84 insertions(+)
diff --git a/src/mesa/main/shaderobj.h b/src/mesa/main/shaderobj.h
index 3d696a1..67c717b 100644
--- a/src/mesa/main/shaderobj.h
+++ b/src/mesa/main/shaderobj.h
@@ -120,6 +120,90 @@ _mesa_shader_enum_to_shader_stage(GLenum v)
}
+static inline const char *
+_mesa_shader_stage_to_subroutine_prefix(gl_shader_stage stage)
+{
+ switch (stage) {
+ case MESA_SHADER_VERTEX:
+return __subu_v;
+ case MESA_SHADER_GEOMETRY:
+return __subu_g;
+ case MESA_SHADER_FRAGMENT:
+return __subu_f;
+ case MESA_SHADER_COMPUTE:
+return __subu_c;
+ default:
+return NULL;
+ }
+}
+
+static inline gl_shader_stage
+_mesa_shader_stage_from_subroutine_uniform(GLenum subuniform)
+{
+ switch (subuniform) {
+ default:
+ case GL_VERTEX_SUBROUTINE_UNIFORM:
+ return MESA_SHADER_VERTEX;
+ case GL_GEOMETRY_SUBROUTINE_UNIFORM:
+ return MESA_SHADER_GEOMETRY;
+ case GL_FRAGMENT_SUBROUTINE_UNIFORM:
+ return MESA_SHADER_FRAGMENT;
+ case GL_COMPUTE_SUBROUTINE_UNIFORM:
+ return MESA_SHADER_COMPUTE;
+ /* TODO - COMPUTE, TESS */
+ }
+}
+
+static inline gl_shader_stage
+_mesa_shader_stage_from_subroutine(GLenum subroutine)
+{
+ switch (subroutine) {
+ case GL_VERTEX_SUBROUTINE:
+ return MESA_SHADER_VERTEX;
+ case GL_GEOMETRY_SUBROUTINE:
+ return MESA_SHADER_GEOMETRY;
+ case GL_FRAGMENT_SUBROUTINE:
+ return MESA_SHADER_FRAGMENT;
+ case GL_COMPUTE_SUBROUTINE:
+ return MESA_SHADER_COMPUTE;
+ /* TODO - TESS */
+ }
+}
+
+static inline GLenum
+_mesa_shader_stage_to_subroutine(gl_shader_stage stage)
+{
+ switch (stage) {
+ default:
+ case MESA_SHADER_VERTEX:
+ return GL_VERTEX_SUBROUTINE;
+ case MESA_SHADER_GEOMETRY:
+ return GL_GEOMETRY_SUBROUTINE;
+ case MESA_SHADER_FRAGMENT:
+ return GL_FRAGMENT_SUBROUTINE;
+ case MESA_SHADER_COMPUTE:
+ return GL_COMPUTE_SUBROUTINE;
+ /* TODO - TESS */
+ }
+}
+
+static inline GLenum
+_mesa_shader_stage_to_subroutine_uniform(gl_shader_stage stage)
+{
+ switch (stage) {
+ default:
+ case MESA_SHADER_VERTEX:
+ return GL_VERTEX_SUBROUTINE_UNIFORM;
+ case MESA_SHADER_GEOMETRY:
+ return GL_GEOMETRY_SUBROUTINE_UNIFORM;
+ case MESA_SHADER_FRAGMENT:
+ return GL_FRAGMENT_SUBROUTINE_UNIFORM;
+ case MESA_SHADER_COMPUTE:
+ return GL_COMPUTE_SUBROUTINE_UNIFORM;
+ /* TODO - TESS */
+ }
+}
+
#ifdef __cplusplus
}
#endif
--
2.4.3
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[Mesa-dev] [PATCH 04/19] mesa: Add glGet support for ARB_shader_subroutine implementation limits
From: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Tapani Pälli tapani.pa...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/mesa/main/config.h | 6 ++
src/mesa/main/get.c | 1 +
src/mesa/main/get_hash_params.py | 4
src/mesa/main/tests/enum_strings.cpp | 9 +
4 files changed, 20 insertions(+)
diff --git a/src/mesa/main/config.h b/src/mesa/main/config.h
index 9c3baf4..07c3474 100644
--- a/src/mesa/main/config.h
+++ b/src/mesa/main/config.h
@@ -272,6 +272,12 @@
#define MAX_VERTEX_STREAMS 4
/*@}*/
+/** For GL_ARB_shader_subroutine */
+/*@{*/
+#define MAX_SUBROUTINES 256
+#define MAX_SUBROUTINE_UNIFORM_LOCATIONS 1024
+/*@}*/
+
/** For GL_INTEL_performance_query */
/*@{*/
#define MAX_PERFQUERY_QUERY_NAME_LENGTH 256
diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index 3d6d639..ac9cba3 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -401,6 +401,7 @@ EXTRA_EXT(ARB_explicit_uniform_location);
EXTRA_EXT(ARB_clip_control);
EXTRA_EXT(EXT_polygon_offset_clamp);
EXTRA_EXT(ARB_framebuffer_no_attachments);
+EXTRA_EXT(ARB_shader_subroutine);
static const int
extra_ARB_color_buffer_float_or_glcore[] = {
diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py
index c25e1b6..842ed6c 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -824,6 +824,10 @@ descriptor=[
[ MIN_FRAGMENT_INTERPOLATION_OFFSET,
CONTEXT_FLOAT(Const.MinFragmentInterpolationOffset), extra_ARB_gpu_shader5 ],
[ MAX_FRAGMENT_INTERPOLATION_OFFSET,
CONTEXT_FLOAT(Const.MaxFragmentInterpolationOffset), extra_ARB_gpu_shader5 ],
[ FRAGMENT_INTERPOLATION_OFFSET_BITS,
CONST(FRAGMENT_INTERPOLATION_OFFSET_BITS), extra_ARB_gpu_shader5 ],
+
+# GL_ARB_shader_subroutine
+ [ MAX_SUBROUTINES, CONST(MAX_SUBROUTINES), extra_ARB_shader_subroutine ],
+ [ MAX_SUBROUTINE_UNIFORM_LOCATIONS,
CONST(MAX_SUBROUTINE_UNIFORM_LOCATIONS), extra_ARB_shader_subroutine ],
]}
]
diff --git a/src/mesa/main/tests/enum_strings.cpp
b/src/mesa/main/tests/enum_strings.cpp
index dc5fe75..d40b82a 100644
--- a/src/mesa/main/tests/enum_strings.cpp
+++ b/src/mesa/main/tests/enum_strings.cpp
@@ -1731,6 +1731,10 @@ const struct enum_info everything[] = {
{ 0x8DDF, GL_MAX_GEOMETRY_UNIFORM_COMPONENTS },
{ 0x8DE0, GL_MAX_GEOMETRY_OUTPUT_VERTICES },
{ 0x8DE1, GL_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS },
+ { 0x8DE5, GL_ACTIVE_SUBROUTINES },
+ { 0x8DE6, GL_ACTIVE_SUBROUTINE_UNIFORMS },
+ { 0x8DE7, GL_MAX_SUBROUTINES },
+ { 0x8DE8, GL_MAX_SUBROUTINE_UNIFORM_LOCATIONS },
{ 0x8DF0, GL_LOW_FLOAT },
{ 0x8DF1, GL_MEDIUM_FLOAT },
{ 0x8DF2, GL_HIGH_FLOAT },
@@ -1759,6 +1763,11 @@ const struct enum_info everything[] = {
{ 0x8E44, GL_TEXTURE_SWIZZLE_B },
{ 0x8E45, GL_TEXTURE_SWIZZLE_A },
{ 0x8E46, GL_TEXTURE_SWIZZLE_RGBA },
+ { 0x8E47, GL_ACTIVE_SUBROUTINE_UNIFORM_LOCATIONS },
+ { 0x8E48, GL_ACTIVE_SUBROUTINE_MAX_LENGTH },
+ { 0x8E49, GL_ACTIVE_SUBROUTINE_UNIFORM_MAX_LENGTH },
+ { 0x8E4A, GL_NUM_COMPATIBLE_SUBROUTINES },
+ { 0x8E4B, GL_COMPATIBLE_SUBROUTINES },
{ 0x8E4C, GL_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION },
{ 0x8E4D, GL_FIRST_VERTEX_CONVENTION },
{ 0x8E4E, GL_LAST_VERTEX_CONVENTION },
--
2.4.3
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[Mesa-dev] [PATCH 02/19] glapi: Add ARB_shader_subroutine functions and enums (v2)
From: Chris Forbes chr...@ijw.co.nz v2: fix output=true and LENGTH typo Reviewed-by: Tapani Pälli tapani.pa...@intel.com Reviewed-by: Kenneth Graunke kenn...@whitecape.org Signed-off-by: Chris Forbes chr...@ijw.co.nz Signed-off-by: Dave Airlie airl...@redhat.com --- src/mapi/glapi/gen/ARB_shader_subroutine.xml | 84 src/mapi/glapi/gen/Makefile.am | 1 + src/mapi/glapi/gen/gl_API.xml| 6 +- 3 files changed, 90 insertions(+), 1 deletion(-) create mode 100644 src/mapi/glapi/gen/ARB_shader_subroutine.xml diff --git a/src/mapi/glapi/gen/ARB_shader_subroutine.xml b/src/mapi/glapi/gen/ARB_shader_subroutine.xml new file mode 100644 index 000..04b75cb --- /dev/null +++ b/src/mapi/glapi/gen/ARB_shader_subroutine.xml @@ -0,0 +1,84 @@ +?xml version=1.0? +!DOCTYPE OpenGLAPI SYSTEM gl_API.dtd + +!-- Note: no GLX protocol info yet. -- + +OpenGLAPI + +category name=GL_ARB_shader_subroutine number=90 + +function name=GetSubroutineUniformLocation offset=assign +param name=program type=GLuint/ +param name=shadertype type=GLenum/ +param name=name type=const GLchar */ +return type=GLint/ +/function + +function name=GetSubroutineIndex offset=assign +param name=program type=GLuint/ +param name=shadertype type=GLenum/ +param name=name type=const GLchar */ +return type=GLuint/ +/function + +function name=GetActiveSubroutineUniformiv offset=assign +param name=program type=GLuint/ +param name=shadertype type=GLenum/ +param name=index type=GLuint/ +param name=pname type=GLenum/ +param name=values type=GLint * output=true/ +/function + +function name=GetActiveSubroutineUniformName offset=assign +param name=program type=GLuint/ +param name=shadertype type=GLenum/ +param name=index type=GLuint/ +param name=bufsize type=GLsizei/ +param name=length type=GLsizei * output=true/ +param name=name type=GLchar * output=true/ +/function + +function name=GetActiveSubroutineName offset=assign +param name=program type=GLuint/ +param name=shadertype type=GLenum/ +param name=index type=GLuint/ +param name=bufsize type=GLsizei/ +param name=length type=GLsizei * output=true/ +param name=name type=GLchar * output=true/ +/function + +function name=UniformSubroutinesuiv offset=assign +param name=shadertype type=GLenum/ +param name=count type=GLsizei/ +param name=indices type=const GLuint */ +/function + +function name=GetUniformSubroutineuiv offset=assign +param name=shadertype type=GLenum/ +param name=location type=GLint/ +param name=params type=GLuint * output=true/ +/function + +function name=GetProgramStageiv offset=assign +param name=program type=GLuint/ +param name=shadertype type=GLenum/ +param name=pname type=GLenum/ +param name=values type=GLint * output=true/ +/function + +enum name=ACTIVE_SUBROUTINES value=0x8DE5/ +enum name=ACTIVE_SUBROUTINE_UNIFORMS value=0x8DE6/ +enum name=ACTIVE_SUBROUTINE_UNIFORM_LOCATIONS value=0x8E47/ +enum name=ACTIVE_SUBROUTINE_MAX_LENGTH value=0x8E48/ +enum name=ACTIVE_SUBROUTINE_UNIFORM_MAX_LENGTH value=0x8E49/ + +enum name=MAX_SUBROUTINES value=0x8DE7/ +enum name=MAX_SUBROUTINE_UNIFORM_LOCATIONS value=0x8DE8/ + +enum name=NUM_COMPATIBLE_SUBROUTINES value=0x8E4A/ +enum name=COMPATIBLE_SUBROUTINES value=0x8E4B/ + +!-- UNIFORM_SIZE, UNIFORM_NAME_LENGTH already in GL3.1 -- + +/category +/OpenGLAPI diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am index 5b163b0..1922c15 100644 --- a/src/mapi/glapi/gen/Makefile.am +++ b/src/mapi/glapi/gen/Makefile.am @@ -151,6 +151,7 @@ API_XML = \ ARB_separate_shader_objects.xml \ ARB_shader_atomic_counters.xml \ ARB_shader_image_load_store.xml \ + ARB_shader_subroutine.xml \ ARB_sync.xml \ ARB_texture_barrier.xml \ ARB_texture_buffer_object.xml \ diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml index 2f33075..64314cf 100644 --- a/src/mapi/glapi/gen/gl_API.xml +++ b/src/mapi/glapi/gen/gl_API.xml @@ -8072,7 +8072,11 @@ xi:include href=ARB_vertex_type_2_10_10_10_rev.xml xmlns:xi=http://www.w3.org/2001/XInclude/ -!-- ARB extensions #86...#93 -- +!-- ARB extensions #86...#89 -- + +xi:include href=ARB_shader_subroutine.xml xmlns:xi=http://www.w3.org/2001/XInclude/ + +!-- ARB extensions #91...#93 -- xi:include href=ARB_draw_indirect.xml xmlns:xi=http://www.w3.org/2001/XInclude/ -- 2.4.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 11/19] glsl: add ast/parser support for subroutine parsing storage (v3.1)
From: Dave Airlie airl...@redhat.com
This is the guts of the GLSL parser and AST support for
shader subroutines.
The code creates a subroutine type in the parser, and
uses that there to validate the identifiers. The parser
also distinguishes between subroutine types/function prototypes
/uniforms and subroutine defintions for functions.
Then in the AST conversion it recreates the types, and
stores the subroutine definition info or subroutine info
into the ir_function along with a side lookup table in
the parser state. It also converts subroutine calls into
the enhanced ir_call.
v2: move to handling method calls in
function handling not in field selection.
v3: merge Chris's previous parser patches in here, to
make it clearer what's changed in one place.
v3.1: add more documentation, drop unused include
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/ast.h | 15 +
src/glsl/ast_function.cpp| 120 +--
src/glsl/ast_to_hir.cpp | 98
src/glsl/ast_type.cpp| 7 ++-
src/glsl/glsl_lexer.ll | 8 +++
src/glsl/glsl_parser.yy | 114 +
src/glsl/glsl_parser_extras.cpp | 22 +++
src/glsl/glsl_parser_extras.h| 19 +++
src/glsl/hir_field_selection.cpp | 39 -
9 files changed, 326 insertions(+), 116 deletions(-)
diff --git a/src/glsl/ast.h b/src/glsl/ast.h
index ef74e51..968aad4 100644
--- a/src/glsl/ast.h
+++ b/src/glsl/ast.h
@@ -304,6 +304,16 @@ private:
* Is this function call actually a constructor?
*/
bool cons;
+ ir_rvalue *
+ handle_method(exec_list *instructions,
+ struct _mesa_glsl_parse_state *state);
+};
+
+class ast_subroutine_list : public ast_node
+{
+public:
+ virtual void print(void) const;
+ exec_list declarations;
};
class ast_array_specifier : public ast_node {
@@ -514,6 +524,10 @@ struct ast_type_qualifier {
unsigned stream:1; /** Has stream value assigned */
unsigned explicit_stream:1; /** stream value assigned explicitly by
shader code */
/** \} */
+
+ /** \name Qualifiers for GL_ARB_shader_subroutine */
+ unsigned subroutine:1; /** Is this marked 'subroutine' */
+ unsigned subroutine_def:1; /** Is this marked 'subroutine' with a
list of types */
}
/** \brief Set of flags, accessed by name. */
q;
@@ -636,6 +650,7 @@ struct ast_type_qualifier {
ast_type_qualifier q,
ast_node* node);
+ ast_subroutine_list *subroutine_list;
};
class ast_declarator_list;
diff --git a/src/glsl/ast_function.cpp b/src/glsl/ast_function.cpp
index 92e26bf..f32de7c 100644
--- a/src/glsl/ast_function.cpp
+++ b/src/glsl/ast_function.cpp
@@ -26,6 +26,7 @@
#include glsl_types.h
#include ir.h
#include main/core.h /* for MIN2 */
+#include main/shaderobj.h
static ir_rvalue *
convert_component(ir_rvalue *src, const glsl_type *desired_type);
@@ -355,6 +356,8 @@ fix_parameter(void *mem_ctx, ir_rvalue *actual, const
glsl_type *formal_type,
static ir_rvalue *
generate_call(exec_list *instructions, ir_function_signature *sig,
exec_list *actual_parameters,
+ ir_variable *sub_var,
+ ir_rvalue *array_idx,
struct _mesa_glsl_parse_state *state)
{
void *ctx = state;
@@ -421,7 +424,8 @@ generate_call(exec_list *instructions,
ir_function_signature *sig,
deref = new(ctx) ir_dereference_variable(var);
}
- ir_call *call = new(ctx) ir_call(sig, deref, actual_parameters);
+
+ ir_call *call = new(ctx) ir_call(sig, deref, actual_parameters, sub_var,
array_idx);
instructions-push_tail(call);
/* Also emit any necessary out-parameter conversions. */
@@ -489,6 +493,40 @@ done:
return sig;
}
+static ir_function_signature *
+match_subroutine_by_name(const char *name,
+ exec_list *actual_parameters,
+ struct _mesa_glsl_parse_state *state,
+ ir_variable **var_r)
+{
+ void *ctx = state;
+ ir_function_signature *sig = NULL;
+ ir_function *f, *found = NULL;
+ const char *new_name;
+ ir_variable *var;
+ bool is_exact = false;
+
+ new_name = ralloc_asprintf(ctx, %s_%s,
_mesa_shader_stage_to_subroutine_prefix(state-stage), name);
+ var = state-symbols-get_variable(new_name);
+ if (!var)
+ return NULL;
+
+ for (int i = 0; i state-num_subroutine_types; i++) {
+ f = state-subroutine_types[i];
+ if (strcmp(f-name, var-type-without_array()-name))
+ continue;
+ found = f;
+ break;
+ }
+
+ if (!found)
+ return NULL;
+ *var_r = var;
+ sig = found-matching_signature(state, actual_parameters,
+ false, is_exact);
+ return sig;
+}
+
static void
print_function_prototypes(_mesa_glsl_parse_state *state,
[Mesa-dev] [PATCH 06/19] glsl: Make `subroutine` a reserved keyword
From: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Tapani Pälli tapani.pa...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/glsl_lexer.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/glsl_lexer.ll b/src/glsl/glsl_lexer.ll
index 10db5b8..5fd22b4 100644
--- a/src/glsl/glsl_lexer.ll
+++ b/src/glsl/glsl_lexer.ll
@@ -577,7 +577,7 @@ usamplerBuffer KEYWORD(140, 300, 140, 0,
USAMPLERBUFFER);
resource KEYWORD(0, 300, 0, 0, RESOURCE);
patch KEYWORD(0, 300, 0, 0, PATCH);
sample KEYWORD_WITH_ALT(400, 300, 400, 0,
yyextra-ARB_gpu_shader5_enable, SAMPLE);
-subroutine KEYWORD(0, 300, 0, 0, SUBROUTINE);
+subroutine KEYWORD_WITH_ALT(400, 300, 400, 0,
yyextra-ARB_shader_subroutine_enable, SUBROUTINE);
[_a-zA-Z][_a-zA-Z0-9]* {
--
2.4.3
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[Mesa-dev] [PATCH 03/19] mesa: Add extension tracking for arb_shader_subroutine (v2)
From: Chris Forbes chr...@ijw.co.nz
v2: [airlied]: merge version check update.
Reviewed-by: Tapani Pälli tapani.pa...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/mesa/main/extensions.c | 1 +
src/mesa/main/mtypes.h | 1 +
src/mesa/main/version.c| 2 +-
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index 4176a69..24ae33e 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -154,6 +154,7 @@ static const struct extension extension_table[] = {
{ GL_ARB_shader_objects, o(dummy_true),
GL, 2002 },
{ GL_ARB_shader_precision,o(ARB_shader_precision),
GL, 2010 },
{ GL_ARB_shader_stencil_export,
o(ARB_shader_stencil_export), GL, 2009 },
+ { GL_ARB_shader_subroutine, o(ARB_shader_subroutine),
GLC,2010 },
{ GL_ARB_shader_texture_lod, o(ARB_shader_texture_lod),
GL, 2009 },
{ GL_ARB_shading_language_100,o(dummy_true),
GLL,2003 },
{ GL_ARB_shading_language_packing,
o(ARB_shading_language_packing),GL, 2011 },
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 7b55677..a93fe94 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3685,6 +3685,7 @@ struct gl_extensions
GLboolean ARB_shader_image_load_store;
GLboolean ARB_shader_precision;
GLboolean ARB_shader_stencil_export;
+ GLboolean ARB_shader_subroutine;
GLboolean ARB_shader_texture_lod;
GLboolean ARB_shading_language_packing;
GLboolean ARB_shading_language_420pack;
diff --git a/src/mesa/main/version.c b/src/mesa/main/version.c
index 8bc00ac..fd7ae53 100644
--- a/src/mesa/main/version.c
+++ b/src/mesa/main/version.c
@@ -309,7 +309,7 @@ compute_version(const struct gl_extensions *extensions,
extensions-ARB_gpu_shader5
extensions-ARB_gpu_shader_fp64
extensions-ARB_sample_shading
- false /*extensions-ARB_shader_subroutine*/
+ extensions-ARB_shader_subroutine
extensions-ARB_tessellation_shader
extensions-ARB_texture_buffer_object_rgb32
extensions-ARB_texture_cube_map_array
--
2.4.3
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[Mesa-dev] [PATCH 09/19] glsl/ir: add subroutine information storage to ir_function (v1.1)
From: Dave Airlie airl...@redhat.com
We need to store two sets of info into the ir_function,
if this is a function definition with a subroutine list
(subroutine_def) or if it a subroutine prototype.
v1.1: add some more documentation.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/ir.cpp | 4
src/glsl/ir.h | 16
src/glsl/ir_clone.cpp | 7 +++
src/glsl/ir_print_visitor.cpp | 2 +-
4 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/src/glsl/ir.cpp b/src/glsl/ir.cpp
index 38a5e2a..2fbc631 100644
--- a/src/glsl/ir.cpp
+++ b/src/glsl/ir.cpp
@@ -1853,6 +1853,7 @@ static void
steal_memory(ir_instruction *ir, void *new_ctx)
{
ir_variable *var = ir-as_variable();
+ ir_function *fn = ir-as_function();
ir_constant *constant = ir-as_constant();
if (var != NULL var-constant_value != NULL)
steal_memory(var-constant_value, ir);
@@ -1860,6 +1861,9 @@ steal_memory(ir_instruction *ir, void *new_ctx)
if (var != NULL var-constant_initializer != NULL)
steal_memory(var-constant_initializer, ir);
+ if (fn != NULL fn-subroutine_types)
+ ralloc_steal(new_ctx, fn-subroutine_types);
+
/* The components of aggregate constants are not visited by the normal
* visitor, so steal their values by hand.
*/
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 092c96b..b5a9e99 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -1121,6 +1121,22 @@ public:
* List of ir_function_signature for each overloaded function with this
name.
*/
struct exec_list signatures;
+
+ /**
+* is this function a subroutine type declaration
+* e.g. subroutine void type1(float arg1);
+*/
+ bool is_subroutine;
+
+ /**
+* is this function associated to a subroutine type
+* e.g. subroutine (type1, type2) function_name { function_body };
+* would have this flag set and num_subroutine_types 2,
+* and pointers to the type1 and type2 types.
+*/
+ bool is_subroutine_def;
+ int num_subroutine_types;
+ const struct glsl_type **subroutine_types;
};
inline const char *ir_function_signature::function_name() const
diff --git a/src/glsl/ir_clone.cpp b/src/glsl/ir_clone.cpp
index 49834ff..bf25d6c 100644
--- a/src/glsl/ir_clone.cpp
+++ b/src/glsl/ir_clone.cpp
@@ -267,6 +267,13 @@ ir_function::clone(void *mem_ctx, struct hash_table *ht)
const
{
ir_function *copy = new(mem_ctx) ir_function(this-name);
+ copy-is_subroutine = this-is_subroutine;
+ copy-is_subroutine_def = this-is_subroutine_def;
+ copy-num_subroutine_types = this-num_subroutine_types;
+ copy-subroutine_types = ralloc_array(mem_ctx, const struct glsl_type *,
copy-num_subroutine_types);
+ for (int i = 0; i copy-num_subroutine_types; i++)
+ copy-subroutine_types[i] = this-subroutine_types[i];
+
foreach_in_list(const ir_function_signature, sig, this-signatures) {
ir_function_signature *sig_copy = sig-clone(mem_ctx, ht);
copy-add_signature(sig_copy);
diff --git a/src/glsl/ir_print_visitor.cpp b/src/glsl/ir_print_visitor.cpp
index 4cbcad4..f210175 100644
--- a/src/glsl/ir_print_visitor.cpp
+++ b/src/glsl/ir_print_visitor.cpp
@@ -229,7 +229,7 @@ void ir_print_visitor::visit(ir_function_signature *ir)
void ir_print_visitor::visit(ir_function *ir)
{
- fprintf(f, (function %s\n, ir-name);
+ fprintf(f, (%s function %s\n, ir-is_subroutine ? subroutine : ,
ir-name);
indentation++;
foreach_in_list(ir_function_signature, sig, ir-signatures) {
indent();
--
2.4.3
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[Mesa-dev] [PATCH 01/19] mesa: Add stubs for ARB_shader_subroutine entrypoints
From: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Tapani Pälli tapani.pa...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/mesa/main/shaderapi.c | 63 +++
src/mesa/main/shaderapi.h | 35 ++
2 files changed, 98 insertions(+)
diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index a4296ad..48ab217 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -1984,3 +1984,66 @@ _mesa_CreateShaderProgramv(GLenum type, GLsizei count,
return _mesa_create_shader_program(ctx, GL_TRUE, type, count, strings);
}
+
+
+/**
+ * ARB_shader_subroutine
+ */
+GLint GLAPIENTRY
+_mesa_GetSubroutineUniformLocation(GLuint program, GLenum shadertype,
+ const GLchar *name)
+{
+ return -1;
+}
+
+
+GLuint GLAPIENTRY
+_mesa_GetSubroutineIndex(GLuint program, GLenum shadertype,
+ const GLchar *name)
+{
+ return GL_INVALID_INDEX;
+}
+
+
+GLvoid GLAPIENTRY
+_mesa_GetActiveSubroutineUniformiv(GLuint program, GLenum shadertype,
+ GLuint index, GLenum pname, GLint *values)
+{
+}
+
+
+GLvoid GLAPIENTRY
+_mesa_GetActiveSubroutineUniformName(GLuint program, GLenum shadertype,
+ GLuint index, GLsizei bufsize,
+ GLsizei *length, GLchar *name)
+{
+}
+
+
+GLvoid GLAPIENTRY
+_mesa_GetActiveSubroutineName(GLuint program, GLenum shadertype,
+ GLuint index, GLsizei bufsize,
+ GLsizei *length, GLchar *name)
+{
+}
+
+
+GLvoid GLAPIENTRY
+_mesa_UniformSubroutinesuiv(GLenum shadertype, GLsizei count,
+const GLuint *indices)
+{
+}
+
+
+GLvoid GLAPIENTRY
+_mesa_GetUniformSubroutineuiv(GLenum shadertype, GLint location,
+ GLuint *params)
+{
+}
+
+
+GLvoid GLAPIENTRY
+_mesa_GetProgramStageiv(GLuint program, GLenum shadertype,
+GLenum pname, GLint *values)
+{
+}
diff --git a/src/mesa/main/shaderapi.h b/src/mesa/main/shaderapi.h
index aba6d5d..eda7170 100644
--- a/src/mesa/main/shaderapi.h
+++ b/src/mesa/main/shaderapi.h
@@ -264,6 +264,41 @@ _mesa_get_program_resourceiv(struct gl_shader_program
*shProg,
GLsizei bufSize, GLsizei *length,
GLint *params);
+/* GL_ARB_shader_subroutine */
+extern GLint GLAPIENTRY
+_mesa_GetSubroutineUniformLocation(GLuint program, GLenum shadertype,
+ const GLchar *name);
+
+extern GLuint GLAPIENTRY
+_mesa_GetSubroutineIndex(GLuint program, GLenum shadertype,
+ const GLchar *name);
+
+extern GLvoid GLAPIENTRY
+_mesa_GetActiveSubroutineUniformiv(GLuint program, GLenum shadertype,
+ GLuint index, GLenum pname, GLint *values);
+
+extern GLvoid GLAPIENTRY
+_mesa_GetActiveSubroutineUniformName(GLuint program, GLenum shadertype,
+ GLuint index, GLsizei bufsize,
+ GLsizei *length, GLchar *name);
+
+extern GLvoid GLAPIENTRY
+_mesa_GetActiveSubroutineName(GLuint program, GLenum shadertype,
+ GLuint index, GLsizei bufsize,
+ GLsizei *length, GLchar *name);
+
+extern GLvoid GLAPIENTRY
+_mesa_UniformSubroutinesuiv(GLenum shadertype, GLsizei count,
+const GLuint *indices);
+
+extern GLvoid GLAPIENTRY
+_mesa_GetUniformSubroutineuiv(GLenum shadertype, GLint location,
+ GLuint *params);
+
+extern GLvoid GLAPIENTRY
+_mesa_GetProgramStageiv(GLuint program, GLenum shadertype,
+GLenum pname, GLint *values);
+
#ifdef __cplusplus
}
#endif
--
2.4.3
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[Mesa-dev] [PATCH 05/19] glsl: Add extension plumbing and define for ARB_shader_subroutine
From: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Tapani Pälli tapani.pa...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/glcpp/glcpp-parse.y| 3 +++
src/glsl/glsl_parser_extras.cpp | 1 +
src/glsl/glsl_parser_extras.h | 2 ++
src/glsl/standalone_scaffolding.cpp | 1 +
4 files changed, 7 insertions(+)
diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index a11b6b2..99b7cdf 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -2483,6 +2483,9 @@ _glcpp_parser_handle_version_declaration(glcpp_parser_t
*parser, intmax_t versio
if (extensions-ARB_shader_precision)
add_builtin_define(parser, GL_ARB_shader_precision, 1);
+
+ if (extensions-ARB_shader_subroutine)
+ add_builtin_define(parser, GL_ARB_shader_subroutine, 1);
}
}
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index 046d5d7..676489f 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -570,6 +570,7 @@ static const _mesa_glsl_extension
_mesa_glsl_supported_extensions[] = {
EXT(ARB_shader_image_load_store,true, false,
ARB_shader_image_load_store),
EXT(ARB_shader_precision, true, false, ARB_shader_precision),
EXT(ARB_shader_stencil_export, true, false,
ARB_shader_stencil_export),
+ EXT(ARB_shader_subroutine, true, false,
ARB_shader_subroutine),
EXT(ARB_shader_texture_lod, true, false,
ARB_shader_texture_lod),
EXT(ARB_shading_language_420pack, true, false,
ARB_shading_language_420pack),
EXT(ARB_shading_language_packing, true, false,
ARB_shading_language_packing),
diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
index 02ddbbd..726a427 100644
--- a/src/glsl/glsl_parser_extras.h
+++ b/src/glsl/glsl_parser_extras.h
@@ -462,6 +462,8 @@ struct _mesa_glsl_parse_state {
bool ARB_shader_precision_warn;
bool ARB_shader_stencil_export_enable;
bool ARB_shader_stencil_export_warn;
+ bool ARB_shader_subroutine_enable;
+ bool ARB_shader_subroutine_warn;
bool ARB_shader_texture_lod_enable;
bool ARB_shader_texture_lod_warn;
bool ARB_shading_language_420pack_enable;
diff --git a/src/glsl/standalone_scaffolding.cpp
b/src/glsl/standalone_scaffolding.cpp
index 172c6f4..15546c2 100644
--- a/src/glsl/standalone_scaffolding.cpp
+++ b/src/glsl/standalone_scaffolding.cpp
@@ -133,6 +133,7 @@ void initialize_context_to_defaults(struct gl_context *ctx,
gl_api api)
ctx-Extensions.ARB_sample_shading = true;
ctx-Extensions.ARB_shader_bit_encoding = true;
ctx-Extensions.ARB_shader_stencil_export = true;
+ ctx-Extensions.ARB_shader_subroutine = true;
ctx-Extensions.ARB_shader_texture_lod = true;
ctx-Extensions.ARB_shading_language_420pack = true;
ctx-Extensions.ARB_shading_language_packing = true;
--
2.4.3
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[Mesa-dev] [PATCH 10/19] glsl/ir: allow ir_call to handle subroutine calling
From: Dave Airlie airl...@redhat.com
This adds a ir_variable which contains the subroutine uniform
and an array rvalue for the deref of that uniform, these
are stored in the ir_call and lowered later.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/ir.h | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index b5a9e99..691c8b6 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -1708,7 +1708,18 @@ public:
ir_call(ir_function_signature *callee,
ir_dereference_variable *return_deref,
exec_list *actual_parameters)
- : ir_instruction(ir_type_call), return_deref(return_deref),
callee(callee)
+ : ir_instruction(ir_type_call), return_deref(return_deref),
callee(callee), sub_var(NULL), array_idx(NULL)
+ {
+ assert(callee-return_type != NULL);
+ actual_parameters-move_nodes_to( this-actual_parameters);
+ this-use_builtin = callee-is_builtin();
+ }
+
+ ir_call(ir_function_signature *callee,
+ ir_dereference_variable *return_deref,
+ exec_list *actual_parameters,
+ ir_variable *var, ir_rvalue *array_idx)
+ : ir_instruction(ir_type_call), return_deref(return_deref),
callee(callee), sub_var(var), array_idx(array_idx)
{
assert(callee-return_type != NULL);
actual_parameters-move_nodes_to( this-actual_parameters);
@@ -1756,6 +1767,14 @@ public:
/** Should this call only bind to a built-in function? */
bool use_builtin;
+
+ /*
+* ARB_shader_subroutine support -
+* the subroutine uniform variable and array index
+* rvalue to be used in the lowering pass later.
+*/
+ ir_variable *sub_var;
+ ir_rvalue *array_idx;
};
--
2.4.3
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[Mesa-dev] [PATCH 16/19] program: add subroutine uniform support (v1.1)
From: Dave Airlie airl...@redhat.com Add support for the subroutine uniform type ir-mesa.cpp v1.1: add subroutine to int to switch Signed-off-by: Dave Airlie airl...@redhat.com --- src/mesa/program/ir_to_mesa.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp index 0b2eb12..6ee6ee8 100644 --- a/src/mesa/program/ir_to_mesa.cpp +++ b/src/mesa/program/ir_to_mesa.cpp @@ -534,6 +534,7 @@ type_size(const struct glsl_type *type) return size; case GLSL_TYPE_SAMPLER: case GLSL_TYPE_IMAGE: + case GLSL_TYPE_SUBROUTINE: /* Samplers take up one slot in UNIFORMS[], but they're baked in * at link time. */ @@ -1342,6 +1343,7 @@ ir_to_mesa_visitor::visit(ir_expression *ir) case ir_unop_dFdx_fine: case ir_unop_dFdy_coarse: case ir_unop_dFdy_fine: + case ir_unop_subroutine_to_int: assert(!not supported); break; @@ -2451,6 +2453,7 @@ _mesa_associate_uniform_storage(struct gl_context *ctx, break; case GLSL_TYPE_SAMPLER: case GLSL_TYPE_IMAGE: + case GLSL_TYPE_SUBROUTINE: format = uniform_native; columns = 1; break; -- 2.4.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 0/4] fence refcnting fixes
On 08.07.2015 22:34, Rob Clark wrote: From: Rob Clark robcl...@freedesktop.org This isn't at all clear for pipe driver writers currently, since it is not documented anywhere. But radeon/nouveau/llvmpipe seem to drop the ref on the **fence passed in to pipe-flush() (if *fence!=NULL). Freedreno/ilo/vc4 where not doing this. Some state trackers do call screen-fence_reference(screen, fence, NULL) before pipe-flush(), but others do not. Add a comment for pipe-flush() to clairify what is expected of the driver, and fixup freedreno/ilo/vc4 to comply. Note: that ilo/vc4 patches are untested Oh, yes please. That also annoyed me once or twice while hacking on the state trackers. Since I'm not into the drivers those changes are Acked-by: Christian König christian.koe...@amd.com Do you want to take care of the state trackers as well or should I look into the video state trackers to fix this myself? Regards, Christian. Rob Clark (4): gallium: clarify reference counting for fence freedreno: unref old fence ilo: unref old fence vc4: unref old fence src/gallium/drivers/freedreno/freedreno_context.c | 2 +- src/gallium/drivers/freedreno/freedreno_fence.c | 2 +- src/gallium/drivers/ilo/ilo_context.c | 5 - src/gallium/drivers/ilo/ilo_screen.c | 2 +- src/gallium/drivers/vc4/vc4_context.c | 3 ++- src/gallium/drivers/vc4/vc4_fence.c | 2 +- src/gallium/include/pipe/p_context.h | 8 +++- 7 files changed, 17 insertions(+), 7 deletions(-) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] r600g: move sampler/ubo index registers before temp reg
On Thu, 09 Jul 2015 08:00:48 +0200, Dave Airlie airl...@gmail.com wrote:
From: Dave Airlie airl...@redhat.com
temp_reg needs to be last, as we increment things
away from it, otherwise on cayman some tests were overwriting
the index regs.
Fixes 2 piglit with ARB_gpu_shader5 forced on cayman.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/r600/r600_shader.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index af7622e..1a72bf6 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1931,15 +1931,14 @@ static int r600_shader_from_tgsi(struct
r600_context *rctx,
ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
ctx.bc-ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
+ ctx.bc-index_reg[0] = ctx.bc-ar_reg + 1;
+ ctx.bc-index_reg[1] = ctx.bc-ar_reg + 2;
+
if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
- ctx.gs_export_gpr_treg = ctx.bc-ar_reg + 1;
- ctx.temp_reg = ctx.bc-ar_reg + 2;
- ctx.bc-index_reg[0] = ctx.bc-ar_reg + 3;
- ctx.bc-index_reg[1] = ctx.bc-ar_reg + 4;
+ ctx.gs_export_gpr_treg = ctx.bc-ar_reg + 3;
+ ctx.temp_reg = ctx.bc-ar_reg + 4;
} else {
- ctx.temp_reg = ctx.bc-ar_reg + 1;
- ctx.bc-index_reg[0] = ctx.bc-ar_reg + 2;
- ctx.bc-index_reg[1] = ctx.bc-ar_reg + 3;
+ ctx.temp_reg = ctx.bc-ar_reg + 3;
}
shader-max_arrays = 0;
Reviewed-by: Glenn Kennard glenn.kenn...@gmail.com
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Re: [Mesa-dev] [PATCH 0/4] fence refcnting fixes
On Thu, Jul 9, 2015 at 4:21 AM, Christian König deathsim...@vodafone.de wrote: On 08.07.2015 22:34, Rob Clark wrote: From: Rob Clark robcl...@freedesktop.org This isn't at all clear for pipe driver writers currently, since it is not documented anywhere. But radeon/nouveau/llvmpipe seem to drop the ref on the **fence passed in to pipe-flush() (if *fence!=NULL). Freedreno/ilo/vc4 where not doing this. Some state trackers do call screen-fence_reference(screen, fence, NULL) before pipe-flush(), but others do not. Add a comment for pipe-flush() to clairify what is expected of the driver, and fixup freedreno/ilo/vc4 to comply. Note: that ilo/vc4 patches are untested Oh, yes please. That also annoyed me once or twice while hacking on the state trackers. Since I'm not into the drivers those changes are Acked-by: Christian König christian.koe...@amd.com Do you want to take care of the state trackers as well or should I look into the video state trackers to fix this myself? I guess w/ the doc change + fixing drivers, we don't strictly need to change the other state trackers to explicitly unref their last_fence, if that is what you had in mind? It probably wouldn't hurt, but shouldn't be required.. BR, -R Regards, Christian. Rob Clark (4): gallium: clarify reference counting for fence freedreno: unref old fence ilo: unref old fence vc4: unref old fence src/gallium/drivers/freedreno/freedreno_context.c | 2 +- src/gallium/drivers/freedreno/freedreno_fence.c | 2 +- src/gallium/drivers/ilo/ilo_context.c | 5 - src/gallium/drivers/ilo/ilo_screen.c | 2 +- src/gallium/drivers/vc4/vc4_context.c | 3 ++- src/gallium/drivers/vc4/vc4_fence.c | 2 +- src/gallium/include/pipe/p_context.h | 8 +++- 7 files changed, 17 insertions(+), 7 deletions(-) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 02/11] i915; remove unused driFd variable
On 8 July 2015 at 18:08, Matt Turner matts...@gmail.com wrote: On Wed, Jul 8, 2015 at 10:07 AM, Emil Velikov emil.l.veli...@gmail.com wrote: Signed-off-by: Emil Velikov emil.l.veli...@gmail.com --- src/mesa/drivers/dri/i915/intel_context.c | 1 - src/mesa/drivers/dri/i915/intel_context.h | 2 -- 2 files changed, 3 deletions(-) diff --git a/src/mesa/drivers/dri/i915/intel_context.c b/src/mesa/drivers/dri/i915/intel_context.c index 5618dcd..c780103 100644 --- a/src/mesa/drivers/dri/i915/intel_context.c +++ b/src/mesa/drivers/dri/i915/intel_context.c @@ -428,7 +428,6 @@ intelInitContext(struct intel_context *intel, driContextPriv-driverPrivate = intel; intel-driContext = driContextPriv; - intel-driFd = sPriv-fd; intel-gen = intelScreen-gen; diff --git a/src/mesa/drivers/dri/i915/intel_context.h b/src/mesa/drivers/dri/i915/intel_context.h index 350d35d..4ec4015 100644 --- a/src/mesa/drivers/dri/i915/intel_context.h +++ b/src/mesa/drivers/dri/i915/intel_context.h @@ -273,8 +273,6 @@ struct intel_context bool use_early_z; - int driFd; - __DRIcontext *driContext; struct intel_screen *intelScreen; -- s/;/:/ in the subject. Wow, that's some DRI1 stuff! I suspect there is more, so if anyone is interested ;-) Reviewed-by: Matt Turner matts...@gmail.com Thanks Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] New stable-branch 10.6 candidate pushed
Hello list, The candidate for the Mesa 10.6.2 is now available. Currently we have: - 37 queued - 26 nominated (outstanding) - and 2 rejected/obsolete patches We have a moderate list of fixes this time around, most of which in the glsl, core mesa, and the i965 nouveau. From a users perspective have the usual GPU lockup and incorrect rendering patches, we revert of the use of SHA1, which was unused and added confusing configure options/extra linking, further libudev related fixes. Note: The series contains three fixes which have not been nominated but address patches that has been cherry-picked for 10.6. Namely: commit 25daf2592c21881eed3cbe1e8439f32878b3eb2f Author: Kenneth Graunke kenn...@whitecape.org Revert glsl: clone inputs and outputs during linking (cherry picked from commit 6218c68bece0cea671f2940a651119a87ab8b24e) commit 6b6e14ac35750e0a7f8194923877a842f9a43e3f Author: Kenneth Graunke kenn...@whitecape.org Revert i965: Delete linked GLSL IR when using NIR. (cherry picked from commit cae701fc8ed0faefd1cf57f6143031edcab2) commit 5e9254194594b863f55f4efcafca7fbb5b21ec8f Author: Neil Roberts n...@linux.intel.com i965: Don't try to print the GLSL IR if it has been freed (cherry picked from commit c0ca6c30eaf7f488f154c462a01a8945cb4a3103) Take a look at section Mesa stable queue for more information. Testing --- The following results are against piglit 246791c51ec. Changes - classic i965(snb) --- Fixes: - glx + glx_arb_sync_control + swapbuffersmsc-divisor-zero fail pass + timing -divisor 1 fail pass + timing -divisor 2 fail pass + timing -fullscreen -divisor 1 fail pass + timing -fullscreen -divisor 2 fail pass + timing -fullscreen -msc-delta 1 fail pass + timing -fullscreen -msc-delta 2 fail pass + timing -msc-delta 1 fail pass + timing -msc-delta 2 fail pass + timing -waitformsc -divisor 1 fail pass + timing -waitformsc -divisor 2 fail pass + timing -waitformsc -msc-delta 1 fail pass + timing -waitformsc -msc-delta 2 fail pass - spec + !opengl 1.4 + fdo25614-genmipmap skip pass Changes - swrast classic Fixes: - spec + !opengl 1.1 + drawbuffer-modesfail pass + !opengl 1.4 + fdo25614-genmipmap skip pass Changes - gallium softpipe -- Fixes: - spec + !opengl 1.4 + fdo25614-genmipmap skip pass Changes - gallium llvmpipe (LLVM 3.6) - Fixes: - spec + !opengl 1.4 + fdo25614-genmipmap skip pass Testing reports/general approval Any testing reports (or general approval of the state of the branch) will be greatly appreciated. Trivial merge conflicts --- commit cc7caf9239903ca3604e90613c4696e7c0f7b0e1 Author: Tapani Pälli tapani.pa...@intel.com glsl: Allow dynamic sampler array indexing with GLSL ES 3.00 (cherry picked from commit edb8383c98ee23385731d0fc23a6b6673528a8ec) commit b150817c197a8e0772114641fed3eb19284f4540 Author: Tapani Pälli tapani.pa...@intel.com i965: use EmitNoIndirectSampler for gen 7 (cherry picked from commit 8852e26e93af1fc4b72bf9d57e847f53e1a1371b) commit afa43fa696e7dd65ebce4c1e95892a4886d6049e Author: Neil Roberts n...@linux.intel.com i965/skl: Set the pulls bary bit in 3DSTATE_PS_EXTRA (cherry picked from commit 493af150fb3b1c007d791b24dcd5ea8a92ad763c) commit 2ca2f3701b9928374911c603178cf92da1e5167b Author: Kenneth Graunke kenn...@whitecape.org i965/vs: Fix matNxM vertex attributes where M != 4. (cherry picked from commit 73d0e7f3451eaeb62ac039d2dcee1e1c6787e3db) The plan is to have 10.6.2 this Friday(10th of July). If you have any questions or comments that you would like to share before the release, please go ahead. Cheers, Emil Mesa stable queue - Nominated (26) == Anuj Phogat (8): mesa: Turn get_readpixels_transfer_ops() in to a global function meta: Fix transfer operations check in meta pbo path for readpixels mesa: Fix conditions to test signed, unsigned integer format mesa: Add a mesa utility function _mesa_need_signed_unsigned_int_conversion() meta: Abort meta pbo path if readpixels need signed-unsigned meta: Don't do fragment color clamping in case of
Re: [Mesa-dev] [PATCH 4/4] vc4: unref old fence
On 9 July 2015 at 01:46, Rob Clark robdcl...@gmail.com wrote:
From: Rob Clark robcl...@freedesktop.org
Some, but not all, state trackers will explicitly unref (and set to
NULL) the previous *fence before calling pipe-flush(). So driver
should use fence_ref() which will unref the old fence if not NULL.
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/drivers/vc4/vc4_context.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/vc4/vc4_context.c
b/src/gallium/drivers/vc4/vc4_context.c
index 630f8e6..316598f 100644
--- a/src/gallium/drivers/vc4/vc4_context.c
+++ b/src/gallium/drivers/vc4/vc4_context.c
@@ -103,8 +103,10 @@ vc4_pipe_flush(struct pipe_context *pctx, struct
pipe_fence_handle **fence,
vc4_flush(pctx);
if (fence) {
+struct pipe_screen *screen = pctx-screen;
struct vc4_fence *f = vc4_fence_create(vc4-screen,
vc4-last_emit_seqno);
+screen-fence_reference(screen, fence, NULL);
The order seems to be reversed comparing to the other patches that
you've sent. Is that intentional ?
-Emil
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Re: [Mesa-dev] [PATCH] i965: bump libdrm requirement to 2.4.61 and drop in-tree workaround
On 08/07/15 18:57, Emil Velikov wrote:
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
configure.ac | 2 +-
src/mesa/drivers/dri/i965/intel_screen.c | 5 -
2 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/configure.ac b/configure.ac
index d819bef..eb7180b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -68,7 +68,7 @@ AC_SUBST([OSMESA_VERSION])
dnl Versions for external dependencies
LIBDRM_REQUIRED=2.4.38
LIBDRM_RADEON_REQUIRED=2.4.56
-LIBDRM_INTEL_REQUIRED=2.4.60
+LIBDRM_INTEL_REQUIRED=2.4.61
LIBDRM_NVVIEUX_REQUIRED=2.4.33
LIBDRM_NOUVEAU_REQUIRED=2.4.62
LIBDRM_FREEDRENO_REQUIRED=2.4.57
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index c0f5c92..fd343ee 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1330,11 +1330,6 @@ set_max_gl_versions(struct intel_screen *screen)
}
}
-/* drop when libdrm 2.4.61 is released */
-#ifndef I915_PARAM_REVISION
-#define I915_PARAM_REVISION 32
-#endif
-
static int
brw_get_revision(int fd)
{
Reviewed-by: Samuel Iglesias Gonsálvez sigles...@igalia.com
Sam
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Re: [Mesa-dev] [PATCH 03/11] radeon: remove dri_mirror state
On 9 July 2015 at 04:45, Michel Dänzer mic...@daenzer.net wrote: On 09.07.2015 02:07, Emil Velikov wrote: Most of the data stored(duplicated) was unused, and for the one that is follow the approach set by other drivers. This eliminates the use of legacy (dri1) types. The commentary below should have been after the --- separator, not in the actual Git commit log. With that fixed, this patch is Reviewed-by: Michel Dänzer michel.daen...@amd.com XXX: The radeon code is the only user of __DRIscreen::drm_version (the only __DRIversion outside of dri1 land). Should we move it into radeon and/or bump the min. required drm module version ? Moving this into radeon sounds good to me, but I'm not sure what exactly you mean by bumping the minimum required version, or what it's supposed to be good for. FWIW though, any code which is specific to radeon DRM major version 1 can be removed, because that's the UMS major version. Here is what we have atm. radeon/r200_context.c: if (major == 1 minor 13) printf(boho no hyperz for you\n) } if (minor =15) // major check anyone ? r_context.texmicrotile = true; // unused since 2009 ccf7814a315(radeon: major cleanups removing old dead codepaths.) radeon_screen.c: if (major = 2) drmCommandReadWrite(DRM_RADEON_INFO) else drmCommandReadWrite(DRM_RADEON_GETPARAM) Considering the amdgpu work (major number), I think we can just error out if major !=2 and cleanup the above ? Cheers, Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 03/11] radeon: remove dri_mirror state
major != 2 can't occur. You don't have to check the major version at all and you can just assume it's always 2. Marek On Thu, Jul 9, 2015 at 2:55 PM, Emil Velikov emil.l.veli...@gmail.com wrote: On 9 July 2015 at 04:45, Michel Dänzer mic...@daenzer.net wrote: On 09.07.2015 02:07, Emil Velikov wrote: Most of the data stored(duplicated) was unused, and for the one that is follow the approach set by other drivers. This eliminates the use of legacy (dri1) types. The commentary below should have been after the --- separator, not in the actual Git commit log. With that fixed, this patch is Reviewed-by: Michel Dänzer michel.daen...@amd.com XXX: The radeon code is the only user of __DRIscreen::drm_version (the only __DRIversion outside of dri1 land). Should we move it into radeon and/or bump the min. required drm module version ? Moving this into radeon sounds good to me, but I'm not sure what exactly you mean by bumping the minimum required version, or what it's supposed to be good for. FWIW though, any code which is specific to radeon DRM major version 1 can be removed, because that's the UMS major version. Here is what we have atm. radeon/r200_context.c: if (major == 1 minor 13) printf(boho no hyperz for you\n) } if (minor =15) // major check anyone ? r_context.texmicrotile = true; // unused since 2009 ccf7814a315(radeon: major cleanups removing old dead codepaths.) radeon_screen.c: if (major = 2) drmCommandReadWrite(DRM_RADEON_INFO) else drmCommandReadWrite(DRM_RADEON_GETPARAM) Considering the amdgpu work (major number), I think we can just error out if major !=2 and cleanup the above ? Cheers, Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC] loader: libudev vs sysfs vs libdrm
On 8 July 2015 at 18:35, Eric Anholt e...@anholt.net wrote: Emil Velikov emil.l.veli...@gmail.com writes: Hello all, A recent patch by Chris, fixing some libudev fun in our loader, made me think if we can clear it up a bit. Having three different ways of retrieving the vendor/device ID does feel a bit excessive. Plus as one gets fixed others are likely to break - and they do. So here is a summary of each method, from portability POV. - libudev: widely common across Linux distributions (but not all). - sysfs: written by Gary Wong to target GNU Hurd and *BSD. The *BSD folk never got to using it though :-\ Huh? There's no sysfs on BSD. I actually don't see a reason for this path to exist, unless we wanted to drop libudev entirely. We should pick one of these two, certainly. There seems to be a libudev equivalent (but not identical from our POV) for *BSD as is some sysfs work. Don't think that either one is baked enough atm. - libdrm: used as a last resource fall-back after the above two. the sole option used by *BSD, MacOS and Android. libdrm seems like a nice middle ground that can be used everywhere. Which begs the question: from a technical POV, is there any advantage/disadvantage of using one over the other ? This use the kernel driver name thing is a bad hack, without some mapping in userspace from kernel driver name to userspace driver name. It's a hack that non-pci are relying on so far, though. Knowing how Winbooze has handled this policy, I agree with you here. Yet something is amiss. Am I reading the code correctly or are the three methods are for retrieving the vendor/device ID? The kernel driver name does not (seem to) pay any role in determining the dri module name. The mapping from device/vendor IDs the common code. Thanks Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 19/19] st/mesa: enable shader subroutine
Should expose that only if hw has glsl 130 support? Roland Am 09.07.2015 um 09:17 schrieb Dave Airlie: From: Dave Airlie airl...@redhat.com I'm not sure if we shouldn't enable this everywhere and rip out the API checks, discuss, Signed-off-by: Dave Airlie airl...@redhat.com --- src/mesa/state_tracker/st_extensions.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/state_tracker/st_extensions.c b/src/mesa/state_tracker/st_extensions.c index b1057f3..3b828fa 100644 --- a/src/mesa/state_tracker/st_extensions.c +++ b/src/mesa/state_tracker/st_extensions.c @@ -598,6 +598,7 @@ void st_init_extensions(struct pipe_screen *screen, extensions-ARB_half_float_vertex = GL_TRUE; extensions-ARB_internalformat_query = GL_TRUE; extensions-ARB_map_buffer_range = GL_TRUE; + extensions-ARB_shader_subroutine = GL_TRUE; extensions-ARB_texture_border_clamp = GL_TRUE; /* XXX temp */ extensions-ARB_texture_cube_map = GL_TRUE; extensions-ARB_texture_env_combine = GL_TRUE; ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2] i965/fs: Don't use the pixel interpolater for centroid interpolation
For centroid interpolation we can just directly use the values set up
in the shader payload instead of querying the pixel interpolator. To
do this we need to modify brw_compute_barycentric_interp_modes to
detect when interpolateAtCentroid is called.
v2: Rebase on top of changes to set the pulls bary bit on SKL
---
As an aside, I was deliberating over whether to call the function
set_up_blah instead of setup_blah because I think the former is more
correct. The rest of Mesa seems to use setup so maybe it's more
important to be consistent than correct.
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 52 +++---
src/mesa/drivers/dri/i965/brw_wm.c | 55
2 files changed, 88 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 5d1ea21..fd7f1b8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1238,6 +1238,25 @@ fs_visitor::emit_percomp(const fs_builder bld, const
fs_inst inst,
}
}
+/* For most messages, we need one reg of ignored data; the hardware requires
+ * mlen==1 even when there is no payload. in the per-slot offset case, we'll
+ * replace this with the proper source data.
+ */
+static void
+setup_pixel_interpolater_instruction(fs_visitor *v,
+ nir_intrinsic_instr *instr,
+ fs_inst *inst,
+ int mlen = 1)
+{
+ inst-mlen = mlen;
+ inst-regs_written = 2 * v-dispatch_width / 8;
+ inst-pi_noperspective = instr-variables[0]-var-data.interpolation ==
+ INTERP_QUALIFIER_NOPERSPECTIVE;
+
+ assert(v-stage == MESA_SHADER_FRAGMENT);
+ ((struct brw_wm_prog_data *) v-prog_data)-pulls_bary = true;
+}
+
void
fs_visitor::nir_emit_intrinsic(const fs_builder bld, nir_intrinsic_instr
*instr)
{
@@ -1482,25 +1501,23 @@ fs_visitor::nir_emit_intrinsic(const fs_builder bld,
nir_intrinsic_instr *instr
case nir_intrinsic_interp_var_at_centroid:
case nir_intrinsic_interp_var_at_sample:
case nir_intrinsic_interp_var_at_offset: {
- assert(stage == MESA_SHADER_FRAGMENT);
-
- ((struct brw_wm_prog_data *) prog_data)-pulls_bary = true;
-
fs_reg dst_xy = bld.vgrf(BRW_REGISTER_TYPE_F, 2);
- /* For most messages, we need one reg of ignored data; the hardware
- * requires mlen==1 even when there is no payload. in the per-slot
- * offset case, we'll replace this with the proper source data.
- */
fs_reg src = vgrf(glsl_type::float_type);
- int mlen = 1; /* one reg unless overriden */
fs_inst *inst;
switch (instr-intrinsic) {
- case nir_intrinsic_interp_var_at_centroid:
- inst = bld.emit(FS_OPCODE_INTERPOLATE_AT_CENTROID,
- dst_xy, src, fs_reg(0u));
+ case nir_intrinsic_interp_var_at_centroid: {
+ enum brw_wm_barycentric_interp_mode interp_mode;
+ if (instr-variables[0]-var-data.interpolation ==
+ INTERP_QUALIFIER_NOPERSPECTIVE)
+interp_mode = BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC;
+ else
+interp_mode = BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC;
+ uint8_t reg = payload.barycentric_coord_reg[interp_mode];
+ dst_xy = fs_reg(brw_vec16_grf(reg, 0));
break;
+ }
case nir_intrinsic_interp_var_at_sample: {
/* XXX: We should probably handle non-constant sample id's */
@@ -1509,6 +1526,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder bld,
nir_intrinsic_instr *instr
unsigned msg_data = const_sample ? const_sample-i[0] 4 : 0;
inst = bld.emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE, dst_xy, src,
fs_reg(msg_data));
+ setup_pixel_interpolater_instruction(this, instr, inst);
break;
}
@@ -1521,6 +1539,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder bld,
nir_intrinsic_instr *instr
inst = bld.emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, dst_xy,
src,
fs_reg(off_x | (off_y 4)));
+setup_pixel_interpolater_instruction(this, instr, inst);
} else {
src = vgrf(glsl_type::ivec2_type);
fs_reg offset_src = retype(get_nir_src(instr-src[0]),
@@ -1550,9 +1569,10 @@ fs_visitor::nir_emit_intrinsic(const fs_builder bld,
nir_intrinsic_instr *instr
bld.SEL(offset(src, bld, i), itemp, fs_reg(7)));
}
-mlen = 2 * dispatch_width / 8;
inst = bld.emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET, dst_xy,
src,
fs_reg(0u));
+setup_pixel_interpolater_instruction(this, instr, inst,
+ 2 * dispatch_width / 8);
}
break;
}
@@ -1561,12 +1581,6 @@
Re: [Mesa-dev] [RFC] loader: libudev vs sysfs vs libdrm
On 8 July 2015 at 18:55, Axel Davy axel.d...@ens.fr wrote: On 08/07/2015 00:15, Emil Velikov wrote : Can anyone shed a light/cast their 2c ? Thanks Emil ___ The DRI3/Wayland/Gallium Nine DRI_PRIME path uses libudev, and I'm not sure it could work without. It is based on the ID_PATH_TAG advertised by udev with the device. Perhaps there is another way to compute that tag though. Yakes forgot about that one. From a quick look we can (I know it feels durty) use readlink( /sys/dev/char/$(major):$(minor)). Everything seems to be there - bus type and exact location of the device on the bus. It's limited to sysfs users, but they are more than the libudev ones (perhaps not by much). How does that sound ? Cheers, Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 03/11] radeon: remove dri_mirror state
On 9 July 2015 at 14:16, Marek Olšák mar...@gmail.com wrote: major != 2 can't occur. You don't have to check the major version at all and you can just assume it's always 2. That's even better than expected. Thanks ! -Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] i965: Support importing R8 and GR88 dma_bufs
On 9 July 2015 at 09:39, Chad Versace chad.vers...@intel.com wrote: EGL_EXT_image_dma_buf_import now supports those formats. Do I have an old version of it (v6) or I simply cannot see those listed ? Thanks Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC] Compatibility between old dri modules and new loaders, and vice verse
On 30 June 2015 at 16:29, Emil Velikov emil.l.veli...@gmail.com wrote:
On 22 June 2015 at 23:19, Dave Airlie airl...@gmail.com wrote:
On 23 June 2015 at 08:16, Ian Romanick i...@freedesktop.org wrote:
On 06/22/2015 11:54 AM, Dave Airlie wrote:
As kindly hinted by Marek, currently we do have a wide selection of
supported dri loader combinations.
Although we like to think that things never break, we have to admit
that not many of us test every possible combinations of dri modules
and loaders. With the chances getting smaller as the time gap (age)
between the two increases. As such I would like to ask if we're
interested in gradually depreciating as the gap grows beyond X years.
The rough idea that I have in my mind is:
- Check for obsolete extensions (requirements for such) - both in the
dri modules and the loaders (including the xserver).
- Add some WARN messages (You're using an old loader/DRI module.
Update to XXX or later) when such code path is hit.
- After X mesa releases, we remove the dri extension from the
module(s) and bump the requirement(s) in the loader(s).
And now the more important question why ?
- Very rarely tested and not actively supported - if it works it
works, we only cover one stable branch.
- Having a quick look at the the if extension extension.version
= y maze does leave most of us speechless.
- Will allow us to start removing a few of the nasty quirks/hacks
that we currently have laying around.
Worth mentioning:
- Depreciation period will be based on the longest time frame set by
LTS versions of distros. For example if Debian A ships X and mesa 3
years apart, while Ubuntu does is ~2.5 and RedHat ~2.8, we'll stick
with 3 years.
- libGL dri1 support... it's been almost four years since the removal
of the dri1 modules. Since then the only activity that I've noticed by
Connor Behan on the r128 front. Although it seems that he has covered
the ddx and is just looking at the kernel side of things. Should we
consider mesa X (10.6 ?) as the last one that supports such old
modules in it's libGL and give it a much needed cleanup ?
How would people feel about this - do we have any strong ack/nack
about the idea ? Are there many people/companies that support distros
where the xserver mesa gap is over, say 2 years ?
We still ship 7.11 based dri1 drivers in RHEL6, and there is still a
chance of us rebasing to newer Mesa in that depending on schedules.
ajax might have a different opinion, on how likely that is, but
that would be at least another year from now where we'd want DRI1
to work.
OK, so DRI1 support for libGL is here to say (a little bit more).
A time line would be good. I think it will take a fair amount of time
to get a new loaderdriver interface in order. If we can't change
anything for two years, then there's not a lot of point to thinking
about it now. If it's a year or less away, that's a different story.
The other possibility would be for RHEL to ship more than one libGL...
one for DRI1 drivers and one for everything else. I don't know how
horrible that would be.
That would worse than impossible, it's bad enough nvidia overwrite
libGL I don't want us to do it as well to ourselves :-)
Perhaps we can think about new interface when the vendor neutral GL
comes around. Until then we can try cleaning up the existing code ?
There is some ~120 lines of spaghetti code that we can nuke from
libEGL/libgbm, not to mention
- libGL could shed a similar amount
- we can drop the nasty symbol hacks - dlopen(libGL/libglapi.so, RTLD_GLOBAL)
- replace the explicit glFlush from libEGL with flush_with_flags()
- remove unused extensions in the DRI modules.
To iterate, the above proposal is to remove support for things that
barely anyone uses nowadays - i.e. mixing dri modules with loader(s)
that are couple of years apart. Alternatively can someone come forward
if they're using/testing/supporting such setups (barring DRI1) ?
Anyone ? For further enjoyment, Boyan has pointed out that the
systemTimeExtension has found its way into glx/dri{sw,2,3}.
I'm suspecting that this DRI1 extension has been blindly copy/pasted
around it never had any users outside of the old dri1 modules.
Cheers,
Emil
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Re: [Mesa-dev] [PATCH] i965/fs: Reimplement nir_op_uadd_carry and _usub_borrow without accumulator.
FYI there's already a lowering pass that does this in the GLSL IR
(CARRY_TO_ARITH in lower_instructions). Perhaps the right place to do
this is NIR though, just wanted to let you know.
On Thu, Jul 9, 2015 at 3:51 PM, Francisco Jerez curroje...@riseup.net wrote:
This gets rid of two no16() fall-backs and should allow better
scheduling of the generated IR. There are no uses of usubBorrow() or
uaddCarry() in shader-db so no changes are expected. However the
arb_gpu_shader5/execution/built-in-functions/fs-usubBorrow and
arb_gpu_shader5/execution/built-in-functions/fs-uaddCarry piglit
tests go from 40 to 28 instructions. The reason is that the plain ADD
instruction can easily be CSE'ed with the original addition, and the
negation can easily be propagated into the source modifier of another
instruction, so effectively both operations can be performed with just
one instruction.
No piglit regressions.
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 33
+---
1 file changed, 13 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 6d9e9d3..3b6aa0a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -829,29 +829,22 @@ fs_visitor::nir_emit_alu(const fs_builder bld,
nir_alu_instr *instr)
bld.emit(SHADER_OPCODE_INT_QUOTIENT, result, op[0], op[1]);
break;
- case nir_op_uadd_carry: {
- if (devinfo-gen = 7)
- no16(SIMD16 explicit accumulator operands unsupported\n);
-
- struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
- BRW_REGISTER_TYPE_UD);
-
- bld.ADDC(bld.null_reg_ud(), op[0], op[1]);
- bld.MOV(result, fs_reg(acc));
+ case nir_op_uadd_carry:
+ /* Use signed operands for the ADD to be easily CSE'ed with the
original
+ * addition (e.g. in case we're implementing the uaddCarry() GLSL
+ * built-in).
+ */
+ bld.ADD(result, retype(op[0], BRW_REGISTER_TYPE_D),
+ retype(op[1], BRW_REGISTER_TYPE_D));
+ bld.CMP(result, retype(result, BRW_REGISTER_TYPE_UD), op[0],
+ BRW_CONDITIONAL_L);
+ bld.MOV(result, negate(result));
break;
- }
- case nir_op_usub_borrow: {
- if (devinfo-gen = 7)
- no16(SIMD16 explicit accumulator operands unsupported\n);
-
- struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
- BRW_REGISTER_TYPE_UD);
-
- bld.SUBB(bld.null_reg_ud(), op[0], op[1]);
- bld.MOV(result, fs_reg(acc));
+ case nir_op_usub_borrow:
+ bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_L);
+ bld.MOV(result, negate(result));
break;
- }
case nir_op_umod:
bld.emit(SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]);
--
2.4.3
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Re: [Mesa-dev] [RFC] gallium: add interface for writable shader images
I'd like to discuss one more thing that will affect whether image slots will be global (shared by all shaders) or not. Which image unit an image uniform uses is not a compile-time thing, but it's specified later using glUniform1i. That means we need a per-shader table that maps image uniforms to global image units. One possible solution is to add this pipe_context function: void (*set_shader_image_mapping)( struct pipe_context *, unsigned shader, unsigned start_decl_index, unsigned count, unsigned *decl_to_slot_mapping); This is only required if the shader image slots are global and not per-shader. (if they are per-shader, st/mesa can reorder the slots for each shader independently just like it already does for textures and UBOs) Shader storage buffer objects suffer from the same issue. Atomic counters don't. Therefore, image slots must be per-shader (like sampler slots) to avoid this craziness and keep things simple. Marek On Tue, Jul 7, 2015 at 10:49 PM, Roland Scheidegger srol...@vmware.com wrote: Am 07.07.2015 um 22:35 schrieb Jose Fonseca: On 07/07/15 21:28, Ilia Mirkin wrote: On Tue, Jul 7, 2015 at 4:24 PM, Jose Fonseca jfons...@vmware.com wrote: I'm not experienced with the semantics around resources that can be read/written by shaders, so I can't really make educated comments. But overall this looks good to me FWIW. On 05/07/15 14:25, Marek Olšák wrote: From: Marek Olšák marek.ol...@amd.com Other approaches are being considered: 1) Don't use resource wrappers (views) and pass all view parameters (format, layer range, level) to set_shader_images just like set_vertex_buffers, set_constant_buffer, or even glBindImageTexture do. I don't know how much pipe drivers leverage this nowadays, but these structures are convenient placeholders for driver data, particular when they don't support something (e.g., a certain format, or need some swizzling), natively. 2) Use pipe_sampler_view instead of pipe_image_view, and maybe even use set_sampler_views instead of set_shader_images. set_sampler_views would have to use start_slot = PIPE_MAX_SAMPLERS for all writable images to allow for OpenGL textures in the lower slots. If pipe_sampler_view and pipe_image_view are the same, we could indeed use one structure for both. While still keeping the separate create/bind/destroy functions. The big difference is that a sampler view has a first/last layer and first/last level, while image views are more like surfaces which just have the one of each. But they also need a byte range for buffer images. D3D11_TEX2D_ARRAY_UAV allows to specify first/last layer https://msdn.microsoft.com/en-us/library/windows/desktop/ff476242.aspx , so it sounds that once pipe_image_view is updated to handle D3D11, the difference would reduce to the absence of last_level Of course we could just ignore that and guarantee that first==last for images. Yes, it might not be a bad idea. You could of course argue then isn't it really more like pipe_surface? At least in d3d11 clearly they are much closer in concept to rts. The actual structures are of course mostly the same in gallium, the differences boil down to pipe_surface having (long obsolete) width/height parameters and a writable flag, whereas sampler views instead have swizzling fields (I don't think they'd have any use for this), support multiple levels (again, not needed for shader images / uavs), and have a target parameter (in d3d10, rts actually have a target parameter too, but it is of no practical consequence, hence there was no need for that in gallium - I'm not sure if it would be required for shader images / uavs, uavs certainly have such target parameter too but I'm not sure it matters). But in any case, I'm pretty impartial to what structure is used, as long as it is created/destroyed separately. Roland ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 09/19] glsl/ir: add subroutine information storage to ir_function (v1.1)
Do you really need is_subroutine_def ? It seems redundant with
num_subroutine_types0.
On Thu, Jul 9, 2015 at 7:17 PM, Dave Airlie airl...@gmail.com wrote:
From: Dave Airlie airl...@redhat.com
We need to store two sets of info into the ir_function,
if this is a function definition with a subroutine list
(subroutine_def) or if it a subroutine prototype.
v1.1: add some more documentation.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/ir.cpp | 4
src/glsl/ir.h | 16
src/glsl/ir_clone.cpp | 7 +++
src/glsl/ir_print_visitor.cpp | 2 +-
4 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/src/glsl/ir.cpp b/src/glsl/ir.cpp
index 38a5e2a..2fbc631 100644
--- a/src/glsl/ir.cpp
+++ b/src/glsl/ir.cpp
@@ -1853,6 +1853,7 @@ static void
steal_memory(ir_instruction *ir, void *new_ctx)
{
ir_variable *var = ir-as_variable();
+ ir_function *fn = ir-as_function();
ir_constant *constant = ir-as_constant();
if (var != NULL var-constant_value != NULL)
steal_memory(var-constant_value, ir);
@@ -1860,6 +1861,9 @@ steal_memory(ir_instruction *ir, void *new_ctx)
if (var != NULL var-constant_initializer != NULL)
steal_memory(var-constant_initializer, ir);
+ if (fn != NULL fn-subroutine_types)
+ ralloc_steal(new_ctx, fn-subroutine_types);
+
/* The components of aggregate constants are not visited by the normal
* visitor, so steal their values by hand.
*/
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 092c96b..b5a9e99 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -1121,6 +1121,22 @@ public:
* List of ir_function_signature for each overloaded function with this
name.
*/
struct exec_list signatures;
+
+ /**
+* is this function a subroutine type declaration
+* e.g. subroutine void type1(float arg1);
+*/
+ bool is_subroutine;
+
+ /**
+* is this function associated to a subroutine type
+* e.g. subroutine (type1, type2) function_name { function_body };
+* would have this flag set and num_subroutine_types 2,
+* and pointers to the type1 and type2 types.
+*/
+ bool is_subroutine_def;
+ int num_subroutine_types;
+ const struct glsl_type **subroutine_types;
};
inline const char *ir_function_signature::function_name() const
diff --git a/src/glsl/ir_clone.cpp b/src/glsl/ir_clone.cpp
index 49834ff..bf25d6c 100644
--- a/src/glsl/ir_clone.cpp
+++ b/src/glsl/ir_clone.cpp
@@ -267,6 +267,13 @@ ir_function::clone(void *mem_ctx, struct hash_table *ht)
const
{
ir_function *copy = new(mem_ctx) ir_function(this-name);
+ copy-is_subroutine = this-is_subroutine;
+ copy-is_subroutine_def = this-is_subroutine_def;
+ copy-num_subroutine_types = this-num_subroutine_types;
+ copy-subroutine_types = ralloc_array(mem_ctx, const struct glsl_type *,
copy-num_subroutine_types);
+ for (int i = 0; i copy-num_subroutine_types; i++)
+ copy-subroutine_types[i] = this-subroutine_types[i];
+
foreach_in_list(const ir_function_signature, sig, this-signatures) {
ir_function_signature *sig_copy = sig-clone(mem_ctx, ht);
copy-add_signature(sig_copy);
diff --git a/src/glsl/ir_print_visitor.cpp b/src/glsl/ir_print_visitor.cpp
index 4cbcad4..f210175 100644
--- a/src/glsl/ir_print_visitor.cpp
+++ b/src/glsl/ir_print_visitor.cpp
@@ -229,7 +229,7 @@ void ir_print_visitor::visit(ir_function_signature *ir)
void ir_print_visitor::visit(ir_function *ir)
{
- fprintf(f, (function %s\n, ir-name);
+ fprintf(f, (%s function %s\n, ir-is_subroutine ? subroutine : ,
ir-name);
indentation++;
foreach_in_list(ir_function_signature, sig, ir-signatures) {
indent();
--
2.4.3
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Re: [Mesa-dev] [RFC] loader: libudev vs sysfs vs libdrm
On 09/07/15 15:40, Axel Davy wrote: On 09/07/2015 15:33, Emil Velikov wrote : Yakes forgot about that one. From a quick look we can (I know it feels durty) use readlink( /sys/dev/char/$(major):$(minor)). Everything seems to be there - bus type and exact location of the device on the bus. It's limited to sysfs users, but they are more than the libudev ones (perhaps not by much). How does that sound ? Cheers, Emil The idea behind using udev for the tag was that arbitrary tag could be used, especially to identify usb devices. So avoid breaking peoples' setup the above example can be used to produce the very same tag(s). Regardles if it's a device on the pci or usb bus. Speaking of usb, are there any devices supported with upstream mesa ? -Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC] gallium: add interface for writable shader images
On Thu, Jul 9, 2015 at 5:05 PM, Marek Olšák mar...@gmail.com wrote: I'd like to discuss one more thing that will affect whether image slots will be global (shared by all shaders) or not. Which image unit an image uniform uses is not a compile-time thing, but it's specified later using glUniform1i. That means we need a per-shader table that maps image uniforms to global image units. One possible solution is to add this pipe_context function: void (*set_shader_image_mapping)( struct pipe_context *, unsigned shader, unsigned start_decl_index, unsigned count, unsigned *decl_to_slot_mapping); This is only required if the shader image slots are global and not per-shader. (if they are per-shader, st/mesa can reorder the slots for each shader independently just like it already does for textures and UBOs) Shader storage buffer objects suffer from the same issue. Atomic counters don't. Therefore, image slots must be per-shader (like sampler slots) to avoid this craziness and keep things simple. I think that's reasonable. The image slots can be fixed at compile-time (like sampler slots), and we can just stick the right images into the right places. But in order to do that, we need the per-stage mapping, so making it like sampler views seems reasonable. -ilia ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 4/4] droi/common: remove unused drm_version variable
As of last commit the only user of it (radeon/r200) no longer uses it.
As such let's remove it and cleanup the nasty hacks that we had in place
to support this.
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
configure.ac| 21 -
src/mesa/drivers/dri/common/Android.mk | 5 -
src/mesa/drivers/dri/common/Makefile.am | 7 ---
src/mesa/drivers/dri/common/SConscript | 2 --
src/mesa/drivers/dri/common/dri_util.c | 15 ---
src/mesa/drivers/dri/common/dri_util.h | 5 -
6 files changed, 55 deletions(-)
diff --git a/configure.ac b/configure.ac
index 98c57c3..9ffd69d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1375,26 +1375,6 @@ if test x$enable_dri = xyes; then
[AC_MSG_ERROR([Expat library required for DRI not
found])])
EXPAT_LIBS=-lexpat])
-DRICOMMON_NEED_LIBDRM=no
-# If we are building any DRI driver other than swrast.
-if test -n $with_dri_drivers; then
-if test x$with_dri_drivers != xswrast; then
-# ... libdrm is required
-if test x$have_libdrm != xyes; then
-AC_MSG_ERROR([DRI drivers requires libdrm = $LIBDRM_REQUIRED])
-fi
-DRICOMMON_NEED_LIBDRM=yes
-fi
-fi
-
-# If we're building any gallium DRI driver other than swrast
-if test -n $with_gallium_drivers -a x$DRICOMMON_NEED_LIBDRM = xno; then
-if test x$with_gallium_drivers != xswrast; then
-# ... build a libdrm aware dricommon
-DRICOMMON_NEED_LIBDRM=yes
-fi
-fi
-
# put all the necessary libs together
DRI_LIB_DEPS=$DRI_LIB_DEPS $SELINUX_LIBS $LIBDRM_LIBS $EXPAT_LIBS -lm
$PTHREAD_LIBS $DLOPEN_LIBS
fi
@@ -2283,7 +2263,6 @@ fi
AC_SUBST([ELF_LIB])
-AM_CONDITIONAL(DRICOMMON_NEED_LIBDRM, test x$DRICOMMON_NEED_LIBDRM = xyes)
AM_CONDITIONAL(HAVE_LIBDRM, test x$have_libdrm = xyes)
AM_CONDITIONAL(HAVE_X11_DRIVER, test x$enable_xlib_glx = xyes)
AM_CONDITIONAL(HAVE_OSMESA, test x$enable_osmesa = xyes)
diff --git a/src/mesa/drivers/dri/common/Android.mk
b/src/mesa/drivers/dri/common/Android.mk
index 6e29baf..f1a7330 100644
--- a/src/mesa/drivers/dri/common/Android.mk
+++ b/src/mesa/drivers/dri/common/Android.mk
@@ -43,11 +43,6 @@ LOCAL_EXPORT_C_INCLUDE_DIRS := \
$(LOCAL_PATH) \
$(intermediates)
-ifneq ($(filter-out swrast,$(MESA_GPU_DRIVERS)),)
-LOCAL_CFLAGS := -DHAVE_LIBDRM
-LOCAL_SHARED_LIBRARIES := libdrm
-endif
-
LOCAL_SRC_FILES := \
$(DRI_COMMON_FILES) \
$(XMLCONFIG_FILES)
diff --git a/src/mesa/drivers/dri/common/Makefile.am
b/src/mesa/drivers/dri/common/Makefile.am
index ee6c691..91ce43d 100644
--- a/src/mesa/drivers/dri/common/Makefile.am
+++ b/src/mesa/drivers/dri/common/Makefile.am
@@ -53,10 +53,3 @@ libdri_test_stubs_la_CFLAGS = $(AM_CFLAGS) -DNO_MAIN
libmegadriver_stub_la_SOURCES = $(megadriver_stub_FILES)
sysconf_DATA = drirc
-
-if DRICOMMON_NEED_LIBDRM
-AM_CFLAGS += $(LIBDRM_CFLAGS)
-libdricommon_la_LIBADD = $(LIBDRM_LIBS)
-else
-AM_CFLAGS += -UHAVE_LIBDRM
-endif
diff --git a/src/mesa/drivers/dri/common/SConscript
b/src/mesa/drivers/dri/common/SConscript
index adaac29..52d201f 100644
--- a/src/mesa/drivers/dri/common/SConscript
+++ b/src/mesa/drivers/dri/common/SConscript
@@ -32,8 +32,6 @@ drienv.AppendUnique(LIBS = [
'expat',
])
-drienv.PkgUseModules('DRM')
-
sources = drienv.ParseSourceList('Makefile.sources', ['DRI_COMMON_FILES',
'XMLCONFIG_FILES' ])
dri_common = drienv.ConvenienceLibrary(
diff --git a/src/mesa/drivers/dri/common/dri_util.c
b/src/mesa/drivers/dri/common/dri_util.c
index 100a727..884a7e0 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -40,9 +40,6 @@
#include stdbool.h
-#ifdef HAVE_LIBDRM
-#include xf86drm.h
-#endif
#include dri_util.h
#include utils.h
#include xmlpool.h
@@ -137,18 +134,6 @@ driCreateNewScreen2(int scrn, int fd,
setupLoaderExtensions(psp, extensions);
-#ifdef HAVE_LIBDRM
-if (fd != -1) {
- drmVersionPtr version = drmGetVersion(fd);
- if (version) {
- psp-drm_version.major = version-version_major;
- psp-drm_version.minor = version-version_minor;
- psp-drm_version.patch = version-version_patchlevel;
- drmFreeVersion(version);
- }
-}
-#endif
-
psp-loaderPrivate = data;
psp-extensions = emptyExtensionList;
diff --git a/src/mesa/drivers/dri/common/dri_util.h
b/src/mesa/drivers/dri/common/dri_util.h
index 1138bf1..6987f55 100644
--- a/src/mesa/drivers/dri/common/dri_util.h
+++ b/src/mesa/drivers/dri/common/dri_util.h
@@ -149,11 +149,6 @@ struct __DRIscreenRec {
int fd;
/**
- * DRM (kernel module) version information.
- */
-__DRIversion drm_version;
-
-/**
* Device-dependent private information (not stored in the SAREA).
*
* This pointer is never touched by the DRI layer.
--
2.4.5
[Mesa-dev] [PATCH v2] configure.ac: do not set HAVE_DRI(23) when libdrm is missing
These conditionals are used to guard both dri modules and loader(s). Currently if we try to build the gallium swrast dri module (without glx) on a system that's missing libdrm the build will fail. v2: Make sure we assign prior to checking the have_libdrm variable. Cc: 10.6 mesa-sta...@lists.freedesktop.org Signed-off-by: Emil Velikov emil.l.veli...@gmail.com --- configure.ac | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/configure.ac b/configure.ac index eb7180b..98c57c3 100644 --- a/configure.ac +++ b/configure.ac @@ -911,6 +911,13 @@ fi AM_CONDITIONAL(HAVE_DRI_GLX, test x$enable_glx = xyes -a \ x$enable_dri = xyes) +# Check for libdrm +PKG_CHECK_MODULES([LIBDRM], [libdrm = $LIBDRM_REQUIRED], + [have_libdrm=yes], [have_libdrm=no]) +if test x$have_libdrm = xyes; then + DEFINES=$DEFINES -DHAVE_LIBDRM +fi + # Select which platform-dependent DRI code gets built case $host_os in darwin*) @@ -923,8 +930,8 @@ esac AM_CONDITIONAL(HAVE_DRICOMMON, test x$enable_dri = xyes ) AM_CONDITIONAL(HAVE_DRISW, test x$enable_dri = xyes ) -AM_CONDITIONAL(HAVE_DRI2, test x$enable_dri = xyes -a x$dri_platform = xdrm ) -AM_CONDITIONAL(HAVE_DRI3, test x$enable_dri3 = xyes -a x$dri_platform = xdrm ) +AM_CONDITIONAL(HAVE_DRI2, test x$enable_dri = xyes -a x$dri_platform = xdrm -a x$have_libdrm = xyes ) +AM_CONDITIONAL(HAVE_DRI3, test x$enable_dri3 = xyes -a x$dri_platform = xdrm -a x$have_libdrm = xyes ) AM_CONDITIONAL(HAVE_APPLEDRI, test x$enable_dri = xyes -a x$dri_platform = xapple ) AC_ARG_ENABLE([shared-glapi], @@ -1112,13 +1119,6 @@ if test x$with_sha1 = x; then fi AM_CONDITIONAL([ENABLE_SHADER_CACHE], [test x$enable_shader_cache = xyes]) -# Check for libdrm -PKG_CHECK_MODULES([LIBDRM], [libdrm = $LIBDRM_REQUIRED], - [have_libdrm=yes], [have_libdrm=no]) -if test x$have_libdrm = xyes; then - DEFINES=$DEFINES -DHAVE_LIBDRM -fi - case $host_os in linux*) need_pci_id=yes ;; -- 2.4.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] i965: Support importing R8 and GR88 dma_bufs
On 9 July 2015 at 21:21, Chad Versace chad.vers...@intel.com wrote: On Thu 09 Jul 2015, Emil Velikov wrote: On 9 July 2015 at 09:39, Chad Versace chad.vers...@intel.com wrote: EGL_EXT_image_dma_buf_import now supports those formats. Do I have an old version of it (v6) or I simply cannot see those listed ? I should have been more clear when I said EGL_EXT_image_dma_buf_import now supports those formats. I meant now supports those formats as of the previous patch. The EGL_EXT_image_dma_buf_import spec itself lists no DRM formats. v6 of the spec refers to drm_fourcc.h for formats by saying this: * EGL_LINUX_DRM_FOURCC_EXT: The pixel format of the buffer, as specified by drm_fourcc.h and used as the pixel_format parameter of the drm_mode_fb_cmd2 ioctl. I was blindly searching for DRI_IMAGE_FOURCC, silly me. Thank you for kindly pointing me in the correct direction. Afaics Gwenole sent out an identical set of patches ~an year ago, and they seems to have fallen through the cracks. -Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/fs: Reimplement nir_op_uadd_carry and _usub_borrow without accumulator.
Ilia Mirkin imir...@alum.mit.edu writes:
FYI there's already a lowering pass that does this in the GLSL IR
(CARRY_TO_ARITH in lower_instructions). Perhaps the right place to do
this is NIR though, just wanted to let you know.
Ah, I wasn't aware of that flag, that seems even better. I just tried
it and it seems to generate one instruction more per op than my assembly
code (apparently because our implementation of b2i is suboptimal, could
probably be fixed), but it would also work to get rid of the no16()
calls, which is all I care about right now.
I'll resend using your approach tomorrow.
On Thu, Jul 9, 2015 at 3:51 PM, Francisco Jerez curroje...@riseup.net wrote:
This gets rid of two no16() fall-backs and should allow better
scheduling of the generated IR. There are no uses of usubBorrow() or
uaddCarry() in shader-db so no changes are expected. However the
arb_gpu_shader5/execution/built-in-functions/fs-usubBorrow and
arb_gpu_shader5/execution/built-in-functions/fs-uaddCarry piglit
tests go from 40 to 28 instructions. The reason is that the plain ADD
instruction can easily be CSE'ed with the original addition, and the
negation can easily be propagated into the source modifier of another
instruction, so effectively both operations can be performed with just
one instruction.
No piglit regressions.
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 33
+---
1 file changed, 13 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 6d9e9d3..3b6aa0a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -829,29 +829,22 @@ fs_visitor::nir_emit_alu(const fs_builder bld,
nir_alu_instr *instr)
bld.emit(SHADER_OPCODE_INT_QUOTIENT, result, op[0], op[1]);
break;
- case nir_op_uadd_carry: {
- if (devinfo-gen = 7)
- no16(SIMD16 explicit accumulator operands unsupported\n);
-
- struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
- BRW_REGISTER_TYPE_UD);
-
- bld.ADDC(bld.null_reg_ud(), op[0], op[1]);
- bld.MOV(result, fs_reg(acc));
+ case nir_op_uadd_carry:
+ /* Use signed operands for the ADD to be easily CSE'ed with the
original
+ * addition (e.g. in case we're implementing the uaddCarry() GLSL
+ * built-in).
+ */
+ bld.ADD(result, retype(op[0], BRW_REGISTER_TYPE_D),
+ retype(op[1], BRW_REGISTER_TYPE_D));
+ bld.CMP(result, retype(result, BRW_REGISTER_TYPE_UD), op[0],
+ BRW_CONDITIONAL_L);
+ bld.MOV(result, negate(result));
break;
- }
- case nir_op_usub_borrow: {
- if (devinfo-gen = 7)
- no16(SIMD16 explicit accumulator operands unsupported\n);
-
- struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
- BRW_REGISTER_TYPE_UD);
-
- bld.SUBB(bld.null_reg_ud(), op[0], op[1]);
- bld.MOV(result, fs_reg(acc));
+ case nir_op_usub_borrow:
+ bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_L);
+ bld.MOV(result, negate(result));
break;
- }
case nir_op_umod:
bld.emit(SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]);
--
2.4.3
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Re: [Mesa-dev] [PATCH 04/11] dri_interface: drop __NOT_HAVE_DRM_H magic
On 9 July 2015 at 18:50, Ian Romanick i...@freedesktop.org wrote: On 07/08/2015 10:07 AM, Emil Velikov wrote: Signed-off-by: Emil Velikov emil.l.veli...@gmail.com --- include/GL/internal/dri_interface.h | 11 --- 1 file changed, 11 deletions(-) diff --git a/include/GL/internal/dri_interface.h b/include/GL/internal/dri_interface.h index c827bb6..c0545b1 100644 --- a/include/GL/internal/dri_interface.h +++ b/include/GL/internal/dri_interface.h @@ -40,20 +40,9 @@ #ifndef DRI_INTERFACE_H #define DRI_INTERFACE_H -/* For archs with no drm.h */ -#if defined(__APPLE__) || defined(__CYGWIN__) || defined(__GNU__) -#ifndef __NOT_HAVE_DRM_H -#define __NOT_HAVE_DRM_H -#endif -#endif - -#ifndef __NOT_HAVE_DRM_H Shouldn't this get changed to use HAVE_LIBDRM as in later patches? I thought about that, but that depends on if the versions of xserver that we care about define it. From a quick look that is not the case for older xservers, on the other hand drm* users which explicitly include drm.h. If others don't mind when/if things break, I'm fine using HAVE_LIBDRM here. I guess drm_context_t and drm_drawable_t are ABI, so they shouldn't ever change. It does feel a little icky to redefine them when not necessary. Yes it is rather nasty. Note that all of the junk is DRI1 stuff. I was thinking about nuking/moving it, but with the see the old dri loader new module, and vice versa topic still open, I've decided to leave thing as is. -Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 4/4] droi/common: remove unused drm_version variable
The title should obviously say dri/common: consider that fixed. Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [HACK] i965/fs: Fix rescale_texcoord() for SIMD16 and remove no16 fall-back.
Aside from the trivial GRF underallocation problem in the
devinfo-gen 6 is_rect if-block, the texrect scale uniform
look-up code was assuming a one-to-one mapping between UNIFORM
register indices and the param array, which only holds during the
SIMD8 run.
It seems dubious that this needs to manipulate the param array
directly even though it doesn't have a fixed meaning (all constants if
you're building SIMD8, push constants if you're building SIMD16). We
would probably be better off not using the ancient state token
tracking stuff which forces you to recompile the program anytime a
sampler uniform binding changes and doesn't work at all for
ARB_gpu_shader5-style variable indexing of samplers. Instead this
could be implemented like images do by passing sampler metadata
preemptively at a fixed offset from the sampler uniform that is later
on eliminated by the optimizer in case it's not needed.
This depends on another patch I sent a while ago i965/fs: Don't
overwrite fs_visitor::uniforms and ::param_size during the SIMD16
run. [1]. No piglit regressions.
[1] http://lists.freedesktop.org/archives/mesa-dev/2015-May/083484.html
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 23 +++
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 94d6a58..dcd2e4e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -708,17 +708,23 @@ fs_visitor::rescale_texcoord(fs_reg coordinate, int
coord_components,
0
};
- no16(rectangle scale uniform setup not supported on SIMD16\n);
- if (dispatch_width == 16) {
-return coordinate;
- }
-
GLuint index = _mesa_add_state_reference(params,
(gl_state_index *)tokens);
/* Try to find existing copies of the texrect scale uniforms. */
for (unsigned i = 0; i uniforms; i++) {
- if (stage_prog_data-param[i] ==
- prog-Parameters-ParameterValues[index][0]) {
+ /* Neat, there's an extra level of indirection between the fake
+ * UNIFORM file and the push/pull param arrays, but *only* during
+ * non-SIMD8 runs (i.e. SIMD16).
+ */
+ const gl_constant_value *param =
+(dispatch_width == 8 ? stage_prog_data-param[i] :
+ push_constant_loc[i] = 0 ?
+stage_prog_data-param[push_constant_loc[i]] :
+ pull_constant_loc[i] = 0 ?
+stage_prog_data-pull_param[pull_constant_loc[i]] :
+ NULL);
+
+ if (param == prog-Parameters-ParameterValues[index][0]) {
scale_x = fs_reg(UNIFORM, i);
scale_y = fs_reg(UNIFORM, i + 1);
break;
@@ -727,6 +733,7 @@ fs_visitor::rescale_texcoord(fs_reg coordinate, int
coord_components,
/* If we didn't already set them up, do so now. */
if (scale_x.file == BAD_FILE) {
+ assert(dispatch_width == 8);
scale_x = fs_reg(UNIFORM, uniforms);
scale_y = fs_reg(UNIFORM, uniforms + 1);
@@ -742,7 +749,7 @@ fs_visitor::rescale_texcoord(fs_reg coordinate, int
coord_components,
* tracking to get the scaling factor.
*/
if (devinfo-gen 6 is_rect) {
- fs_reg dst = fs_reg(GRF, alloc.allocate(coord_components));
+ fs_reg dst = bld.vgrf(BRW_REGISTER_TYPE_F, coord_components);
fs_reg src = coordinate;
coordinate = dst;
--
2.4.3
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Re: [Mesa-dev] [HACK] i965/fs: Fix ordering of src0 alpha and oMask in the framebuffer write payload.
On Jul 9, 2015 7:57 AM, Francisco Jerez curroje...@riseup.net wrote:
We were passing src0 alpha and oMask in reverse order. There seems to
be no good way to pass them in the correct order to the new-style
LOAD_PAYLOAD (how surprising) because src0 alpha is per-channel while
oMask is not. Just split src0 alpha in fixed-width registers and pass
them to LOAD_PAYLOAD as if they were part of the header as work-around
for now.
Bah... I came across this when I did the LOAD_PAYLOAD rework but thought it
was only theoretical. I wasn't very familiar with what omask actually did
and, since piglit didn't hit it, I wasn't sure if it was a real problem or
not. I probably should have done more digging and written a piglit test at
the time. My bad.
One solution that I proposed at the time was to turn header_size into
header_mask in the obvious way. We can still use 8 bits because we should
never have a header source higher than 8.
Thoughts?
--Jason
I've written a piglit test that demonstrates the problem by using
gl_SampleMask from a fragment shader with multiple color outputs [1].
[1] http://lists.freedesktop.org/archives/piglit/2015-July/016499.html
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 26
+-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 94d6a58..304ae74 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1535,6 +1535,19 @@ fs_visitor::emit_single_fb_write(const fs_builder
bld,
length++;
}
+ if (src0_alpha.file != BAD_FILE color0.file != BAD_FILE) {
+ /* Neat, we need to chop the src0 alpha component and pass it as
part of
+ * the header even though it has per-channel semantics, because
the next
+ * optional field is header-like and LOAD_PAYLOAD requires all such
+ * fields to form a contiguous segment at the beginning of the
message.
+ */
+ for (unsigned i = 0; i exec_size / 8; i++) {
+ setup_color_payload(sources[length], src0_alpha, 1, 8,
+ use_2nd_half || i == 1);
+ length++;
+ }
+ }
+
prog_data-uses_omask =
prog-OutputsWritten BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK);
if (prog_data-uses_omask) {
@@ -1561,19 +1574,14 @@ fs_visitor::emit_single_fb_write(const fs_builder
bld,
offset(this-outputs[0], bld, 3),
1, exec_size, false);
length += 4;
- } else if (color1.file == BAD_FILE) {
- if (src0_alpha.file != BAD_FILE) {
- setup_color_payload(sources[length], src0_alpha, 1, exec_size,
false);
- length++;
- }
-
- setup_color_payload(sources[length], color0, components,
- exec_size, use_2nd_half);
- length += 4;
} else {
setup_color_payload(sources[length], color0, components,
exec_size, use_2nd_half);
length += 4;
+
+ }
+
+ if (color1.file != BAD_FILE) {
setup_color_payload(sources[length], color1, components,
exec_size, use_2nd_half);
length += 4;
--
2.4.3
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[Mesa-dev] [PATCH] i965/fs: Reimplement nir_op_uadd_carry and _usub_borrow without accumulator.
This gets rid of two no16() fall-backs and should allow better
scheduling of the generated IR. There are no uses of usubBorrow() or
uaddCarry() in shader-db so no changes are expected. However the
arb_gpu_shader5/execution/built-in-functions/fs-usubBorrow and
arb_gpu_shader5/execution/built-in-functions/fs-uaddCarry piglit
tests go from 40 to 28 instructions. The reason is that the plain ADD
instruction can easily be CSE'ed with the original addition, and the
negation can easily be propagated into the source modifier of another
instruction, so effectively both operations can be performed with just
one instruction.
No piglit regressions.
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 33 +---
1 file changed, 13 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 6d9e9d3..3b6aa0a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -829,29 +829,22 @@ fs_visitor::nir_emit_alu(const fs_builder bld,
nir_alu_instr *instr)
bld.emit(SHADER_OPCODE_INT_QUOTIENT, result, op[0], op[1]);
break;
- case nir_op_uadd_carry: {
- if (devinfo-gen = 7)
- no16(SIMD16 explicit accumulator operands unsupported\n);
-
- struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
- BRW_REGISTER_TYPE_UD);
-
- bld.ADDC(bld.null_reg_ud(), op[0], op[1]);
- bld.MOV(result, fs_reg(acc));
+ case nir_op_uadd_carry:
+ /* Use signed operands for the ADD to be easily CSE'ed with the original
+ * addition (e.g. in case we're implementing the uaddCarry() GLSL
+ * built-in).
+ */
+ bld.ADD(result, retype(op[0], BRW_REGISTER_TYPE_D),
+ retype(op[1], BRW_REGISTER_TYPE_D));
+ bld.CMP(result, retype(result, BRW_REGISTER_TYPE_UD), op[0],
+ BRW_CONDITIONAL_L);
+ bld.MOV(result, negate(result));
break;
- }
- case nir_op_usub_borrow: {
- if (devinfo-gen = 7)
- no16(SIMD16 explicit accumulator operands unsupported\n);
-
- struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
- BRW_REGISTER_TYPE_UD);
-
- bld.SUBB(bld.null_reg_ud(), op[0], op[1]);
- bld.MOV(result, fs_reg(acc));
+ case nir_op_usub_borrow:
+ bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_L);
+ bld.MOV(result, negate(result));
break;
- }
case nir_op_umod:
bld.emit(SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]);
--
2.4.3
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[Mesa-dev] [PATCH 3/4] radeon, r200: allow hyperz for radeon DRM module v2
The original code only half considered hyperz as an option. As per
previous commit major != 2 cannot occur we can simply things, and
allow users to set the option if they choose to do so.
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/mesa/drivers/dri/r200/r200_context.c | 10 ++
src/mesa/drivers/dri/radeon/radeon_context.c | 9 ++---
2 files changed, 4 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/r200/r200_context.c
b/src/mesa/drivers/dri/r200/r200_context.c
index 40cc50a..2a42ab3 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -225,14 +225,8 @@ GLboolean r200CreateContext( gl_api api,
rmesa-radeon.initialMaxAnisotropy =
driQueryOptionf(rmesa-radeon.optionCache,
def_max_anisotropy);
- if ( sPriv-drm_version.major == 1
-driQueryOptionb( rmesa-radeon.optionCache, hyperz ) ) {
- if ( sPriv-drm_version.minor 13 )
-fprintf( stderr, DRM version 1.%d too old to support HyperZ,
- disabling.\n, sPriv-drm_version.minor );
- else
-rmesa-using_hyperz = GL_TRUE;
- }
+ if (driQueryOptionb( rmesa-radeon.optionCache, hyperz))
+ rmesa-using_hyperz = GL_TRUE;
/* Init default driver functions then plug in our R200-specific functions
* (the texture functions are especially important)
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c
b/src/mesa/drivers/dri/radeon/radeon_context.c
index edb154c..a9e2ab5 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -191,13 +191,8 @@ r100CreateContext( gl_api api,
rmesa-radeon.initialMaxAnisotropy =
driQueryOptionf(rmesa-radeon.optionCache,
def_max_anisotropy);
- if ( driQueryOptionb( rmesa-radeon.optionCache, hyperz ) ) {
- if ( sPriv-drm_version.minor 13 )
-fprintf( stderr, DRM version 1.%d too old to support HyperZ,
- disabling.\n, sPriv-drm_version.minor );
- else
-rmesa-using_hyperz = GL_TRUE;
- }
+ if (driQueryOptionb(rmesa-radeon.optionCache, hyperz))
+ rmesa-using_hyperz = GL_TRUE;
/* Init default driver functions then plug in our Radeon-specific functions
* (the texture functions are especially important)
--
2.4.5
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[Mesa-dev] [PATCH 1/4] radeon, r200: remove unused variable texmicrotile
Dead since at least 2009 with commit ccf7814a315(radeon: major cleanups
removing old dead codepaths.)
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/mesa/drivers/dri/r200/r200_context.c | 3 ---
src/mesa/drivers/dri/r200/r200_context.h | 1 -
src/mesa/drivers/dri/radeon/radeon_context.c | 3 ---
src/mesa/drivers/dri/radeon/radeon_context.h | 1 -
4 files changed, 8 deletions(-)
diff --git a/src/mesa/drivers/dri/r200/r200_context.c
b/src/mesa/drivers/dri/r200/r200_context.c
index fb15082..40cc50a 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -234,9 +234,6 @@ GLboolean r200CreateContext( gl_api api,
rmesa-using_hyperz = GL_TRUE;
}
- if ( sPriv-drm_version.minor = 15 )
- rmesa-texmicrotile = GL_TRUE;
-
/* Init default driver functions then plug in our R200-specific functions
* (the texture functions are especially important)
*/
diff --git a/src/mesa/drivers/dri/r200/r200_context.h
b/src/mesa/drivers/dri/r200/r200_context.h
index eb498f7..2ca1c7a 100644
--- a/src/mesa/drivers/dri/r200/r200_context.h
+++ b/src/mesa/drivers/dri/r200/r200_context.h
@@ -618,7 +618,6 @@ struct r200_context {
struct r200_swtcl_info swtcl;
GLboolean using_hyperz;
- GLboolean texmicrotile;
struct ati_fragment_shader *afs_loaded;
};
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c
b/src/mesa/drivers/dri/radeon/radeon_context.c
index d4d1935..edb154c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -199,9 +199,6 @@ r100CreateContext( gl_api api,
rmesa-using_hyperz = GL_TRUE;
}
- if ( sPriv-drm_version.minor = 15 )
- rmesa-texmicrotile = GL_TRUE;
-
/* Init default driver functions then plug in our Radeon-specific functions
* (the texture functions are especially important)
*/
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h
b/src/mesa/drivers/dri/radeon/radeon_context.h
index 4032532..badabd9 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_context.h
@@ -426,7 +426,6 @@ struct r100_context {
struct r100_swtcl_info swtcl;
GLboolean using_hyperz;
- GLboolean texmicrotile;
/* Performance counters
*/
--
2.4.5
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[Mesa-dev] [PATCH 2/4] radeon, r200: remove support for UMS radeon DRM module
As mentioned by Michel Dänzer
FWIW though, any code which is specific to radeon DRM major version 1
can be removed, because that's the UMS major version.
and Marek Olšák
major != 2 can't occur. You don't have to check the major version at
all and you can just assume it's always 2.
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/mesa/drivers/dri/radeon/radeon_screen.c | 44 +++--
1 file changed, 17 insertions(+), 27 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c
b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 45d9b2b..98b4741 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -135,36 +135,26 @@ DRI_CONF_END
static int
radeonGetParam(__DRIscreen *sPriv, int param, void *value)
{
- int ret;
- drm_radeon_getparam_t gp = { 0 };
struct drm_radeon_info info = { 0 };
- if (sPriv-drm_version.major = 2) {
- info.value = (uint64_t)(uintptr_t)value;
- switch (param) {
- case RADEON_PARAM_DEVICE_ID:
- info.request = RADEON_INFO_DEVICE_ID;
- break;
- case RADEON_PARAM_NUM_GB_PIPES:
- info.request = RADEON_INFO_NUM_GB_PIPES;
- break;
- case RADEON_PARAM_NUM_Z_PIPES:
- info.request = RADEON_INFO_NUM_Z_PIPES;
- break;
- case RADEON_INFO_TILE_CONFIG:
- info.request = RADEON_INFO_TILE_CONFIG;
- break;
- default:
- return -EINVAL;
- }
- ret = drmCommandWriteRead(sPriv-fd, DRM_RADEON_INFO, info,
sizeof(info));
- } else {
- gp.param = param;
- gp.value = value;
-
- ret = drmCommandWriteRead(sPriv-fd, DRM_RADEON_GETPARAM, gp,
sizeof(gp));
+ info.value = (uint64_t)(uintptr_t)value;
+ switch (param) {
+ case RADEON_PARAM_DEVICE_ID:
+info.request = RADEON_INFO_DEVICE_ID;
+break;
+ case RADEON_PARAM_NUM_GB_PIPES:
+info.request = RADEON_INFO_NUM_GB_PIPES;
+break;
+ case RADEON_PARAM_NUM_Z_PIPES:
+info.request = RADEON_INFO_NUM_Z_PIPES;
+break;
+ case RADEON_INFO_TILE_CONFIG:
+info.request = RADEON_INFO_TILE_CONFIG;
+break;
+ default:
+return -EINVAL;
}
- return ret;
+ return drmCommandWriteRead(sPriv-fd, DRM_RADEON_INFO, info, sizeof(info));
}
#if defined(RADEON_R100)
--
2.4.5
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Re: [Mesa-dev] [PATCH 2/2] i965: Support importing R8 and GR88 dma_bufs
On Thu 09 Jul 2015, Emil Velikov wrote: On 9 July 2015 at 09:39, Chad Versace chad.vers...@intel.com wrote: EGL_EXT_image_dma_buf_import now supports those formats. Do I have an old version of it (v6) or I simply cannot see those listed ? I should have been more clear when I said EGL_EXT_image_dma_buf_import now supports those formats. I meant now supports those formats as of the previous patch. The EGL_EXT_image_dma_buf_import spec itself lists no DRM formats. v6 of the spec refers to drm_fourcc.h for formats by saying this: * EGL_LINUX_DRM_FOURCC_EXT: The pixel format of the buffer, as specified by drm_fourcc.h and used as the pixel_format parameter of the drm_mode_fb_cmd2 ioctl. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] [v2] i965: Split out gen8 push constant state upload
While implementing the workaround in the previous patch I noticed things were
starting to get a bit messy. Since gen8 works differently enough from gen7, I
thought splitting it out with be good.
While here, get rid of gen8 MOCS which does nothing and was in the wrong place
anyway.
This patch is totally optional. I'd be willing to just always use buffer #2 on
gen8+. Pre-HSW this wasn't allowed, but it looks like it's okay for gen8 too.
v2: Move inactive batch generation to the top of the function in order to make
the rest of the code easier to read.
Jenkins results (still a bunch of spurious failures, I miss Mark):
http://otc-mesa-ci.jf.intel.com/job/bwidawsk/169/
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com (v1)
---
I had a minor bug in v1 which prevented me from pushing this sooner. I'd like to
merge this patch unless anyone has complaints?
---
src/mesa/drivers/dri/i965/brw_state.h | 6 +-
src/mesa/drivers/dri/i965/gen6_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_vs_state.c | 3 +-
src/mesa/drivers/dri/i965/gen6_wm_state.c | 3 +-
src/mesa/drivers/dri/i965/gen7_vs_state.c | 93 ---
5 files changed, 68 insertions(+), 39 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 987672f..f45459d 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -368,9 +368,9 @@ brw_upload_pull_constants(struct brw_context *brw,
/* gen7_vs_state.c */
void
-gen7_upload_constant_state(struct brw_context *brw,
- const struct brw_stage_state *stage_state,
- bool active, unsigned opcode);
+brw_upload_constant_state(struct brw_context *brw,
+ const struct brw_stage_state *stage_state,
+ bool active, unsigned opcode);
#ifdef __cplusplus
}
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c
b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index eb4c586..19568b0 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -48,7 +48,7 @@ gen6_upload_gs_push_constants(struct brw_context *brw)
}
if (brw-gen = 7)
- gen7_upload_constant_state(brw, stage_state, gp, _3DSTATE_CONSTANT_GS);
+ brw_upload_constant_state(brw, stage_state, gp, _3DSTATE_CONSTANT_GS);
}
const struct brw_tracked_state gen6_gs_push_constants = {
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c
b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 35d10ef..c33607d 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -140,8 +140,7 @@ gen6_upload_vs_push_constants(struct brw_context *brw)
if (brw-gen == 7 !brw-is_haswell !brw-is_baytrail)
gen7_emit_vs_workaround_flush(brw);
- gen7_upload_constant_state(brw, stage_state, true /* active */,
- _3DSTATE_CONSTANT_VS);
+ brw_upload_constant_state(brw, stage_state, true, _3DSTATE_CONSTANT_VS);
}
}
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c
b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index d1748ba..ced4ad6 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -50,8 +50,7 @@ gen6_upload_wm_push_constants(struct brw_context *brw)
stage_state, AUB_TRACE_WM_CONSTANTS);
if (brw-gen = 7) {
- gen7_upload_constant_state(brw, brw-wm.base, true,
- _3DSTATE_CONSTANT_PS);
+ brw_upload_constant_state(brw, brw-wm.base, true,
_3DSTATE_CONSTANT_PS);
}
}
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c
b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 4b17d06..6a51934 100644
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -29,20 +29,23 @@
#include program/prog_statevars.h
#include intel_batchbuffer.h
-
-void
-gen7_upload_constant_state(struct brw_context *brw,
+static void
+gen8_upload_constant_state(struct brw_context *brw,
const struct brw_stage_state *stage_state,
bool active, unsigned opcode)
{
- uint32_t mocs = brw-gen 8 ? GEN7_MOCS_L3 : 0;
- /* Disable if the shader stage is inactive or there are no push constants.
*/
- active = active stage_state-push_const_size != 0;
+ /* FINISHME: determine if we should use mocs on gen9 */
- int dwords = brw-gen = 8 ? 11 : 7;
- BEGIN_BATCH(dwords);
- OUT_BATCH(opcode 16 | (dwords - 2));
+ BEGIN_BATCH(11);
+ OUT_BATCH(opcode 16 | (11 - 2));
+
+ if (!active) {
+ for (int i = 0; i 11; i++)
+ OUT_BATCH(0);
+
+ return;
+ }
/* Workaround for SKL+ (we use option #2 until we have a need for more
* constant buffers). This comes from the documentation for
3DSTATE_CONSTANT_*
@@ -55,44 +58,42
[Mesa-dev] [Bug 66346] shader_query.cpp:49: error: invalid conversion from 'void*' to 'GLuint'
https://bugs.freedesktop.org/show_bug.cgi?id=66346 --- Comment #19 from José Fonseca jfons...@vmware.com --- (In reply to Vinson Lee from comment #18) mesa: 0166b4c165271bd7525a91049e58e390cb596c60 (master 10.7.0-devel) Still see this build error. BUILDING_MESA is only defined for darwin DRI enabled builds. It should be a matter of adding the define on SCons builds too. But I don't know if there's much point for building Mesa w/ SCons on Mac -- we don't actually build an usable libGL there. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
