Re: [Mesa-dev] [PATCH] nir: Handle double-precision in fabs, frsq, fsqrt, fexp2 and flog2

On Thu, May 19, 2016 at 3:36 AM, Iago Toral Quiroga wrote: > We agreed in the list that it would be better to have these if they were > easy to implement. > --- > src/compiler/nir/nir_opcodes.py | 10 +- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git

Re: [Mesa-dev] [PATCH 08/12] nir: Add a simple nir_lower_wpos_center() pass for Vulkan drivers.

On Wed, May 18, 2016 at 3:00 PM, Kenneth Graunke wrote: > nir_lower_wpos_ytransform() is great for OpenGL, which allows > applications to choose whether their coordinate system's origin is > upper left/lower left, and whether the pixel center should be on >

Re: [Mesa-dev] [PATCH 09/12] i965, anv: Use NIR FragCoord re-center and y-transform passes.

On Wed, May 18, 2016 at 3:00 PM, Kenneth Graunke wrote: > This handles gl_FragCoord transformations and other window system vs. > user FBO coordinate system flipping by multiplying/adding uniform > values, rather than recompiles. > > This is much better because we have no

Re: [Mesa-dev] [PATCH] gallium/tgsi: use _mesa_roundevenf in micro_rnd

On Thu, May 19, 2016 at 2:34 PM, Lars Hamre wrote: > Fixes the following piglit tests (for softpipe): > > /spec/glsl-1.30/execution/built-in-functions/... > fs-roundeven-float > fs-roundeven-vec2 > fs-roundeven-vec3 > fs-roundeven-vec4 > vs-roundeven-float > vs-roundeven-vec2

[Mesa-dev] [PATCH v2 08/13] i965/draw: Use the real size for vertex buffers

Previously, we were using the size of the BO which may be substantially larger than the actual vertex buffer size. v2: Use actual tight bounds on Bay Trail and Haswell+ --- src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_draw_upload.c | 16 +++-

[Mesa-dev] [PATCH 7.9/13] i965/draw: Use 3-channel formats for vertex fetch when possible.

For a long time, several of the 3-channel vertex formats didn't exist so we faked them with 4-channel versions. Starting with Sandy Bridge, we can use R16G16B16_FLOAT and 8 and 16-bit integer formats become available on Haswell and Bay Trail. --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 48

Re: [Mesa-dev] [PATCH] i965: Fix strerror error code sign

On Thu, May 19, 2016 at 01:51:08PM -0700, Mark Janes wrote: > This trivial fix to error-handling corrects the sign of drm error > codes before passing them to strerror. > > Identified by Coverity: CID1358581 Reviewed-by: Ben Widawsky [snip]

Re: [Mesa-dev] [RFC 3/7] nir: coverity unitialized pointer read

On Thu, May 19, 2016 at 4:42 PM, Matt Turner wrote: > On Wed, May 18, 2016 at 8:54 AM, Rob Clark wrote: >> From: Rob Clark >> >> Not sure how coverity arrives at the conclusion that we can read comp[j] >> unitialized (around

[Mesa-dev] [PATCH v2 13/13] i965: Enable arb_robust_buffer_access_behavior on BYT and HSW+

--- src/mesa/drivers/dri/i965/intel_extensions.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 8b4f685..511ef5c 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++

[Mesa-dev] [PATCH 7.8/13] i965/surface_formats: Update the VB column for new formats added on BYT

Bay Trail and Haswell added a bunch of new vertex formats. There was also the addition of 64-bit passthrough formats for BDW+. --- src/mesa/drivers/dri/i965/brw_surface_formats.c | 32 - 1 file changed, 16 insertions(+), 16 deletions(-) diff --git

Re: [Mesa-dev] [RFC 2/7] nir: coverity sign-extension fix

Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] i965: Fix strerror error code sign

This trivial fix to error-handling corrects the sign of drm error codes before passing them to strerror. Identified by Coverity: CID1358581 --- src/mesa/drivers/dri/i965/intel_screen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c

Re: [Mesa-dev] [RFC 7/7] nir/validate: assume() that hashtable entry exists

Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] nv50/ir: fix SUSTx constraints on Kepler

Reviewed-by: Ilia Mirkin I actually think this is wrong for SUSTB, but ... meh. Also, since we know the format, we could avoid computing the colors that aren't present in the image, but again ... meh. On Thu, May 19, 2016 at 6:52 PM, Samuel Pitoiset

Re: [Mesa-dev] tilers and out-of-order rendering..

On Thu, May 19, 2016 at 6:21 PM, Eric Anholt wrote: > Rob Clark writes: > >> So some rendering patterns that I've seen in apps turn out to be >> somewhat evil for tiling gpu's.. couple cases I've seen: >> >> 1) stk has some silliness where it binds an fbo,

[Mesa-dev] [PATCH] nv50/ir: fix SUSTx constraints on Kepler

To prevent out-of-bounds access and format mismatch we add a predicate on sustp, but we have to account for it when the sources are condensed because a predicate is a source. Using the range 3:6 will only condense the input data and it's always the case. This also fixes constraints when an

Re: [Mesa-dev] [PATCH] glxcmds: glXGetFBConfigs, fix screen bounds

I suspect you'll want to go ahead and commit that for him. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] tilers and out-of-order rendering..

So some rendering patterns that I've seen in apps turn out to be somewhat evil for tiling gpu's.. couple cases I've seen: 1) stk has some silliness where it binds an fbo, clears, binds other fbo clears, binds previous fbo and draws, and so on. This one is probably not too hard to just fix in

Re: [Mesa-dev] [PATCH 04/13] i965/draw: Delay when we get the bo for vertex buffers

On Thu, May 19, 2016 at 7:48 AM, Iago Toral wrote: > On Thu, 2016-05-19 at 00:21 -0700, Jason Ekstrand wrote: > > The previous code got the BO the first time we encountered it. However, > > this can potentially lead to problems if the BO is used for multiple > arrays > > with

Re: [Mesa-dev] [PATCH 11/13] glsl: Add an option to clamp block indices when lowering UBO/SSBOs

On Thu, May 19, 2016 at 10:07 AM, Ian Romanick wrote: > So... what did we decide for arrays of atomic counters? Do we need an > extra pass for that or ... ? > > Also... how does this handle the possibly unsized (actually > draw-time-sized) array at the end of an SSBO? >

[Mesa-dev] [PATCH] i965: Pass nir_src/nir_dest by reference.

Cuts 6K of .text. textdata bss dec hex filename 5772372 264648 29320 6066340 5c90a4 lib/i965_dri.so before 5766074 264648 29320 6060042 5c780a lib/i965_dri.so after --- src/mesa/drivers/dri/i965/brw_fs.h | 4 ++-- src/mesa/drivers/dri/i965/brw_fs_nir.cpp |

Re: [Mesa-dev] tilers and out-of-order rendering..

Rob Clark writes: > So some rendering patterns that I've seen in apps turn out to be > somewhat evil for tiling gpu's.. couple cases I've seen: > > 1) stk has some silliness where it binds an fbo, clears, binds other > fbo clears, binds previous fbo and draws, and so on.

Re: [Mesa-dev] [PATCH 11/12] i965: Delete dead dFdy flipping code.

On Wed, May 18, 2016 at 3:00 PM, Kenneth Graunke wrote: > Rob's pass flips dFdy in the opposite case of what I expected, "Rob's pass" might not mean anything to a future reader. I'd call it out by name. > so we always take the negate_value case. It doesn't really matter.

Re: [Mesa-dev] [RFC 1/7] nir/glsl_to_nir: quell some uninit_member coverity errors

On Wed, May 18, 2016 at 8:54 AM, Rob Clark wrote: > From: Rob Clark > > --- > src/compiler/nir/glsl_to_nir.cpp | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/src/compiler/nir/glsl_to_nir.cpp > b/src/compiler/nir/glsl_to_nir.cpp >

[Mesa-dev] [PATCH] gallium/tgsi: use _mesa_roundevenf in micro_rnd

Fixes the following piglit tests (for softpipe): /spec/glsl-1.30/execution/built-in-functions/... fs-roundeven-float fs-roundeven-vec2 fs-roundeven-vec3 fs-roundeven-vec4 vs-roundeven-float vs-roundeven-vec2 vs-roundeven-vec3 vs-roundeven-vec4 /spec/glsl-1.50/execution/built-in-functions/...

Re: [Mesa-dev] [RFC 3/7] nir: coverity unitialized pointer read

On Wed, May 18, 2016 at 8:54 AM, Rob Clark wrote: > From: Rob Clark > > Not sure how coverity arrives at the conclusion that we can read comp[j] > unitialized (around line 204), other than not being aware that ncomp is > greater than 1 so it won't

[Mesa-dev] [PATCH] glsl: handle same struct redeclaration (v2)

From: Dave Airlie This works around a bug in older version of UE4, where a shader defines the same structure twice. Although we aren't sure this is correct GLSL (it most likely isn't) there are enough UE4 based things out there we should deal with this. This drops the error

Re: [Mesa-dev] [PATCH 2/2] nvc0: account for shader-allocated local memory needs

I wonder why we don't set up the local memory size on nv50 (maybe we don't need to?). Anyway this will only affect OpenCL programs which is not going to happen in the near future. I would suggest to add a comment which explains why we need that (ie. spilling). Assuming info->bin.tlsSpace is

Re: [Mesa-dev] [PATCH 07/12] nir: Don't use ffma in nir_lower_wpos_ytransform().

On Thu, May 19, 2016 at 6:41 PM, Kenneth Graunke wrote: > On Thursday, May 19, 2016 12:57:44 PM PDT Rob Clark wrote: >> On Wed, May 18, 2016 at 6:00 PM, Kenneth Graunke > wrote: >> > ffma is an explicitly fused multiply add with higher precision. >>

Re: [Mesa-dev] [PATCH 00/14] radeonsi: Offchip tessellation

> Bas, > > do we see this with Mesa 11.3 / 12.0? > Should read did you have an updated version ready for release? > > Thanks, > Dieter Hi Dieter, There is a v2 on the list on which there are still some comments I need to resolve. However, I have been and am away from my dev machine this week.

Re: [Mesa-dev] [PATCH 08/12] nir: Add a simple nir_lower_wpos_center() pass for Vulkan drivers.

On Thursday, May 19, 2016 1:21:16 PM PDT Matt Turner wrote: > On Wed, May 18, 2016 at 3:00 PM, Kenneth Graunke wrote: > > nir_lower_wpos_ytransform() is great for OpenGL, which allows > > applications to choose whether their coordinate system's origin is > > upper

Re: [Mesa-dev] [PATCH] nir: drop assert for new arrays code.

On Thu, May 19, 2016 at 8:48 PM, Dave Airlie wrote: > From: Dave Airlie > > This code handles 0 length fine, Um... No it doesn't. A length of 0 means unsized which means we really need to to a get_array_length call and loop. Am I messing something? >

Re: [Mesa-dev] [PATCH 07/12] nir: Don't use ffma in nir_lower_wpos_ytransform().

On Thursday, May 19, 2016 12:57:44 PM PDT Rob Clark wrote: > On Wed, May 18, 2016 at 6:00 PM, Kenneth Graunke wrote: > > ffma is an explicitly fused multiply add with higher precision. > > The optimizer will take care of promoting mul/add to fma when > > it's beneficial to

Re: [Mesa-dev] [PATCH v2 4/4] anv/pipeline: Bounds-check resource indices when robuts_buffer_access is enabled

On May 19, 2016 12:50 AM, "Michael Schellenberger Costa" < mschellenbergerco...@googlemail.com> wrote: > > Hi Jason, > > Am 19.05.2016 um 09:22 schrieb Jason Ekstrand: > > --- > > src/intel/vulkan/anv_nir_apply_pipeline_layout.c | 52 > > 1 file changed, 35 insertions(+),

Re: [Mesa-dev] [PATCH 00/14] radeonsi: Offchip tessellation

Am 10.05.2016 12:52, schrieb Bas Nieuwenhuizen: This patchset implements offchip tessellation after which we can finally process more than one patch per wave without decreasing tessmark scores. For tessmark this improves performance by ~20% for the x32 case and ~80% for the x64 case. x8 and

[Mesa-dev] [PATCH] vc4: Fix failed instruction path of QIR validate pass

Correct use of qir_dump_inst() within QIR validate pass. Reported by the following GCC warning: mesa/src/gallium/drivers/vc4/vc4_qir_validate.c: In function 'fail_instr': mesa/src/gallium/drivers/vc4/vc4_qir_validate.c:31:23: warning: passing argument 1 of 'qir_dump_inst' from incompatible

[Mesa-dev] [PATCH 1/4] glsl: make max array trackers ints and use -1 as base.

From: Dave Airlie This fixes a bug that breaks cull distances. The problem is the max array accessors can't tell the difference between an never accessed unsized array and an accessed at location 0 unsized array. This leads to converting an undeclared unused gl_ClipDistance

[Mesa-dev] [PATCH 1/3] i965/draw: Expose vertex buffer state setup

Also change the interface to use start and end offsets. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_draw.h| 13 ++ src/mesa/drivers/dri/i965/brw_draw_upload.c | 39 + 2 files changed, 36 insertions(+),

[Mesa-dev] [PATCH 2/3] i965/gen8: Fix the vertex buffer size

And refactor to use the same upload logic with earlier gens. On gen >= 8 one doesn't provide ending address but number of bytes available. This is relative to the given offset. Until now we programmed the full size of the buffer regardless of the used offset. Signed-off-by: Topi Pohjolainen

[Mesa-dev] [PATCH 3/3] i965/blorp: Use core vertex buffer state setup

Also split the setup from the setup of vertex elements. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.c | 102 - 1 file changed, 36 insertions(+), 66 deletions(-) diff --git

[Mesa-dev] [PATCH] nir: drop assert for new arrays code.

From: Dave Airlie This code handles 0 length fine, and with the new glsl layer code to handle unsized array better, we can hit this path with ./bin/arb_separate_shader_object-GetProgramPipelineiv removing the assert works fine. Signed-off-by: Dave Airlie

[Mesa-dev] [PATCH 4/4] st/mesa: reenable culling

From: Dave Airlie Now the lowering pass if fixed, reenable ARB_cull_distance. Signed-off-by: Dave Airlie --- src/mesa/state_tracker/st_extensions.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH 2/4] glsl: rewrite clip/cull distance lowering pass

From: Dave Airlie The last version of this broke clipping, and I had to spend sometime getting this working properly. I had to introduce a third pass to count the clip/cull totals, all due to one messy corner case. We have a piglit test tes-input-gl_ClipDistance.shader_test

[Mesa-dev] [PATCH 3/4] i965: reenable ARB_cull_distance.

From: Dave Airlie Now the lowering pass is fixed we can reenable culling. Signed-off-by: Dave Airlie --- src/mesa/drivers/dri/i965/intel_extensions.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [Mesa-dev] [PATCH] i965: Pass nir_src/nir_dest by reference.

On May 19, 2016 2:42 PM, "Matt Turner" wrote: > > Cuts 6K of .text. Nice! Reviewed-by: Jason Ekstrand >textdata bss dec hex filename > 5772372 264648 29320 6066340 5c90a4 lib/i965_dri.so before > 5766074 264648 29320 6060042

Re: [Mesa-dev] [PATCH 01/13] vbo: Declare the index range invalid for DrawIndirect

Reviewed-by: Marek Olšák Marek On Thu, May 19, 2016 at 9:20 AM, Jason Ekstrand wrote: > Right now, we're just setting the range to [0, MAX_UINT32] which, while > correct isn't helpful. With DrawIndirect, you can't really know what the > actual range

Re: [Mesa-dev] [PATCH 02/13] vbo: Declare the index range invalid for DrawTransformFeedback

Reviewed-by: Marek Olšák Marek On Thu, May 19, 2016 at 9:20 AM, Jason Ekstrand wrote: > Right now, we're setting the range to [0, 0] which is obviously bogus. > Instead, we should set it to be invalid like we do for DrawIndirect. > > Cc: "10.2"

[Mesa-dev] [PATCH] nir: Handle double-precision in fabs, frsq, fsqrt, fexp2 and flog2

We agreed in the list that it would be better to have these if they were easy to implement. --- src/compiler/nir/nir_opcodes.py | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index 8a3a80f..6dc0c90

[Mesa-dev] [PATCH 03/10] radeonsi: set some image descriptor fields at bind time

From: Marek Olšák mainly the fields that can change by reallocating a texture and changing the tile mode --- src/gallium/drivers/radeonsi/si_descriptors.c | 64 + src/gallium/drivers/radeonsi/si_pipe.h| 3 + src/gallium/drivers/radeonsi/si_state.c

[Mesa-dev] [PATCH 04/10] radeonsi: move code for setting one shader image into separate function

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_descriptors.c | 144 ++ 1 file changed, 75 insertions(+), 69 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index

[Mesa-dev] [PATCH 08/10] gallium/radeon: degrade tiled textures mapped often to linear

From: Marek Olšák --- src/gallium/drivers/radeon/r600_pipe_common.h | 1 + src/gallium/drivers/radeon/r600_texture.c | 102 ++ 2 files changed, 103 insertions(+) diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h

[Mesa-dev] [PATCH 10/10] gallium/radeon: lower memory usage during texture transfers

From: Marek Olšák This improves throughput by keeping TTM overhead down. Some piglit tests such as texelFetch and streaming-texture-leak will use less memory now. --- src/gallium/drivers/radeon/r600_pipe_common.h | 1 + src/gallium/drivers/radeon/r600_texture.c | 32

[Mesa-dev] [PATCH 07/10] gallium/radeon: clean up and better comment use_staging_texture

From: Marek Olšák Next commits will add other things around this. --- src/gallium/drivers/radeon/r600_texture.c | 42 +-- 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_texture.c

[Mesa-dev] [PATCH 09/10] gallium/radeon: invalidate busy linear textures for whole-texture uploads

From: Marek Olšák --- src/gallium/drivers/radeon/r600_texture.c | 30 -- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 5a0bd23..1333a25

[Mesa-dev] [PATCH 05/10] radeonsi: implement global resetting of texture descriptors

From: Marek Olšák it will be used by texture reallocation --- src/gallium/drivers/radeon/r600_pipe_common.h | 7 src/gallium/drivers/radeonsi/si_descriptors.c | 53 --- src/gallium/drivers/radeonsi/si_state.h | 1 +

[Mesa-dev] [PATCH 00/10] RadeonSI: Improve texture streaming upload performance

Hi, This series improves texture streaming upload performance. Please review. Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 06/10] radeonsi: set some colorbuffer register fields at emit time

From: Marek Olšák to allow reallocating the texture storage with different parameters --- src/gallium/drivers/radeon/r600_pipe_common.h | 1 + src/gallium/drivers/radeon/r600_texture.c | 2 + src/gallium/drivers/radeonsi/si_state.c | 94

[Mesa-dev] [PATCH 01/10] gallium/util: add util_texrange_covers_whole_level from radeon

From: Marek Olšák --- src/gallium/auxiliary/util/u_inlines.h| 12 src/gallium/drivers/radeon/r600_texture.c | 23 ++- 2 files changed, 18 insertions(+), 17 deletions(-) diff --git a/src/gallium/auxiliary/util/u_inlines.h

[Mesa-dev] [PATCH 02/10] gallium/radeon: strenghten some checking for DMA preparation

From: Marek Olšák Just for consistency. This doesn't fix anything, because DCC is not supported with non-mipmapped textures. --- src/gallium/drivers/radeon/r600_texture.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH] i965/fs: do not depend on std140 alignment rules for UBO loads

The previous implementation relied on the std140 alignment rules to avoid handling misalignment in the case where we are loading more than 2 double components from a vector, which requires to emit a second load message. This alternative implementation deals with misalignment and is more flexible

[Mesa-dev] AMDGPU SI userspace support - experimental

Hi, The following branches add SI support to the amdgpu side of our graphics driver stack. git://people.freedesktop.org/~mareko/mesa amdgpu-si git://people.freedesktop.org/~mareko/libdrm amdgpu-si git://people.freedesktop.org/~mareko/xf86-video-amdgpu amdgpu-si Thanks to Ronie Salgado

Re: [Mesa-dev] [PATCH 1/2] nvc0: clear out surfaces bufctx before rebinding everything

On 09:28 PM - May 18 2016, Ilia Mirkin wrote: > Otherwise we can end up in a situation where that bin just grows and > grows. > > Signed-off-by: Ilia Mirkin > --- > src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git

Re: [Mesa-dev] [PATCH 04/13] i965/draw: Delay when we get the bo for vertex buffers

On Thu, 2016-05-19 at 00:21 -0700, Jason Ekstrand wrote: > The previous code got the BO the first time we encountered it. However, > this can potentially lead to problems if the BO is used for multiple arrays > with the same buffer object because the range we declare as busy may not be > quite

Re: [Mesa-dev] [PATCH] winsys/amdgpu: add back multithreaded command submission

On 18.05.2016 13:23, Marek Olšák wrote: ,On Wed, May 18, 2016 at 7:48 PM, Nicolai Hähnle wrote: On 18.05.2016 11:58, Marek Olšák wrote: On Sat, May 7, 2016 at 5:12 PM, Nicolai Hähnle wrote: Looks good to me, just two remarks below... On 06.05.2016

Re: [Mesa-dev] [PATCH] nir: Use double-precision pow() when bit_size is 64, powf() otherwise

I have just noticed that this was never pushed, right? I noticed this while working on providing double-precision implementation for the other functions discussed in the thread. Iago On Wed, 2016-03-23 at 20:09 -0700, Jason Ekstrand wrote: > Is there a 64-bit pow in GLSL? If so, this is the

Re: [Mesa-dev] [PATCH 2/2] egl: Check if API is supported when using eglBindAPI.

On Wed, May 18, 2016 at 8:44 PM, Ian Romanick wrote: > On 05/18/2016 11:45 AM, Manolova, Plamena wrote: > > Hi Ian, > > Thanks for reviewing! > > > > On Wed, May 18, 2016 at 4:33 PM, Ian Romanick > > wrote: > > > > On

Re: [Mesa-dev] [PATCH 1/2] nvc0: clear out surfaces bufctx before rebinding everything

Yes, oops. Shouldn't fix any invalidation issues. Could fix unbounded memory growth due to switching back and forth between cp and 3d without setting any new images. Please fold this into your series. On May 19, 2016 4:13 AM, "Samuel Pitoiset" wrote: Oops? Your patch

Re: [Mesa-dev] [PATCH 01/13] vbo: Declare the index range invalid for DrawIndirect

I left a minor comment in patch 4, but other than that patches 1-4 are: Reviewed-by: Iago Toral Quiroga On Thu, 2016-05-19 at 00:20 -0700, Jason Ekstrand wrote: > Right now, we're just setting the range to [0, MAX_UINT32] which, while > correct isn't helpful. With

Re: [Mesa-dev] [PATCH 02/12] nir: Fix fddy swizzles in nir_lower_wpos_ytransform().

On Wed, May 18, 2016 at 6:00 PM, Kenneth Graunke wrote: > The original value might have been swizzled. That's taken care of in > the fmul source - we don't want to reswizzle it again. > > Fixes validation failures in glsl-derivs-varyings on a branch of mine > which uses

Re: [Mesa-dev] [PATCH v2] docs: add swr to GL3.txt

Reviewed-by: Bruce Cherniak On 5/17/16, 5:46 PM, "mesa-dev on behalf of Tim Rowley" wrote: >--- > docs/GL3.txt | 82 ++-- > 1

Re: [Mesa-dev] [PATCH 5/5] anv: Enable textureCompressionASTC_LDR on Gen9+

On Wed, May 18, 2016 at 10:18:30PM -0700, Jason Ekstrand wrote: > Do we pass all the ASTC CTS tests? If so, > > Reviewed-by: Jason Ekstrand > We do. Thanks! > That wasn't nearly as much work as we'd feared it would be. Hooray for ISL! Yes, ISL made this work quite

Re: [Mesa-dev] [PATCH 10/13] glsl/linker: Add a helper variable for compiler options

This patch is Reviewed-by: Ian Romanick On 05/19/2016 12:21 AM, Jason Ekstrand wrote: > --- > src/compiler/glsl/linker.cpp | 7 +-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp >

Re: [Mesa-dev] [PATCH 11/13] glsl: Add an option to clamp block indices when lowering UBO/SSBOs

So... what did we decide for arrays of atomic counters? Do we need an extra pass for that or ... ? Also... how does this handle the possibly unsized (actually draw-time-sized) array at the end of an SSBO? For UBOs, I think this patch is definitely sufficient, and I think it improves things

Re: [Mesa-dev] [PATCH 06/12] nir: Handle fddy_fine and fddy_coarse in nir_lower_wpos_ytransform.

On Wed, May 18, 2016 at 6:00 PM, Kenneth Graunke wrote: > These also need flipping! > > Signed-off-by: Kenneth Graunke Reviewed-by: Rob Clark > --- > src/compiler/nir/nir_lower_wpos_ytransform.c | 4 +++- > 1 file changed, 3

Re: [Mesa-dev] [PATCH 03/12] nir: Add interp_var_at_offset flipping.

On Wed, May 18, 2016 at 6:00 PM, Kenneth Graunke wrote: > The Y-offset needs flipping as well, similar to ddy. > > Signed-off-by: Kenneth Graunke Reviewed-by: Rob Clark > --- > src/compiler/nir/nir_lower_wpos_ytransform.c |

Re: [Mesa-dev] [PATCH 07/12] nir: Don't use ffma in nir_lower_wpos_ytransform().

On Wed, May 18, 2016 at 6:00 PM, Kenneth Graunke wrote: > ffma is an explicitly fused multiply add with higher precision. > The optimizer will take care of promoting mul/add to fma when > it's beneficial to do so. > > This fixes failures on Gen4-5 when using this pass, as

Re: [Mesa-dev] [PATCH 01/13] vbo: Declare the index range invalid for DrawIndirect

On 05/19/2016 12:20 AM, Jason Ekstrand wrote: > Right now, we're just setting the range to [0, MAX_UINT32] which, while > correct isn't helpful. With DrawIndirect, you can't really know what the > actual range is so we may as well flag it as being an invalid range. This > is what we do for draws

[Mesa-dev] [PATCH] nv50/ir: Add missing handling of U64/S64 in inlines

Signed-off-by: Pierre Moreau --- U64/S64 support is missing in other places of codegen (like in nv50_ir_peephole.cpp for example), however its absence will result in code not being as optimised as it could have. Adding that support is not as straight forward as this patch,

[Mesa-dev] [PATCH 1/8] drm/amdgpu/gfx7: expand cp jt size to handle GDS as well

The size needs to handle the CP JT and GDS. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index

[Mesa-dev] [PATCH 7/8] drm/amdgpu/gfx8: clean up polaris11 PG enable

Fix the logic for enabling/disabling. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 18 +- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

[Mesa-dev] [PATCH 6/8] drm/amdgpu/gfx8: add powergating support for CZ/ST

This implements powergating support for CZ/ST asics. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 132 -- 1 file changed, 126 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

[Mesa-dev] [PATCH 2/8] drm/radeon/gfx7: expand cp jt size to handle GDS as well

The size needs to handle the CP JT and GDS. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/cik.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index ba192a3..5c88c1c 100644 ---

[Mesa-dev] [PATCH 4/8] drm/amdgpu/gfx8: rename some pg functions

So they can be shared with other asics. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 22 -- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

[Mesa-dev] [PATCH 0/8] Add GFX powergating support for CZ

This patch set adds powergating support for the gfx block on Carrizo. Also fixes a few issues with powergating setup on older asics. Powergating improves idle powersaving. Alex Deucher (7): drm/amdgpu/gfx7: expand cp jt size to handle GDS as well drm/radeon/gfx7: expand cp jt size to handle

Re: [Mesa-dev] [PATCH] nv50/ir: Add missing handling of U64/S64 in inlines

Reviewed-by: Ilia Mirkin On Thu, May 19, 2016 at 2:13 PM, Pierre Moreau wrote: > Signed-off-by: Pierre Moreau > --- > > U64/S64 support is missing in other places of codegen (like in > nv50_ir_peephole.cpp for example),

[Mesa-dev] [PATCH 3/8] drm/amdgpu/gfx8: add state setup for CZ/ST GFX power gating

This sets up the CP jump table and GDS buffer and sets the PG state registers. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 133 -- 1 file changed, 128 insertions(+), 5 deletions(-) diff --git

[Mesa-dev] [PATCH 5/8] drm/amdgpu: add new GFX powergating types

Add some new GFX powergating flags. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/amd_shared.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index

[Mesa-dev] [PATCH 8/8] drm/amdgpu/gfx8: Enable GFX PG on CZ

From: Tom St Denis Based on Alex's patches this enables GFX PG on CZ. Tested with xonotic-glx/glxgears/supertuxkart and idle desktop. Also read-back registers via umr for verificiation that the bits are truly enabled. Signed-off-by: Tom St Denis

Re: [Mesa-dev] [PATCH v2] docs: add swr to GL3.txt

Looks good to me. Reviewed-by: Ian Romanick On 05/17/2016 03:46 PM, Tim Rowley wrote: > --- > docs/GL3.txt | 82 > ++-- > 1 file changed, 41 insertions(+), 41 deletions(-) > > diff --git a/docs/GL3.txt

Re: [Mesa-dev] [PATCH 1/2] nvc0: clear out surfaces bufctx before rebinding everything

On 05/19/2016 12:02 PM, Pierre Moreau wrote: On 09:28 PM - May 18 2016, Ilia Mirkin wrote: Otherwise we can end up in a situation where that bin just grows and grows. Signed-off-by: Ilia Mirkin --- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 5 + 1 file changed,

Re: [Mesa-dev] [PATCH v2 00/19] swr: update rasterizer

Reviewed-by: Bruce Cherniak On 5/17/16, 5:36 PM, "mesa-dev on behalf of Tim Rowley" wrote: >Mostly small cleanups this round. > >v2: > remove definition of offsetof > more

[Mesa-dev] [PATCH 2/2] mesa: Replace uses of Shared->Mutex with hash-table mutexes

We were locking the Shared->Mutex and then using calling functions like _mesa_HashInsert that do additional per-hash-table locking internally. Instead just lock each hash-table's mutex and use functions like _mesa_HashInsertLocked and the new _mesa_HashRemoveLocked. In order to do this, we need

[Mesa-dev] [PATCH 1/2] hash: Add _mesa_HashRemoveLocked() function.

Reviewed-by: Timothy Arceri Reviewed-by: Brian Paul --- I sent these last summer as part of a larger (13) patch series. The middle of that series was rejected, and I committed the first 4 patches last year. These two, from the end of the series should

Re: [Mesa-dev] [PATCH 07/12] nir: Don't use ffma in nir_lower_wpos_ytransform().

On Thursday, May 19, 2016 8:39:45 AM PDT Michael Schellenberger Costa wrote: > Hi Kenneth, > > Am 19.05.2016 um 00:00 schrieb Kenneth Graunke: > > ffma is an explicitly fused multiply add with higher precision. > > The optimizer will take care of promoting mul/add to fma when > > it's beneficial

[Mesa-dev] [PATCH 01/13] vbo: Declare the index range invalid for DrawIndirect

Right now, we're just setting the range to [0, MAX_UINT32] which, while correct isn't helpful. With DrawIndirect, you can't really know what the actual range is so we may as well flag it as being an invalid range. This is what we do for draws with index buffer which is similar (the indices

[Mesa-dev] [PATCH 13/13] i965: Enable arb_robust_buffer_access_behavior on gen5+

--- src/mesa/drivers/dri/i965/intel_extensions.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 8b4f685..a544263 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++

[Mesa-dev] [PATCH v2 3/4] anv/pipeline: Only do buffer bounds checks if robustBufferAccess is enabled

--- src/intel/vulkan/anv_nir_apply_dynamic_offsets.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_nir_apply_dynamic_offsets.c b/src/intel/vulkan/anv_nir_apply_dynamic_offsets.c index 84fed0a..80ef8ee 100644 ---

[Mesa-dev] [PATCH 11/13] glsl: Add an option to clamp block indices when lowering UBO/SSBOs

This prevents array overflow when the block is actually an array of UBOs or SSBOs. On some hardware such as i965, such overflows can cause GPU hangs. --- src/compiler/glsl/ir_optimization.h | 2 +- src/compiler/glsl/linker.cpp | 3 ++-

[Mesa-dev] [PATCH 09/13] i965/draw: Use the real size for index buffers

Previously, we were using the size of the whole BO which may be substantially larger than the actual index buffer size. --- src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_draw_upload.c | 8 ++-- src/mesa/drivers/dri/i965/gen8_draw_upload.c | 2 +- 3 files

[Mesa-dev] [PATCH 08/13] i965/draw: Use the real size for vertex buffers

Previously, we were using the size of the BO which may be substantially larger than the actual vertex buffer size. --- src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_draw_upload.c | 52 +++- src/mesa/drivers/dri/i965/gen8_draw_upload.c

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