Re: [Mesa-dev] [PATCH] radeonsi: avoid int-to-pointer-cast warnings on 32bit

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Sat, Feb 3, 2018 at 11:19 PM, Grazvydas Ignotas  wrote:
> I hope the actual dropping of MSB is ok, but that's what's already
> happened before this change.
> ---
>  src/gallium/drivers/radeonsi/si_descriptors.c | 18 --
>  1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
> b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 17115e1..009e803 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -2263,11 +2263,12 @@ static uint64_t si_create_texture_handle(struct 
> pipe_context *ctx,
> return 0;
> }
>
> handle = tex_handle->desc_slot;
>
> -   if (!_mesa_hash_table_insert(sctx->tex_handles, (void *)handle,
> +   if (!_mesa_hash_table_insert(sctx->tex_handles,
> +(void *)(uintptr_t)handle,
>  tex_handle)) {
> FREE(tex_handle);
> return 0;
> }
>
> @@ -2282,11 +2283,12 @@ static void si_delete_texture_handle(struct 
> pipe_context *ctx, uint64_t handle)
>  {
> struct si_context *sctx = (struct si_context *)ctx;
> struct si_texture_handle *tex_handle;
> struct hash_entry *entry;
>
> -   entry = _mesa_hash_table_search(sctx->tex_handles, (void *)handle);
> +   entry = _mesa_hash_table_search(sctx->tex_handles,
> +   (void *)(uintptr_t)handle);
> if (!entry)
> return;
>
> tex_handle = (struct si_texture_handle *)entry->data;
>
> @@ -2304,11 +2306,12 @@ static void si_make_texture_handle_resident(struct 
> pipe_context *ctx,
> struct si_context *sctx = (struct si_context *)ctx;
> struct si_texture_handle *tex_handle;
> struct si_sampler_view *sview;
> struct hash_entry *entry;
>
> -   entry = _mesa_hash_table_search(sctx->tex_handles, (void *)handle);
> +   entry = _mesa_hash_table_search(sctx->tex_handles,
> +   (void *)(uintptr_t)handle);
> if (!entry)
> return;
>
> tex_handle = (struct si_texture_handle *)entry->data;
> sview = (struct si_sampler_view *)tex_handle->view;
> @@ -2406,11 +2409,12 @@ static uint64_t si_create_image_handle(struct 
> pipe_context *ctx,
> return 0;
> }
>
> handle = img_handle->desc_slot;
>
> -   if (!_mesa_hash_table_insert(sctx->img_handles, (void *)handle,
> +   if (!_mesa_hash_table_insert(sctx->img_handles,
> +(void *)(uintptr_t)handle,
>  img_handle)) {
> FREE(img_handle);
> return 0;
> }
>
> @@ -2425,11 +2429,12 @@ static void si_delete_image_handle(struct 
> pipe_context *ctx, uint64_t handle)
>  {
> struct si_context *sctx = (struct si_context *)ctx;
> struct si_image_handle *img_handle;
> struct hash_entry *entry;
>
> -   entry = _mesa_hash_table_search(sctx->img_handles, (void *)handle);
> +   entry = _mesa_hash_table_search(sctx->img_handles,
> +   (void *)(uintptr_t)handle);
> if (!entry)
> return;
>
> img_handle = (struct si_image_handle *)entry->data;
>
> @@ -2446,11 +2451,12 @@ static void si_make_image_handle_resident(struct 
> pipe_context *ctx,
> struct si_image_handle *img_handle;
> struct pipe_image_view *view;
> struct r600_resource *res;
> struct hash_entry *entry;
>
> -   entry = _mesa_hash_table_search(sctx->img_handles, (void *)handle);
> +   entry = _mesa_hash_table_search(sctx->img_handles,
> +   (void *)(uintptr_t)handle);
> if (!entry)
> return;
>
> img_handle = (struct si_image_handle *)entry->data;
> view = _handle->view;
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH] gallium/hud: update some query functions

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Sat, Feb 3, 2018 at 11:19 PM, Grazvydas Ignotas  wrote:
> It seems these were missed when struct pipe_context * argument was
> added to hud_graph::query_new_value.
>
> Fixes: 3132afdf4c "gallium/hud: pass pipe_context explicitly to most 
> functions"
> ---
>  src/gallium/auxiliary/hud/hud_cpufreq.c  | 2 +-
>  src/gallium/auxiliary/hud/hud_diskstat.c | 2 +-
>  src/gallium/auxiliary/hud/hud_nic.c  | 2 +-
>  src/gallium/auxiliary/hud/hud_sensors_temp.c | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/auxiliary/hud/hud_cpufreq.c 
> b/src/gallium/auxiliary/hud/hud_cpufreq.c
> index f5b7c0f2..78a6607 100644
> --- a/src/gallium/auxiliary/hud/hud_cpufreq.c
> +++ b/src/gallium/auxiliary/hud/hud_cpufreq.c
> @@ -89,11 +89,11 @@ get_file_value(const char *fn, uint64_t *KHz)
>
> return ret;
>  }
>
>  static void
> -query_cfi_load(struct hud_graph *gr)
> +query_cfi_load(struct hud_graph *gr, struct pipe_context *pipe)
>  {
> struct cpufreq_info *cfi = gr->query_data;
>
> uint64_t now = os_time_get();
> if (cfi->last_time) {
> diff --git a/src/gallium/auxiliary/hud/hud_diskstat.c 
> b/src/gallium/auxiliary/hud/hud_diskstat.c
> index 44174d6..7eaaf35 100644
> --- a/src/gallium/auxiliary/hud/hud_diskstat.c
> +++ b/src/gallium/auxiliary/hud/hud_diskstat.c
> @@ -115,11 +115,11 @@ get_file_values(const char *fn, struct stat_s *s)
>
> return ret;
>  }
>
>  static void
> -query_dsi_load(struct hud_graph *gr)
> +query_dsi_load(struct hud_graph *gr, struct pipe_context *pipe)
>  {
> /* The framework calls us periodically, compensate for the
>  * calling interval accordingly when reporting per second.
>  */
> struct diskstat_info *dsi = gr->query_data;
> diff --git a/src/gallium/auxiliary/hud/hud_nic.c 
> b/src/gallium/auxiliary/hud/hud_nic.c
> index 1de5705..b6c0d9e 100644
> --- a/src/gallium/auxiliary/hud/hud_nic.c
> +++ b/src/gallium/auxiliary/hud/hud_nic.c
> @@ -169,11 +169,11 @@ query_nic_rssi(const struct nic_info *nic, uint64_t 
> *leveldBm)
>
> close(sockfd);
>  }
>
>  static void
> -query_nic_load(struct hud_graph *gr)
> +query_nic_load(struct hud_graph *gr, struct pipe_context *pipe)
>  {
> /* The framework calls us at a regular but indefined period,
>  * not once per second, compensate the statistics accordingly.
>  */
>
> diff --git a/src/gallium/auxiliary/hud/hud_sensors_temp.c 
> b/src/gallium/auxiliary/hud/hud_sensors_temp.c
> index 4d3a11b..c26e7b9 100644
> --- a/src/gallium/auxiliary/hud/hud_sensors_temp.c
> +++ b/src/gallium/auxiliary/hud/hud_sensors_temp.c
> @@ -152,11 +152,11 @@ find_sti_by_name(const char *n, unsigned int mode)
> }
> return 0;
>  }
>
>  static void
> -query_sti_load(struct hud_graph *gr)
> +query_sti_load(struct hud_graph *gr, struct pipe_context *pipe)
>  {
> struct sensors_temp_info *sti = gr->query_data;
> uint64_t now = os_time_get();
>
> if (sti->last_time) {
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH v2] util: remove redundant check for the __clang__ macro

[Vlad Golovkin]

2018-02-06 17:19 GMT+02:00 Brian Paul :
> On 02/06/2018 06:48 AM, Vlad Golovkin wrote:
>>
>> Clang defines __GNUC__ macro, so one doesn't need to check __clang__
>> macro in this particular case.
>>
>> v2: added comment as per Brian Paul's suggestion
>> ---
>>   src/util/macros.h | 3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/util/macros.h b/src/util/macros.h
>> index 432d513930..e3c785af50 100644
>> --- a/src/util/macros.h
>> +++ b/src/util/macros.h
>> @@ -137,8 +137,9 @@ do {   \
>>   #endif
>> /* Forced function inlining */
>> +/* Note: Clang also sets __GNUC__ (see other cases below) */
>>   #ifndef ALWAYS_INLINE
>> -#  if defined(__GNUC__) || defined(__clang__)
>> +#  if defined(__GNUC__)
>>   #define ALWAYS_INLINE inline __attribute__((always_inline))
>>   #  elif defined(_MSC_VER)
>>   #define ALWAYS_INLINE __forceinline
>>
>
> Thanks!
>
> Reviewed-by: Brian Paul 
>
> Do you need me to push this for you?


I don't have push access, so that would be great.

Thanks.
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Re: [Mesa-dev] [PATCH] winsys/amdgpu: allow non page-aligned size bo creation from pointer

[Marek Olšák]

Pushed, thanks!

Marek

On Sun, Feb 4, 2018 at 8:24 PM, Michal Navratil  wrote:
> Fix INVALID_OPERATION caused by BufferData with target
> EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD when the buffer size is
> not page aligned.
> ---
>  src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 11 +++
>  1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
> b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
> index 5d565ff..ba48cad 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
> @@ -1388,19 +1388,22 @@ static struct pb_buffer *amdgpu_bo_from_ptr(struct 
> radeon_winsys *rws,
>  struct amdgpu_winsys_bo *bo;
>  uint64_t va;
>  amdgpu_va_handle va_handle;
> +/* Avoid failure when the size is not page aligned */
> +uint64_t aligned_size = align64(size, ws->info.gart_page_size);
>
>  bo = CALLOC_STRUCT(amdgpu_winsys_bo);
>  if (!bo)
>  return NULL;
>
> -if (amdgpu_create_bo_from_user_mem(ws->dev, pointer, size, _handle))
> +if (amdgpu_create_bo_from_user_mem(ws->dev, pointer,
> +   aligned_size, _handle))
>  goto error;
>
>  if (amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,
> -  size, 1 << 12, 0, , _handle, 0))
> +  aligned_size, 1 << 12, 0, , _handle, 0))
>  goto error_va_alloc;
>
> -if (amdgpu_bo_va_op(buf_handle, 0, size, va, 0, AMDGPU_VA_OP_MAP))
> +if (amdgpu_bo_va_op(buf_handle, 0, aligned_size, va, 0, 
> AMDGPU_VA_OP_MAP))
>  goto error_va_map;
>
>  /* Initialize it. */
> @@ -1416,7 +1419,7 @@ static struct pb_buffer *amdgpu_bo_from_ptr(struct 
> radeon_winsys *rws,
>  bo->initial_domain = RADEON_DOMAIN_GTT;
>  bo->unique_id = __sync_fetch_and_add(>next_bo_unique_id, 1);
>
> -ws->allocated_gtt += align64(bo->base.size, ws->info.gart_page_size);
> +ws->allocated_gtt += aligned_size;
>
>  amdgpu_add_buffer_to_global_list(bo);
>
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH v2 1/3] st/glsl_to_tgsi: move nir detection earlier

[Marek Olšák]

For the series:

Reviewed-by: Marek Olšák 

Marek

On Fri, Feb 2, 2018 at 7:08 AM, Timothy Arceri  wrote:
> We move the nir check before the shader cache call so that we can
> call a nir based caching function in a following patch.
>
> Also with this change we simply check if vertex shaders support
> NIR rather than looping over the stages as mixing of shader types
> is not supported anyway.
> ---
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 15 +++
>  1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 84ed614927..355ba28218 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -6916,15 +6916,20 @@ extern "C" {
>  GLboolean
>  st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
>  {
> +   struct pipe_screen *pscreen = ctx->st->pipe->screen;
> +
> +   enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
> +  pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
> +PIPE_SHADER_CAP_PREFERRED_IR);
> +   bool use_nir = preferred_ir == PIPE_SHADER_IR_NIR;
> +
> /* Return early if we are loading the shader from on-disk cache */
> if (st_load_tgsi_from_disk_cache(ctx, prog)) {
>return GL_TRUE;
> }
>
> -   struct pipe_screen *pscreen = ctx->st->pipe->screen;
> assert(prog->data->LinkStatus);
>
> -   bool use_nir = false;
> for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
>if (prog->_LinkedShaders[i] == NULL)
>   continue;
> @@ -6944,12 +6949,6 @@ st_link_shader(struct gl_context *ctx, struct 
> gl_shader_program *prog)
>unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
>  
> PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
>
> -  enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
> - pscreen->get_shader_param(pscreen, ptarget,
> -   PIPE_SHADER_CAP_PREFERRED_IR);
> -  if (preferred_ir == PIPE_SHADER_IR_NIR)
> - use_nir = true;
> -
>/* If there are forms of indirect addressing that the driver
> * cannot handle, perform the lowering pass.
> */
> --
> 2.14.3
>
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Re: [Mesa-dev] [PATCH] travis: radeonsi and radv need LLVM 4.0

[Kyriazis, George]

As far as SWR is concerned, we’ll have to ask our customers.  Will respond 
shortly.

Thanks,

George

> On Feb 6, 2018, at 9:42 AM, Andres Gomez  wrote:
> 
> Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
> Cc: Marek Olšák 
> Cc: Emil Velikov 
> Cc: Jan Vesely 
> Signed-off-by: Andres Gomez 
> ---
> 
> Additionally, AMD's support removal for LLVM 3.9 has also affected the
> distcheck target.
> 
> Unfortunately, SWR distribution needs 3.9.x, therefore, we cannot
> simply use LLVM 4.0 to generate the distribution tarball.
> 
> Either SWR upgrades its minimal dependency to LLVM 4.0 or we find a
> way of instructing distcheck so it would use LLVM 3.9 for the tarball
> generation and LLVM 4.0 for the check stage of the distcheck ...
> 
> .travis.yml | 46 --
> 1 file changed, 36 insertions(+), 10 deletions(-)
> 
> diff --git a/.travis.yml b/.travis.yml
> index 0156eefb7ad..3651d00169f 100644
> --- a/.travis.yml
> +++ b/.travis.yml
> @@ -37,12 +37,12 @@ matrix:
>   addons:
> apt:
>   sources:
> -- llvm-toolchain-trusty-3.9
> +- llvm-toolchain-trusty-4.0
>   packages:
> # LLVM packaging is broken and misses these dependencies
> - libedit-dev
> # From sources above
> -- llvm-3.9-dev
> +- llvm-4.0-dev
> # Common
> - xz-utils
> - libexpat1-dev
> @@ -119,6 +119,35 @@ matrix:
> - libx11-xcb-dev
> - libelf-dev
> - libunwind8-dev
> +- env:
> +- LABEL="make Gallium Drivers RadeonSI"
> +- BUILD=make
> +- MAKEFLAGS="-j4"
> +- MAKE_CHECK_COMMAND="true"
> +- LLVM_VERSION=4.0
> +- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
> +- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
> +- DRI_DRIVERS=""
> +- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa 
> --disable-nine --disable-xvmc --disable-vdpau --disable-va 
> --disable-omx-bellagio --disable-gallium-osmesa"
> +- GALLIUM_DRIVERS="radeonsi"
> +- VULKAN_DRIVERS=""
> +- LIBUNWIND_FLAGS="--enable-libunwind"
> +  addons:
> +apt:
> +  sources:
> +- llvm-toolchain-trusty-4.0
> +  packages:
> +# LLVM packaging is broken and misses these dependencies
> +- libedit-dev
> +# From sources above
> +- llvm-4.0-dev
> +# Common
> +- xz-utils
> +- x11proto-xf86vidmode-dev
> +- libexpat1-dev
> +- libx11-xcb-dev
> +- libelf-dev
> +- libunwind8-dev
> - env:
> - LABEL="make Gallium Drivers Other"
> - BUILD=make
> @@ -131,7 +160,7 @@ matrix:
> - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
> - DRI_DRIVERS=""
> - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa 
> --disable-nine --disable-xvmc --disable-vdpau --disable-va 
> --disable-omx-bellagio --disable-gallium-osmesa"
> -- 
> GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
> +- 
> GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
> - VULKAN_DRIVERS=""
> - LIBUNWIND_FLAGS="--enable-libunwind"
>   addons:
> @@ -166,7 +195,7 @@ matrix:
> - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
> - DRI_DRIVERS=""
> - GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd 
> --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau 
> --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
> -- GALLIUM_DRIVERS="r600,radeonsi"
> +- GALLIUM_DRIVERS="r600"
> - VULKAN_DRIVERS=""
> - LIBUNWIND_FLAGS="--enable-libunwind"
>   addons:
> @@ -303,10 +332,8 @@ matrix:
> - BUILD=make
> - MAKEFLAGS="-j4"
> - MAKE_CHECK_COMMAND="make -C src/gtest check && make -C src/intel 
> check"
> -- LLVM_VERSION=3.9
> +- LLVM_VERSION=4.0
> - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
> -# New binutils linker is required for llvm-3.9
> -- OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
> - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl 
> --with-platforms=x11,wayland"
> - DRI_DRIVERS=""
> - GALLIUM_ST="--enable-dri --enable-dri3 --disable-opencl 
> --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va 
> --disable-omx-bellagio --disable-gallium-osmesa"
> @@ -316,13 +343,12 @@ matrix:
>   addons:
> apt:
>   sources:
> -- llvm-toolchain-trusty-3.9
> +- llvm-toolchain-trusty-4.0
>   packages:
> -- binutils-2.26
>

[Mesa-dev] [PATCH] travis: radeonsi and radv need LLVM 4.0

[Andres Gomez]

Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
Cc: Marek Olšák 
Cc: Emil Velikov 
Cc: Jan Vesely 
Signed-off-by: Andres Gomez 
---

Additionally, AMD's support removal for LLVM 3.9 has also affected the
distcheck target.

Unfortunately, SWR distribution needs 3.9.x, therefore, we cannot
simply use LLVM 4.0 to generate the distribution tarball.

Either SWR upgrades its minimal dependency to LLVM 4.0 or we find a
way of instructing distcheck so it would use LLVM 3.9 for the tarball
generation and LLVM 4.0 for the check stage of the distcheck ...

 .travis.yml | 46 --
 1 file changed, 36 insertions(+), 10 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 0156eefb7ad..3651d00169f 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -37,12 +37,12 @@ matrix:
   addons:
 apt:
   sources:
-- llvm-toolchain-trusty-3.9
+- llvm-toolchain-trusty-4.0
   packages:
 # LLVM packaging is broken and misses these dependencies
 - libedit-dev
 # From sources above
-- llvm-3.9-dev
+- llvm-4.0-dev
 # Common
 - xz-utils
 - libexpat1-dev
@@ -119,6 +119,35 @@ matrix:
 - libx11-xcb-dev
 - libelf-dev
 - libunwind8-dev
+- env:
+- LABEL="make Gallium Drivers RadeonSI"
+- BUILD=make
+- MAKEFLAGS="-j4"
+- MAKE_CHECK_COMMAND="true"
+- LLVM_VERSION=4.0
+- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
+- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
+- DRI_DRIVERS=""
+- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa 
--disable-nine --disable-xvmc --disable-vdpau --disable-va 
--disable-omx-bellagio --disable-gallium-osmesa"
+- GALLIUM_DRIVERS="radeonsi"
+- VULKAN_DRIVERS=""
+- LIBUNWIND_FLAGS="--enable-libunwind"
+  addons:
+apt:
+  sources:
+- llvm-toolchain-trusty-4.0
+  packages:
+# LLVM packaging is broken and misses these dependencies
+- libedit-dev
+# From sources above
+- llvm-4.0-dev
+# Common
+- xz-utils
+- x11proto-xf86vidmode-dev
+- libexpat1-dev
+- libx11-xcb-dev
+- libelf-dev
+- libunwind8-dev
 - env:
 - LABEL="make Gallium Drivers Other"
 - BUILD=make
@@ -131,7 +160,7 @@ matrix:
 - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
 - DRI_DRIVERS=""
 - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa 
--disable-nine --disable-xvmc --disable-vdpau --disable-va 
--disable-omx-bellagio --disable-gallium-osmesa"
-- 
GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
+- 
GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
 - VULKAN_DRIVERS=""
 - LIBUNWIND_FLAGS="--enable-libunwind"
   addons:
@@ -166,7 +195,7 @@ matrix:
 - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
 - DRI_DRIVERS=""
 - GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd 
--enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau 
--disable-va --disable-omx-bellagio --disable-gallium-osmesa"
-- GALLIUM_DRIVERS="r600,radeonsi"
+- GALLIUM_DRIVERS="r600"
 - VULKAN_DRIVERS=""
 - LIBUNWIND_FLAGS="--enable-libunwind"
   addons:
@@ -303,10 +332,8 @@ matrix:
 - BUILD=make
 - MAKEFLAGS="-j4"
 - MAKE_CHECK_COMMAND="make -C src/gtest check && make -C src/intel 
check"
-- LLVM_VERSION=3.9
+- LLVM_VERSION=4.0
 - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
-# New binutils linker is required for llvm-3.9
-- OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
 - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl 
--with-platforms=x11,wayland"
 - DRI_DRIVERS=""
 - GALLIUM_ST="--enable-dri --enable-dri3 --disable-opencl --disable-xa 
--disable-nine --disable-xvmc --disable-vdpau --disable-va 
--disable-omx-bellagio --disable-gallium-osmesa"
@@ -316,13 +343,12 @@ matrix:
   addons:
 apt:
   sources:
-- llvm-toolchain-trusty-3.9
+- llvm-toolchain-trusty-4.0
   packages:
-- binutils-2.26
 # LLVM packaging is broken and misses these dependencies
 - libedit-dev
 # From sources above
-- llvm-3.9-dev
+- llvm-4.0-dev
 # Common
 - xz-utils
 - x11proto-xf86vidmode-dev
-- 
2.15.1

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Re: [Mesa-dev] [PATCH 8/8] drivers/radeonsi: enable uvd encode for HEVC main

[Boyuan Zhang]

this patch is Reviewed-by: Boyuan Zhang 


On 2018-02-05 12:16 PM, James Zhu wrote:

Enable UVD encode for HEVC main profile

Signed-off-by: James Zhu 
---
  src/gallium/drivers/radeonsi/si_get.c | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index 8002362..64f76b4 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -24,6 +24,7 @@
  #include "si_pipe.h"
  #include "radeon/radeon_video.h"
  #include "radeon/radeon_vce.h"
+#include "radeon/radeon_uvd_enc.h"
  #include "ac_llvm_util.h"
  #include "vl/vl_decoder.h"
  #include "vl/vl_video_buffer.h"
@@ -587,7 +588,8 @@ static int si_get_video_param(struct pipe_screen *screen,
(si_vce_is_fw_version_supported(sscreen) ||
sscreen->info.family == CHIP_RAVEN)) ||
(profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
-   sscreen->info.family == CHIP_RAVEN);
+   (sscreen->info.family == CHIP_RAVEN ||
+   si_radeon_uvd_enc_supported(sscreen)));
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
return 1;
case PIPE_VIDEO_CAP_MAX_WIDTH:


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Re: [Mesa-dev] [PATCH v2 1/6] android: Move gralloc handle struct to libdrm

[Robert Foss]

On 02/06/2018 01:08 AM, Rob Herring wrote:

On Mon, Jan 29, 2018 at 11:37 AM, Robert Foss  wrote:

This struct is used in mesa and drm_hwcomposer.
Versions of if have been implemented in several grallocs:
drm_gralloc, gbm_gralloc, minigbm and intel-minigbm.

Other than the 1:1 move of the struct a new generic name
has been chosen and variables have had comments added to them.

Signed-off-by: Robert Foss 
---
Changes since v1:
  Suggested by Rob Herring:
  - Fixed copyright statement
  - Moved FDs to be first in handle
  - Initialize native_handle_t using native_handle_create()

  Android.mk   |   8 +++-
  Makefile.sources |   3 ++
  android/gralloc_handle.h | 102 +++
  3 files changed, 111 insertions(+), 2 deletions(-)
  create mode 100644 android/gralloc_handle.h

diff --git a/Android.mk b/Android.mk
index 292be2360263..8611c5e316d8 100644
--- a/Android.mk
+++ b/Android.mk
@@ -28,7 +28,7 @@ LIBDRM_TOP := $(LOCAL_PATH)

  include $(CLEAR_VARS)

-# Import variables LIBDRM_{,H_,INCLUDE_H_,INCLUDE_VMWGFX_H_}FILES
+# Import variables 
LIBDRM_{,H,INCLUDE_H,INCLUDE_ANDROID_H,INCLUDE_VMWGFX_H}_FILES
  include $(LOCAL_PATH)/Makefile.sources

  #static library for the device (recovery)
@@ -38,7 +38,8 @@ LOCAL_MODULE := libdrm
  LOCAL_SRC_FILES := $(LIBDRM_FILES)
  LOCAL_EXPORT_C_INCLUDE_DIRS := \
 $(LOCAL_PATH) \
-   $(LOCAL_PATH)/include/drm
+   $(LOCAL_PATH)/include/drm \
+   $(LOCAL_PATH)/android

  LOCAL_C_INCLUDES := \
 $(LOCAL_PATH)/include/drm
@@ -54,6 +55,9 @@ LOCAL_SRC_FILES := $(LIBDRM_FILES)
  LOCAL_EXPORT_C_INCLUDE_DIRS := \
  $(LOCAL_PATH)/include/drm

+LOCAL_SHARED_LIBRARIES := \
+   libcutils
+
  LOCAL_C_INCLUDES := \
  $(LOCAL_PATH)/include/drm

diff --git a/Makefile.sources b/Makefile.sources
index 10aa1d0f4b6e..1f8372bca183 100644
--- a/Makefile.sources
+++ b/Makefile.sources
@@ -37,5 +37,8 @@ LIBDRM_INCLUDE_H_FILES := \
 include/drm/via_drm.h \
 include/drm/virtgpu_drm.h

+LIBDRM_INCLUDE_ANDROID_H_FILES := \
+   android/gralloc_handle.h
+
  LIBDRM_INCLUDE_VMWGFX_H_FILES := \
 include/drm/vmwgfx_drm.h
diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h
new file mode 100644
index ..770ee7adb4b5
--- /dev/null
+++ b/android/gralloc_handle.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2018 Robert Foss 


Sorry, if I wasn't clear, but this obviously comes from
gralloc_drm_handle.h. You should maintain those copyrights (and make
sure we aren't changing the license).


Oh, sorry about the confusion. I'll send a v3, containing a fix.


Rob.




+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 
THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *Robert Foss 
+ */
+
+#ifndef __ANDROID_GRALLOC_HANDLE_H__
+#define __ANDROID_GRALLOC_HANDLE_H__
+
+#include 
+
+/* support users of drm_gralloc/gbm_gralloc */
+#define gralloc_gbm_handle_t gralloc_handle_t
+#define gralloc_drm_handle_t gralloc_handle_t
+
+struct gralloc_handle_t {
+   native_handle_t base;
+
+   /* dma-buf file descriptor
+* Must be located first since, native_handle_t is allocated
+* using native_handle_create(), which allocates space for
+* sizeof(native_handle_t) + sizeof(int) * (numFds + numInts)
+* numFds = GRALLOC_HANDLE_NUM_FDS
+* numInts = GRALLOC_HANDLE_NUM_INTS
+* Where numFds represents the number of FDs and
+* numInts represents the space needed for the
+* remainder of this struct.
+* And the FDs are expected to be found first following
+* native_handle_t.
+*/
+   int prime_fd;
+
+   int magic; /* differentiate between allocator impls */
+
+   int width; /* width of buffer in pixels */
+   int height; /* height of buffer in 

Re: [Mesa-dev] [PATCH] mesa: Factor out _mesa_disable_vertex_array_attrib.

[Brian Paul]

All three look good to me.

Reviewed-by: Brian Paul 


On 02/06/2018 12:59 AM, mathias.froehl...@gmx.net wrote:

From: Mathias Fröhlich 

Hi,

Simple code deduplication and factoring out a function that
will be usefull soon.

please review

thanks!!

Mathias



And use it in the enable code path.
Move _mesa_update_attribute_map_mode into its only remaining file.

Signed-off-by: Mathias Fröhlich 
---
  src/mesa/main/arrayobj.h | 26 
  src/mesa/main/enable.c   | 64 ++--
  src/mesa/main/varray.c   | 58 ---
  src/mesa/main/varray.h   |  7 ++
  4 files changed, 75 insertions(+), 80 deletions(-)

diff --git a/src/mesa/main/arrayobj.h b/src/mesa/main/arrayobj.h
index 411ed65c50..5de74505bb 100644
--- a/src/mesa/main/arrayobj.h
+++ b/src/mesa/main/arrayobj.h
@@ -99,32 +99,6 @@ extern const GLubyte
  _mesa_vao_attribute_map[ATTRIBUTE_MAP_MODE_MAX][VERT_ATTRIB_MAX];
  
  
-/**

- * Depending on the position and generic0 attributes enable flags select
- * the one that is used for both attributes.
- * The generic0 attribute takes precedence.
- */
-static inline void
-_mesa_update_attribute_map_mode(const struct gl_context *ctx,
-struct gl_vertex_array_object *vao)
-{
-   /*
-* There is no need to change the mapping away from the
-* identity mapping if we are not in compat mode.
-*/
-   if (ctx->API != API_OPENGL_COMPAT)
-  return;
-   /* The generic0 attribute superseeds the position attribute */
-   const GLbitfield enabled = vao->_Enabled;
-   if (enabled & VERT_BIT_GENERIC0)
-  vao->_AttributeMapMode = ATTRIBUTE_MAP_MODE_GENERIC0;
-   else if (enabled & VERT_BIT_POS)
-  vao->_AttributeMapMode = ATTRIBUTE_MAP_MODE_POSITION;
-   else
-  vao->_AttributeMapMode = ATTRIBUTE_MAP_MODE_IDENTITY;
-}
-
-
  /**
   * Apply the position/generic0 aliasing map to a bitfield from the vao.
   * Use for example to convert gl_vertex_array_object::_Enabled
diff --git a/src/mesa/main/enable.c b/src/mesa/main/enable.c
index bc22410bda..967d23080c 100644
--- a/src/mesa/main/enable.c
+++ b/src/mesa/main/enable.c
@@ -40,6 +40,7 @@
  #include "mtypes.h"
  #include "enums.h"
  #include "texstate.h"
+#include "varray.h"
  
  
  
@@ -58,55 +59,56 @@ update_derived_primitive_restart_state(struct gl_context *ctx)

|| ctx->Array.PrimitiveRestartFixedIndex;
  }
  
+

+/**
+ * Helper to enable/disable VAO client-side state.
+ */
+static void
+vao_state(struct gl_context *ctx, gl_vert_attrib attr, GLboolean state)
+{
+   if (state)
+  _mesa_enable_vertex_array_attrib(ctx, ctx->Array.VAO, attr);
+   else
+  _mesa_disable_vertex_array_attrib(ctx, ctx->Array.VAO, attr);
+}
+
+
  /**
   * Helper to enable/disable client-side state.
   */
  static void
  client_state(struct gl_context *ctx, GLenum cap, GLboolean state)
  {
-   struct gl_vertex_array_object *vao = ctx->Array.VAO;
-   GLbitfield vert_attrib_bit;
-   GLboolean *enable_var;
-
 switch (cap) {
case GL_VERTEX_ARRAY:
- enable_var = >VertexAttrib[VERT_ATTRIB_POS].Enabled;
- vert_attrib_bit = VERT_BIT_POS;
+ vao_state(ctx, VERT_ATTRIB_POS, state);
   break;
case GL_NORMAL_ARRAY:
- enable_var = >VertexAttrib[VERT_ATTRIB_NORMAL].Enabled;
- vert_attrib_bit = VERT_BIT_NORMAL;
+ vao_state(ctx, VERT_ATTRIB_NORMAL, state);
   break;
case GL_COLOR_ARRAY:
- enable_var = >VertexAttrib[VERT_ATTRIB_COLOR0].Enabled;
- vert_attrib_bit = VERT_BIT_COLOR0;
+ vao_state(ctx, VERT_ATTRIB_COLOR0, state);
   break;
case GL_INDEX_ARRAY:
- enable_var = >VertexAttrib[VERT_ATTRIB_COLOR_INDEX].Enabled;
- vert_attrib_bit = VERT_BIT_COLOR_INDEX;
+ vao_state(ctx, VERT_ATTRIB_COLOR_INDEX, state);
   break;
case GL_TEXTURE_COORD_ARRAY:
- enable_var = 
>VertexAttrib[VERT_ATTRIB_TEX(ctx->Array.ActiveTexture)].Enabled;
- vert_attrib_bit = VERT_BIT_TEX(ctx->Array.ActiveTexture);
+ vao_state(ctx, VERT_ATTRIB_TEX(ctx->Array.ActiveTexture), state);
   break;
case GL_EDGE_FLAG_ARRAY:
- enable_var = >VertexAttrib[VERT_ATTRIB_EDGEFLAG].Enabled;
- vert_attrib_bit = VERT_BIT_EDGEFLAG;
+ vao_state(ctx, VERT_ATTRIB_EDGEFLAG, state);
   break;
case GL_FOG_COORDINATE_ARRAY_EXT:
- enable_var = >VertexAttrib[VERT_ATTRIB_FOG].Enabled;
- vert_attrib_bit = VERT_BIT_FOG;
+ vao_state(ctx, VERT_ATTRIB_FOG, state);
   break;
case GL_SECONDARY_COLOR_ARRAY_EXT:
- enable_var = >VertexAttrib[VERT_ATTRIB_COLOR1].Enabled;
- vert_attrib_bit = VERT_BIT_COLOR1;
+ vao_state(ctx, VERT_ATTRIB_COLOR1, state);
   break;
  
case GL_POINT_SIZE_ARRAY_OES:

- enable_var = 

Re: [Mesa-dev] [PATCH] radeonsi: set indent_size in .editorconfig

[Grazvydas Ignotas]

On Tue, Feb 6, 2018 at 1:37 PM, Eric Engestrom
 wrote:
> On Sunday, 2018-02-04 00:19:33 +0200, Grazvydas Ignotas wrote:
>> At least with vim, this is needed to actually get tab instead of
>> 3 spaces after hitting the tab key.
>
> Are you sure?

For my copy of vim (7.4.1689) yes. Not sure what version of
editorconfig plugin I have, can't find a version anywhere.

I don't know about other editors, src/amd/ has the same settings and
nobody complained or changed them.

>
> The doc [1] says:
>
>> indent_size:
>> [...]
>> When set to tab, the value of tab_width (if specified) will be used.
>
>> tab_width:
>> a whole number defining the number of columns used to represent a tab
>> character. This defaults to the value of indent_size and doesn't
>> usually need to be specified.
>
> This sounds to me like `indent_size=tab` means that you want to indent
> with `tab_width` spaces?

That's not how I read it, to me it's the user's preferred tab width
that they configured outside of mesa.

Gražvydas
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Re: [Mesa-dev] [PATCH v4] i965: Avoid problems from referencing orphaned BOs after growing.

[Kenneth Graunke]

On Thursday, January 25, 2018 3:29:01 AM PST Emil Velikov wrote:
> On 18 January 2018 at 07:36, Kenneth Graunke  wrote:
> > Growing the batch/state buffer is a lot more dangerous than I thought.
> >
> > A number of places emit multiple state buffer sections, and then write
> > data to the returned pointer, or save a pointer to brw->batch.state.bo
> > and then use it in relocations.  If each call can grow, this can result
> > in stale map references or stale BO pointers.  Furthermore, fences refer
> > to the old batch BO, and that reference needs to continue working.
> >
> > To avoid these woes, we avoid ever swapping the brw->batch.*.bo pointer,
> > instead exchanging the brw_bo structures in place.  That way, stale BO
> > references are fine - the GEM handle changes, but the brw_bo pointer
> > doesn't.  We also defer the memcpy until a quiescent point, so callers
> > can write to the returned pointer - which may be in either BO - and
> > we'll sort it out and combine the two properly in the end.
> >
> > v2/v3:
> > - Handle stale pointers in the shadow copy case, where realloc may or
> >   may not move our shadow copy to a new address.
> > - Track the partial map explicitly, to avoid problems with buffer reuse
> >   where multiple map modes exist (caught by Chris Wilson).
> >
> > v4:
> > - Don't use realloc in the CPU shadow case, it isn't safe.
> >
> > Fixes: 2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need 
> > space and can't flush."
> > Reviewed-by: Iago Toral Quiroga  [v3]
> > ---
> Hi Ken,
> 
> Picking this patch leads to a few picky conflicts. Can you please
> provide a backport for 17.3?
> Using --subject-prefix="BACKPORT 17.3". would be amazing.
> 
> 
> Thanks
> Emil
> 

Hi Emil,

Sorry, looks like I poorly labeled things...this was the only patch that
"fixes" an issue in an earlier patch, but it needs prior commits.

$ git cherry-pick -x 02c1c25b1a620a336f2e18d39bba188635363f24
# i965: Replace cpu_map pointers with a "use_shadow_copy" boolean.
$ git cherry-pick -x 81ca8e69e327f07f57d597fa6ce23ff67b932de8
# i965: Make a helper for recreating growing buffers.
$ git cherry-pick -x d139b5e4ccf0da19f37428434bf0ef7c76c85049
# i965: Pass brw_growing_bo to grow_buffer().
$ git cherry-pick -x c7dcee58b5fe183e1653c13bff6a212f0d157b29
# i965: Avoid problems from referencing orphaned BOs after growing.

will make it apply cleanly.


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Re: [Mesa-dev] [PATCH 2/3] st/dri: only expose config formats that are display targets

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Sun, Feb 4, 2018 at 8:09 PM, Ilia Mirkin  wrote:
> In the case of NVIDIA hardware, ABGR is displayable but ARGB is not.
> Only advertise the one set in the visuals list.
>
> Signed-off-by: Ilia Mirkin 
> ---
>
> Not sure if this is the right thing, esp for a PRIME-type setup. However
> for the common single-GPU case, it does seem right.
>
>  src/gallium/state_trackers/dri/dri_screen.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/state_trackers/dri/dri_screen.c 
> b/src/gallium/state_trackers/dri/dri_screen.c
> index bd0925b9055..aaee9870776 100644
> --- a/src/gallium/state_trackers/dri/dri_screen.c
> +++ b/src/gallium/state_trackers/dri/dri_screen.c
> @@ -249,7 +249,8 @@ dri_fill_in_modes(struct dri_screen *screen)
>
>if (!p_screen->is_format_supported(p_screen, pipe_formats[format],
>   PIPE_TEXTURE_2D, 0,
> - PIPE_BIND_RENDER_TARGET))
> + PIPE_BIND_RENDER_TARGET |
> + PIPE_BIND_DISPLAY_TARGET))
>   continue;
>
>for (i = 1; i <= msaa_samples_max; i++) {
> --
> 2.13.6
>
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Re: [Mesa-dev] [PATCH 3/4] ac: move get_elem_bits() to ac_llvm_build.c

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Tue, Feb 6, 2018 at 5:58 AM, Timothy Arceri  wrote:
> ---
>  src/amd/common/ac_llvm_build.c  | 19 +++
>  src/amd/common/ac_llvm_build.h  |  3 +++
>  src/amd/common/ac_nir_to_llvm.c | 34 --
>  3 files changed, 30 insertions(+), 26 deletions(-)
>
> diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
> index 6375b106f7..08c488775e 100644
> --- a/src/amd/common/ac_llvm_build.c
> +++ b/src/amd/common/ac_llvm_build.c
> @@ -128,6 +128,25 @@ ac_llvm_extract_elem(struct ac_llvm_context *ac,
>LLVMConstInt(ac->i32, index, false), 
> "");
>  }
>
> +int
> +ac_get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
> +{
> +   if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
> +   type = LLVMGetElementType(type);
> +
> +   if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
> +   return LLVMGetIntTypeWidth(type);
> +
> +   if (type == ctx->f16)
> +   return 16;
> +   if (type == ctx->f32)
> +   return 32;
> +   if (type == ctx->f64)
> +   return 64;
> +
> +   unreachable("Unhandled type kind in get_elem_bits");
> +}
> +
>  unsigned
>  ac_get_type_size(LLVMTypeRef type)
>  {
> diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
> index 78991b3e99..fa09bd10a5 100644
> --- a/src/amd/common/ac_llvm_build.h
> +++ b/src/amd/common/ac_llvm_build.h
> @@ -92,6 +92,9 @@ ac_llvm_context_init(struct ac_llvm_context *ctx, 
> LLVMContextRef context,
>  int
>  ac_get_llvm_num_components(LLVMValueRef value);
>
> +int
> +ac_get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type);
> +
>  LLVMValueRef
>  ac_llvm_extract_elem(struct ac_llvm_context *ac,
>  LLVMValueRef value,
> diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
> index e06a22f8a9..e284795fdc 100644
> --- a/src/amd/common/ac_nir_to_llvm.c
> +++ b/src/amd/common/ac_nir_to_llvm.c
> @@ -329,24 +329,6 @@ create_llvm_function(LLVMContextRef ctx, LLVMModuleRef 
> module,
> return main_function;
>  }
>
> -static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
> -{
> -   if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
> -   type = LLVMGetElementType(type);
> -
> -   if (LLVMGetTypeKind(type) == LLVMIntegerTypeKind)
> -   return LLVMGetIntTypeWidth(type);
> -
> -   if (type == ctx->f16)
> -   return 16;
> -   if (type == ctx->f32)
> -   return 32;
> -   if (type == ctx->f64)
> -   return 64;
> -
> -   unreachable("Unhandled type kind in get_elem_bits");
> -}
> -
>  static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
>  LLVMValueRef param, unsigned rshift,
>  unsigned bitwidth)
> @@ -1267,7 +1249,7 @@ static LLVMValueRef emit_intrin_1f_param(struct 
> ac_llvm_context *ctx,
> };
>
> MAYBE_UNUSED const int length = snprintf(name, sizeof(name), 
> "%s.f%d", intrin,
> -get_elem_bits(ctx, 
> result_type));
> +ac_get_elem_bits(ctx, 
> result_type));
> assert(length < sizeof(name));
> return ac_build_intrinsic(ctx, name, result_type, params, 1, 
> AC_FUNC_ATTR_READNONE);
>  }
> @@ -1284,7 +1266,7 @@ static LLVMValueRef emit_intrin_2f_param(struct 
> ac_llvm_context *ctx,
> };
>
> MAYBE_UNUSED const int length = snprintf(name, sizeof(name), 
> "%s.f%d", intrin,
> -get_elem_bits(ctx, 
> result_type));
> +ac_get_elem_bits(ctx, 
> result_type));
> assert(length < sizeof(name));
> return ac_build_intrinsic(ctx, name, result_type, params, 2, 
> AC_FUNC_ATTR_READNONE);
>  }
> @@ -1302,7 +1284,7 @@ static LLVMValueRef emit_intrin_3f_param(struct 
> ac_llvm_context *ctx,
> };
>
> MAYBE_UNUSED const int length = snprintf(name, sizeof(name), 
> "%s.f%d", intrin,
> -get_elem_bits(ctx, 
> result_type));
> +ac_get_elem_bits(ctx, 
> result_type));
> assert(length < sizeof(name));
> return ac_build_intrinsic(ctx, name, result_type, params, 3, 
> AC_FUNC_ATTR_READNONE);
>  }
> @@ -1922,7 +1904,7 @@ static void visit_alu(struct ac_nir_context *ctx, const 
> nir_alu_instr *instr)
> result = ac_build_intrinsic(>ac, "llvm.bitreverse.i32", 
> ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
> break;
> case nir_op_bit_count:
> -   if (get_elem_bits(>ac, LLVMTypeOf(src[0])) == 32)
> +   if (ac_get_elem_bits(>ac, LLVMTypeOf(src[0])) == 32)
>   

Re: [Mesa-dev] [PATCH] mesa: add glsl version query

[Brian Paul]

On 02/06/2018 09:32 AM, Vadym Shovkoplias wrote:

From: Vadym Shovkoplias 

Add support for GL_NUM_SHADING_LANGUAGE_VERSIONS
and glGetStringi for GL_SHADING_LANGUAGE_VERSION

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104915
Signed-off-by: Andriy Khulap 
Signed-off-by: Vadym Shovkoplias 
---
  src/mapi/glapi/gen/GL4x.xml  |  1 +
  src/mesa/main/get.c  | 31 ++
  src/mesa/main/get_hash_params.py |  3 +++
  src/mesa/main/getstring.c| 56 
  4 files changed, 91 insertions(+)

diff --git a/src/mapi/glapi/gen/GL4x.xml b/src/mapi/glapi/gen/GL4x.xml
index cd2e3b831e..2116286b35 100644
--- a/src/mapi/glapi/gen/GL4x.xml
+++ b/src/mapi/glapi/gen/GL4x.xml
@@ -42,6 +42,7 @@
  
  


+  



diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index 516e8d174c..958bb62dc6 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -1084,6 +1084,37 @@ find_custom_value(struct gl_context *ctx, const struct 
value_desc *d, union valu
   v->value_int = 0;
}
break;
+   /* GL_NUM_SHADING_LANGUAGE_VERSIONS */


I think that a more useful comment would be /* GL 4.3 */



+   case GL_NUM_SHADING_LANGUAGE_VERSIONS:
+  {
+ int num = 0;
+ /* GLSL es */
+ if (ctx->API == API_OPENGLES2 || 
ctx->Extensions.ARB_ES2_compatibility)
+num++;
+ if (_mesa_is_gles3(ctx) || ctx->Extensions.ARB_ES3_compatibility)
+num++;
+ if (_mesa_is_gles31(ctx) || ctx->Extensions.ARB_ES3_1_compatibility)
+num++;
+ if ((ctx->API == API_OPENGLES2 && ctx->Version >= 32) ||
+  ctx->Extensions.ARB_ES3_2_compatibility)
+num++;
+ /* GLSL core */
+ if (ctx->Const.GLSLVersion >= 120) num++;
+ if (ctx->Const.GLSLVersion >= 130) num++;
+ if (ctx->Const.GLSLVersion >= 140) num++;
+ if (ctx->Const.GLSLVersion >= 150) num++;
+ if (ctx->Const.GLSLVersion >= 330) num++;
+ if (ctx->Const.GLSLVersion >= 400) num++;
+ if (ctx->Const.GLSLVersion >= 410) num++;
+ if (ctx->Const.GLSLVersion >= 420) num++;
+ if (ctx->Const.GLSLVersion >= 430) num++;
+ if (ctx->Const.GLSLVersion >= 440) num++;
+ if (ctx->Const.GLSLVersion >= 450) num++;
+ if (ctx->Const.GLSLVersion >= 460) num++;


It would be nice if that code could be combined with the 
shading_language_version_index() code below so that when a new SL 
version comes along, only one function would have to be updated instead 
of two.  You're already computing the number of versions there too.




+
+ v->value_int = num;
+  }
+  break;
 /* GL_ARB_draw_indirect */
 case GL_DRAW_INDIRECT_BUFFER_BINDING:
v->value_int = ctx->DrawIndirectBuffer->Name;
diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py
index df082af207..be716f6f6e 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -543,6 +543,9 @@ descriptor=[
  
# GL_ARB_texture_cube_map_array

[ "TEXTURE_BINDING_CUBE_MAP_ARRAY_ARB", "LOC_CUSTOM, TYPE_INT, 
TEXTURE_CUBE_ARRAY_INDEX, extra_ARB_texture_cube_map_array_OES_texture_cube_map_array" ],
+
+  # GL_NUM_SHADING_LANGUAGE_VERSIONS
+  [ "NUM_SHADING_LANGUAGE_VERSIONS", "LOC_CUSTOM, TYPE_INT, 0, NO_EXTRA" ],
  ]},
  
  # Enums in OpenGL Core profile and ES 3.0

diff --git a/src/mesa/main/getstring.c b/src/mesa/main/getstring.c
index 931f6a476c..50136b91b3 100644
--- a/src/mesa/main/getstring.c
+++ b/src/mesa/main/getstring.c
@@ -99,6 +99,60 @@ shading_language_version(struct gl_context *ctx)
  }
  
  
+/**

+ * Return the string for a glGetStringi(GL_SHADING_LANGUAGE_VERSION) query.
+ */
+static const GLubyte *
+shading_language_version_index(struct gl_context *ctx, GLuint index)
+{
+   char *supported_versions[17];
+   int num_supported = 0;
+
+   /* Reversed order */
+   /* GLSL es */
+   if (ctx->API == API_OPENGLES2 || ctx->Extensions.ARB_ES2_compatibility)
+  supported_versions[num_supported++] = "100";
+   if (_mesa_is_gles3(ctx) || ctx->Extensions.ARB_ES3_compatibility)
+  supported_versions[num_supported++] = "300 es";
+   if (_mesa_is_gles31(ctx) || ctx->Extensions.ARB_ES3_1_compatibility)
+  supported_versions[num_supported++] = "310 es";
+   if ((ctx->API == API_OPENGLES2 && ctx->Version >= 32) ||
+   ctx->Extensions.ARB_ES3_2_compatibility)
+  supported_versions[num_supported++] = "320 es";
+
+   /* GLSL core */
+   if (ctx->Const.GLSLVersion >= 120)
+  supported_versions[num_supported++] = "120";
+   if (ctx->Const.GLSLVersion >= 130)
+  supported_versions[num_supported++] = "130";
+   if (ctx->Const.GLSLVersion >= 140)
+  supported_versions[num_supported++] = "140";
+   if (ctx->Const.GLSLVersion >= 150)
+  

Re: [Mesa-dev] [PATCH 3/3] st/mesa: use st_access_flags_to_transfer_flags() helper in more places

[Marek Olšák]

For the series:

Reviewed-by: Marek Olšák 

Marek

On Mon, Feb 5, 2018 at 6:22 PM, Brian Paul  wrote:
> ---
>  src/mesa/state_tracker/st_cb_fbo.c | 18 +-
>  src/mesa/state_tracker/st_cb_texture.c | 17 -
>  2 files changed, 17 insertions(+), 18 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_cb_fbo.c 
> b/src/mesa/state_tracker/st_cb_fbo.c
> index 3a5c03c..0800f5b 100644
> --- a/src/mesa/state_tracker/st_cb_fbo.c
> +++ b/src/mesa/state_tracker/st_cb_fbo.c
> @@ -47,6 +47,7 @@
>  #include "pipe/p_screen.h"
>  #include "st_atom.h"
>  #include "st_context.h"
> +#include "st_cb_bufferobjects.h"
>  #include "st_cb_fbo.h"
>  #include "st_cb_flush.h"
>  #include "st_cb_texture.h"
> @@ -780,7 +781,6 @@ st_MapRenderbuffer(struct gl_context *ctx,
> struct st_renderbuffer *strb = st_renderbuffer(rb);
> struct pipe_context *pipe = st->pipe;
> const GLboolean invert = rb->Name == 0;
> -   unsigned usage;
> GLuint y2;
> GLubyte *map;
>
> @@ -800,13 +800,13 @@ st_MapRenderbuffer(struct gl_context *ctx,
>return;
> }
>
> -   usage = 0x0;
> -   if (mode & GL_MAP_READ_BIT)
> -  usage |= PIPE_TRANSFER_READ;
> -   if (mode & GL_MAP_WRITE_BIT)
> -  usage |= PIPE_TRANSFER_WRITE;
> -   if (mode & GL_MAP_INVALIDATE_RANGE_BIT)
> -  usage |= PIPE_TRANSFER_DISCARD_RANGE;
> +   /* Check for unexpected flags */
> +   assert((mode & ~(GL_MAP_READ_BIT |
> +GL_MAP_WRITE_BIT |
> +GL_MAP_INVALIDATE_RANGE_BIT)) == 0);
> +
> +   const enum pipe_transfer_usage transfer_flags =
> +  st_access_flags_to_transfer_flags(mode, false);
>
> /* Note: y=0=bottom of buffer while y2=0=top of buffer.
>  * 'invert' will be true for window-system buffers and false for
> @@ -821,7 +821,7 @@ st_MapRenderbuffer(struct gl_context *ctx,
>  strb->texture,
>  strb->surface->u.tex.level,
>  strb->surface->u.tex.first_layer,
> -usage, x, y2, w, h, >transfer);
> +transfer_flags, x, y2, w, h, >transfer);
> if (map) {
>if (invert) {
>   *rowStrideOut = -(int) strb->transfer->stride;
> diff --git a/src/mesa/state_tracker/st_cb_texture.c 
> b/src/mesa/state_tracker/st_cb_texture.c
> index 98f2443..6345ead 100644
> --- a/src/mesa/state_tracker/st_cb_texture.c
> +++ b/src/mesa/state_tracker/st_cb_texture.c
> @@ -254,19 +254,18 @@ st_MapTextureImage(struct gl_context *ctx,
>  {
> struct st_context *st = st_context(ctx);
> struct st_texture_image *stImage = st_texture_image(texImage);
> -   unsigned pipeMode;
> GLubyte *map;
> struct pipe_transfer *transfer;
>
> -   pipeMode = 0x0;
> -   if (mode & GL_MAP_READ_BIT)
> -  pipeMode |= PIPE_TRANSFER_READ;
> -   if (mode & GL_MAP_WRITE_BIT)
> -  pipeMode |= PIPE_TRANSFER_WRITE;
> -   if (mode & GL_MAP_INVALIDATE_RANGE_BIT)
> -  pipeMode |= PIPE_TRANSFER_DISCARD_RANGE;
> +   /* Check for unexpected flags */
> +   assert((mode & ~(GL_MAP_READ_BIT |
> +GL_MAP_WRITE_BIT |
> +GL_MAP_INVALIDATE_RANGE_BIT)) == 0);
>
> -   map = st_texture_image_map(st, stImage, pipeMode, x, y, slice, w, h, 1,
> +   const enum pipe_transfer_usage transfer_flags =
> +  st_access_flags_to_transfer_flags(mode, false);
> +
> +   map = st_texture_image_map(st, stImage, transfer_flags, x, y, slice, w, 
> h, 1,
>);
> if (map) {
>if (st_etc_fallback(st, texImage)) {
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH 1/4] ac: create ac_unpack_64_2x32_split_x() helper

[Marek Olšák]

You don't need this helper. You can just use LLVMBuildTrunc.

Marek

On Tue, Feb 6, 2018 at 5:58 AM, Timothy Arceri  wrote:
> This will be used in the following commits.
> ---
>  src/amd/common/ac_llvm_build.c  | 8 
>  src/amd/common/ac_llvm_build.h  | 3 +++
>  src/amd/common/ac_nir_to_llvm.c | 6 +-
>  3 files changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
> index a86ba962fa..6375b106f7 100644
> --- a/src/amd/common/ac_llvm_build.c
> +++ b/src/amd/common/ac_llvm_build.c
> @@ -1992,6 +1992,14 @@ LLVMValueRef ac_find_lsb(struct ac_llvm_context *ctx,
>LLVMConstInt(ctx->i32, -1, 0), lsb, "");
>  }
>
> +LLVMValueRef ac_unpack_64_2x32_split_x(struct ac_llvm_context *ctx,
> +  LLVMValueRef src0)
> +{
> +   LLVMValueRef tmp = LLVMBuildBitCast(ctx->builder, src0,
> +   ctx->v2i32, "");
> +   return LLVMBuildExtractElement(ctx->builder, tmp, ctx->i32_0, "");
> +}
> +
>  LLVMTypeRef ac_array_in_const_addr_space(LLVMTypeRef elem_type)
>  {
> return LLVMPointerType(LLVMArrayType(elem_type, 0),
> diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
> index 47c843fb4b..78991b3e99 100644
> --- a/src/amd/common/ac_llvm_build.h
> +++ b/src/amd/common/ac_llvm_build.h
> @@ -348,6 +348,9 @@ LLVMValueRef ac_find_lsb(struct ac_llvm_context *ctx,
>  LLVMTypeRef dst_type,
>  LLVMValueRef src0);
>
> +LLVMValueRef ac_unpack_64_2x32_split_x(struct ac_llvm_context *ctx,
> +  LLVMValueRef src0);
> +
>  LLVMTypeRef ac_array_in_const_addr_space(LLVMTypeRef elem_type);
>
>  #ifdef __cplusplus
> diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
> index 9a9db2dce9..ac4af12b3e 100644
> --- a/src/amd/common/ac_nir_to_llvm.c
> +++ b/src/amd/common/ac_nir_to_llvm.c
> @@ -2042,11 +2042,7 @@ static void visit_alu(struct ac_nir_context *ctx, 
> const nir_alu_instr *instr)
>
> case nir_op_unpack_64_2x32_split_x: {
> assert(instr->src[0].src.ssa->num_components == 1);
> -   LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
> -   ctx->ac.v2i32,
> -   "");
> -   result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
> -ctx->ac.i32_0, "");
> +   result = ac_unpack_64_2x32_split_x(>ac, src[0]);
> break;
> }
>
> --
> 2.14.3
>
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[Mesa-dev] [PATCH 3/3] etnaviv: fix in-place resolve tile count

[Lucas Stach]

TS tiles map to a fixed amount of bytes in the color/depth surface,
so the blocksize of the format needs to be taken into account when
calculating the number of tiles to fill.

The simplest fix is to just use the layer stride, which is the surface
size in bytes.

Signed-off-by: Lucas Stach 
---
 src/gallium/drivers/etnaviv/etnaviv_rs.c | 5 +++--
 src/gallium/drivers/etnaviv/etnaviv_rs.h | 1 +
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_rs.c 
b/src/gallium/drivers/etnaviv/etnaviv_rs.c
index 7d9e8e0e3894..bd40cebb5375 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_rs.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_rs.c
@@ -149,7 +149,7 @@ etna_compile_rs_state(struct etna_context *ctx, struct 
compiled_rs_state *cs,
  !rs->swap_rb && !rs->flip &&
  !rs->clear_mode && rs->source_padded_width) {
   /* Total number of tiles (same as for autodisable) */
-  cs->RS_KICKER_INPLACE = rs->source_padded_width * 
rs->source_padded_height / 16;
+  cs->RS_KICKER_INPLACE = rs->tile_count;
}
cs->source_ts_valid = rs->source_ts_valid;
 }
@@ -725,7 +725,8 @@ etna_try_rs_blit(struct pipe_context *pctx,
   .dither = {0x, 0x}, // XXX dither when going from 24 to 
16 bit?
   .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_DISABLED,
   .width = width,
-  .height = height
+  .height = height,
+  .tile_count = src_lev->layer_stride / 64
});
 
etna_submit_rs_state(ctx, _to_screen);
diff --git a/src/gallium/drivers/etnaviv/etnaviv_rs.h 
b/src/gallium/drivers/etnaviv/etnaviv_rs.h
index e71dfa0b8a0a..125a13a9ad34 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_rs.h
+++ b/src/gallium/drivers/etnaviv/etnaviv_rs.h
@@ -56,6 +56,7 @@ struct rs_state {
uint32_t clear_bits;
uint32_t clear_mode; /* VIVS_RS_CLEAR_CONTROL_MODE_XXX */
uint32_t clear_value[4];
+   uint32_t tile_count;
uint8_t aa;
uint8_t endian_mode; /* ENDIAN_MODE_XXX */
 };
-- 
2.15.1

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[Mesa-dev] [PATCH 1/3] etnaviv: add debug switch to disable single buffer feature

[Lucas Stach]

This feature has caused some trouble already. Add a debug switch to
allow users to quickly check if a specific issue is caused by this
feature.

Signed-off-by: Lucas Stach 
---
 src/gallium/drivers/etnaviv/etnaviv_debug.h  | 1 +
 src/gallium/drivers/etnaviv/etnaviv_screen.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_debug.h 
b/src/gallium/drivers/etnaviv/etnaviv_debug.h
index f47dffe59008..4051e95dd5fb 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_debug.h
+++ b/src/gallium/drivers/etnaviv/etnaviv_debug.h
@@ -52,6 +52,7 @@
 #define ETNA_DBG_ZERO0x20 /* Zero all resources after 
allocation */
 #define ETNA_DBG_DRAW_STALL  0x40 /* Stall FE/PE after every draw op */
 #define ETNA_DBG_SHADERDB0x80 /* dump program compile information 
*/
+#define ETNA_DBG_NO_SINGLEBUF0x100 /* disable single buffer feature */
 
 extern int etna_mesa_debug; /* set in etna_screen.c from ETNA_DEBUG */
 
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c 
b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index d5d1f4fdad2c..7b4034641d18 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -68,6 +68,7 @@ static const struct debug_named_value debug_options[] = {
{"zero",   ETNA_DBG_ZERO, "Zero all resources after allocation"},
{"draw_stall", ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered 
primitive"},
{"shaderdb",   ETNA_DBG_SHADERDB, "Enable shaderdb output"},
+   {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"},
DEBUG_NAMED_VALUE_END
 };
 
@@ -967,6 +968,8 @@ etna_screen_create(struct etna_device *dev, struct etna_gpu 
*gpu,
   screen->features[viv_chipMinorFeatures1] &= 
~chipMinorFeatures1_AUTO_DISABLE;
if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
   screen->specs.can_supertile = 0;
+   if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF))
+  screen->specs.single_buffer = 0;
 
pscreen->destroy = etna_screen_destroy;
pscreen->get_param = etna_screen_get_param;
-- 
2.15.1

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[Mesa-dev] [PATCH 2/3] etnaviv: switch magic single buffer state to "3"

[Lucas Stach]

Some of the 16bit formats misrender with missing tiles with the current
"2" state. As all the previously working formats also work with the "3"
state, just always use that one.

Signed-off-by: Lucas Stach 
---
 src/gallium/drivers/etnaviv/etnaviv_state.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_state.c 
b/src/gallium/drivers/etnaviv/etnaviv_state.c
index e4ad0f62f176..87ba10b0dc98 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_state.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_state.c
@@ -323,7 +323,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
 * one per color buffer / depth buffer. To keep the logic simple always use
 * single buffer when this feature is available.
 */
-   cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 
2 : 0);
+   cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 
3 : 0);
 
ctx->framebuffer_s = *sv; /* keep copy of original structure */
ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_DERIVE_TS;
-- 
2.15.1

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Re: [Mesa-dev] [PATCH] radeonsi: set indent_size in .editorconfig

[Eric Engestrom]

On Sunday, 2018-02-04 00:19:33 +0200, Grazvydas Ignotas wrote:
> At least with vim, this is needed to actually get tab instead of
> 3 spaces after hitting the tab key.

Are you sure?

The doc [1] says:

> indent_size:
> [...]
> When set to tab, the value of tab_width (if specified) will be used.

> tab_width:
> a whole number defining the number of columns used to represent a tab
> character. This defaults to the value of indent_size and doesn't
> usually need to be specified.

This sounds to me like `indent_size=tab` means that you want to indent
with `tab_width` spaces?

[1] http://editorconfig.org/#supported-properties

> ---
>  src/gallium/drivers/radeonsi/.editorconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/gallium/drivers/radeonsi/.editorconfig 
> b/src/gallium/drivers/radeonsi/.editorconfig
> index cc8e11f..21a3c7d 100644
> --- a/src/gallium/drivers/radeonsi/.editorconfig
> +++ b/src/gallium/drivers/radeonsi/.editorconfig
> @@ -1,2 +1,3 @@
>  [*.{c,h}]
>  indent_style = tab
> +indent_size = tab
> -- 
> 2.7.4
> 
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[Mesa-dev] [PATCH] ac/nir: fix GS load input type.

[Bas Nieuwenhuizen]

Fixes: df1d5174fc "ac/nir: replace SI.buffer.load.dword with amdgcn.buffer.load"
---
 src/amd/common/ac_nir_to_llvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 3fe08f0a19..faf62ac74b 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3077,7 +3077,7 @@ load_gs_input(struct ac_shader_abi *abi,
}
}
result = ac_build_varying_gather_values(>ac, value, 
num_components, component);
-
+   result = ac_to_integer(>ac, result);
return result;
 }
 
-- 
2.16.1

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Re: [Mesa-dev] [PATCH] meson: ensure xmlpool/options.h is generated for libgallium

[Eric Engestrom]

On Monday, 2018-02-05 21:58:33 +, Jon Turney wrote:
> In file included from ../src/gallium/targets/dri/target.c:1:
> In file included from ../src/gallium/auxiliary/target-helpers/drm_helper.h:8:
> ../src/util/xmlpool.h:103:10: fatal error: 'xmlpool/options.h' file not found
> 
> See also 26bde1e3.
> 
> Signed-off-by: Jon Turney 

Reviewed-by: Eric Engestrom 

> ---
>  src/gallium/targets/dri/meson.build | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/gallium/targets/dri/meson.build 
> b/src/gallium/targets/dri/meson.build
> index 30368c2152..75ce94ab2c 100644
> --- a/src/gallium/targets/dri/meson.build
> +++ b/src/gallium/targets/dri/meson.build
> @@ -51,7 +51,7 @@ endif
>  
>  libgallium_dri = shared_library(
>'gallium_dri',
> -  files('target.c'),
> +  [files('target.c'), xmlpool_options_h],
>include_directories : [
>  inc_common, inc_util, inc_dri_common, inc_gallium_drivers,
>  inc_gallium_winsys, include_directories('../../state_trackers/dri'),
> -- 
> 2.16.1
> 
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[Mesa-dev] [PATCH] ac/nir: fix GS load input type.

[Bas Nieuwenhuizen]

Fixes: df1d5174fc "ac/nir: replace SI.buffer.load.dword with amdgcn.buffer.load"
---
 src/amd/common/ac_nir_to_llvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 3fe08f0a19..faf62ac74b 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3077,7 +3077,7 @@ load_gs_input(struct ac_shader_abi *abi,
}
}
result = ac_build_varying_gather_values(>ac, value, 
num_components, component);
-
+   result = ac_to_integer(>ac, result);
return result;
 }
 
-- 
2.16.1

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[Mesa-dev] [Bug 104949] swrast: Epiphany WEB browser core dumps under Mesa 17.3.3

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104949

--- Comment #5 from Wayne Blaszczyk  ---
es2_info does not return EGL_WL_bind_wayland_display either before or after the
patch, if that is what you were asking for?

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[Mesa-dev] [Bug 104949] swrast: Epiphany WEB browser core dumps under Mesa 17.3.3

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104949

--- Comment #6 from Eric Engestrom  ---
(In reply to Wayne Blaszczyk from comment #5)
> es2_info does not return EGL_WL_bind_wayland_display either before or after
> the patch, if that is what you were asking for?

for egl information you'll want eglinfo, es2_info outputs gles2 information ;)

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[Mesa-dev] [Bug 104949] swrast: Epiphany WEB browser core dumps under Mesa 17.3.3

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104949

--- Comment #7 from Wayne Blaszczyk  ---
(In reply to Eric Engestrom from comment #6)
> (In reply to Wayne Blaszczyk from comment #5)
> > es2_info does not return EGL_WL_bind_wayland_display either before or after
> > the patch, if that is what you were asking for?
> 
> for egl information you'll want eglinfo, es2_info outputs gles2 information
> ;)

I don't have eglinfo. What package does that come from?
es2_info did come back with EGL_WL_bind_wayland_display on my host box which
has an Intel HD chip.

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Re: [Mesa-dev] [PATCH] gallium: Mute arrays for several meta like callbacks.

[Marek Olšák]

You probably want to add new ST_PIPELINE_xxx. See how state filtering
works with ST_PIPELINE_CLEAR.

Marek

On Tue, Feb 6, 2018 at 9:18 PM,   wrote:
> From: Mathias Fröhlich 
>
> Hi Brian,
>
> I think you are right the _mesa_set_drawing_arrays better belong into
> the state tracker. You mean like the below?
> I added also two other callbacks that lookes suspicious to me.
> I just sent the single patch in question out of the series of three.
> Tested with piglit quick on radeonsi, classic swrast and i965
> without regressions.
>
> best and thanks
> Mathias
>
>
> Set the _DrawArray pointer to NULL when calling into the Drivers
> Bitmap/CopyPixels/DrawAtlasBitmaps/DrawPixels/DrawTex hooks.
> This fixes an assert that gets uncovered with the following
> patch gets applied.
>
> v2: Mute from within the state tracker instead of generic mesa.
>
> Signed-off-by: Mathias Fröhlich 
> ---
>  src/mesa/state_tracker/st_cb_bitmap.c | 7 +++
>  src/mesa/state_tracker/st_cb_drawpixels.c | 7 +++
>  src/mesa/state_tracker/st_cb_drawtex.c| 4 
>  3 files changed, 18 insertions(+)
>
> diff --git a/src/mesa/state_tracker/st_cb_bitmap.c 
> b/src/mesa/state_tracker/st_cb_bitmap.c
> index a5c7ed0ee6..a1e35994de 100644
> --- a/src/mesa/state_tracker/st_cb_bitmap.c
> +++ b/src/mesa/state_tracker/st_cb_bitmap.c
> @@ -36,6 +36,7 @@
>  #include "main/dlist.h"
>  #include "main/macros.h"
>  #include "main/pbo.h"
> +#include "main/varray.h"
>  #include "program/program.h"
>  #include "program/prog_print.h"
>
> @@ -613,6 +614,9 @@ st_Bitmap(struct gl_context *ctx, GLint x, GLint y,
> assert(width > 0);
> assert(height > 0);
>
> +   /* Prevent st_atom_array from accessing stale draw array data */
> +   _mesa_set_drawing_arrays(ctx, NULL);
> +
> st_invalidate_readpix_cache(st);
>
> if (!st->bitmap.vs) {
> @@ -675,6 +679,9 @@ st_DrawAtlasBitmaps(struct gl_context *ctx,
> struct pipe_vertex_buffer vb = {0};
> unsigned i;
>
> +   /* Prevent st_atom_array from accessing stale draw array data */
> +   _mesa_set_drawing_arrays(ctx, NULL);
> +
> if (!st->bitmap.vs) {
>init_bitmap_state(st);
> }
> diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c 
> b/src/mesa/state_tracker/st_cb_drawpixels.c
> index ff3eb9b614..73108812da 100644
> --- a/src/mesa/state_tracker/st_cb_drawpixels.c
> +++ b/src/mesa/state_tracker/st_cb_drawpixels.c
> @@ -45,6 +45,7 @@
>  #include "main/texformat.h"
>  #include "main/teximage.h"
>  #include "main/texstore.h"
> +#include "main/varray.h"
>  #include "main/glformats.h"
>  #include "program/program.h"
>  #include "program/prog_print.h"
> @@ -1142,6 +1143,9 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
> /* Mesa state should be up to date by now */
> assert(ctx->NewState == 0x0);
>
> +   /* Prevent st_atom_array from accessing stale draw array data */
> +   _mesa_set_drawing_arrays(ctx, NULL);
> +
> _mesa_update_draw_buffer_bounds(ctx, ctx->DrawBuffer);
>
> st_flush_bitmap_cache(st);
> @@ -1509,6 +1513,9 @@ st_CopyPixels(struct gl_context *ctx, GLint srcx, GLint 
> srcy,
> GLint readX, readY, readW, readH;
> struct gl_pixelstore_attrib pack = ctx->DefaultPacking;
>
> +   /* Prevent st_atom_array from accessing stale draw array data */
> +   _mesa_set_drawing_arrays(ctx, NULL);
> +
> _mesa_update_draw_buffer_bounds(ctx, ctx->DrawBuffer);
>
> st_flush_bitmap_cache(st);
> diff --git a/src/mesa/state_tracker/st_cb_drawtex.c 
> b/src/mesa/state_tracker/st_cb_drawtex.c
> index 01c5757a73..0df0ab4713 100644
> --- a/src/mesa/state_tracker/st_cb_drawtex.c
> +++ b/src/mesa/state_tracker/st_cb_drawtex.c
> @@ -17,6 +17,7 @@
>  #include "main/macros.h"
>  #include "main/teximage.h"
>  #include "main/framebuffer.h"
> +#include "main/varray.h"
>  #include "program/program.h"
>  #include "program/prog_print.h"
>
> @@ -117,6 +118,9 @@ st_DrawTex(struct gl_context *ctx, GLfloat x, GLfloat y, 
> GLfloat z,
> struct pipe_vertex_element velements[2 + MAX_TEXTURE_UNITS];
> unsigned offset;
>
> +   /* Prevent st_atom_array from accessing stale draw array data */
> +   _mesa_set_drawing_arrays(ctx, NULL);
> +
> st_flush_bitmap_cache(st);
> st_invalidate_readpix_cache(st);
>
> --
> 2.14.3
>
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Re: [Mesa-dev] [PATCH] i965: Do null pointer check before dereferencing vue_prog_data

[Nanley Chery]

On Mon, Feb 05, 2018 at 04:08:40PM -0800, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat 
> ---
>  src/mesa/drivers/dri/i965/genX_state_upload.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
> b/src/mesa/drivers/dri/i965/genX_state_upload.c
> index aa4d64d08e..67fb328dbc 100644
> --- a/src/mesa/drivers/dri/i965/genX_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
> @@ -3966,7 +3966,8 @@ genX(upload_ds_state)(struct brw_context *brw)
> tes_prog_data->domain == BRW_TESS_DOMAIN_TRI;
>  
>  #if GEN_GEN >= 8
> -if (vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8)
> +if (vue_prog_data &&
> +vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8)

In this else case (where tes_prog_data != NULL) this variable is also
guaranteed to be non-NULL. They point to the same location in memory as
far as I can tell.

Though, what I find confusing is that we can simultaneously access
fields of struct brw_tes_prog_data as well as struct brw_vue_prog_data
even though neither is a subclass of the other.

> ds.DispatchMode = DISPATCH_MODE_SIMD8_SINGLE_PATCH;
>  ds.UserClipDistanceCullTestEnableBitmask =
>  vue_prog_data->cull_distance_mask;
> -- 
> 2.13.6
> 
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Re: [Mesa-dev] [PATCH 5/8] drivers/radeon:add uvd hevc enc functions

[James Zhu]

Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode


On 2018-02-05 02:30 PM, James Zhu wrote:



On 2018-02-05 01:04 PM, Alex Deucher wrote:

On Mon, Feb 5, 2018 at 12:16 PM, James Zhu  wrote:

Implement UVD hevc encode functions

Signed-off-by: James Zhu 
---
  1   |  21 ++
  src/gallium/drivers/radeon/radeon_uvd_enc.c | 340 


  2 files changed, 361 insertions(+)
  create mode 100644 1
  create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c

diff --git a/1 b/1
new file mode 100644
index 000..51dd09e
--- /dev/null
+++ b/1
@@ -0,0 +1,21 @@
+r c80294d drivers/radeon:Add uvd hevc enc hw interface header
+pick 2d924d5 drivers/radeon:add uvd hevc enc hw ib implementation
+
+# Rebase f2b9031..2d924d5 onto f2b9031 (2 command(s))
+#
+# Commands:
+# p, pick = use commit
+# r, reword = use commit, but edit the commit message
+# e, edit = use commit, but stop for amending
+# s, squash = use commit, but meld into previous commit
+# f, fixup = like "squash", but discard this commit's log message
+# x, exec = run command (the rest of the line) using shell
+# d, drop = remove commit
+#
+# These lines can be re-ordered; they are executed from top to bottom.
+#
+# If you remove a line here THAT COMMIT WILL BE LOST.
+#
+# However, if you remove everything, the rebase will be aborted.
+#
+# Note that empty commits are commented out

Looks like some garbage got accidently added here.

Removed garbage file. send out version 2 patches.
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c

new file mode 100644
index 000..6eb6cda
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -0,0 +1,340 @@
+/** 


+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person 
obtaining a

+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, 
subject to

+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including 
the
+ * next paragraph) shall be included in all copies or substantial 
portions

+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
EXPRESS

+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 
NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE 
FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 
CONTRACT,

+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ 
**/

+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder 
*enc, struct pipe_h265_enc_picture_desc *picture)

+{
+  struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;

+  enc->enc_pic.picture_type = pic->picture_type;
+  enc->enc_pic.frame_num = pic->frame_num;
+  enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+  enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+  enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+  enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+  enc->enc_pic.not_referenced = pic->not_referenced;
+  enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
+    (pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_I);

+  enc->enc_pic.crop_left = 0;
+  enc->enc_pic.crop_right = (align(enc->base.width, 16) - 
enc->base.width) / 2;

+  enc->enc_pic.crop_top = 0;
+  enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - 
enc->base.height) / 2;

+  enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+  enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+  enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+  enc->enc_pic.max_poc = pic->seq.intra_period;
+  enc->enc_pic.log2_max_poc = 0;
+  for (int i = enc->enc_pic.max_poc; i != 0; 
enc->enc_pic.log2_max_poc++)

+ i = (i >> 1);
+  enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
+  enc->enc_pic.pic_width_in_luma_samples = 

Re: [Mesa-dev] [PATCH 8/8] drivers/radeonsi: enable uvd encode for HEVC main

[James Zhu]

Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode


On 2018-02-06 11:13 AM, Boyuan Zhang wrote:

this patch is Reviewed-by: Boyuan Zhang 


On 2018-02-05 12:16 PM, James Zhu wrote:

Enable UVD encode for HEVC main profile

Signed-off-by: James Zhu 
---
  src/gallium/drivers/radeonsi/si_get.c | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c

index 8002362..64f76b4 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -24,6 +24,7 @@
  #include "si_pipe.h"
  #include "radeon/radeon_video.h"
  #include "radeon/radeon_vce.h"
+#include "radeon/radeon_uvd_enc.h"
  #include "ac_llvm_util.h"
  #include "vl/vl_decoder.h"
  #include "vl/vl_video_buffer.h"
@@ -587,7 +588,8 @@ static int si_get_video_param(struct pipe_screen 
*screen,

  (si_vce_is_fw_version_supported(sscreen) ||
  sscreen->info.family == CHIP_RAVEN)) ||
  (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
-    sscreen->info.family == CHIP_RAVEN);
+    (sscreen->info.family == CHIP_RAVEN ||
+    si_radeon_uvd_enc_supported(sscreen)));
  case PIPE_VIDEO_CAP_NPOT_TEXTURES:
  return 1;
  case PIPE_VIDEO_CAP_MAX_WIDTH:




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Re: [Mesa-dev] [PATCH 2/8] amdgpu/drm:add uvd hevc enc support in amdgpu cs

[James Zhu]

Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode


On 2018-02-05 04:12 PM, Boyuan Zhang wrote:



On 2018-02-05 12:16 PM, James Zhu wrote:

Signed-off-by: James Zhu 
---
  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 6 ++
  1 file changed, 6 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

index 1927a3a..6f305b7 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -376,6 +376,7 @@ static bool amdgpu_cs_has_user_fence(struct 
amdgpu_cs_context *cs)

  {
 return cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD &&
    cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCE &&
+  cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD_ENC &&
    cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_DEC &&
    cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_ENC;
  }
@@ -818,6 +819,10 @@ static bool amdgpu_init_cs_context(struct 
amdgpu_cs_context *cs,

    cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD;
    break;
  +   case RING_UVD_ENC:
+   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD_ENC;
+   break;
+


Please follow previous indentation, use space instead of tab here.

Also, the patch name might better be changed to winsys/amdgpu.

With those fixed, this patch is
Reviewed-by: Boyuan Zhang 

Thanks,
Boyuan



 case RING_VCE:
    cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCE;
    break;
@@ -1533,6 +1538,7 @@ static int amdgpu_cs_flush(struct 
radeon_winsys_cs *rcs,
    ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) 
* 4;

    break;
 case RING_UVD:
+   case RING_UVD_ENC:
    while (rcs->current.cdw & 15)
   radeon_emit(rcs, 0x8000); /* type2 nop packet */
    break;




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Re: [Mesa-dev] [PATCH v2 1/8] amd/common:add uvd hevc enc support check in hw query

[Bas Nieuwenhuizen]

On Tue, Feb 6, 2018 at 9:05 PM, James Zhu  wrote:
> Based on amdgpu hardware query information to check if UVD hevc enc support
>
> Signed-off-by: James Zhu 
> ---
>  src/amd/common/ac_gpu_info.c | 10 +-
>  src/amd/common/ac_gpu_info.h |  1 +
>  2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
> index 6d9dcb5..2494967 100644
> --- a/src/amd/common/ac_gpu_info.c
> +++ b/src/amd/common/ac_gpu_info.c
> @@ -98,7 +98,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
>  {
> struct amdgpu_buffer_size_alignments alignment_info = {};
> struct amdgpu_heap_info vram, vram_vis, gtt;
> -   struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = 
> {}, vcn_dec = {}, vcn_enc = {};
> +   struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, 
> uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_enc = {};
> uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, 
> uvd_feature = 0;
> int r, i, j;
> drmDevicePtr devinfo;
> @@ -166,6 +166,12 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
> return false;
> }
>
> +   r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, _enc);
> +   if (r) {
> +   fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) 
> failed.\n");
> +   return false;
> +   }

Don't we need to check info->drm_minor here too, as old AMDGPU might
not support the query?

> +
> if (info->drm_major == 3 && info->drm_minor >= 17) {
> r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, 
> _dec);
> if (r) {
> @@ -275,6 +281,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
> uvd.available_rings ? uvd_version : 0;
> info->vce_fw_version =
> vce.available_rings ? vce_version : 0;
> +   info->uvd_enc_supported =
> +   uvd_enc.available_rings ? true : false;
> info->has_userptr = true;
> info->has_syncobj = has_syncobj(fd);
> info->has_syncobj_wait_for_submit = info->has_syncobj && 
> info->drm_minor >= 20;
> diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
> index cca3e98..36714ee 100644
> --- a/src/amd/common/ac_gpu_info.h
> +++ b/src/amd/common/ac_gpu_info.h
> @@ -65,6 +65,7 @@ struct radeon_info {
> uint32_tnum_compute_rings;
> uint32_tuvd_fw_version;
> uint32_tvce_fw_version;
> +   booluvd_enc_supported;
> uint32_tme_fw_version;
> uint32_tme_fw_feature;
> uint32_tpfp_fw_version;
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH] intel/isl: Add assertion for aux surface pitch

[Nanley Chery]

On Mon, Feb 05, 2018 at 04:07:19PM -0800, Anuj Phogat wrote:
> I don't have a test case hitting this assert. But, it's nice to have
> an assert checking the limit.
> 
> Signed-off-by: Anuj Phogat 
> ---
>  src/intel/isl/isl_surface_state.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/src/intel/isl/isl_surface_state.c 
> b/src/intel/isl/isl_surface_state.c
> index bfb27fa4a4..afd4b80ddb 100644
> --- a/src/intel/isl/isl_surface_state.c
> +++ b/src/intel/isl/isl_surface_state.c
> @@ -566,6 +566,8 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, 
> void *state,
>s.AuxiliarySurfaceBaseAddress = info->aux_address;
>s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
>  
> +  assert(s.AuxiliarySurfacePitch <= 511);
> +

genxml already performs this assertion for us, see:
__gen_uint(values->AuxiliarySurfacePitch, 3, 11)


>  #if GEN_GEN >= 8
>assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
>/* Auxiliary surfaces in ISL have compressed formats but the hardware
> -- 
> 2.13.6
> 
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[Mesa-dev] [PATCH RFC] intel/tools: new intel_sanitize_gpu tool

[Scott D Phillips]

From: Kevin Rogovin 

Adds a new debug tool to pad each GEM BO allocated with (weak)
pseudo-random noise values which are then checked after each
batchbuffer dispatch to the kernel. This can be quite valuable to
find diffucult to track down heisenberg style bugs.

[scott.d.phill...@intel.com: split to separate tool]
---
Hi Kevin, here's another take on your out-of-bounds write detection
code, packaged as a separate tool instead of in the driver code. Doing
it this way could make it easier to use across i965 and anv (although
USERPTR is needed for anv support). The build bits of this are less than
half baked at the moment. What do you think?

 src/intel/tools/intel_sanitize_gpu.c   | 306 +
 src/intel/tools/meson.build|  10 ++
 src/intel/tools/run_intel_sanitize_gpu |   5 +
 3 files changed, 321 insertions(+)
 create mode 100644 src/intel/tools/intel_sanitize_gpu.c
 create mode 100755 src/intel/tools/run_intel_sanitize_gpu

diff --git a/src/intel/tools/intel_sanitize_gpu.c 
b/src/intel/tools/intel_sanitize_gpu.c
new file mode 100644
index 000..d74492bb02e
--- /dev/null
+++ b/src/intel/tools/intel_sanitize_gpu.c
@@ -0,0 +1,306 @@
+/*
+ * Copyright © 2015-2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#undef _FILE_OFFSET_BITS /* prevent #define open open64 */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "util/hash_table.h"
+#include "util/set.h"
+
+#define INTEL_LOG_TAG "INTEL-SANITIZE-GPU"
+#include "common/intel_log.h"
+#include "common/gen_clflush.h"
+
+static int (*libc_open)(const char *pathname, int flags, mode_t mode);
+static int (*libc_close)(int fd);
+static int (*libc_ioctl)(int fd, unsigned long request, void *argp);
+static int (*libc_fcntl)(int fd, int cmd, int param);
+
+#define DRM_MAJOR 226
+
+/* TODO: we want to make sure that the padding forces
+ * the BO to take another page on the (PP)GTT; 4KB
+ * may or may not be the page size for the BO. Indeed,
+ * depending on GPU, kernel version and GEM size, the
+ * page size can be one of 4KB, 64KB or 2M.
+ */
+#define PADDING_SIZE 4096
+
+static struct set *drm_fds = NULL;
+static struct hash_table *bo_sizes = NULL;
+
+#define IS_DRM_FD(fd) (_mesa_set_search(drm_fds,   
\
+(void*)(uintptr_t)(fd)) != NULL)
+#define BO_SIZE(handle) ({ 
\
+   struct hash_entry *e = _mesa_hash_table_search(bo_sizes,
\
+  (void*)(uintptr_t)(handle)); 
\
+   e ? (uintptr_t)e->data : 0; 
\
+})
+
+/* Our goal is not to have noise good enough for cryto,
+ * but instead values that are unique-ish enough that
+ * it is incredibly unlikely that a buffer overwrite
+ * will produce the exact same values.
+ */
+static uint8_t
+next_noise_value(uint8_t prev_noise)
+{
+   uint32_t v = prev_noise;
+   return (v * 103u + 227u) & 0xFF;
+}
+
+static void
+fill_noise_buffer(uint8_t *dst, uint8_t start, uint32_t length)
+{
+   for(uint32_t i = 0; i < length; ++i) {
+  dst[i] = start;
+  start = next_noise_value(start);
+   }
+}
+
+static bool
+padding_is_good(int fd, uint32_t handle)
+{
+   struct drm_i915_gem_mmap mmap_arg = {
+  .handle = handle,
+  .offset = BO_SIZE(handle),
+  .size = PADDING_SIZE,
+  .flags = 0,
+   };
+
+   if (!mmap_arg.offset) {
+  intel_logd("Unknown buffer handle %d.", handle);
+  return false;
+   }
+
+   uint8_t *mapped;
+   int ret;
+   uint8_t expected_value;
+
+   ret = libc_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP, _arg);
+   if (ret != 0) {
+  intel_logd("Unable to map buffer %d for pad checking.", handle);
+  

Re: [Mesa-dev] [PATCH] Haiku: convert to autotools

[Dylan Baker]

Quoting kallisti5 (2018-02-05 20:24:20)
> On 2018-02-05 18:13, Dylan Baker wrote:
> > 
> > Pretty close. I lied, apparently the pthreads fix is in 0.44
> > 
> > https://github.com/mesonbuild/meson/commit/fc547ad05e5a8e650ae5bc2ecc7d40e4dbcc9f0f
> > 
> > Here's my branch, but it needs rebase pretty bad, there's also a patch 
> > to use
> > shared glapi that I added trying to see if that would get the build 
> > working that
> > needs to be removed:
> > 
> > https://github.com/dcbaker/mesa/tree/wip/meson-haiku
> > 
> 
> Ok. I went over and got Haiku building with menson with the following 
> change:
> 
> https://github.com/kallisti5/mesa/commit/e33dfab54d99edacdf1d24c402d29f50818631b3
> 
> Any feedback welcome. I need to review your branch now and see if I can 
> make improvements
> based on your changes.
> 
>   Thanks!
> 
>   -- Alex

I pushed the non-shared glapi fixes I had queued, and rebased on my branch just
now on master, including a few fixups for things that have changed since I wrote
that (like landing support for the BSDs). Hopefully that helps you.

Dylan


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Re: [Mesa-dev] [PATCH] Haiku: convert to autotools

[Dylan Baker]

Quoting Dylan Baker (2018-02-06 15:19:48)
> Quoting kallisti5 (2018-02-05 20:24:20)
> > On 2018-02-05 18:13, Dylan Baker wrote:
> > > 
> > > Pretty close. I lied, apparently the pthreads fix is in 0.44
> > > 
> > > https://github.com/mesonbuild/meson/commit/fc547ad05e5a8e650ae5bc2ecc7d40e4dbcc9f0f
> > > 
> > > Here's my branch, but it needs rebase pretty bad, there's also a patch 
> > > to use
> > > shared glapi that I added trying to see if that would get the build 
> > > working that
> > > needs to be removed:
> > > 
> > > https://github.com/dcbaker/mesa/tree/wip/meson-haiku
> > > 
> > 
> > Ok. I went over and got Haiku building with menson with the following 
> > change:
> > 
> > https://github.com/kallisti5/mesa/commit/e33dfab54d99edacdf1d24c402d29f50818631b3
> > 
> > Any feedback welcome. I need to review your branch now and see if I can 
> > make improvements
> > based on your changes.
> > 
> >   Thanks!
> > 
> >   -- Alex
> 
> I pushed the non-shared glapi fixes I had queued, and rebased on my branch 
> just
> now on master, including a few fixups for things that have changed since I 
> wrote
> that (like landing support for the BSDs). Hopefully that helps you.
> 
> Dylan
> 

One thing I just realized I didn't do, but you'll probably want to, is make sure
any new meson.build files (like hgl and gallium/*) get added to the EXTRA_DIST
values in autotools so they go into the tarballs.

Dylan


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[Mesa-dev] [PATCH 2/2] i965: perf: cleanup detection of kernel support for loadable configs

[Lionel Landwerlin]

The initial revision of the patch adding loadable configs was testing
the feature's availability by adding a new config successfully and
then removing it.

A second version tested the availability just by exercising the
removal. But some unused code remained.

Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_performance_query.c | 17 ++---
 1 file changed, 2 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index f4ff858bd5d..c0bb4442bec 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1832,21 +1832,8 @@ kernel_has_dynamic_config_support(struct brw_context 
*brw,
 
   /* Look for the test config, which we know we can't replace. */
   if (read_file_uint64(config_path, _id) && config_id == 1) {
- uint32_t mux_regs[] = { 0x9888 /* NOA_WRITE */, 0x0 };
- struct drm_i915_perf_oa_config config;
-
- memset(, 0, sizeof(config));
-
- memcpy(config.uuid, query->guid, sizeof(config.uuid));
-
- config.n_mux_regs = 1;
- config.mux_regs_ptr = (uintptr_t) mux_regs;
-
- if (drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG, 
_id) < 0 &&
- errno == ENOENT)
-return true;
-
- break;
+ return drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG,
+ _id) < 0 && errno == ENOENT;
   }
}
 
-- 
2.16.1

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[Mesa-dev] [PATCH 1/2] i965: perf: use drmIoctl() instead of ioctl()

[Lionel Landwerlin]

ioctl() might be interrupted, use drmIoctl() instead as it'll retry
automatically.

Fixes: 27ee83eaf7e "i965: perf: add support for userspace configurations"
Cc: "18.0" 
Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_performance_query.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 5b8f30db2f8..f4ff858bd5d 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1842,7 +1842,7 @@ kernel_has_dynamic_config_support(struct brw_context *brw,
  config.n_mux_regs = 1;
  config.mux_regs_ptr = (uintptr_t) mux_regs;
 
- if (ioctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG, _id) 
< 0 &&
+ if (drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG, 
_id) < 0 &&
  errno == ENOENT)
 return true;
 
@@ -1889,7 +1889,7 @@ init_oa_configs(struct brw_context *brw, const char 
*sysfs_dev_dir)
   config.n_flex_regs = query->n_flex_regs;
   config.flex_regs_ptr = (uintptr_t) query->flex_regs;
 
-  ret = ioctl(screen->fd, DRM_IOCTL_I915_PERF_ADD_CONFIG, );
+  ret = drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_ADD_CONFIG, );
   if (ret < 0) {
  DBG("Failed to load \"%s\" (%s) metrics set in kernel: %s\n",
  query->name, query->guid, strerror(errno));
-- 
2.16.1

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Re: [Mesa-dev] [PATCH 10.5/24] st/mesa: don't set sampler states for TBOs

[Ilia Mirkin]

This breaks nouveau (at least on nv50). Same deal as in commit
2b938a390c15a06be8cf706083890c822979508f which fixed a similar issue
where this assumption that buffer doesn't need sampler was also
temporarily introduced.

Do I need to go change a ton of stuff in nouveau, or can we stick with
the original rule where there's a always a sampler associated with a
view?

Generically you're right - no good reason for texelFetch to need a
sampler. Bug I dug around a bunch last time, and I didn't find any
great workarounds. I'll dig around again, but IMO this should be a
candidate for revert.

On Wed, Jun 14, 2017 at 9:08 PM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> ---
>
> This prevents a crash later in the series, and it's generally a good
> thing to do.
>
>  src/mesa/state_tracker/st_atom_sampler.c | 11 +--
>  src/mesa/state_tracker/st_texture.c  |  5 +++--
>  2 files changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_atom_sampler.c 
> b/src/mesa/state_tracker/st_atom_sampler.c
> index 21af5ef..7a85a55 100644
> --- a/src/mesa/state_tracker/st_atom_sampler.c
> +++ b/src/mesa/state_tracker/st_atom_sampler.c
> @@ -227,20 +227,21 @@ void
>  st_convert_sampler_from_unit(const struct st_context *st,
>   struct pipe_sampler_state *sampler,
>   GLuint texUnit)
>  {
> const struct gl_texture_object *texobj;
> struct gl_context *ctx = st->ctx;
> const struct gl_sampler_object *msamp;
>
> texobj = ctx->Texture.Unit[texUnit]._Current;
> assert(texobj);
> +   assert(texobj->Target != GL_TEXTURE_BUFFER);
>
> msamp = _mesa_get_samplerobj(ctx, texUnit);
>
> st_convert_sampler(st, texobj, msamp, sampler);
>
> sampler->lod_bias += ctx->Texture.Unit[texUnit].LodBias;
> sampler->seamless_cube_map |= ctx->Texture.CubeMapSeamless;
>  }
>
>
> @@ -248,37 +249,43 @@ st_convert_sampler_from_unit(const struct st_context 
> *st,
>   * Update the gallium driver's sampler state for fragment, vertex or
>   * geometry shader stage.
>   */
>  static void
>  update_shader_samplers(struct st_context *st,
> enum pipe_shader_type shader_stage,
> const struct gl_program *prog,
> struct pipe_sampler_state *samplers,
> unsigned *out_num_samplers)
>  {
> +   struct gl_context *ctx = st->ctx;
> GLbitfield samplers_used = prog->SamplersUsed;
> GLbitfield free_slots = ~prog->SamplersUsed;
> GLbitfield external_samplers_used = prog->ExternalSamplersUsed;
> unsigned unit, num_samplers;
> const struct pipe_sampler_state *states[PIPE_MAX_SAMPLERS];
>
> if (samplers_used == 0x0)
>return;
>
> num_samplers = util_last_bit(samplers_used);
>
> /* loop over sampler units (aka tex image units) */
> for (unit = 0; samplers_used; unit++, samplers_used >>= 1) {
>struct pipe_sampler_state *sampler = samplers + unit;
> +  unsigned tex_unit = prog->SamplerUnits[unit];
>
> -  if (samplers_used & 1) {
> - st_convert_sampler_from_unit(st, sampler, prog->SamplerUnits[unit]);
> +  /* Don't update the sampler for TBOs. cso_context will not bind sampler
> +   * states that are NULL.
> +   */
> +  if (samplers_used & 1 &&
> +  ctx->Texture.Unit[tex_unit]._Current->Target != GL_TEXTURE_BUFFER) 
> {
> + st_convert_sampler_from_unit(st, sampler, tex_unit);
>   states[unit] = sampler;
>} else {
>   states[unit] = NULL;
>}
> }
>
> /* For any external samplers with multiplaner YUV, stuff the additional
>  * sampler states we need at the end.
>  *
>  * Just re-use the existing sampler-state from the primary slot.
> diff --git a/src/mesa/state_tracker/st_texture.c 
> b/src/mesa/state_tracker/st_texture.c
> index 9de3b9a..07c3844 100644
> --- a/src/mesa/state_tracker/st_texture.c
> +++ b/src/mesa/state_tracker/st_texture.c
> @@ -505,26 +505,27 @@ st_destroy_bound_image_handles(struct st_context *st)
>   * Create a texture handle from a texture unit.
>   */
>  static GLuint64
>  st_create_texture_handle_from_unit(struct st_context *st,
> struct gl_program *prog, GLuint texUnit)
>  {
> struct gl_context *ctx = st->ctx;
> struct gl_texture_object *texObj;
> struct pipe_context *pipe = st->pipe;
> struct pipe_sampler_view *view;
> -   struct pipe_sampler_state sampler;
> +   struct pipe_sampler_state sampler = {0};
>
> if (!st_update_single_texture(st, , texUnit, prog->sh.data->Version))
>return 0;
>
> -   st_convert_sampler_from_unit(st, , texUnit);
> +   if (view->target != PIPE_BUFFER)
> +  st_convert_sampler_from_unit(st, , texUnit);
>
> texObj = ctx->Texture.Unit[texUnit]._Current;
> assert(texObj);
>
> return pipe->create_texture_handle(pipe, view, );
>  }
>
>
>  /**
>   * Create an 

[Mesa-dev] [PATCH] radv: don't support tc-compat on multisample d32s8 at all.

[Dave Airlie]

From: Dave Airlie 

RX550 fails
dEQP-VK.renderpass.suballocation.multisample.d32_sfloat_s8_uint.samples_2

So increase the range of the workaround.

Fixes: f4c534ef6 (radv: don't enable tc compat for d32s8 + 4/8 samples (v1.1))

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_image.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index b4de7255c7b..5ac0f72589d 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -116,8 +116,8 @@ radv_init_surface(struct radv_device *device,
pCreateInfo->mipLevels <= 1 &&
device->physical_device->rad_info.chip_class >= VI &&
((pCreateInfo->format == VK_FORMAT_D32_SFLOAT ||
- /* for some reason TC compat with 4/8 samples breaks some 
cts tests - disable for now */
- (pCreateInfo->samples < 4 && pCreateInfo->format == 
VK_FORMAT_D32_SFLOAT_S8_UINT)) ||
+ /* for some reason TC compat with 2/4/8 samples breaks 
some cts tests - disable for now */
+ (pCreateInfo->samples < 2 && pCreateInfo->format == 
VK_FORMAT_D32_SFLOAT_S8_UINT)) ||
 (device->physical_device->rad_info.chip_class >= GFX9 &&
  pCreateInfo->format == VK_FORMAT_D16_UNORM)))
surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
-- 
2.14.3

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[Mesa-dev] [PATCH v2 8/8] radeonsi: enable uvd encode for HEVC main

[James Zhu]

Enable UVD encode for HEVC main profile

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeonsi/si_get.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index 8002362..64f76b4 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -24,6 +24,7 @@
 #include "si_pipe.h"
 #include "radeon/radeon_video.h"
 #include "radeon/radeon_vce.h"
+#include "radeon/radeon_uvd_enc.h"
 #include "ac_llvm_util.h"
 #include "vl/vl_decoder.h"
 #include "vl/vl_video_buffer.h"
@@ -587,7 +588,8 @@ static int si_get_video_param(struct pipe_screen *screen,
(si_vce_is_fw_version_supported(sscreen) ||
sscreen->info.family == CHIP_RAVEN)) ||
(profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
-   sscreen->info.family == CHIP_RAVEN);
+   (sscreen->info.family == CHIP_RAVEN ||
+   si_radeon_uvd_enc_supported(sscreen)));
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
return 1;
case PIPE_VIDEO_CAP_MAX_WIDTH:
-- 
2.7.4

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[Mesa-dev] [PATCH v2 2/8] winsys/amdgpu:add uvd hevc enc support in amdgpu cs

[James Zhu]

Support UVD HEVC encode in amdgpu cs

Signed-off-by: James Zhu 
---
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 1927a3a..92d5394 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -376,6 +376,7 @@ static bool amdgpu_cs_has_user_fence(struct 
amdgpu_cs_context *cs)
 {
return cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD &&
   cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCE &&
+  cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD_ENC &&
   cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_DEC &&
   cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_ENC;
 }
@@ -818,6 +819,10 @@ static bool amdgpu_init_cs_context(struct 
amdgpu_cs_context *cs,
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD;
   break;
 
+   case RING_UVD_ENC:
+  cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD_ENC;
+  break;
+
case RING_VCE:
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCE;
   break;
@@ -1533,6 +1538,7 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
   ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
   break;
case RING_UVD:
+   case RING_UVD_ENC:
   while (rcs->current.cdw & 15)
  radeon_emit(rcs, 0x8000); /* type2 nop packet */
   break;
-- 
2.7.4

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[Mesa-dev] [PATCH v2 1/8] amd/common:add uvd hevc enc support check in hw query

[James Zhu]

Based on amdgpu hardware query information to check if UVD hevc enc support

Signed-off-by: James Zhu 
---
 src/amd/common/ac_gpu_info.c | 10 +-
 src/amd/common/ac_gpu_info.h |  1 +
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 6d9dcb5..2494967 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -98,7 +98,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 {
struct amdgpu_buffer_size_alignments alignment_info = {};
struct amdgpu_heap_info vram, vram_vis, gtt;
-   struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = 
{}, vcn_dec = {}, vcn_enc = {};
+   struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, uvd_enc 
= {}, vce = {}, vcn_dec = {}, vcn_enc = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature 
= 0;
int r, i, j;
drmDevicePtr devinfo;
@@ -166,6 +166,12 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
return false;
}
 
+   r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, _enc);
+   if (r) {
+   fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) 
failed.\n");
+   return false;
+   }
+
if (info->drm_major == 3 && info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, 
_dec);
if (r) {
@@ -275,6 +281,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
uvd.available_rings ? uvd_version : 0;
info->vce_fw_version =
vce.available_rings ? vce_version : 0;
+   info->uvd_enc_supported =
+   uvd_enc.available_rings ? true : false;
info->has_userptr = true;
info->has_syncobj = has_syncobj(fd);
info->has_syncobj_wait_for_submit = info->has_syncobj && 
info->drm_minor >= 20;
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index cca3e98..36714ee 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -65,6 +65,7 @@ struct radeon_info {
uint32_tnum_compute_rings;
uint32_tuvd_fw_version;
uint32_tvce_fw_version;
+   booluvd_enc_supported;
uint32_tme_fw_version;
uint32_tme_fw_feature;
uint32_tpfp_fw_version;
-- 
2.7.4

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[Mesa-dev] [PATCH v2 6/8] radeon/uvd:add uvd hevc enc files in Makefile list

[James Zhu]

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/Makefile.sources | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index b756d72..f8ee860 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -15,6 +15,9 @@ C_SOURCES := \
radeon_vcn_enc_1_2.c \
radeon_vcn_enc.c \
radeon_vcn_enc.h \
+   radeon_uvd_enc_1_1.c \
+   radeon_uvd_enc.c \
+   radeon_uvd_enc.h \
radeon_vce_40_2_2.c \
radeon_vce_50.c \
radeon_vce_52.c \
-- 
2.7.4

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[Mesa-dev] [Bug 94194] New Account Request

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=94194

Martin Peres  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #8 from Martin Peres  ---
Done, welcome to Freedesktop Plamena!

And thanks for keeping up your contributions!

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Re: [Mesa-dev] [PATCH 5/8] drivers/radeon:add uvd hevc enc functions

[James Zhu]

Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode


On 2018-02-06 10:27 AM, Boyuan Zhang wrote:



On 2018-02-05 02:41 PM, James Zhu wrote:

Implement UVD hevc encode functions

Signed-off-by: James Zhu 
---
  src/gallium/drivers/radeon/radeon_uvd_enc.c | 340 


  1 file changed, 340 insertions(+)
  create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c

new file mode 100644
index 000..6eb6cda
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -0,0 +1,340 @@
+/** 


+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person 
obtaining a

+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, 
subject to

+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial 
portions

+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
EXPRESS

+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 
NON-INFRINGEMENT.

+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 
CONTRACT,

+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ 
**/

+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc, 
struct pipe_h265_enc_picture_desc *picture)

+{
+  struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;


This line is unnecessary. Same type on both sides.


+  enc->enc_pic.picture_type = pic->picture_type;
+  enc->enc_pic.frame_num = pic->frame_num;
+  enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+  enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+  enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+  enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+  enc->enc_pic.not_referenced = pic->not_referenced;
+  enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
+    (pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_I);

+  enc->enc_pic.crop_left = 0;
+  enc->enc_pic.crop_right = (align(enc->base.width, 16) - 
enc->base.width) / 2;

+  enc->enc_pic.crop_top = 0;
+  enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - 
enc->base.height) / 2;

+  enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+  enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+  enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+  enc->enc_pic.max_poc = pic->seq.intra_period;
+  enc->enc_pic.log2_max_poc = 0;
+  for (int i = enc->enc_pic.max_poc; i != 0; 
enc->enc_pic.log2_max_poc++)

+ i = (i >> 1);
+  enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
+  enc->enc_pic.pic_width_in_luma_samples = 
pic->seq.pic_width_in_luma_samples;
+  enc->enc_pic.pic_height_in_luma_samples = 
pic->seq.pic_height_in_luma_samples;
+  enc->enc_pic.log2_diff_max_min_luma_coding_block_size = 
pic->seq.log2_diff_max_min_luma_coding_block_size;
+  enc->enc_pic.log2_min_transform_block_size_minus2 = 
pic->seq.log2_min_transform_block_size_minus2;
+  enc->enc_pic.log2_diff_max_min_transform_block_size = 
pic->seq.log2_diff_max_min_transform_block_size;
+  enc->enc_pic.max_transform_hierarchy_depth_inter = 
pic->seq.max_transform_hierarchy_depth_inter;
+  enc->enc_pic.max_transform_hierarchy_depth_intra = 
pic->seq.max_transform_hierarchy_depth_intra;
+  enc->enc_pic.log2_parallel_merge_level_minus2 = 
pic->pic.log2_parallel_merge_level_minus2;
+  enc->enc_pic.bit_depth_luma_minus8 = 
pic->seq.bit_depth_luma_minus8;
+  enc->enc_pic.bit_depth_chroma_minus8 = 
pic->seq.bit_depth_chroma_minus8;

+  enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
+  enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand;
+  enc->enc_pic.sample_adaptive_offset_enabled_flag = 

Re: [Mesa-dev] [PATCH 7/8] drivers/radeonsi:create uvd hevc enc entry

[James Zhu]

Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode


On 2018-02-05 03:25 PM, Boyuan Zhang wrote:



On 2018-02-05 12:16 PM, James Zhu wrote:

Add UVD hevc encode pipe video codec creation entry

Signed-off-by: James Zhu 
---
  src/gallium/drivers/radeonsi/si_uvd.c | 13 +
  1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_uvd.c 
b/src/gallium/drivers/radeonsi/si_uvd.c

index 64f2f8e..fa43a96 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -31,7 +31,8 @@
  #include "radeon/radeon_vce.h"
  #include "radeon/radeon_vcn_dec.h"
  #include "radeon/radeon_vcn_enc.h"
-
+#include "radeon/radeon_uvd_enc.h"
+#include "util/u_video.h"

Could you add back the blank line please?

  /**
   * creates an video buffer with an UVD compatible memory layout
   */
@@ -146,9 +147,13 @@ struct pipe_video_codec 
*si_uvd_create_decoder(struct pipe_context *context,

  struct si_context *ctx = (struct si_context *)context;
  bool vcn = (ctx->b.family == CHIP_RAVEN) ? true : false;
  -    if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
-    return (vcn) ? radeon_create_encoder(context, templ, 
ctx->b.ws, si_vce_get_buffer) :
-   si_vce_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);

+    if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+    if (u_reduce_video_profile(templ->profile) == 
PIPE_VIDEO_FORMAT_HEVC) {
+    return (vcn) ? radeon_create_encoder(context, templ, 
ctx->b.ws, si_vce_get_buffer) :
+    radeon_uvd_create_encoder(context, 
templ, ctx->b.ws, si_vce_get_buffer);

+    } else
+    return si_vce_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);

+    }
It seems that this change will break the original logic for vcn h.264 
encode case, please fix it.


Thanks,
Boyuan


    return (vcn) ? radeon_create_decoder(context, templ) :
  si_common_uvd_create_decoder(context, templ, si_uvd_set_dtb);




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Re: [Mesa-dev] [PATCH] travis: radeonsi and radv need LLVM 4.0

[Kyriazis, George]

SWR is OK with moving to LLVM 4.0 and above.

Just to clarify: This goes to master, which means mesa 18.0 is not affected, 
just 18.1 and later.  Correct?

Thanks,

George

> On Feb 6, 2018, at 11:07 AM, Kyriazis, George  
> wrote:
> 
> As far as SWR is concerned, we’ll have to ask our customers.  Will respond 
> shortly.
> 
> Thanks,
> 
> George
> 
>> On Feb 6, 2018, at 9:42 AM, Andres Gomez  wrote:
>> 
>> Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
>> Cc: Marek Olšák 
>> Cc: Emil Velikov 
>> Cc: Jan Vesely 
>> Signed-off-by: Andres Gomez 
>> ---
>> 
>> Additionally, AMD's support removal for LLVM 3.9 has also affected the
>> distcheck target.
>> 
>> Unfortunately, SWR distribution needs 3.9.x, therefore, we cannot
>> simply use LLVM 4.0 to generate the distribution tarball.
>> 
>> Either SWR upgrades its minimal dependency to LLVM 4.0 or we find a
>> way of instructing distcheck so it would use LLVM 3.9 for the tarball
>> generation and LLVM 4.0 for the check stage of the distcheck ...
>> 
>> .travis.yml | 46 --
>> 1 file changed, 36 insertions(+), 10 deletions(-)
>> 
>> diff --git a/.travis.yml b/.travis.yml
>> index 0156eefb7ad..3651d00169f 100644
>> --- a/.travis.yml
>> +++ b/.travis.yml
>> @@ -37,12 +37,12 @@ matrix:
>>  addons:
>>apt:
>>  sources:
>> -- llvm-toolchain-trusty-3.9
>> +- llvm-toolchain-trusty-4.0
>>  packages:
>># LLVM packaging is broken and misses these dependencies
>>- libedit-dev
>># From sources above
>> -- llvm-3.9-dev
>> +- llvm-4.0-dev
>># Common
>>- xz-utils
>>- libexpat1-dev
>> @@ -119,6 +119,35 @@ matrix:
>>- libx11-xcb-dev
>>- libelf-dev
>>- libunwind8-dev
>> +- env:
>> +- LABEL="make Gallium Drivers RadeonSI"
>> +- BUILD=make
>> +- MAKEFLAGS="-j4"
>> +- MAKE_CHECK_COMMAND="true"
>> +- LLVM_VERSION=4.0
>> +- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
>> +- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
>> +- DRI_DRIVERS=""
>> +- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa 
>> --disable-nine --disable-xvmc --disable-vdpau --disable-va 
>> --disable-omx-bellagio --disable-gallium-osmesa"
>> +- GALLIUM_DRIVERS="radeonsi"
>> +- VULKAN_DRIVERS=""
>> +- LIBUNWIND_FLAGS="--enable-libunwind"
>> +  addons:
>> +apt:
>> +  sources:
>> +- llvm-toolchain-trusty-4.0
>> +  packages:
>> +# LLVM packaging is broken and misses these dependencies
>> +- libedit-dev
>> +# From sources above
>> +- llvm-4.0-dev
>> +# Common
>> +- xz-utils
>> +- x11proto-xf86vidmode-dev
>> +- libexpat1-dev
>> +- libx11-xcb-dev
>> +- libelf-dev
>> +- libunwind8-dev
>>- env:
>>- LABEL="make Gallium Drivers Other"
>>- BUILD=make
>> @@ -131,7 +160,7 @@ matrix:
>>- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
>>- DRI_DRIVERS=""
>>- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa 
>> --disable-nine --disable-xvmc --disable-vdpau --disable-va 
>> --disable-omx-bellagio --disable-gallium-osmesa"
>> -- 
>> GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
>> +- 
>> GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
>>- VULKAN_DRIVERS=""
>>- LIBUNWIND_FLAGS="--enable-libunwind"
>>  addons:
>> @@ -166,7 +195,7 @@ matrix:
>>- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
>>- DRI_DRIVERS=""
>>- GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd 
>> --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau 
>> --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
>> -- GALLIUM_DRIVERS="r600,radeonsi"
>> +- GALLIUM_DRIVERS="r600"
>>- VULKAN_DRIVERS=""
>>- LIBUNWIND_FLAGS="--enable-libunwind"
>>  addons:
>> @@ -303,10 +332,8 @@ matrix:
>>- BUILD=make
>>- MAKEFLAGS="-j4"
>>- MAKE_CHECK_COMMAND="make -C src/gtest check && make -C src/intel 
>> check"
>> -- LLVM_VERSION=3.9
>> +- LLVM_VERSION=4.0
>>- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
>> -# New binutils linker is required for llvm-3.9
>> -- OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
>>- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl 
>> --with-platforms=x11,wayland"
>>- DRI_DRIVERS=""
>>- GALLIUM_ST="--enable-dri --enable-dri3 

[Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode

[James Zhu]

The whole series are the updated version. Changes are made mainly based 
on the comments from prevous code review from Alex, Leo and Boyuan

James Zhu (8):
  amd/common:add uvd hevc enc support check in hw query
  winsys/amdgpu:add uvd hevc enc support in amdgpu cs
  radeon/uvd:add uvd hevc enc hw interface header
  radeon/uvd:add uvd hevc enc hw ib implementation
  radeon/uvd:add uvd hevc enc functions
  radeon/uvd:add uvd hevc enc files in Makefile list
  radeonsi:create uvd hevc enc entry
  radeonsi: enable uvd encode for HEVC main

 src/amd/common/ac_gpu_info.c|   10 +-
 src/amd/common/ac_gpu_info.h|1 +
 src/gallium/drivers/radeon/Makefile.sources |3 +
 src/gallium/drivers/radeon/radeon_uvd_enc.c |  370 
 src/gallium/drivers/radeon/radeon_uvd_enc.h |  471 ++
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 1115 +++
 src/gallium/drivers/radeonsi/si_get.c   |4 +-
 src/gallium/drivers/radeonsi/si_uvd.c   |   15 +-
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c   |6 +
 9 files changed, 1990 insertions(+), 5 deletions(-)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.h
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c

-- 
2.7.4

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[Mesa-dev] [PATCH v2 3/8] radeon/uvd:add uvd hevc enc hw interface header

[James Zhu]

Add hevc encode hardware interface for UVD

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc.h | 471 
 1 file changed, 471 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.h

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.h 
b/src/gallium/drivers/radeon/radeon_uvd_enc.h
new file mode 100644
index 000..1cca0d2
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.h
@@ -0,0 +1,471 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#ifndef _RADEON_UVD_ENC_H
+#define _RADEON_UVD_ENC_H
+
+#define RENC_UVD_FW_INTERFACE_MAJOR_VERSION 1
+#define RENC_UVD_FW_INTERFACE_MINOR_VERSION 1
+
+#define RENC_UVD_IB_PARAM_SESSION_INFO  0x0001
+#define RENC_UVD_IB_PARAM_TASK_INFO 0x0002
+#define RENC_UVD_IB_PARAM_SESSION_INIT  0x0003
+#define RENC_UVD_IB_PARAM_LAYER_CONTROL 0x0004
+#define RENC_UVD_IB_PARAM_LAYER_SELECT  0x0005
+#define RENC_UVD_IB_PARAM_SLICE_CONTROL 0x0006
+#define RENC_UVD_IB_PARAM_SPEC_MISC 0x0007
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x0008
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT   0x0009
+#define RENC_UVD_IB_PARAM_RATE_CONTROL_PER_PICTURE  0x000a
+#define RENC_UVD_IB_PARAM_SLICE_HEADER  0x000b
+#define RENC_UVD_IB_PARAM_ENCODE_PARAMS 0x000c
+#define RENC_UVD_IB_PARAM_QUALITY_PARAMS0x000d
+#define RENC_UVD_IB_PARAM_DEBLOCKING_FILTER 0x000e
+#define RENC_UVD_IB_PARAM_INTRA_REFRESH 0x000f
+#define RENC_UVD_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0010
+#define RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER0x0011
+#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER   0x0012
+#define RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER0x0013
+#define RENC_UVD_IB_PARAM_FEEDBACK_BUFFER_ADDITIONAL0x0014
+
+#define RENC_UVD_IB_OP_INITIALIZE   0x0801
+#define RENC_UVD_IB_OP_CLOSE_SESSION0x0802
+#define RENC_UVD_IB_OP_ENCODE   0x0803
+#define RENC_UVD_IB_OP_INIT_RC  0x0804
+#define RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x0805
+#define RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE  0x0806
+#define RENC_UVD_IB_OP_SET_BALANCE_ENCODING_MODE0x0807
+#define RENC_UVD_IB_OP_SET_QUALITY_ENCODING_MODE0x0808
+
+#define RENC_UVD_IF_MAJOR_VERSION_MASK  0x
+#define RENC_UVD_IF_MAJOR_VERSION_SHIFT 16
+#define RENC_UVD_IF_MINOR_VERSION_MASK  0x
+#define RENC_UVD_IF_MINOR_VERSION_SHIFT 0
+
+#define RENC_UVD_PREENCODE_MODE_NONE0x
+#define RENC_UVD_PREENCODE_MODE_1X  0x0001
+#define RENC_UVD_PREENCODE_MODE_2X  0x0002
+#define RENC_UVD_PREENCODE_MODE_4X  0x0004
+
+#define RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS  0x
+#define RENC_UVD_SLICE_CONTROL_MODE_FIXED_BITS  0x0001
+
+#define RENC_UVD_RATE_CONTROL_METHOD_NONE   0x
+#define RENC_UVD_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR0x0001
+#define RENC_UVD_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR   0x0002
+#define RENC_UVD_RATE_CONTROL_METHOD_CBR0x0003
+
+#define RENC_UVD_NALU_TYPE_AUD  0x0001
+#define 

[Mesa-dev] [PATCH v2 4/8] radeon/uvd:add uvd hevc enc hw ib implementation

[James Zhu]

Implement required IBs for UVD HEVC encode.

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 1115 +++
 1 file changed, 1115 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
new file mode 100644
index 000..17a39c2
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -0,0 +1,1115 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+#define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = 
(value))
+#define RADEON_ENC_BEGIN(cmd) { \
+   uint32_t *begin = >cs->current.buf[enc->cs->current.cdw++]; \
+RADEON_ENC_CS(cmd)
+#define RADEON_ENC_READ(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READ, (domain), (off))
+#define RADEON_ENC_WRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_WRITE, (domain), (off))
+#define RADEON_ENC_READWRITE(buf, domain, off) radeon_uvd_enc_add_buffer(enc, 
(buf), RADEON_USAGE_READWRITE, (domain), (off))
+#define RADEON_ENC_END() *begin = (>cs->current.buf[enc->cs->current.cdw] 
- begin) * 4; \
+   enc->total_task_size += *begin;}
+
+static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
+static const unsigned index_to_shifts[4] = { 24, 16, 8, 0 };
+
+static void
+radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc,
+  struct pb_buffer *buf, enum radeon_bo_usage usage,
+  enum radeon_bo_domain domain, signed offset)
+{
+   enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
+  domain, RADEON_PRIO_VCE);
+   uint64_t addr;
+   addr = enc->ws->buffer_get_virtual_address(buf);
+   addr = addr + offset;
+   RADEON_ENC_CS(addr >> 32);
+   RADEON_ENC_CS(addr);
+}
+
+static void
+radeon_uvd_enc_set_emulation_prevention(struct radeon_uvd_encoder *enc,
+bool set)
+{
+   if (set != enc->emulation_prevention) {
+  enc->emulation_prevention = set;
+  enc->num_zeros = 0;
+   }
+}
+
+static void
+radeon_uvd_enc_output_one_byte(struct radeon_uvd_encoder *enc,
+   unsigned char byte)
+{
+   if (enc->byte_index == 0)
+  enc->cs->current.buf[enc->cs->current.cdw] = 0;
+   enc->cs->current.buf[enc->cs->current.cdw] |=
+  ((unsigned int) (byte) << index_to_shifts[enc->byte_index]);
+   enc->byte_index++;
+
+   if (enc->byte_index >= 4) {
+  enc->byte_index = 0;
+  enc->cs->current.cdw++;
+   }
+}
+
+static void
+radeon_uvd_enc_emulation_prevention(struct radeon_uvd_encoder *enc,
+unsigned char byte)
+{
+   if (enc->emulation_prevention) {
+  if ((enc->num_zeros >= 2)
+  && ((byte == 0x00) || (byte == 0x01) || (byte == 0x03))) {
+ radeon_uvd_enc_output_one_byte(enc, 0x03);
+ enc->bits_output += 8;
+ enc->num_zeros = 0;
+  }
+  enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
+   }
+}
+
+static void
+radeon_uvd_enc_code_fixed_bits(struct radeon_uvd_encoder *enc,
+   unsigned int value, unsigned int num_bits)
+{
+   unsigned int bits_to_pack = 0;
+
+   while (num_bits > 0) {
+  unsigned int value_to_pack = value & (0x >> (32 - num_bits));
+  

[Mesa-dev] [PATCH v2 7/8] radeonsi:create uvd hevc enc entry

[James Zhu]

Add UVD hevc encode pipe video codec creation entry

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeonsi/si_uvd.c | 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_uvd.c 
b/src/gallium/drivers/radeonsi/si_uvd.c
index 64f2f8e..3906bbd 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -31,6 +31,8 @@
 #include "radeon/radeon_vce.h"
 #include "radeon/radeon_vcn_dec.h"
 #include "radeon/radeon_vcn_enc.h"
+#include "radeon/radeon_uvd_enc.h"
+#include "util/u_video.h"
 
 /**
  * creates an video buffer with an UVD compatible memory layout
@@ -146,9 +148,16 @@ struct pipe_video_codec *si_uvd_create_decoder(struct 
pipe_context *context,
struct si_context *ctx = (struct si_context *)context;
bool vcn = (ctx->b.family == CHIP_RAVEN) ? true : false;
 
-   if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
-   return (vcn) ? radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer) :
-   si_vce_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
+   if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+   if (vcn) {
+   radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);
+   } else {
+   if (u_reduce_video_profile(templ->profile) == 
PIPE_VIDEO_FORMAT_HEVC)
+   return radeon_uvd_create_encoder(context, 
templ, ctx->b.ws, si_vce_get_buffer);
+   else
+   return si_vce_create_encoder(context, templ, 
ctx->b.ws, si_vce_get_buffer);
+   }
+   }
 
return (vcn) ?  radeon_create_decoder(context, templ) :
si_common_uvd_create_decoder(context, templ, si_uvd_set_dtb);
-- 
2.7.4

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[Mesa-dev] [PATCH v2 5/8] radeon/uvd:add uvd hevc enc functions

[James Zhu]

Implement UVD hevc encode functions

Signed-off-by: James Zhu 
---
 src/gallium/drivers/radeon/radeon_uvd_enc.c | 370 
 1 file changed, 370 insertions(+)
 create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
new file mode 100644
index 000..f162589
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -0,0 +1,370 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+static void
+radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
+ struct pipe_h265_enc_picture_desc *pic)
+{
+   enc->enc_pic.picture_type = pic->picture_type;
+   enc->enc_pic.frame_num = pic->frame_num;
+   enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+   enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+   enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+   enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+   enc->enc_pic.not_referenced = pic->not_referenced;
+   enc->enc_pic.is_idr = (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR)
+  || (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I);
+   enc->enc_pic.crop_left = 0;
+   enc->enc_pic.crop_right =
+  (align(enc->base.width, 16) - enc->base.width) / 2;
+   enc->enc_pic.crop_top = 0;
+   enc->enc_pic.crop_bottom =
+  (align(enc->base.height, 16) - enc->base.height) / 2;
+   enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+   enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+   enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+   enc->enc_pic.max_poc = pic->seq.intra_period;
+   enc->enc_pic.log2_max_poc = 0;
+   for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
+  i = (i >> 1);
+   enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
+   enc->enc_pic.pic_width_in_luma_samples =
+  pic->seq.pic_width_in_luma_samples;
+   enc->enc_pic.pic_height_in_luma_samples =
+  pic->seq.pic_height_in_luma_samples;
+   enc->enc_pic.log2_diff_max_min_luma_coding_block_size =
+  pic->seq.log2_diff_max_min_luma_coding_block_size;
+   enc->enc_pic.log2_min_transform_block_size_minus2 =
+  pic->seq.log2_min_transform_block_size_minus2;
+   enc->enc_pic.log2_diff_max_min_transform_block_size =
+  pic->seq.log2_diff_max_min_transform_block_size;
+   enc->enc_pic.max_transform_hierarchy_depth_inter =
+  pic->seq.max_transform_hierarchy_depth_inter;
+   enc->enc_pic.max_transform_hierarchy_depth_intra =
+  pic->seq.max_transform_hierarchy_depth_intra;
+   enc->enc_pic.log2_parallel_merge_level_minus2 =
+  pic->pic.log2_parallel_merge_level_minus2;
+   enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
+   enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
+   enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
+   enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand;
+   enc->enc_pic.sample_adaptive_offset_enabled_flag =
+  pic->seq.sample_adaptive_offset_enabled_flag;
+   enc->enc_pic.pcm_enabled_flag = pic->seq.pcm_enabled_flag;
+   enc->enc_pic.sps_temporal_mvp_enabled_flag =
+  pic->seq.sps_temporal_mvp_enabled_flag;
+}
+
+static void
+flush(struct radeon_uvd_encoder *enc)
+{
+   enc->ws->cs_flush(enc->cs, PIPE_FLUSH_ASYNC, NULL);
+}
+
+static void
+radeon_uvd_enc_flush(struct pipe_video_codec 

Re: [Mesa-dev] [PATCH] r600: clean up initial shader register setup

[Gert Wollny]

I like that, 
Reviewed-By: Gert Wollny 

Am Mittwoch, den 07.02.2018, 06:25 +1000 schrieb Dave Airlie:
> From: Glenn Kennard 
> 
> This is taken from Glenn Kennards scratch series, but separated
> out as a cleanup by me.
> 
> Signed-off-by: Dave Airlie 
> ---
>  src/gallium/drivers/r600/r600_shader.c | 37 --
> 
>  1 file changed, 17 insertions(+), 20 deletions(-)
> 
> diff --git a/src/gallium/drivers/r600/r600_shader.c
> b/src/gallium/drivers/r600/r600_shader.c
> index c3bcb9b77d..fc93da8c75 100644
> --- a/src/gallium/drivers/r600/r600_shader.c
> +++ b/src/gallium/drivers/r600/r600_shader.c
> @@ -3368,41 +3368,38 @@ static int r600_shader_from_tgsi(struct
> r600_context *rctx,
>   ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
>  
>   ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
> - ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
> - ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
> - ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
> - ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
> +
> + int regno = ctx.file_offset[TGSI_FILE_TEMPORARY] +
> + ctx.info.file_max[TGSI_FILE_TEMPORARY];
> + ctx.bc->ar_reg = ++regno;
> + ctx.bc->index_reg[0] = ++regno;
> + ctx.bc->index_reg[1] = ++regno;
>  
>   if (ctx.type == PIPE_SHADER_TESS_CTRL) {
> - ctx.tess_input_info = ctx.bc->ar_reg + 3;
> - ctx.tess_output_info = ctx.bc->ar_reg + 4;
> - ctx.temp_reg = ctx.bc->ar_reg + 5;
> + ctx.tess_input_info = ++regno;
> + ctx.tess_output_info = ++regno;
>   } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
>   ctx.tess_input_info = 0;
> - ctx.tess_output_info = ctx.bc->ar_reg + 3;
> - ctx.temp_reg = ctx.bc->ar_reg + 4;
> + ctx.tess_output_info = ++regno;
>   } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
> - ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
> - ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
> - ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
> - ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
> - ctx.temp_reg = ctx.bc->ar_reg + 7;
> + ctx.gs_export_gpr_tregs[0] = ++regno;
> + ctx.gs_export_gpr_tregs[1] = ++regno;
> + ctx.gs_export_gpr_tregs[2] = ++regno;
> + ctx.gs_export_gpr_tregs[3] = ++regno;
>   if (ctx.shader->gs_tri_strip_adj_fix) {
> - ctx.gs_rotated_input[0] = ctx.bc->ar_reg +
> 7;
> - ctx.gs_rotated_input[1] = ctx.bc->ar_reg +
> 8;
> - ctx.temp_reg += 2;
> + ctx.gs_rotated_input[0] = ++regno;
> + ctx.gs_rotated_input[1] = ++regno;
>   } else {
>   ctx.gs_rotated_input[0] = 0;
>   ctx.gs_rotated_input[1] = 1;
>   }
> - } else {
> - ctx.temp_reg = ctx.bc->ar_reg + 3;
>   }
>  
>   if (shader->uses_images) {
> - ctx.thread_id_gpr = ctx.temp_reg++;
> + ctx.thread_id_gpr = ++regno;
>   ctx.thread_id_gpr_loaded = false;
>   }
> + ctx.temp_reg = ++regno;
>  
>   shader->max_arrays = 0;
>   shader->num_arrays = 0;
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[Mesa-dev] [PATCH] r600: clean up initial shader register setup

[Dave Airlie]

From: Glenn Kennard 

This is taken from Glenn Kennards scratch series, but separated
out as a cleanup by me.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/r600_shader.c | 37 --
 1 file changed, 17 insertions(+), 20 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index c3bcb9b77d..fc93da8c75 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -3368,41 +3368,38 @@ static int r600_shader_from_tgsi(struct r600_context 
*rctx,
ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
 
ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
-   ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
-   ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
-   ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
-   ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
+
+   int regno = ctx.file_offset[TGSI_FILE_TEMPORARY] +
+   ctx.info.file_max[TGSI_FILE_TEMPORARY];
+   ctx.bc->ar_reg = ++regno;
+   ctx.bc->index_reg[0] = ++regno;
+   ctx.bc->index_reg[1] = ++regno;
 
if (ctx.type == PIPE_SHADER_TESS_CTRL) {
-   ctx.tess_input_info = ctx.bc->ar_reg + 3;
-   ctx.tess_output_info = ctx.bc->ar_reg + 4;
-   ctx.temp_reg = ctx.bc->ar_reg + 5;
+   ctx.tess_input_info = ++regno;
+   ctx.tess_output_info = ++regno;
} else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
ctx.tess_input_info = 0;
-   ctx.tess_output_info = ctx.bc->ar_reg + 3;
-   ctx.temp_reg = ctx.bc->ar_reg + 4;
+   ctx.tess_output_info = ++regno;
} else if (ctx.type == PIPE_SHADER_GEOMETRY) {
-   ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
-   ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
-   ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
-   ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
-   ctx.temp_reg = ctx.bc->ar_reg + 7;
+   ctx.gs_export_gpr_tregs[0] = ++regno;
+   ctx.gs_export_gpr_tregs[1] = ++regno;
+   ctx.gs_export_gpr_tregs[2] = ++regno;
+   ctx.gs_export_gpr_tregs[3] = ++regno;
if (ctx.shader->gs_tri_strip_adj_fix) {
-   ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
-   ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
-   ctx.temp_reg += 2;
+   ctx.gs_rotated_input[0] = ++regno;
+   ctx.gs_rotated_input[1] = ++regno;
} else {
ctx.gs_rotated_input[0] = 0;
ctx.gs_rotated_input[1] = 1;
}
-   } else {
-   ctx.temp_reg = ctx.bc->ar_reg + 3;
}
 
if (shader->uses_images) {
-   ctx.thread_id_gpr = ctx.temp_reg++;
+   ctx.thread_id_gpr = ++regno;
ctx.thread_id_gpr_loaded = false;
}
+   ctx.temp_reg = ++regno;
 
shader->max_arrays = 0;
shader->num_arrays = 0;
-- 
2.14.3

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[Mesa-dev] [PATCH] ac/nir: use new pknorm_i16/u16 and pk_i16/u16 LLVM intrinsics

[Samuel Pitoiset]

Ported from RadeonSI.

Only one F1 2017 shader is affected, code size decreased
from 532 to 488 on both Polaris10 and Vega10.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/common/ac_nir_to_llvm.c | 146 +---
 1 file changed, 47 insertions(+), 99 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 67da79b975..9264d065af 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -5730,27 +5730,6 @@ setup_shared(struct ac_nir_context *ctx,
}
 }
 
-static LLVMValueRef
-emit_float_saturate(struct ac_llvm_context *ctx, LLVMValueRef v, float lo, 
float hi)
-{
-   v = ac_to_float(ctx, v);
-   v = emit_intrin_2f_param(ctx, "llvm.maxnum", ctx->f32, v, 
LLVMConstReal(ctx->f32, lo));
-   return emit_intrin_2f_param(ctx, "llvm.minnum", ctx->f32, v, 
LLVMConstReal(ctx->f32, hi));
-}
-
-
-static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
-   LLVMValueRef src0, LLVMValueRef src1)
-{
-   LLVMValueRef const16 = LLVMConstInt(ctx->ac.i32, 16, false);
-   LLVMValueRef comp[2];
-
-   comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx->ac.i32, 
65535, 0), "");
-   comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx->ac.i32, 
65535, 0), "");
-   comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
-   return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
-}
-
 /* Initialize arguments for the shader export intrinsic */
 static void
 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
@@ -5780,11 +5759,15 @@ si_llvm_init_export_args(struct nir_to_llvm_context 
*ctx,
return;
 
if (ctx->stage == MESA_SHADER_FRAGMENT && target >= 
V_008DFC_SQ_EXP_MRT) {
-   LLVMValueRef val[4];
unsigned index = target - V_008DFC_SQ_EXP_MRT;
unsigned col_format = (ctx->options->key.fs.col_format >> (4 * 
index)) & 0xf;
bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
+   unsigned chan;
+
+   LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef 
args[2]) = NULL;
+   LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef 
args[2],
+ unsigned bits, bool hi) = NULL;
 
switch(col_format) {
case V_028714_SPI_SHADER_ZERO:
@@ -5810,101 +5793,66 @@ si_llvm_init_export_args(struct nir_to_llvm_context 
*ctx,
break;
 
case V_028714_SPI_SHADER_FP16_ABGR:
-   args->compr = 1;
-
-   for (unsigned chan = 0; chan < 2; chan++) {
-   LLVMValueRef pack_args[2] = {
-   values[2 * chan],
-   values[2 * chan + 1]
-   };
-   LLVMValueRef packed;
-
-   packed = ac_build_cvt_pkrtz_f16(>ac, 
pack_args);
-   args->out[chan] = packed;
-   }
+   packf = ac_build_cvt_pkrtz_f16;
break;
 
case V_028714_SPI_SHADER_UNORM16_ABGR:
-   for (unsigned chan = 0; chan < 4; chan++) {
-   val[chan] = ac_build_clamp(>ac, 
values[chan]);
-   val[chan] = LLVMBuildFMul(ctx->builder, 
val[chan],
-   
LLVMConstReal(ctx->ac.f32, 65535), "");
-   val[chan] = LLVMBuildFAdd(ctx->builder, 
val[chan],
-   
LLVMConstReal(ctx->ac.f32, 0.5), "");
-   val[chan] = LLVMBuildFPToUI(ctx->builder, 
val[chan],
-   ctx->ac.i32, "");
-   }
-
-   args->compr = 1;
-   args->out[0] = emit_pack_int16(ctx, val[0], val[1]);
-   args->out[1] = emit_pack_int16(ctx, val[2], val[3]);
+   packf = ac_build_cvt_pknorm_u16;
break;
 
case V_028714_SPI_SHADER_SNORM16_ABGR:
-   for (unsigned chan = 0; chan < 4; chan++) {
-   val[chan] = emit_float_saturate(>ac, 
values[chan], -1, 1);
-   val[chan] = LLVMBuildFMul(ctx->builder, 
val[chan],
-   
LLVMConstReal(ctx->ac.f32, 32767), "");
-
-   /* If positive, add 0.5, else add -0.5. */
-   val[chan] = LLVMBuildFAdd(ctx->builder, 
val[chan],
-   

[Mesa-dev] [Bug 94194] New Account Request

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=94194

--- Comment #7 from Kenneth Graunke  ---
Pam has a number of solid contributions to i965 now, I'd be in favor of
granting her commit access.

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Re: [Mesa-dev] [PATCH 7/8] drivers/radeonsi:create uvd hevc enc entry

[James Zhu]

Updated in [Mesa-dev] [PATCH v2 0/8] The 2nd version for UVD HEVC encode


On 2018-02-06 08:56 AM, Leo Liu wrote:

General comments:

1. The patch title: please refer to previous commits under the directory,

https://cgit.freedesktop.org/mesa/mesa/log/src/gallium/drivers/radeon

Normally either "radeon/uvd" or "radeonsi"

Applies to changes on other directory.

2. Code style and indentation refer to:

https://cgit.freedesktop.org/mesa/mesa/tree/docs/codingstyle.html

3. If you have changes on the initial version, you'd better to add v2, 
v3. It's good practice in that way.

please refer to lots of commits in Mesa.

4. Once you resend your v2 version, you'd better to add 
"--in-reply-to="message-id", so that the newer patch will be in the 
same thread with your initial patch.



Leo

On 02/05/2018 04:14 PM, James Zhu wrote:

Add UVD hevc encode pipe video codec creation entry

Signed-off-by: James Zhu 
---
  src/gallium/drivers/radeonsi/si_uvd.c | 15 ---
  1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_uvd.c 
b/src/gallium/drivers/radeonsi/si_uvd.c

index 64f2f8e..0dea60d 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -31,6 +31,8 @@
  #include "radeon/radeon_vce.h"
  #include "radeon/radeon_vcn_dec.h"
  #include "radeon/radeon_vcn_enc.h"
+#include "radeon/radeon_uvd_enc.h"
+#include "util/u_video.h"
    /**
   * creates an video buffer with an UVD compatible memory layout
@@ -146,9 +148,16 @@ struct pipe_video_codec 
*si_uvd_create_decoder(struct pipe_context *context,

  struct si_context *ctx = (struct si_context *)context;
  bool vcn = (ctx->b.family == CHIP_RAVEN) ? true : false;
  -    if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
-    return (vcn) ? radeon_create_encoder(context, templ, 
ctx->b.ws, si_vce_get_buffer) :
-   si_vce_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);

+    if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+    if (vcn) {
+    radeon_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);

+    } else {
+    if (u_reduce_video_profile(templ->profile) == 
PIPE_VIDEO_FORMAT_HEVC)
+    radeon_uvd_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);

+    else
+    si_vce_create_encoder(context, templ, ctx->b.ws, 
si_vce_get_buffer);

+    }
+    }
    return (vcn) ? radeon_create_decoder(context, templ) :
  si_common_uvd_create_decoder(context, templ, si_uvd_set_dtb);




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[Mesa-dev] [PATCH] gallium: Mute arrays for several meta like callbacks.

[Mathias . Froehlich]

From: Mathias Fröhlich 

Hi Brian,

I think you are right the _mesa_set_drawing_arrays better belong into
the state tracker. You mean like the below?
I added also two other callbacks that lookes suspicious to me.
I just sent the single patch in question out of the series of three.
Tested with piglit quick on radeonsi, classic swrast and i965
without regressions.

best and thanks
Mathias


Set the _DrawArray pointer to NULL when calling into the Drivers
Bitmap/CopyPixels/DrawAtlasBitmaps/DrawPixels/DrawTex hooks.
This fixes an assert that gets uncovered with the following
patch gets applied.

v2: Mute from within the state tracker instead of generic mesa.

Signed-off-by: Mathias Fröhlich 
---
 src/mesa/state_tracker/st_cb_bitmap.c | 7 +++
 src/mesa/state_tracker/st_cb_drawpixels.c | 7 +++
 src/mesa/state_tracker/st_cb_drawtex.c| 4 
 3 files changed, 18 insertions(+)

diff --git a/src/mesa/state_tracker/st_cb_bitmap.c 
b/src/mesa/state_tracker/st_cb_bitmap.c
index a5c7ed0ee6..a1e35994de 100644
--- a/src/mesa/state_tracker/st_cb_bitmap.c
+++ b/src/mesa/state_tracker/st_cb_bitmap.c
@@ -36,6 +36,7 @@
 #include "main/dlist.h"
 #include "main/macros.h"
 #include "main/pbo.h"
+#include "main/varray.h"
 #include "program/program.h"
 #include "program/prog_print.h"
 
@@ -613,6 +614,9 @@ st_Bitmap(struct gl_context *ctx, GLint x, GLint y,
assert(width > 0);
assert(height > 0);
 
+   /* Prevent st_atom_array from accessing stale draw array data */
+   _mesa_set_drawing_arrays(ctx, NULL);
+
st_invalidate_readpix_cache(st);
 
if (!st->bitmap.vs) {
@@ -675,6 +679,9 @@ st_DrawAtlasBitmaps(struct gl_context *ctx,
struct pipe_vertex_buffer vb = {0};
unsigned i;
 
+   /* Prevent st_atom_array from accessing stale draw array data */
+   _mesa_set_drawing_arrays(ctx, NULL);
+
if (!st->bitmap.vs) {
   init_bitmap_state(st);
}
diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c 
b/src/mesa/state_tracker/st_cb_drawpixels.c
index ff3eb9b614..73108812da 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -45,6 +45,7 @@
 #include "main/texformat.h"
 #include "main/teximage.h"
 #include "main/texstore.h"
+#include "main/varray.h"
 #include "main/glformats.h"
 #include "program/program.h"
 #include "program/prog_print.h"
@@ -1142,6 +1143,9 @@ st_DrawPixels(struct gl_context *ctx, GLint x, GLint y,
/* Mesa state should be up to date by now */
assert(ctx->NewState == 0x0);
 
+   /* Prevent st_atom_array from accessing stale draw array data */
+   _mesa_set_drawing_arrays(ctx, NULL);
+
_mesa_update_draw_buffer_bounds(ctx, ctx->DrawBuffer);
 
st_flush_bitmap_cache(st);
@@ -1509,6 +1513,9 @@ st_CopyPixels(struct gl_context *ctx, GLint srcx, GLint 
srcy,
GLint readX, readY, readW, readH;
struct gl_pixelstore_attrib pack = ctx->DefaultPacking;
 
+   /* Prevent st_atom_array from accessing stale draw array data */
+   _mesa_set_drawing_arrays(ctx, NULL);
+
_mesa_update_draw_buffer_bounds(ctx, ctx->DrawBuffer);
 
st_flush_bitmap_cache(st);
diff --git a/src/mesa/state_tracker/st_cb_drawtex.c 
b/src/mesa/state_tracker/st_cb_drawtex.c
index 01c5757a73..0df0ab4713 100644
--- a/src/mesa/state_tracker/st_cb_drawtex.c
+++ b/src/mesa/state_tracker/st_cb_drawtex.c
@@ -17,6 +17,7 @@
 #include "main/macros.h"
 #include "main/teximage.h"
 #include "main/framebuffer.h"
+#include "main/varray.h"
 #include "program/program.h"
 #include "program/prog_print.h"
 
@@ -117,6 +118,9 @@ st_DrawTex(struct gl_context *ctx, GLfloat x, GLfloat y, 
GLfloat z,
struct pipe_vertex_element velements[2 + MAX_TEXTURE_UNITS];
unsigned offset;
 
+   /* Prevent st_atom_array from accessing stale draw array data */
+   _mesa_set_drawing_arrays(ctx, NULL);
+
st_flush_bitmap_cache(st);
st_invalidate_readpix_cache(st);
 
-- 
2.14.3

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[Mesa-dev] [PATCH v3 0/6] Implement commont gralloc_handle_t in libdrm

[Robert Foss]

This series moves {gbm,drm,cros}_gralloc_handle_t struct to libdrm,
since at least 4 implementations exist, and share a lot of contents.
The idea is to keep the common stuff defined in one place, and libdrm
is the common codebase to all of these platforms.

Additionally, having this struct defined in libdrm will make it
easier for mesa and gralloc implementations to communicate.

A second series is expected to be submitted, which will contain an accessor
function implementation that should that would allow each gralloc to
implementation to supply their own accessors.

Robert Foss (6):
  android: Move gralloc handle struct to libdrm
  android: Add version variable to gralloc_handle_t
  android: Mark gralloc_handle_t magic variable as const
  android: Remove member name from gralloc_handle_t
  android: Change gralloc_handle_t format from Android format to fourcc
  android: Change gralloc_handle_t members to be fixed width

 Android.mk   |   8 +++-
 Makefile.sources |   3 ++
 android/gralloc_handle.h | 108 +++
 3 files changed, 117 insertions(+), 2 deletions(-)
 create mode 100644 android/gralloc_handle.h

-- 
2.14.1

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Re: [Mesa-dev] [PATCH 01/11] radeonsi/nir: gather some compute info in si_nir_scan_shader()

[Marek Olšák]

On Fri, Feb 2, 2018 at 5:03 AM, Timothy Arceri  wrote:
> ---
>  src/gallium/drivers/radeonsi/si_shader_nir.c | 30 
> +++-
>  1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
> b/src/gallium/drivers/radeonsi/si_shader_nir.c
> index 128be585cd..28b031d935 100644
> --- a/src/gallium/drivers/radeonsi/si_shader_nir.c
> +++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
> @@ -86,6 +86,27 @@ static void scan_instruction(struct tgsi_shader_info *info,
> case nir_intrinsic_load_invocation_id:
> info->uses_invocationid = true;
> break;
> +   case nir_intrinsic_load_num_work_groups:
> +   info->uses_grid_size = true;
> +   break;
> +   case nir_intrinsic_load_local_group_size:
> +   /* The block size is translated to IMM with a fixed 
> block size. */
> +   if 
> (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
> +   info->uses_block_size = true;
> +   break;
> +   case nir_intrinsic_load_local_invocation_id:
> +   case nir_intrinsic_load_work_group_id: {
> +   unsigned mask = 
> nir_ssa_def_components_read(>dest.ssa);
> +   while (mask) {
> +   unsigned i = u_bit_scan();
> +
> +   if (intr->intrinsic == 
> nir_intrinsic_load_work_group_id)
> +   info->uses_block_id[i] = true;
> +   else
> +   info->uses_thread_id[i] = true;
> +   }
> +   break;
> +   }
> case nir_intrinsic_load_vertex_id:
> info->uses_vertexid = 1;
> break;
> @@ -226,7 +247,8 @@ void si_nir_scan_shader(const struct nir_shader *nir,
>nir->info.stage == MESA_SHADER_GEOMETRY ||
>nir->info.stage == MESA_SHADER_TESS_CTRL ||
>nir->info.stage == MESA_SHADER_TESS_EVAL ||
> -  nir->info.stage == MESA_SHADER_FRAGMENT);
> +  nir->info.stage == MESA_SHADER_FRAGMENT ||
> +  nir->info.stage == MESA_SHADER_COMPUTE);

You can just remove this tautological assertion.

Marek
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Re: [Mesa-dev] [PATCH 11/11] r600/radeonsi/clover: always assume PIPE_SHADER_IR_NATIVE for clover

[Marek Olšák]

On Fri, Feb 2, 2018 at 8:07 AM, Timothy Arceri  wrote:
>
>
> On 02/02/18 17:21, Timothy Arceri wrote:
>>
>> On 02/02/18 16:38, Jan Vesely wrote:
>>>
>>> On Fri, 2018-02-02 at 15:03 +1100, Timothy Arceri wrote:

 When PIPE_SHADER_IR_LLVM existed this query made sense but now it
 always returns PIPE_SHADER_IR_NATIVE. Also it is now conlicting
 with PIPE_SHADER_IR_NIR for compute shaders, so just assume this
 is always PIPE_SHADER_IR_NATIVE for clover.

 This change indirectly enables NIR support for compute shaders
 on radeonsi.
 ---
   src/gallium/drivers/r600/r600_pipe.c  | 6 +-
   src/gallium/drivers/radeonsi/si_get.c | 3 ---
   src/gallium/state_trackers/clover/core/device.cpp | 3 +--
   3 files changed, 2 insertions(+), 10 deletions(-)

 diff --git a/src/gallium/drivers/r600/r600_pipe.c
 b/src/gallium/drivers/r600/r600_pipe.c
 index 6c021e568d..287fe497ca 100644
 --- a/src/gallium/drivers/r600/r600_pipe.c
 +++ b/src/gallium/drivers/r600/r600_pipe.c
 @@ -595,11 +595,7 @@ static int r600_get_shader_param(struct
 pipe_screen* pscreen,
   case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
   return 16;
   case PIPE_SHADER_CAP_PREFERRED_IR:
 -if (shader == PIPE_SHADER_COMPUTE) {
 -return PIPE_SHADER_IR_NATIVE;
 -} else {
 -return PIPE_SHADER_IR_TGSI;
 -}
 +return PIPE_SHADER_IR_TGSI;
   case PIPE_SHADER_CAP_SUPPORTED_IRS:
   if (rscreen->b.family >= CHIP_CEDAR)
   return (1 << PIPE_SHADER_IR_TGSI);
 diff --git a/src/gallium/drivers/radeonsi/si_get.c
 b/src/gallium/drivers/radeonsi/si_get.c
 index 40f4cc267e..46cc190db1 100644
 --- a/src/gallium/drivers/radeonsi/si_get.c
 +++ b/src/gallium/drivers/radeonsi/si_get.c
 @@ -391,9 +391,6 @@ static int si_get_shader_param(struct pipe_screen*
 pscreen,
   break;
   case PIPE_SHADER_COMPUTE:
   switch (param) {
 -case PIPE_SHADER_CAP_PREFERRED_IR:
 -return PIPE_SHADER_IR_NATIVE;
 -
   case PIPE_SHADER_CAP_SUPPORTED_IRS: {
   int ir = 1 << PIPE_SHADER_IR_NATIVE;
 diff --git a/src/gallium/state_trackers/clover/core/device.cpp
 b/src/gallium/state_trackers/clover/core/device.cpp
 index 9dd7eed3f1..116f0c7604 100644
 --- a/src/gallium/state_trackers/clover/core/device.cpp
 +++ b/src/gallium/state_trackers/clover/core/device.cpp
 @@ -243,8 +243,7 @@ device::vendor_name() const {
   enum pipe_shader_ir
   device::ir_format() const {
 -   return (enum pipe_shader_ir) pipe->get_shader_param(
 -  pipe, PIPE_SHADER_COMPUTE, PIPE_SHADER_CAP_PREFERRED_IR);
 +   return PIPE_SHADER_IR_NATIVE;
>>>
>>>
>>> This looks like it forces IR_NATIVE for absolutely everybody. Why
>>> should other devices use IR_NATIVE just because radeonsi wants
>>> experimental NIR for GL?
>>
>>
>> It's not just about experimental NIR. If say freedreno or any other nir
>> driver was to use clover they would have the same problem.
>
>
> Well it would be return PIPE_SHADER_IR_NIR here at least.
>
>> Also I'm 99% certain that no drivers other than radeonsi and r600 even
>> care what this value is. All other drivers have this set to
>> PIPE_SHADER_IR_TGSI does that make anymore sense?
>
>
> I see no there is indeed a tgsi path for clover. I guess maybe this change
> has more impact than I first thought.
>
> Happy to here suggestions for solving the current conflict in uses of
> PIPE_SHADER_CAP_PREFERRED_IR.

If clover wants a CAP, it can have its own CAP.

Or this CAP can be removed and everybody can just use
PIPE_SHADER_CAP_SUPPORTED_IRS. st/mesa can prefer NIR if supported,
and clover can prefer native if supported. Problem solved.

Marek
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Re: [Mesa-dev] [PATCH 11/11] r600/radeonsi/clover: always assume PIPE_SHADER_IR_NATIVE for clover

[Marek Olšák]

I made a comment on patch 1. With that addressed, the series is:

Reviewed-by: Marek Olšák 

Marek

On Fri, Feb 2, 2018 at 5:03 AM, Timothy Arceri  wrote:
> When PIPE_SHADER_IR_LLVM existed this query made sense but now it
> always returns PIPE_SHADER_IR_NATIVE. Also it is now conlicting
> with PIPE_SHADER_IR_NIR for compute shaders, so just assume this
> is always PIPE_SHADER_IR_NATIVE for clover.
>
> This change indirectly enables NIR support for compute shaders
> on radeonsi.
> ---
>  src/gallium/drivers/r600/r600_pipe.c  | 6 +-
>  src/gallium/drivers/radeonsi/si_get.c | 3 ---
>  src/gallium/state_trackers/clover/core/device.cpp | 3 +--
>  3 files changed, 2 insertions(+), 10 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/r600_pipe.c 
> b/src/gallium/drivers/r600/r600_pipe.c
> index 6c021e568d..287fe497ca 100644
> --- a/src/gallium/drivers/r600/r600_pipe.c
> +++ b/src/gallium/drivers/r600/r600_pipe.c
> @@ -595,11 +595,7 @@ static int r600_get_shader_param(struct pipe_screen* 
> pscreen,
> case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
> return 16;
>  case PIPE_SHADER_CAP_PREFERRED_IR:
> -   if (shader == PIPE_SHADER_COMPUTE) {
> -   return PIPE_SHADER_IR_NATIVE;
> -   } else {
> -   return PIPE_SHADER_IR_TGSI;
> -   }
> +   return PIPE_SHADER_IR_TGSI;
> case PIPE_SHADER_CAP_SUPPORTED_IRS:
> if (rscreen->b.family >= CHIP_CEDAR)
> return (1 << PIPE_SHADER_IR_TGSI);
> diff --git a/src/gallium/drivers/radeonsi/si_get.c 
> b/src/gallium/drivers/radeonsi/si_get.c
> index 40f4cc267e..46cc190db1 100644
> --- a/src/gallium/drivers/radeonsi/si_get.c
> +++ b/src/gallium/drivers/radeonsi/si_get.c
> @@ -391,9 +391,6 @@ static int si_get_shader_param(struct pipe_screen* 
> pscreen,
> break;
> case PIPE_SHADER_COMPUTE:
> switch (param) {
> -   case PIPE_SHADER_CAP_PREFERRED_IR:
> -   return PIPE_SHADER_IR_NATIVE;
> -
> case PIPE_SHADER_CAP_SUPPORTED_IRS: {
> int ir = 1 << PIPE_SHADER_IR_NATIVE;
>
> diff --git a/src/gallium/state_trackers/clover/core/device.cpp 
> b/src/gallium/state_trackers/clover/core/device.cpp
> index 9dd7eed3f1..116f0c7604 100644
> --- a/src/gallium/state_trackers/clover/core/device.cpp
> +++ b/src/gallium/state_trackers/clover/core/device.cpp
> @@ -243,8 +243,7 @@ device::vendor_name() const {
>
>  enum pipe_shader_ir
>  device::ir_format() const {
> -   return (enum pipe_shader_ir) pipe->get_shader_param(
> -  pipe, PIPE_SHADER_COMPUTE, PIPE_SHADER_CAP_PREFERRED_IR);
> +   return PIPE_SHADER_IR_NATIVE;
>  }
>
>  std::string
> --
> 2.14.3
>
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[Mesa-dev] [PATCH] mesa: add glsl version query

[Vadym Shovkoplias]

From: Vadym Shovkoplias 

Add support for GL_NUM_SHADING_LANGUAGE_VERSIONS
and glGetStringi for GL_SHADING_LANGUAGE_VERSION

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104915
Signed-off-by: Andriy Khulap 
Signed-off-by: Vadym Shovkoplias 
---
 src/mapi/glapi/gen/GL4x.xml  |  1 +
 src/mesa/main/get.c  | 31 ++
 src/mesa/main/get_hash_params.py |  3 +++
 src/mesa/main/getstring.c| 56 
 4 files changed, 91 insertions(+)

diff --git a/src/mapi/glapi/gen/GL4x.xml b/src/mapi/glapi/gen/GL4x.xml
index cd2e3b831e..2116286b35 100644
--- a/src/mapi/glapi/gen/GL4x.xml
+++ b/src/mapi/glapi/gen/GL4x.xml
@@ -42,6 +42,7 @@
 
 
   
+  
   
   
   
diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index 516e8d174c..958bb62dc6 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -1084,6 +1084,37 @@ find_custom_value(struct gl_context *ctx, const struct 
value_desc *d, union valu
  v->value_int = 0;
   }
   break;
+   /* GL_NUM_SHADING_LANGUAGE_VERSIONS */
+   case GL_NUM_SHADING_LANGUAGE_VERSIONS:
+  {
+ int num = 0;
+ /* GLSL es */
+ if (ctx->API == API_OPENGLES2 || 
ctx->Extensions.ARB_ES2_compatibility)
+num++;
+ if (_mesa_is_gles3(ctx) || ctx->Extensions.ARB_ES3_compatibility)
+num++;
+ if (_mesa_is_gles31(ctx) || ctx->Extensions.ARB_ES3_1_compatibility)
+num++;
+ if ((ctx->API == API_OPENGLES2 && ctx->Version >= 32) ||
+  ctx->Extensions.ARB_ES3_2_compatibility)
+num++;
+ /* GLSL core */
+ if (ctx->Const.GLSLVersion >= 120) num++;
+ if (ctx->Const.GLSLVersion >= 130) num++;
+ if (ctx->Const.GLSLVersion >= 140) num++;
+ if (ctx->Const.GLSLVersion >= 150) num++;
+ if (ctx->Const.GLSLVersion >= 330) num++;
+ if (ctx->Const.GLSLVersion >= 400) num++;
+ if (ctx->Const.GLSLVersion >= 410) num++;
+ if (ctx->Const.GLSLVersion >= 420) num++;
+ if (ctx->Const.GLSLVersion >= 430) num++;
+ if (ctx->Const.GLSLVersion >= 440) num++;
+ if (ctx->Const.GLSLVersion >= 450) num++;
+ if (ctx->Const.GLSLVersion >= 460) num++;
+
+ v->value_int = num;
+  }
+  break;
/* GL_ARB_draw_indirect */
case GL_DRAW_INDIRECT_BUFFER_BINDING:
   v->value_int = ctx->DrawIndirectBuffer->Name;
diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py
index df082af207..be716f6f6e 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -543,6 +543,9 @@ descriptor=[
 
   # GL_ARB_texture_cube_map_array
   [ "TEXTURE_BINDING_CUBE_MAP_ARRAY_ARB", "LOC_CUSTOM, TYPE_INT, 
TEXTURE_CUBE_ARRAY_INDEX, 
extra_ARB_texture_cube_map_array_OES_texture_cube_map_array" ],
+
+  # GL_NUM_SHADING_LANGUAGE_VERSIONS
+  [ "NUM_SHADING_LANGUAGE_VERSIONS", "LOC_CUSTOM, TYPE_INT, 0, NO_EXTRA" ],
 ]},
 
 # Enums in OpenGL Core profile and ES 3.0
diff --git a/src/mesa/main/getstring.c b/src/mesa/main/getstring.c
index 931f6a476c..50136b91b3 100644
--- a/src/mesa/main/getstring.c
+++ b/src/mesa/main/getstring.c
@@ -99,6 +99,60 @@ shading_language_version(struct gl_context *ctx)
 }
 
 
+/**
+ * Return the string for a glGetStringi(GL_SHADING_LANGUAGE_VERSION) query.
+ */
+static const GLubyte *
+shading_language_version_index(struct gl_context *ctx, GLuint index)
+{
+   char *supported_versions[17];
+   int num_supported = 0;
+
+   /* Reversed order */
+   /* GLSL es */
+   if (ctx->API == API_OPENGLES2 || ctx->Extensions.ARB_ES2_compatibility)
+  supported_versions[num_supported++] = "100";
+   if (_mesa_is_gles3(ctx) || ctx->Extensions.ARB_ES3_compatibility)
+  supported_versions[num_supported++] = "300 es";
+   if (_mesa_is_gles31(ctx) || ctx->Extensions.ARB_ES3_1_compatibility)
+  supported_versions[num_supported++] = "310 es";
+   if ((ctx->API == API_OPENGLES2 && ctx->Version >= 32) ||
+   ctx->Extensions.ARB_ES3_2_compatibility)
+  supported_versions[num_supported++] = "320 es";
+
+   /* GLSL core */
+   if (ctx->Const.GLSLVersion >= 120)
+  supported_versions[num_supported++] = "120";
+   if (ctx->Const.GLSLVersion >= 130)
+  supported_versions[num_supported++] = "130";
+   if (ctx->Const.GLSLVersion >= 140)
+  supported_versions[num_supported++] = "140";
+   if (ctx->Const.GLSLVersion >= 150)
+  supported_versions[num_supported++] = "150";
+   if (ctx->Const.GLSLVersion >= 330)
+  supported_versions[num_supported++] = "330";
+   if (ctx->Const.GLSLVersion >= 400)
+  supported_versions[num_supported++] = "400";
+   if (ctx->Const.GLSLVersion >= 410)
+  supported_versions[num_supported++] = "410";
+   if (ctx->Const.GLSLVersion >= 420)
+  supported_versions[num_supported++] = "420";
+   if (ctx->Const.GLSLVersion 

Re: [Mesa-dev] [PATCH] travis: radeonsi and radv need LLVM 4.0

[Andres Gomez]

On Tue, 2018-02-06 at 11:01 -0500, Jan Vesely wrote:
> On Tue, 2018-02-06 at 17:42 +0200, Andres Gomez wrote:
> > Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
> > Cc: Marek Olšák 
> > Cc: Emil Velikov 
> > Cc: Jan Vesely 
> > Signed-off-by: Andres Gomez 
> > ---
> > 

[...]

> > @@ -131,7 +160,7 @@ matrix:
> >  - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
> >  - DRI_DRIVERS=""
> >  - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa 
> > --disable-nine --disable-xvmc --disable-vdpau --disable-va 
> > --disable-omx-bellagio --disable-gallium-osmesa"
> > -- 
> > GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
> > +- 
> > GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
> >  - VULKAN_DRIVERS=""
> >  - LIBUNWIND_FLAGS="--enable-libunwind"
> >addons:
> > @@ -166,7 +195,7 @@ matrix:
> >  - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
> >  - DRI_DRIVERS=""
> >  - GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd 
> > --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau 
> > --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
> > -- GALLIUM_DRIVERS="r600,radeonsi"
> > +- GALLIUM_DRIVERS="r600"
> 
> Why is this necessary? Has there been any change that disqualifies
> llvm-3.9 for radeonsi OpenCL?

Unless I'm missing something, what it is said in the commit log.

3bf1e036e8a removed support for LLVM 3.9 in radeonsi and radv.

-- 
Br,

Andres
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[Mesa-dev] [PATCH] vulkan/wsi: Fix OOM behavior with prime images.

[Bas Nieuwenhuizen]

Fixes: d50937f137 "vulkan/wsi: Implement prime in a completely generic way"
---
 src/vulkan/wsi/wsi_common.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/vulkan/wsi/wsi_common.c b/src/vulkan/wsi/wsi_common.c
index e9e43e1204..90ed07b785 100644
--- a/src/vulkan/wsi/wsi_common.c
+++ b/src/vulkan/wsi/wsi_common.c
@@ -429,8 +429,10 @@ wsi_create_prime_image(const struct wsi_swapchain *chain,
   vk_zalloc(>alloc,
 sizeof(VkCommandBuffer) * wsi->queue_family_count, 8,
 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
-   if (!image->prime.blit_cmd_buffers)
+   if (!image->prime.blit_cmd_buffers) {
+  result = VK_ERROR_OUT_OF_HOST_MEMORY;
   goto fail;
+   }
 
for (uint32_t i = 0; i < wsi->queue_family_count; i++) {
   const VkCommandBufferAllocateInfo cmd_buffer_info = {
-- 
2.16.1

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Re: [Mesa-dev] [PATCH v2] radeonsi/nir: always set input_usage_mask as using all components

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek


On Tue, Feb 6, 2018 at 1:11 AM, Timothy Arceri  wrote:
> This fixes a regression for now, in the future we should gather
> the used components properly.
>
> V2: just set for VS and correctly handle doubles
>
> Fixes: be973ed21f6e "radeonsi: load the right number of components for VS 
> inputs and TBOs"
>
> Cc: Marek Olšák 
> ---
>  src/gallium/drivers/radeonsi/si_shader_nir.c | 14 ++
>  1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
> b/src/gallium/drivers/radeonsi/si_shader_nir.c
> index 8abffdb8fc..06d9354363 100644
> --- a/src/gallium/drivers/radeonsi/si_shader_nir.c
> +++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
> @@ -304,14 +304,22 @@ void si_nir_scan_shader(const struct nir_shader *nir,
> unsigned attrib_count = glsl_count_attribute_slots(type,
>
> nir->info.stage == MESA_SHADER_VERTEX);
>
> +   i = variable->data.driver_location;
> +
> /* Vertex shader inputs don't have semantics. The state
>  * tracker has already mapped them to attributes via
>  * variable->data.driver_location.
>  */
> if (nir->info.stage == MESA_SHADER_VERTEX) {
> -   if (glsl_type_is_dual_slot(variable->type))
> +   /* TODO: gather the actual input useage and remove 
> this. */
> +   info->input_usage_mask[i] = TGSI_WRITEMASK_XYZW;
> +
> +   if (glsl_type_is_dual_slot(variable->type)) {
> num_inputs += 2;
> -   else
> +
> +   /* TODO: gather the actual input useage and 
> remove this. */
> +   info->input_usage_mask[i+1] = 
> TGSI_WRITEMASK_XYZW;
> +   } else
> num_inputs++;
> continue;
> }
> @@ -327,8 +335,6 @@ void si_nir_scan_shader(const struct nir_shader *nir,
> continue;
> }
>
> -   i = variable->data.driver_location;
> -
> for (unsigned j = 0; j < attrib_count; j++, i++) {
>
> if (processed_inputs & ((uint64_t)1 << i))
> --
> 2.14.3
>
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Re: [Mesa-dev] [PATCH v2] util: remove redundant check for the __clang__ macro

[Brian Paul]

On 02/06/2018 06:48 AM, Vlad Golovkin wrote:

Clang defines __GNUC__ macro, so one doesn't need to check __clang__
macro in this particular case.

v2: added comment as per Brian Paul's suggestion
---
  src/util/macros.h | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/util/macros.h b/src/util/macros.h
index 432d513930..e3c785af50 100644
--- a/src/util/macros.h
+++ b/src/util/macros.h
@@ -137,8 +137,9 @@ do {   \
  #endif
  
  /* Forced function inlining */

+/* Note: Clang also sets __GNUC__ (see other cases below) */
  #ifndef ALWAYS_INLINE
-#  if defined(__GNUC__) || defined(__clang__)
+#  if defined(__GNUC__)
  #define ALWAYS_INLINE inline __attribute__((always_inline))
  #  elif defined(_MSC_VER)
  #define ALWAYS_INLINE __forceinline



Thanks!

Reviewed-by: Brian Paul 

Do you need me to push this for you?
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Re: [Mesa-dev] [PATCH] travis: radeonsi and radv need LLVM 4.0

[Jan Vesely]

On Tue, 2018-02-06 at 17:42 +0200, Andres Gomez wrote:
> Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9")
> Cc: Marek Olšák 
> Cc: Emil Velikov 
> Cc: Jan Vesely 
> Signed-off-by: Andres Gomez 
> ---
> 
> Additionally, AMD's support removal for LLVM 3.9 has also affected the
> distcheck target.
> 
> Unfortunately, SWR distribution needs 3.9.x, therefore, we cannot
> simply use LLVM 4.0 to generate the distribution tarball.
> 
> Either SWR upgrades its minimal dependency to LLVM 4.0 or we find a
> way of instructing distcheck so it would use LLVM 3.9 for the tarball
> generation and LLVM 4.0 for the check stage of the distcheck ...
> 
>  .travis.yml | 46 --
>  1 file changed, 36 insertions(+), 10 deletions(-)
> 
> diff --git a/.travis.yml b/.travis.yml
> index 0156eefb7ad..3651d00169f 100644
> --- a/.travis.yml
> +++ b/.travis.yml
> @@ -37,12 +37,12 @@ matrix:
>addons:
>  apt:
>sources:
> -- llvm-toolchain-trusty-3.9
> +- llvm-toolchain-trusty-4.0
>packages:
>  # LLVM packaging is broken and misses these dependencies
>  - libedit-dev
>  # From sources above
> -- llvm-3.9-dev
> +- llvm-4.0-dev
>  # Common
>  - xz-utils
>  - libexpat1-dev
> @@ -119,6 +119,35 @@ matrix:
>  - libx11-xcb-dev
>  - libelf-dev
>  - libunwind8-dev
> +- env:
> +- LABEL="make Gallium Drivers RadeonSI"
> +- BUILD=make
> +- MAKEFLAGS="-j4"
> +- MAKE_CHECK_COMMAND="true"
> +- LLVM_VERSION=4.0
> +- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
> +- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
> +- DRI_DRIVERS=""
> +- GALLIUM_ST="--enable-dri --disable-opencl --disable-xa 
> --disable-nine --disable-xvmc --disable-vdpau --disable-va 
> --disable-omx-bellagio --disable-gallium-osmesa"
> +- GALLIUM_DRIVERS="radeonsi"
> +- VULKAN_DRIVERS=""
> +- LIBUNWIND_FLAGS="--enable-libunwind"
> +  addons:
> +apt:
> +  sources:
> +- llvm-toolchain-trusty-4.0
> +  packages:
> +# LLVM packaging is broken and misses these dependencies
> +- libedit-dev
> +# From sources above
> +- llvm-4.0-dev
> +# Common
> +- xz-utils
> +- x11proto-xf86vidmode-dev
> +- libexpat1-dev
> +- libx11-xcb-dev
> +- libelf-dev
> +- libunwind8-dev
>  - env:
>  - LABEL="make Gallium Drivers Other"
>  - BUILD=make
> @@ -131,7 +160,7 @@ matrix:
>  - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
>  - DRI_DRIVERS=""
>  - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa 
> --disable-nine --disable-xvmc --disable-vdpau --disable-va 
> --disable-omx-bellagio --disable-gallium-osmesa"
> -- 
> GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
> +- 
> GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,freedreno,svga,swrast,vc4,virgl,etnaviv,imx"
>  - VULKAN_DRIVERS=""
>  - LIBUNWIND_FLAGS="--enable-libunwind"
>addons:
> @@ -166,7 +195,7 @@ matrix:
>  - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
>  - DRI_DRIVERS=""
>  - GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd 
> --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau 
> --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
> -- GALLIUM_DRIVERS="r600,radeonsi"
> +- GALLIUM_DRIVERS="r600"

Why is this necessary? Has there been any change that disqualifies
llvm-3.9 for radeonsi OpenCL?

Jan

>  - VULKAN_DRIVERS=""
>  - LIBUNWIND_FLAGS="--enable-libunwind"
>addons:
> @@ -303,10 +332,8 @@ matrix:
>  - BUILD=make
>  - MAKEFLAGS="-j4"
>  - MAKE_CHECK_COMMAND="make -C src/gtest check && make -C src/intel 
> check"
> -- LLVM_VERSION=3.9
> +- LLVM_VERSION=4.0
>  - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
> -# New binutils linker is required for llvm-3.9
> -- OVERRIDE_PATH=/usr/lib/binutils-2.26/bin
>  - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl 
> --with-platforms=x11,wayland"
>  - DRI_DRIVERS=""
>  - GALLIUM_ST="--enable-dri --enable-dri3 --disable-opencl 
> --disable-xa --disable-nine --disable-xvmc --disable-vdpau --disable-va 
> --disable-omx-bellagio --disable-gallium-osmesa"
> @@ -316,13 +343,12 @@ matrix:
>addons:
>  apt:
>sources:
> -- llvm-toolchain-trusty-3.9
> +- llvm-toolchain-trusty-4.0
>packages:
> - 

[Mesa-dev] [PATCH] i965: perf: add debug messages for loaded configs

[Lionel Landwerlin]

This helps figuring out potential problems when metrics don't show up
on frameretrace for example.

Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_performance_query.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index f2aa2b8469d..5b8f30db2f8 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1871,6 +1871,7 @@ init_oa_configs(struct brw_context *brw, const char 
*sysfs_dev_dir)
 
   /* Don't recreate already loaded configs. */
   if (read_file_uint64(config_path, _id)) {
+ DBG("metric set: %s (already loaded)\n", query->guid);
  register_oa_config(brw, query, config_id);
  continue;
   }
@@ -1896,6 +1897,7 @@ init_oa_configs(struct brw_context *brw, const char 
*sysfs_dev_dir)
   }
 
   register_oa_config(brw, query, config_id);
+  DBG("metric set: %s (added)\n", query->guid);
}
 }
 
-- 
2.16.1

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[Mesa-dev] [PATCH v3 1/6] android: Move gralloc handle struct to libdrm

[Robert Foss]

This struct is used in mesa and drm_hwcomposer.
Versions of if have been implemented in several grallocs:
drm_gralloc, gbm_gralloc, minigbm and intel-minigbm.

Other than the 1:1 move of the struct a new generic name
has been chosen and variables have had comments added to them.

Signed-off-by: Robert Foss 
---
Changes since v2:
 Suggested by Rob Herring:
 - Switch to gbm_gralloc copyright statement as a base

Changes since v1:
 Suggested by Rob Herring:
 - Fixed copyright statement
 - Moved FDs to be first in handle
 - Initialize native_handle_t using native_handle_create()

 Android.mk   |   8 +++-
 Makefile.sources |   3 ++
 android/gralloc_handle.h | 101 +++
 3 files changed, 110 insertions(+), 2 deletions(-)
 create mode 100644 android/gralloc_handle.h

diff --git a/Android.mk b/Android.mk
index 292be2360263..8611c5e316d8 100644
--- a/Android.mk
+++ b/Android.mk
@@ -28,7 +28,7 @@ LIBDRM_TOP := $(LOCAL_PATH)
 
 include $(CLEAR_VARS)
 
-# Import variables LIBDRM_{,H_,INCLUDE_H_,INCLUDE_VMWGFX_H_}FILES
+# Import variables 
LIBDRM_{,H,INCLUDE_H,INCLUDE_ANDROID_H,INCLUDE_VMWGFX_H}_FILES
 include $(LOCAL_PATH)/Makefile.sources
 
 #static library for the device (recovery)
@@ -38,7 +38,8 @@ LOCAL_MODULE := libdrm
 LOCAL_SRC_FILES := $(LIBDRM_FILES)
 LOCAL_EXPORT_C_INCLUDE_DIRS := \
$(LOCAL_PATH) \
-   $(LOCAL_PATH)/include/drm
+   $(LOCAL_PATH)/include/drm \
+   $(LOCAL_PATH)/android
 
 LOCAL_C_INCLUDES := \
$(LOCAL_PATH)/include/drm
@@ -54,6 +55,9 @@ LOCAL_SRC_FILES := $(LIBDRM_FILES)
 LOCAL_EXPORT_C_INCLUDE_DIRS := \
 $(LOCAL_PATH)/include/drm
 
+LOCAL_SHARED_LIBRARIES := \
+   libcutils
+
 LOCAL_C_INCLUDES := \
 $(LOCAL_PATH)/include/drm
 
diff --git a/Makefile.sources b/Makefile.sources
index 10aa1d0f4b6e..1f8372bca183 100644
--- a/Makefile.sources
+++ b/Makefile.sources
@@ -37,5 +37,8 @@ LIBDRM_INCLUDE_H_FILES := \
include/drm/via_drm.h \
include/drm/virtgpu_drm.h
 
+LIBDRM_INCLUDE_ANDROID_H_FILES := \
+   android/gralloc_handle.h
+
 LIBDRM_INCLUDE_VMWGFX_H_FILES := \
include/drm/vmwgfx_drm.h
diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h
new file mode 100644
index ..45b9f2e9b8dc
--- /dev/null
+++ b/android/gralloc_handle.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2010-2011 Chia-I Wu 
+ * Copyright (C) 2010-2011 LunarG Inc.
+ * Copyright (C) 2016 Linaro, Ltd., Rob Herring 
+ * Copyright (C) 2018 Collabora, Robert Foss 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __ANDROID_GRALLOC_HANDLE_H__
+#define __ANDROID_GRALLOC_HANDLE_H__
+
+#include 
+
+/* support users of drm_gralloc/gbm_gralloc */
+#define gralloc_gbm_handle_t gralloc_handle_t
+#define gralloc_drm_handle_t gralloc_handle_t
+
+struct gralloc_handle_t {
+   native_handle_t base;
+
+   /* dma-buf file descriptor
+* Must be located first since, native_handle_t is allocated
+* using native_handle_create(), which allocates space for
+* sizeof(native_handle_t) + sizeof(int) * (numFds + numInts)
+* numFds = GRALLOC_HANDLE_NUM_FDS
+* numInts = GRALLOC_HANDLE_NUM_INTS
+* Where numFds represents the number of FDs and
+* numInts represents the space needed for the
+* remainder of this struct.
+* And the FDs are expected to be found first following
+* native_handle_t.
+*/
+   int prime_fd;
+
+   int magic; /* differentiate between allocator impls */
+
+   int width; /* width of buffer in pixels */
+   int height; /* height of buffer in pixels */
+   int format; /* pixel format (Android) */
+   int usage; /* android libhardware usage flags */
+
+   int name;   /* the name of the bo */
+   int stride; /* the stride in bytes */
+   

[Mesa-dev] [PATCH v3 3/6] android: Mark gralloc_handle_t magic variable as const

[Robert Foss]

Mark magic member of gralloc_handle_t as const.

Signed-off-by: Robert Foss 
---
 android/gralloc_handle.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h
index 7cbc8ee7cef3..5d8a19ea0c2e 100644
--- a/android/gralloc_handle.h
+++ b/android/gralloc_handle.h
@@ -51,7 +51,7 @@ struct gralloc_handle_t {
int prime_fd;
 
/* api variables */
-   int magic; /* differentiate between allocator impls */
+   const int magic; /* differentiate between allocator impls */
const uint32_t version; /* api version */
 
int width; /* width of buffer in pixels */
-- 
2.14.1

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[Mesa-dev] [PATCH v3 4/6] android: Remove member name from gralloc_handle_t

[Robert Foss]

The name member of gralloc_handle_t is no longer needed and has been removed.
The version field has also been bumped.

Signed-off-by: Robert Foss 
---
 android/gralloc_handle.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h
index 5d8a19ea0c2e..9648b006c982 100644
--- a/android/gralloc_handle.h
+++ b/android/gralloc_handle.h
@@ -59,7 +59,6 @@ struct gralloc_handle_t {
int format; /* pixel format (Android) */
int usage; /* android libhardware usage flags */
 
-   int name;   /* the name of the bo */
int stride; /* the stride in bytes */
uint64_t modifier; /* buffer modifiers */
 
@@ -70,7 +69,7 @@ struct gralloc_handle_t {
} __attribute__((aligned(8)));
 };
 
-#define GRALLOC_HANDLE_VERSION 1
+#define GRALLOC_HANDLE_VERSION 2
 #define GRALLOC_HANDLE_MAGIC 0x60585350
 #define GRALLOC_HANDLE_NUM_FDS 1
 #define GRALLOC_HANDLE_NUM_INTS (  \
-- 
2.14.1

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[Mesa-dev] [PATCH v3 6/6] android: Change gralloc_handle_t members to be fixed width

[Robert Foss]

In order to lessen future alignment issues, lets switch to
fixed width integers where possible.

This excludes the data_owner since it is a pid_t which
in theory could be larger than 32 bits.

Signed-off-by: Robert Foss 
---
 android/gralloc_handle.h | 20 +++-
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h
index 60895a0a5255..caf64fe4114c 100644
--- a/android/gralloc_handle.h
+++ b/android/gralloc_handle.h
@@ -51,15 +51,15 @@ struct gralloc_handle_t {
int prime_fd;
 
/* api variables */
-   const int magic; /* differentiate between allocator impls */
+   const uint32_t magic; /* differentiate between allocator impls */
const uint32_t version; /* api version */
 
-   int width; /* width of buffer in pixels */
-   int height; /* height of buffer in pixels */
-   int format; /* pixel format (fourcc) */
-   int usage; /* android libhardware usage flags */
+   uint32_t width; /* width of buffer in pixels */
+   uint32_t height; /* height of buffer in pixels */
+   uint32_t format; /* pixel format (fourcc) */
+   uint32_t usage; /* android libhardware usage flags */
 
-   int stride; /* the stride in bytes */
+   uint32_t stride; /* the stride in bytes */
uint64_t modifier; /* buffer modifiers */
 
int data_owner; /* owner of data (for validation) */
@@ -69,7 +69,7 @@ struct gralloc_handle_t {
} __attribute__((aligned(8)));
 };
 
-#define GRALLOC_HANDLE_VERSION 3
+#define GRALLOC_HANDLE_VERSION 4
 #define GRALLOC_HANDLE_MAGIC 0x60585350
 #define GRALLOC_HANDLE_NUM_FDS 1
 #define GRALLOC_HANDLE_NUM_INTS (  \
@@ -79,8 +79,10 @@ struct gralloc_handle_t {
 /**
  * Create a buffer handle.
  */
-static struct gralloc_handle_t gralloc_handle_create(int width, int height,
- int format, int usage)
+static struct gralloc_handle_t gralloc_handle_create(int32_t width,
+ int32_t height,
+ int32_t format,
+ int32_t usage)
 {
struct alloc_handle_t handle = {
.magic = GRALLOC_HANDLE_MAGIC,
-- 
2.14.1

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[Mesa-dev] [PATCH v3 2/6] android: Add version variable to gralloc_handle_t

[Robert Foss]

The version variable will be used for versioning of this
struct and the corresponding accessor functions.

Signed-off-by: Robert Foss 
---
 android/gralloc_handle.h | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h
index 45b9f2e9b8dc..7cbc8ee7cef3 100644
--- a/android/gralloc_handle.h
+++ b/android/gralloc_handle.h
@@ -27,6 +27,7 @@
 #define __ANDROID_GRALLOC_HANDLE_H__
 
 #include 
+#include 
 
 /* support users of drm_gralloc/gbm_gralloc */
 #define gralloc_gbm_handle_t gralloc_handle_t
@@ -49,7 +50,9 @@ struct gralloc_handle_t {
 */
int prime_fd;
 
+   /* api variables */
int magic; /* differentiate between allocator impls */
+   const uint32_t version; /* api version */
 
int width; /* width of buffer in pixels */
int height; /* height of buffer in pixels */
@@ -67,6 +70,7 @@ struct gralloc_handle_t {
} __attribute__((aligned(8)));
 };
 
+#define GRALLOC_HANDLE_VERSION 1
 #define GRALLOC_HANDLE_MAGIC 0x60585350
 #define GRALLOC_HANDLE_NUM_FDS 1
 #define GRALLOC_HANDLE_NUM_INTS (  \
@@ -79,7 +83,9 @@ struct gralloc_handle_t {
 static struct gralloc_handle_t gralloc_handle_create(int width, int height,
  int format, int usage)
 {
-   struct gralloc_handle_t handle = { .magic = GRALLOC_HANDLE_MAGIC };
+   struct alloc_handle_t handle = {
+   .magic = GRALLOC_HANDLE_MAGIC,
+   .version = GRALLOC_HANDLE_VERSION };
 
native_handle_t *nhandle = native_handle_create(GRALLOC_HANDLE_NUM_FDS,

GRALLOC_HANDLE_NUM_INTS);
-- 
2.14.1

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[Mesa-dev] [PATCH v3 5/6] android: Change gralloc_handle_t format from Android format to fourcc

[Robert Foss]

Change the gralloc_handle_t format to signify the fourcc pixel format
code instead of the Android pixel format definition.

This is desirable since the fourcc code is what is used within the DRM
subsystem. Naturally translation will still have to happen somewhere.

Also bump the gralloc_handle_t version.

Sign-off-by: Robert Foss 
---
 android/gralloc_handle.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h
index 9648b006c982..60895a0a5255 100644
--- a/android/gralloc_handle.h
+++ b/android/gralloc_handle.h
@@ -56,7 +56,7 @@ struct gralloc_handle_t {
 
int width; /* width of buffer in pixels */
int height; /* height of buffer in pixels */
-   int format; /* pixel format (Android) */
+   int format; /* pixel format (fourcc) */
int usage; /* android libhardware usage flags */
 
int stride; /* the stride in bytes */
@@ -69,7 +69,7 @@ struct gralloc_handle_t {
} __attribute__((aligned(8)));
 };
 
-#define GRALLOC_HANDLE_VERSION 2
+#define GRALLOC_HANDLE_VERSION 3
 #define GRALLOC_HANDLE_MAGIC 0x60585350
 #define GRALLOC_HANDLE_NUM_FDS 1
 #define GRALLOC_HANDLE_NUM_INTS (  \
-- 
2.14.1

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Re: [Mesa-dev] [PATCH 5/8] drivers/radeon:add uvd hevc enc functions

[Boyuan Zhang]

On 2018-02-05 02:41 PM, James Zhu wrote:

Implement UVD hevc encode functions

Signed-off-by: James Zhu 
---
  src/gallium/drivers/radeon/radeon_uvd_enc.c | 340 
  1 file changed, 340 insertions(+)
  create mode 100644 src/gallium/drivers/radeon/radeon_uvd_enc.c

diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c 
b/src/gallium/drivers/radeon/radeon_uvd_enc.c
new file mode 100644
index 000..6eb6cda
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -0,0 +1,340 @@
+/**
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include 
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+#include "util/u_memory.h"
+
+#include "vl/vl_video_buffer.h"
+
+#include "radeonsi/si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_uvd_enc.h"
+
+static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc, struct 
pipe_h265_enc_picture_desc *picture)
+{
+  struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;


This line is unnecessary. Same type on both sides.


+  enc->enc_pic.picture_type = pic->picture_type;
+  enc->enc_pic.frame_num = pic->frame_num;
+  enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
+  enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
+  enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
+  enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
+  enc->enc_pic.not_referenced = pic->not_referenced;
+  enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_IDR) ||
+(pic->picture_type == 
PIPE_H265_ENC_PICTURE_TYPE_I);
+  enc->enc_pic.crop_left = 0;
+  enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) 
/ 2;
+  enc->enc_pic.crop_top = 0;
+  enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - 
enc->base.height) / 2;
+  enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
+  enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
+  enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
+  enc->enc_pic.max_poc = pic->seq.intra_period;
+  enc->enc_pic.log2_max_poc = 0;
+  for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
+ i = (i >> 1);
+  enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
+  enc->enc_pic.pic_width_in_luma_samples = 
pic->seq.pic_width_in_luma_samples;
+  enc->enc_pic.pic_height_in_luma_samples = 
pic->seq.pic_height_in_luma_samples;
+  enc->enc_pic.log2_diff_max_min_luma_coding_block_size = 
pic->seq.log2_diff_max_min_luma_coding_block_size;
+  enc->enc_pic.log2_min_transform_block_size_minus2 = 
pic->seq.log2_min_transform_block_size_minus2;
+  enc->enc_pic.log2_diff_max_min_transform_block_size = 
pic->seq.log2_diff_max_min_transform_block_size;
+  enc->enc_pic.max_transform_hierarchy_depth_inter = 
pic->seq.max_transform_hierarchy_depth_inter;
+  enc->enc_pic.max_transform_hierarchy_depth_intra = 
pic->seq.max_transform_hierarchy_depth_intra;
+  enc->enc_pic.log2_parallel_merge_level_minus2 = 
pic->pic.log2_parallel_merge_level_minus2;
+  enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
+  enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
+  enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
+  enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand;
+  enc->enc_pic.sample_adaptive_offset_enabled_flag = 
pic->seq.sample_adaptive_offset_enabled_flag;
+  enc->enc_pic.pcm_enabled_flag = pic->seq.pcm_enabled_flag;
+  

[Mesa-dev] [PATCH 2/2] mesa: minor whitespace fixes, line wrapping in texcompress.c

[Brian Paul]

---
 src/mesa/main/texcompress.c | 26 ++
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 1cc13a5..1c128e4 100644
--- a/src/mesa/main/texcompress.c
+++ b/src/mesa/main/texcompress.c
@@ -361,25 +361,26 @@ _mesa_get_compressed_formats(struct gl_context *ctx, 
GLint *formats)
 *"Interactions with OpenGL 4.2
 *
 *OpenGL 4.2 supports the feature that compressed textures can be
-*compressed online, by passing the compressed texture format enum 
as
-*the internal format when uploading a texture using TexImage1D,
+*compressed online, by passing the compressed texture format enum
+*as the internal format when uploading a texture using TexImage1D,
 *TexImage2D or TexImage3D (see Section 3.9.3, Texture Image
 *Specification, subsection Encoding of Special Internal Formats).
 *
-*Due to the complexity of the ASTC compression algorithm, it is not
-*usually suitable for online use, and therefore ASTC support will 
be
-*limited to pre-compressed textures only. Where on-device 
compression
-*is required, a domain-specific limited compressor will typically
-*be used, and this is therefore not suitable for implementation in
-*the driver.
+*Due to the complexity of the ASTC compression algorithm, it is
+*not usually suitable for online use, and therefore ASTC support
+*will be limited to pre-compressed textures only. Where on-device
+*compression is required, a domain-specific limited compressor
+*will typically be used, and this is therefore not suitable for
+*implementation in the driver.
 *
 *In particular, the ASTC format specifiers will not be added to
 *Table 3.14, and thus will not be accepted by the TexImage*D
 *functions, and will not be returned by the (already deprecated)
 *COMPRESSED_TEXTURE_FORMATS query."
 *
-* The ES and the desktop specs diverge here. In OpenGL ES, the 
COMPRESSED_TEXTURE_FORMATS
-* query returns the set of supported specific compressed formats.
+* The ES and the desktop specs diverge here. In OpenGL ES, the
+* COMPRESSED_TEXTURE_FORMATS query returns the set of supported specific
+* compressed formats.
 */
if (ctx->API == API_OPENGLES2 &&
ctx->Extensions.KHR_texture_compression_astc_ldr) {
@@ -642,7 +643,8 @@ _mesa_glenum_to_compressed_format(GLenum format)
  * internal format unchanged.
  */
 GLenum
-_mesa_compressed_format_to_glenum(struct gl_context *ctx, mesa_format 
mesaFormat)
+_mesa_compressed_format_to_glenum(struct gl_context *ctx,
+  mesa_format mesaFormat)
 {
switch (mesaFormat) {
case MESA_FORMAT_RGB_FXT1:
@@ -900,7 +902,7 @@ _mesa_decompress_image(mesa_format format, GLuint width, 
GLuint height,
   _mesa_problem(NULL, "Unexpected format in _mesa_decompress_image()");
   return;
}
- 
+
stride = srcRowStride * bh / bytes;
 
for (j = 0; j < height; j++) {
-- 
2.7.4

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[Mesa-dev] [PATCH 1/2] mesa: simplify _mesa_get_compressed_formats()

[Brian Paul]

Instead of testing for formats==NULL everywhere, just point formats at
a dummy array which will be discarded.
---
 src/mesa/main/texcompress.c | 200 ++--
 1 file changed, 83 insertions(+), 117 deletions(-)

diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 15970a7..1cc13a5 100644
--- a/src/mesa/main/texcompress.c
+++ b/src/mesa/main/texcompress.c
@@ -263,27 +263,23 @@ _mesa_gl_compressed_format_base_format(GLenum format)
 GLuint
 _mesa_get_compressed_formats(struct gl_context *ctx, GLint *formats)
 {
+   GLint discard_formats[100];
GLuint n = 0;
+
+   if (!formats) {
+  formats = discard_formats;
+   }
+
if (_mesa_is_desktop_gl(ctx) &&
ctx->Extensions.TDFX_texture_compression_FXT1) {
-  if (formats) {
- formats[n++] = GL_COMPRESSED_RGB_FXT1_3DFX;
- formats[n++] = GL_COMPRESSED_RGBA_FXT1_3DFX;
-  }
-  else {
- n += 2;
-  }
+  formats[n++] = GL_COMPRESSED_RGB_FXT1_3DFX;
+  formats[n++] = GL_COMPRESSED_RGBA_FXT1_3DFX;
}
 
if (ctx->Extensions.EXT_texture_compression_s3tc) {
-  if (formats) {
- formats[n++] = GL_COMPRESSED_RGB_S3TC_DXT1_EXT;
- formats[n++] = GL_COMPRESSED_RGBA_S3TC_DXT3_EXT;
- formats[n++] = GL_COMPRESSED_RGBA_S3TC_DXT5_EXT;
-  }
-  else {
- n += 3;
-  }
+  formats[n++] = GL_COMPRESSED_RGB_S3TC_DXT1_EXT;
+  formats[n++] = GL_COMPRESSED_RGBA_S3TC_DXT3_EXT;
+  formats[n++] = GL_COMPRESSED_RGBA_S3TC_DXT5_EXT;
 
   /* The ES and desktop GL specs diverge here.
*
@@ -315,11 +311,7 @@ _mesa_get_compressed_formats(struct gl_context *ctx, GLint 
*formats)
* Note that the addition is only to the OpenGL ES specification!
*/
   if (_mesa_is_gles(ctx)) {
- if (formats) {
-formats[n++] = GL_COMPRESSED_RGBA_S3TC_DXT1_EXT;
- } else {
-n += 1;
- }
+ formats[n++] = GL_COMPRESSED_RGBA_S3TC_DXT1_EXT;
   }
}
 
@@ -332,54 +324,36 @@ _mesa_get_compressed_formats(struct gl_context *ctx, 
GLint *formats)
 */
if (_mesa_is_gles(ctx)
&& ctx->Extensions.OES_compressed_ETC1_RGB8_texture) {
-  if (formats) {
- formats[n++] = GL_ETC1_RGB8_OES;
-  }
-  else {
- n += 1;
-  }
+  formats[n++] = GL_ETC1_RGB8_OES;
}
 
if (ctx->API == API_OPENGLES) {
-  if (formats) {
-formats[n++] = GL_PALETTE4_RGB8_OES;
-formats[n++] = GL_PALETTE4_RGBA8_OES;
-formats[n++] = GL_PALETTE4_R5_G6_B5_OES;
-formats[n++] = GL_PALETTE4_RGBA4_OES;
-formats[n++] = GL_PALETTE4_RGB5_A1_OES;
-formats[n++] = GL_PALETTE8_RGB8_OES;
-formats[n++] = GL_PALETTE8_RGBA8_OES;
-formats[n++] = GL_PALETTE8_R5_G6_B5_OES;
-formats[n++] = GL_PALETTE8_RGBA4_OES;
-formats[n++] = GL_PALETTE8_RGB5_A1_OES;
-  }
-  else {
-n += 10;
-  }
+  formats[n++] = GL_PALETTE4_RGB8_OES;
+  formats[n++] = GL_PALETTE4_RGBA8_OES;
+  formats[n++] = GL_PALETTE4_R5_G6_B5_OES;
+  formats[n++] = GL_PALETTE4_RGBA4_OES;
+  formats[n++] = GL_PALETTE4_RGB5_A1_OES;
+  formats[n++] = GL_PALETTE8_RGB8_OES;
+  formats[n++] = GL_PALETTE8_RGBA8_OES;
+  formats[n++] = GL_PALETTE8_R5_G6_B5_OES;
+  formats[n++] = GL_PALETTE8_RGBA4_OES;
+  formats[n++] = GL_PALETTE8_RGB5_A1_OES;
}
 
if (_mesa_is_gles3(ctx) || ctx->Extensions.ARB_ES3_compatibility) {
-  if (formats) {
- formats[n++] = GL_COMPRESSED_RGB8_ETC2;
- formats[n++] = GL_COMPRESSED_RGBA8_ETC2_EAC;
- formats[n++] = GL_COMPRESSED_R11_EAC;
- formats[n++] = GL_COMPRESSED_RG11_EAC;
- formats[n++] = GL_COMPRESSED_SIGNED_R11_EAC;
- formats[n++] = GL_COMPRESSED_SIGNED_RG11_EAC;
- formats[n++] = GL_COMPRESSED_RGB8_PUNCHTHROUGH_ALPHA1_ETC2;
-  } else {
- n += 7;
-  }
+  formats[n++] = GL_COMPRESSED_RGB8_ETC2;
+  formats[n++] = GL_COMPRESSED_RGBA8_ETC2_EAC;
+  formats[n++] = GL_COMPRESSED_R11_EAC;
+  formats[n++] = GL_COMPRESSED_RG11_EAC;
+  formats[n++] = GL_COMPRESSED_SIGNED_R11_EAC;
+  formats[n++] = GL_COMPRESSED_SIGNED_RG11_EAC;
+  formats[n++] = GL_COMPRESSED_RGB8_PUNCHTHROUGH_ALPHA1_ETC2;
}
 
if (_mesa_is_gles3(ctx)) {
-  if (formats) {
- formats[n++] = GL_COMPRESSED_SRGB8_ETC2;
- formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ETC2_EAC;
- formats[n++] = GL_COMPRESSED_SRGB8_PUNCHTHROUGH_ALPHA1_ETC2;
-  } else {
- n += 3;
-  }
+  formats[n++] = GL_COMPRESSED_SRGB8_ETC2;
+  formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ETC2_EAC;
+  formats[n++] = GL_COMPRESSED_SRGB8_PUNCHTHROUGH_ALPHA1_ETC2;
}
 
/* The KHR_texture_compression_astc_hdr spec says:
@@ -409,70 +383,62 @@ _mesa_get_compressed_formats(struct gl_context *ctx, 
GLint *formats)
 */
if (ctx->API == API_OPENGLES2 &&

Re: [Mesa-dev] [PATCH 1/2] mesa: simplify _mesa_get_compressed_formats()

[Eric Engestrom]

On Tuesday, 2018-02-06 09:59:32 -0700, Brian Paul wrote:
> Instead of testing for formats==NULL everywhere, just point formats at
> a dummy array which will be discarded.
> ---
>  src/mesa/main/texcompress.c | 200 
> ++--
>  1 file changed, 83 insertions(+), 117 deletions(-)
> 
> diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
> index 15970a7..1cc13a5 100644
> --- a/src/mesa/main/texcompress.c
> +++ b/src/mesa/main/texcompress.c
> @@ -263,27 +263,23 @@ _mesa_gl_compressed_format_base_format(GLenum format)
>  GLuint
>  _mesa_get_compressed_formats(struct gl_context *ctx, GLint *formats)
>  {
> +   GLint discard_formats[100];

Current max size is 75, so that's big enough.

> GLuint n = 0;
> +
> +   if (!formats) {
> +  formats = discard_formats;
> +   }
> +
> if (_mesa_is_desktop_gl(ctx) &&
> ctx->Extensions.TDFX_texture_compression_FXT1) {
> -  if (formats) {
> - formats[n++] = GL_COMPRESSED_RGB_FXT1_3DFX;
> - formats[n++] = GL_COMPRESSED_RGBA_FXT1_3DFX;
> -  }
> -  else {
> - n += 2;
> -  }
> +  formats[n++] = GL_COMPRESSED_RGB_FXT1_3DFX;
> +  formats[n++] = GL_COMPRESSED_RGBA_FXT1_3DFX;
> }
>  
> if (ctx->Extensions.EXT_texture_compression_s3tc) {
> -  if (formats) {
> - formats[n++] = GL_COMPRESSED_RGB_S3TC_DXT1_EXT;
> - formats[n++] = GL_COMPRESSED_RGBA_S3TC_DXT3_EXT;
> - formats[n++] = GL_COMPRESSED_RGBA_S3TC_DXT5_EXT;
> -  }
> -  else {
> - n += 3;
> -  }
> +  formats[n++] = GL_COMPRESSED_RGB_S3TC_DXT1_EXT;
> +  formats[n++] = GL_COMPRESSED_RGBA_S3TC_DXT3_EXT;
> +  formats[n++] = GL_COMPRESSED_RGBA_S3TC_DXT5_EXT;
>  
>/* The ES and desktop GL specs diverge here.
> *
> @@ -315,11 +311,7 @@ _mesa_get_compressed_formats(struct gl_context *ctx, 
> GLint *formats)
> * Note that the addition is only to the OpenGL ES specification!
> */
>if (_mesa_is_gles(ctx)) {
> - if (formats) {
> -formats[n++] = GL_COMPRESSED_RGBA_S3TC_DXT1_EXT;
> - } else {
> -n += 1;
> - }
> + formats[n++] = GL_COMPRESSED_RGBA_S3TC_DXT1_EXT;
>}
> }
>  
> @@ -332,54 +324,36 @@ _mesa_get_compressed_formats(struct gl_context *ctx, 
> GLint *formats)
>  */
> if (_mesa_is_gles(ctx)
> && ctx->Extensions.OES_compressed_ETC1_RGB8_texture) {
> -  if (formats) {
> - formats[n++] = GL_ETC1_RGB8_OES;
> -  }
> -  else {
> - n += 1;
> -  }
> +  formats[n++] = GL_ETC1_RGB8_OES;
> }
>  
> if (ctx->API == API_OPENGLES) {
> -  if (formats) {
> -  formats[n++] = GL_PALETTE4_RGB8_OES;
> -  formats[n++] = GL_PALETTE4_RGBA8_OES;
> -  formats[n++] = GL_PALETTE4_R5_G6_B5_OES;
> -  formats[n++] = GL_PALETTE4_RGBA4_OES;
> -  formats[n++] = GL_PALETTE4_RGB5_A1_OES;
> -  formats[n++] = GL_PALETTE8_RGB8_OES;
> -  formats[n++] = GL_PALETTE8_RGBA8_OES;
> -  formats[n++] = GL_PALETTE8_R5_G6_B5_OES;
> -  formats[n++] = GL_PALETTE8_RGBA4_OES;
> -  formats[n++] = GL_PALETTE8_RGB5_A1_OES;
> -  }
> -  else {
> -  n += 10;
> -  }
> +  formats[n++] = GL_PALETTE4_RGB8_OES;
> +  formats[n++] = GL_PALETTE4_RGBA8_OES;
> +  formats[n++] = GL_PALETTE4_R5_G6_B5_OES;
> +  formats[n++] = GL_PALETTE4_RGBA4_OES;
> +  formats[n++] = GL_PALETTE4_RGB5_A1_OES;
> +  formats[n++] = GL_PALETTE8_RGB8_OES;
> +  formats[n++] = GL_PALETTE8_RGBA8_OES;
> +  formats[n++] = GL_PALETTE8_R5_G6_B5_OES;
> +  formats[n++] = GL_PALETTE8_RGBA4_OES;
> +  formats[n++] = GL_PALETTE8_RGB5_A1_OES;
> }
>  
> if (_mesa_is_gles3(ctx) || ctx->Extensions.ARB_ES3_compatibility) {
> -  if (formats) {
> - formats[n++] = GL_COMPRESSED_RGB8_ETC2;
> - formats[n++] = GL_COMPRESSED_RGBA8_ETC2_EAC;
> - formats[n++] = GL_COMPRESSED_R11_EAC;
> - formats[n++] = GL_COMPRESSED_RG11_EAC;
> - formats[n++] = GL_COMPRESSED_SIGNED_R11_EAC;
> - formats[n++] = GL_COMPRESSED_SIGNED_RG11_EAC;
> - formats[n++] = GL_COMPRESSED_RGB8_PUNCHTHROUGH_ALPHA1_ETC2;
> -  } else {
> - n += 7;
> -  }
> +  formats[n++] = GL_COMPRESSED_RGB8_ETC2;
> +  formats[n++] = GL_COMPRESSED_RGBA8_ETC2_EAC;
> +  formats[n++] = GL_COMPRESSED_R11_EAC;
> +  formats[n++] = GL_COMPRESSED_RG11_EAC;
> +  formats[n++] = GL_COMPRESSED_SIGNED_R11_EAC;
> +  formats[n++] = GL_COMPRESSED_SIGNED_RG11_EAC;
> +  formats[n++] = GL_COMPRESSED_RGB8_PUNCHTHROUGH_ALPHA1_ETC2;
> }
>  
> if (_mesa_is_gles3(ctx)) {
> -  if (formats) {
> - formats[n++] = GL_COMPRESSED_SRGB8_ETC2;
> - formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ETC2_EAC;
> - formats[n++] = GL_COMPRESSED_SRGB8_PUNCHTHROUGH_ALPHA1_ETC2;
> -  } else {
> - n += 3;
> -  }
> +  formats[n++] = 

[Mesa-dev] [PATCH kmscube] drm-legacy: fix poll for flip event, actually exit on user input

[Ilia Mirkin]

The select fds have to be reinitialized before each call to select.

Signed-off-by: Ilia Mirkin 
---
 drm-legacy.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drm-legacy.c b/drm-legacy.c
index a0b419a..fd98a38 100644
--- a/drm-legacy.c
+++ b/drm-legacy.c
@@ -53,10 +53,6 @@ static int legacy_run(const struct gbm *gbm, const struct 
egl *egl)
uint32_t i = 0;
int ret;
 
-   FD_ZERO();
-   FD_SET(0, );
-   FD_SET(drm.fd, );
-
eglSwapBuffers(egl->display, egl->surface);
bo = gbm_surface_lock_front_buffer(gbm->surface);
fb = drm_fb_get_from_bo(bo);
@@ -100,6 +96,10 @@ static int legacy_run(const struct gbm *gbm, const struct 
egl *egl)
}
 
while (waiting_for_flip) {
+   FD_ZERO();
+   FD_SET(0, );
+   FD_SET(drm.fd, );
+
ret = select(drm.fd + 1, , NULL, NULL, NULL);
if (ret < 0) {
printf("select err: %s\n", strerror(errno));
@@ -109,7 +109,7 @@ static int legacy_run(const struct gbm *gbm, const struct 
egl *egl)
return -1;
} else if (FD_ISSET(0, )) {
printf("user interrupted!\n");
-   break;
+   return 0;
}
drmHandleEvent(drm.fd, );
}
-- 
2.13.6

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[Mesa-dev] [PATCH 2/2] u_blit, u_simple_shaders: add shader to convert from xrbias format

[sroland]

From: Roland Scheidegger 

We need this to handle some oddball dx10 format
(DXGI_FORMAT_R10G10B10_XR_BIAS_A2_UNORM). What you can do with this
format is very limited, hence we don't want to add it as a gallium
format (we could not express the properties of this format as
ordinary format properties neither, so like all special formats
it would need specific code for handling it in any case).
While here, also nuke the array for different shaders for different
writemasks, as it was not actually used (always full masks are
passed in for generating shaders).
---
 src/gallium/auxiliary/util/u_blit.c   | 40 +-
 src/gallium/auxiliary/util/u_blit.h   |  3 +-
 src/gallium/auxiliary/util/u_simple_shaders.c | 48 +++
 src/gallium/auxiliary/util/u_simple_shaders.h |  4 +++
 4 files changed, 79 insertions(+), 16 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_blit.c 
b/src/gallium/auxiliary/util/u_blit.c
index 3f92476..bf1dea7 100644
--- a/src/gallium/auxiliary/util/u_blit.c
+++ b/src/gallium/auxiliary/util/u_blit.c
@@ -65,7 +65,7 @@ struct blit_state
struct pipe_vertex_element velem[2];
 
void *vs;
-   void *fs[PIPE_MAX_TEXTURE_TYPES][TGSI_WRITEMASK_XYZW + 1][3];
+   void *fs[PIPE_MAX_TEXTURE_TYPES][4];
 
struct pipe_resource *vbuf;  /**< quad vertices */
unsigned vbuf_slot;
@@ -135,17 +135,15 @@ void
 util_destroy_blit(struct blit_state *ctx)
 {
struct pipe_context *pipe = ctx->pipe;
-   unsigned i, j, k;
+   unsigned i, j;
 
if (ctx->vs)
   pipe->delete_vs_state(pipe, ctx->vs);
 
for (i = 0; i < ARRAY_SIZE(ctx->fs); i++) {
   for (j = 0; j < ARRAY_SIZE(ctx->fs[i]); j++) {
- for (k = 0; k < ARRAY_SIZE(ctx->fs[i][j]); k++) {
-if (ctx->fs[i][j][k])
-   pipe->delete_fs_state(pipe, ctx->fs[i][j][k]);
- }
+ if (ctx->fs[i][j])
+pipe->delete_fs_state(pipe, ctx->fs[i][j]);
   }
}
 
@@ -159,8 +157,9 @@ util_destroy_blit(struct blit_state *ctx)
  * Helper function to set the fragment shaders.
  */
 static inline void
-set_fragment_shader(struct blit_state *ctx, uint writemask,
+set_fragment_shader(struct blit_state *ctx,
 enum pipe_format format,
+boolean src_xrbias,
 enum pipe_texture_target pipe_tex)
 {
enum tgsi_return_type stype;
@@ -177,19 +176,29 @@ set_fragment_shader(struct blit_state *ctx, uint 
writemask,
   idx = 2;
}
 
-   if (!ctx->fs[pipe_tex][writemask][idx]) {
+   if (src_xrbias) {
+  assert(stype == TGSI_RETURN_TYPE_FLOAT);
+  idx = 3;
+  if (!ctx->fs[pipe_tex][idx]) {
+ unsigned tgsi_tex = util_pipe_tex_to_tgsi_tex(pipe_tex, 0);
+ ctx->fs[pipe_tex][idx] =
+util_make_fragment_tex_shader_xrbias(ctx->pipe, tgsi_tex);
+  }
+   }
+
+   else if (!ctx->fs[pipe_tex][idx]) {
   unsigned tgsi_tex = util_pipe_tex_to_tgsi_tex(pipe_tex, 0);
 
   /* OpenGL does not allow blits from signed to unsigned integer
* or vice versa. */
-  ctx->fs[pipe_tex][writemask][idx] =
+  ctx->fs[pipe_tex][idx] =
  util_make_fragment_tex_shader_writemask(ctx->pipe, tgsi_tex,
  TGSI_INTERPOLATE_LINEAR,
- writemask,
+ TGSI_WRITEMASK_XYZW,
  stype, stype, false, false);
}
 
-   cso_set_fragment_shader_handle(ctx->cso, ctx->fs[pipe_tex][writemask][idx]);
+   cso_set_fragment_shader_handle(ctx->cso, ctx->fs[pipe_tex][idx]);
 }
 
 
@@ -491,8 +500,8 @@ util_blit_pixels(struct blit_state *ctx,
  * The sampler view's first_layer indicate the layer to use, but for
  * cube maps it must point to the first face.  Face is passed in src_face.
  *
- * The main advantage over util_blit_pixels is that it allows to specify 
swizzles in
- * pipe_sampler_view::swizzle_?.
+ * The main advantage over util_blit_pixels is that it allows to specify
+ * swizzles in pipe_sampler_view::swizzle_?.
  *
  * But there is no control over blitting Z and/or stencil.
  */
@@ -505,7 +514,8 @@ util_blit_pixels_tex(struct blit_state *ctx,
  struct pipe_surface *dst,
  int dstX0, int dstY0,
  int dstX1, int dstY1,
- float z, uint filter)
+ float z, uint filter,
+ boolean src_xrbias)
 {
boolean normalized = src_sampler_view->texture->target != PIPE_TEXTURE_RECT;
struct pipe_framebuffer_state fb;
@@ -593,7 +603,7 @@ util_blit_pixels_tex(struct blit_state *ctx,
cso_set_sampler_views(ctx->cso, PIPE_SHADER_FRAGMENT, 1, _sampler_view);
 
/* shaders */
-   set_fragment_shader(ctx, TGSI_WRITEMASK_XYZW,
+   set_fragment_shader(ctx, src_xrbias,
src_sampler_view->format,

[Mesa-dev] [PATCH 1/2] u_simple_shaders: fix mask handling in util_make_fragment_tex_shader_writemask

[sroland]

From: Roland Scheidegger 

The writemask handling was busted, since writing defaults to output
meant they got overwritten by the tex sampling anyway. Albeit the
affected components were undefined, so maybe with some luck it
still would have worked with some drivers - if not could as well
kill it... (This would have affected u_blitter but not u_blit since
the latter always used xyzw mask.)
---
 src/gallium/auxiliary/util/u_simple_shaders.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/util/u_simple_shaders.c 
b/src/gallium/auxiliary/util/u_simple_shaders.c
index 9679545..a301c05 100644
--- a/src/gallium/auxiliary/util/u_simple_shaders.c
+++ b/src/gallium/auxiliary/util/u_simple_shaders.c
@@ -275,7 +275,7 @@ util_make_fragment_tex_shader_writemask(struct pipe_context 
*pipe,
if (writemask != TGSI_WRITEMASK_XYZW) {
   struct ureg_src imm = ureg_imm4f( ureg, 0, 0, 0, 1 );
 
-  ureg_MOV( ureg, out, imm );
+  ureg_MOV(ureg, temp, imm);
}
 
if (tex_target == TGSI_TEXTURE_BUFFER)
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] intel/isl: Add assertion for aux surface pitch

[Anuj Phogat]

On Tue, Feb 6, 2018 at 4:22 PM, Nanley Chery  wrote:

> On Mon, Feb 05, 2018 at 04:07:19PM -0800, Anuj Phogat wrote:
> > I don't have a test case hitting this assert. But, it's nice to have
> > an assert checking the limit.
> >
> > Signed-off-by: Anuj Phogat 
> > ---
> >  src/intel/isl/isl_surface_state.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/src/intel/isl/isl_surface_state.c
> b/src/intel/isl/isl_surface_state.c
> > index bfb27fa4a4..afd4b80ddb 100644
> > --- a/src/intel/isl/isl_surface_state.c
> > +++ b/src/intel/isl/isl_surface_state.c
> > @@ -566,6 +566,8 @@ isl_genX(surf_fill_state_s)(const struct isl_device
> *dev, void *state,
> >s.AuxiliarySurfaceBaseAddress = info->aux_address;
> >s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
> >
> > +  assert(s.AuxiliarySurfacePitch <= 511);
> > +
>
> genxml already performs this assertion for us, see:
> __gen_uint(values->AuxiliarySurfacePitch, 3, 11)
>
​
right​. I'll drop this patch.



>
>
> >  #if GEN_GEN >= 8
> >assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
> >/* Auxiliary surfaces in ISL have compressed formats but the
> hardware
> > --
> > 2.13.6
> >
> > ___
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> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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Re: [Mesa-dev] [PATCH v3 20/24] anv/cmd_buffer: Rework aux tracking

[Nanley Chery]

On Mon, Feb 05, 2018 at 06:16:26PM -0800, Jason Ekstrand wrote:
> This commit completely reworks aux tracking.  This includes a number of
> somewhat distinct changes:
> 
>  1) Since we are no longer fast-clearing multiple slices, we only need
> to track one fast clear color and one fast clear type.
> 
>  2) We store two bits for fast clear instead of one to let us
> distinguish between zero and non-zero fast clear colors.  This is
> needed so that we can do full resolves when transitioning to
> PRESENT_SRC_KHR with gen9 CCS images where we allow zero clear
> values in all sorts of places we wouldn't normally.
> 
>  3) We now track compression state as a boolean separate from fast clear
> type and this is tracked on a per-slice granularity.
> 
> The previous scheme had some issues when it came to individual slices of
> a multi-LOD images.  In particular, we only tracked "needs resolve"
> per-LOD but you could do a vkCmdPipelineBarrier that would only resolve
> a portion of the image and would set "needs resolve" to false anyway.
> Also, any transition from an undefined layout would reset the clear
> color for the entire LOD regardless of whether or not there was some
> clear color on some other slice.
> 
> As far as full/partial resolves go, he assumptions of the previous
> scheme held because the one case where we do need a full resolve when
> CCS_E is enabled is for window-system images.  Since we only ever
> allowed X-tiled window-system images, CCS was entirely disabled on gen9+
> and we never got CCS_E.  With the advent of Y-tiled window-system
> buffers, we now need to properly support doing a full resolve of images
> marked CCS_E.
> 
> v2 (Jason Ekstrand):
>  - Fix an bug in the compressed flag offset calculation
>  - Treat 3D images as multi-slice for the purposes of resolve tracking
> 
> Reviewed-by: Topi Pohjolainen 
> ---
>  src/intel/vulkan/anv_blorp.c   |   3 +-
>  src/intel/vulkan/anv_image.c   | 100 ++-
>  src/intel/vulkan/anv_private.h |  60 ---
>  src/intel/vulkan/genX_cmd_buffer.c | 340 
> +++--
>  4 files changed, 345 insertions(+), 158 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> index 497ae6f..fc3b717 100644
> --- a/src/intel/vulkan/anv_blorp.c
> +++ b/src/intel/vulkan/anv_blorp.c
> @@ -1758,8 +1758,7 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
> * particular value and don't care about format or clear value.
> */
>const struct anv_address clear_color_addr =
> - anv_image_get_clear_color_addr(cmd_buffer->device, image,
> -aspect, level);
> + anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
>surf.clear_color_addr = anv_to_blorp_address(clear_color_addr);
> }
>  
> diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
> index 11942d0..011e952 100644
> --- a/src/intel/vulkan/anv_image.c
> +++ b/src/intel/vulkan/anv_image.c
> @@ -190,46 +190,54 @@ all_formats_ccs_e_compatible(const struct 
> gen_device_info *devinfo,
>   * fast-clear values in non-trivial cases (e.g., outside of a render pass in
>   * which a fast clear has occurred).
>   *
> - * For the purpose of discoverability, the algorithm used to manage this 
> buffer
> - * is described here. A clear value in this buffer is updated when a fast 
> clear
> - * is performed on a subresource. One of two synchronization operations is
> - * performed in order for a following memory access to use the fast-clear
> - * value:
> - *a. Copy the value from the buffer to the surface state object used for
> - *   reading. This is done implicitly when the value is the clear value
> - *   predetermined to be the default in other surface state objects. This
> - *   is currently only done explicitly for the operation below.
> - *b. Do (a) and use the surface state object to resolve the subresource.
> - *   This is only done during layout transitions for decent performance.
> + * In order to avoid having multiple clear colors for a single plane of an
> + * image (hence a single RENDER_SURFACE_STATE), we only allow fast-clears on
> + * the first slice (level 0, layer 0).  At the time of our testing (Jan 17,
> + * 2018), there were no known applications which would benefit from fast-
> + * clearing more than just the first slice.
>   *
> - * With the above scheme, we can fast-clear whenever the hardware allows 
> except
> - * for two cases in which synchronization becomes impossible or undesirable:
> - ** The subresource is in the GENERAL layout and is cleared to a value
> - *  other than the special default value.
> + * The fast clear portion of the image is laid out in the following order:
>   *
> - *  Performing a synchronization operation in order to read from the
> - *  subresource is undesirable in this case. Firstly, 

[Mesa-dev] [PATCH 1/2] intel/compiler: Memory fence commit must always be enabled for gen10+

[Anuj Phogat]

Commit bit in the message descriptor (Bit 13) must be always set
to true in CNL+ for memory fence messages. It also fixes a piglit
GPU hang on cnl+ in simulation environment.
Piglit test: arb_shader_image_load_store-shader-mem-barrier
See HSD ES # 1404612949

Signed-off-by: Anuj Phogat 
Cc: mesa-sta...@lists.freedesktop.org
---
 src/intel/compiler/brw_eu_emit.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index c25d8d6eda..1fb9aab51c 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3275,7 +3275,9 @@ brw_memory_fence(struct brw_codegen *p,
  struct brw_reg dst)
 {
const struct gen_device_info *devinfo = p->devinfo;
-   const bool commit_enable = devinfo->gen == 7 && !devinfo->is_haswell;
+   const bool commit_enable =
+  devinfo->gen >= 10 || /* HSD ES # 1404612949 */
+  (devinfo->gen == 7 && !devinfo->is_haswell);
struct brw_inst *insn;
 
brw_push_insn_state(p);
-- 
2.13.6

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[Mesa-dev] [PATCH 2/2] intel/compiler: Use null destination register for memory fence messages

[Anuj Phogat]

From Message Descriptor section in gfxspecs:
 "Memory fence messages without Commit Enable set do not return
  anything to the thread (response length is 0 and destination
  register is null)."

It fixes a piglit GPU hang in simulation environment.
Piglit test: arb_shader_image_load_store-shader-mem-barrier

Signed-off-by: Anuj Phogat 
Cc: mesa-sta...@lists.freedesktop.org
---
 src/intel/compiler/brw_eu_emit.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 1fb9aab51c..c66b813af8 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3290,7 +3290,13 @@ brw_memory_fence(struct brw_codegen *p,
 */
insn = next_insn(p, BRW_OPCODE_SEND);
dst = retype(dst, BRW_REGISTER_TYPE_UW);
-   brw_set_dest(p, insn, dst);
+
+  /* From Message Descriptor section in gfxspecs:
+"Memory fence messages without Commit Enable set do not return
+ anything to the thread (response length is 0 and destination
+ register is null).
+   */
+   brw_set_dest(p, insn, retype(vec1(brw_null_reg()), BRW_REGISTER_TYPE_UW));
brw_set_src0(p, insn, dst);
brw_set_memory_fence_message(p, insn, GEN7_SFID_DATAPORT_DATA_CACHE,
 commit_enable);
-- 
2.13.6

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Re: [Mesa-dev] [PATCH 11/11] r600/radeonsi/clover: always assume PIPE_SHADER_IR_NATIVE for clover

[Jan Vesely]

On Fri, 2018-02-02 at 10:22 +0100, Pierre Moreau wrote:
> On 2018-02-02 — 18:07, Timothy Arceri wrote:
> > 
> > 
> > On 02/02/18 17:21, Timothy Arceri wrote:
> > > On 02/02/18 16:38, Jan Vesely wrote:
> > > > On Fri, 2018-02-02 at 15:03 +1100, Timothy Arceri wrote:
> > > > > When PIPE_SHADER_IR_LLVM existed this query made sense but now it
> > > > > always returns PIPE_SHADER_IR_NATIVE. Also it is now conlicting
> > > > > with PIPE_SHADER_IR_NIR for compute shaders, so just assume this
> > > > > is always PIPE_SHADER_IR_NATIVE for clover.
> > > > > 
> > > > > This change indirectly enables NIR support for compute shaders
> > > > > on radeonsi.
> > > > > ---
> > > > >   src/gallium/drivers/r600/r600_pipe.c  | 6 +-
> > > > >   src/gallium/drivers/radeonsi/si_get.c | 3 ---
> > > > >   src/gallium/state_trackers/clover/core/device.cpp | 3 +--
> > > > >   3 files changed, 2 insertions(+), 10 deletions(-)
> > > > > 
> > > > > diff --git a/src/gallium/drivers/r600/r600_pipe.c
> > > > > b/src/gallium/drivers/r600/r600_pipe.c
> > > > > index 6c021e568d..287fe497ca 100644
> > > > > --- a/src/gallium/drivers/r600/r600_pipe.c
> > > > > +++ b/src/gallium/drivers/r600/r600_pipe.c
> > > > > @@ -595,11 +595,7 @@ static int r600_get_shader_param(struct
> > > > > pipe_screen* pscreen,
> > > > >   case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
> > > > >   return 16;
> > > > >   case PIPE_SHADER_CAP_PREFERRED_IR:
> > > > > -if (shader == PIPE_SHADER_COMPUTE) {
> > > > > -return PIPE_SHADER_IR_NATIVE;
> > > > > -} else {
> > > > > -return PIPE_SHADER_IR_TGSI;
> > > > > -}
> > > > > +return PIPE_SHADER_IR_TGSI;
> > > > >   case PIPE_SHADER_CAP_SUPPORTED_IRS:
> > > > >   if (rscreen->b.family >= CHIP_CEDAR)
> > > > >   return (1 << PIPE_SHADER_IR_TGSI);
> > > > > diff --git a/src/gallium/drivers/radeonsi/si_get.c
> > > > > b/src/gallium/drivers/radeonsi/si_get.c
> > > > > index 40f4cc267e..46cc190db1 100644
> > > > > --- a/src/gallium/drivers/radeonsi/si_get.c
> > > > > +++ b/src/gallium/drivers/radeonsi/si_get.c
> > > > > @@ -391,9 +391,6 @@ static int si_get_shader_param(struct
> > > > > pipe_screen* pscreen,
> > > > >   break;
> > > > >   case PIPE_SHADER_COMPUTE:
> > > > >   switch (param) {
> > > > > -case PIPE_SHADER_CAP_PREFERRED_IR:
> > > > > -return PIPE_SHADER_IR_NATIVE;
> > > > > -
> > > > >   case PIPE_SHADER_CAP_SUPPORTED_IRS: {
> > > > >   int ir = 1 << PIPE_SHADER_IR_NATIVE;
> > > > > diff --git a/src/gallium/state_trackers/clover/core/device.cpp
> > > > > b/src/gallium/state_trackers/clover/core/device.cpp
> > > > > index 9dd7eed3f1..116f0c7604 100644
> > > > > --- a/src/gallium/state_trackers/clover/core/device.cpp
> > > > > +++ b/src/gallium/state_trackers/clover/core/device.cpp
> > > > > @@ -243,8 +243,7 @@ device::vendor_name() const {
> > > > >   enum pipe_shader_ir
> > > > >   device::ir_format() const {
> > > > > -   return (enum pipe_shader_ir) pipe->get_shader_param(
> > > > > -  pipe, PIPE_SHADER_COMPUTE, PIPE_SHADER_CAP_PREFERRED_IR);
> > > > > +   return PIPE_SHADER_IR_NATIVE;
> > > > 
> > > > This looks like it forces IR_NATIVE for absolutely everybody. Why
> > > > should other devices use IR_NATIVE just because radeonsi wants
> > > > experimental NIR for GL?
> > > 
> > > It's not just about experimental NIR. If say freedreno or any other nir
> > > driver was to use clover they would have the same problem.
> > 
> > Well it would be return PIPE_SHADER_IR_NIR here at least.
> > 
> > > Also I'm 99% certain that no drivers other than radeonsi and r600 even
> > > care what this value is. All other drivers have this set to 
> > > PIPE_SHADER_IR_TGSI does that make anymore sense?
> > 
> > I see no there is indeed a tgsi path for clover. I guess maybe this change
> > has more impact than I first thought.
> 
> I’ll be removing the tgsi path for clover in my v3 for adding SPIR-V support
> series for clover, as that path is unused.
> 
> > Happy to here suggestions for solving the current conflict in uses of
> > PIPE_SHADER_CAP_PREFERRED_IR.
> 
> One option could be to:
> * look at the preferred IR
>   |-> if clover supports it, use it
>   |-> else, check if any IR supported by clover are supported by the driver,
>   and pick the first one that works
> 
> Also, clover will be switching (experimentally first) to using SPIR-V as the
> canonical IR, for all the compiling and linking internally, before translating
> the resulting executable to a representation the driver can handle.

Why? what is this good for? Is the expected path for radeonsi:
 clc->llvm->spirv->nir->llvm->isa, or clc->llvm->spirv->llvm->isa ?

What advantages does it bring to any target? why can't the targets that
are not natively supported by llvm just consume llvm IR and do the
necessary translations on driver side?


> So once
> spirv_to_nir supports OpenCL 

Re: [Mesa-dev] [PATCH v3 20/24] anv/cmd_buffer: Rework aux tracking

[Jason Ekstrand]

On Tue, Feb 6, 2018 at 5:09 PM, Nanley Chery  wrote:

> On Mon, Feb 05, 2018 at 06:16:26PM -0800, Jason Ekstrand wrote:
> > This commit completely reworks aux tracking.  This includes a number of
> > somewhat distinct changes:
> >
> >  1) Since we are no longer fast-clearing multiple slices, we only need
> > to track one fast clear color and one fast clear type.
> >
> >  2) We store two bits for fast clear instead of one to let us
> > distinguish between zero and non-zero fast clear colors.  This is
> > needed so that we can do full resolves when transitioning to
> > PRESENT_SRC_KHR with gen9 CCS images where we allow zero clear
> > values in all sorts of places we wouldn't normally.
> >
> >  3) We now track compression state as a boolean separate from fast clear
> > type and this is tracked on a per-slice granularity.
> >
> > The previous scheme had some issues when it came to individual slices of
> > a multi-LOD images.  In particular, we only tracked "needs resolve"
> > per-LOD but you could do a vkCmdPipelineBarrier that would only resolve
> > a portion of the image and would set "needs resolve" to false anyway.
> > Also, any transition from an undefined layout would reset the clear
> > color for the entire LOD regardless of whether or not there was some
> > clear color on some other slice.
> >
> > As far as full/partial resolves go, he assumptions of the previous
> > scheme held because the one case where we do need a full resolve when
> > CCS_E is enabled is for window-system images.  Since we only ever
> > allowed X-tiled window-system images, CCS was entirely disabled on gen9+
> > and we never got CCS_E.  With the advent of Y-tiled window-system
> > buffers, we now need to properly support doing a full resolve of images
> > marked CCS_E.
> >
> > v2 (Jason Ekstrand):
> >  - Fix an bug in the compressed flag offset calculation
> >  - Treat 3D images as multi-slice for the purposes of resolve tracking
> >
> > Reviewed-by: Topi Pohjolainen 
> > ---
> >  src/intel/vulkan/anv_blorp.c   |   3 +-
> >  src/intel/vulkan/anv_image.c   | 100 ++-
> >  src/intel/vulkan/anv_private.h |  60 ---
> >  src/intel/vulkan/genX_cmd_buffer.c | 340 +++---
> ---
> >  4 files changed, 345 insertions(+), 158 deletions(-)
> >
> > diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> > index 497ae6f..fc3b717 100644
> > --- a/src/intel/vulkan/anv_blorp.c
> > +++ b/src/intel/vulkan/anv_blorp.c
> > @@ -1758,8 +1758,7 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
> > * particular value and don't care about format or clear value.
> > */
> >const struct anv_address clear_color_addr =
> > - anv_image_get_clear_color_addr(cmd_buffer->device, image,
> > -aspect, level);
> > + anv_image_get_clear_color_addr(cmd_buffer->device, image,
> aspect);
> >surf.clear_color_addr = anv_to_blorp_address(clear_color_addr);
> > }
> >
> > diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
> > index 11942d0..011e952 100644
> > --- a/src/intel/vulkan/anv_image.c
> > +++ b/src/intel/vulkan/anv_image.c
> > @@ -190,46 +190,54 @@ all_formats_ccs_e_compatible(const struct
> gen_device_info *devinfo,
> >   * fast-clear values in non-trivial cases (e.g., outside of a render
> pass in
> >   * which a fast clear has occurred).
> >   *
> > - * For the purpose of discoverability, the algorithm used to manage
> this buffer
> > - * is described here. A clear value in this buffer is updated when a
> fast clear
> > - * is performed on a subresource. One of two synchronization operations
> is
> > - * performed in order for a following memory access to use the
> fast-clear
> > - * value:
> > - *a. Copy the value from the buffer to the surface state object
> used for
> > - *   reading. This is done implicitly when the value is the clear
> value
> > - *   predetermined to be the default in other surface state
> objects. This
> > - *   is currently only done explicitly for the operation below.
> > - *b. Do (a) and use the surface state object to resolve the
> subresource.
> > - *   This is only done during layout transitions for decent
> performance.
> > + * In order to avoid having multiple clear colors for a single plane of
> an
> > + * image (hence a single RENDER_SURFACE_STATE), we only allow
> fast-clears on
> > + * the first slice (level 0, layer 0).  At the time of our testing (Jan
> 17,
> > + * 2018), there were no known applications which would benefit from
> fast-
> > + * clearing more than just the first slice.
> >   *
> > - * With the above scheme, we can fast-clear whenever the hardware
> allows except
> > - * for two cases in which synchronization becomes impossible or
> undesirable:
> > - ** The subresource is in the GENERAL layout and is cleared to a
> value
> > - 

[Mesa-dev] [Bug 104983] current version, warning during make process in glsl

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104983

Bug ID: 104983
   Summary: current version, warning during make process in glsl
   Product: Mesa
   Version: unspecified
  Hardware: ARM
OS: Linux (All)
Status: NEW
  Severity: minor
  Priority: medium
 Component: glsl-compiler
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: randy.rans...@gmail.com
QA Contact: intel-3d-b...@lists.freedesktop.org

during a make, there is a warning while entering the .../mesa/src/compiler
directory:

glsl/glsl_lexer.cpp:  In function 'int yy_get_next_buffer(yyscan_t)';
glsl/glsl_lexer.cpp:3488:47 warning: comparison between signed and unsigned
integer expressions [-Wsign-compare]
  if ((int) (yyg->yy_n_chars + number_to_move) >
YY_CURRENT_BUFFER_LVALUE->yy_buf_size) {


(it's probably more my bug, i tried to not get any intel stuff in my libraries
at all, and i think glsl is an intel thing; it's not a feature i plan on using)

the make finished fine, it was only a warning
i just want mesa3d to only get better, and better, and better... :)
anyways, my autogen command was as follows, which is probably why i was making
glsl even though i don't think i need it:

 ./autogen.sh --prefix=/usr --libdir=/usr/lib/arm-linux-gnueabihf
--with-gallium-drivers="vc4,swrast" --sysconfdir=/etc
--with-platforms="drm,x11,wayland" --with-dri-drivers="swrast"

(if i didnt specify --with-dri-drivers=(something) it tried to load intel stuff
on me)

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[Mesa-dev] [PATCH 5/6] st/mesa: use tgsi_semantic enum type

[Brian Paul]

---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 10 ++
 src/mesa/state_tracker/st_glsl_to_tgsi.h   |  3 ++-
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 5e1674c..39a81fa 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -5456,7 +5456,7 @@ struct st_translate {
 };
 
 /** Map Mesa's SYSTEM_VALUE_x to TGSI_SEMANTIC_x */
-unsigned
+enum tgsi_semantic
 _mesa_sysval_to_semantic(unsigned sysval)
 {
switch (sysval) {
@@ -6379,7 +6379,8 @@ st_translate_program(
  }
 
  src = ureg_DECL_fs_input_cyl_centroid_layout(ureg,
-  inputSemanticName[slot], inputSemanticIndex[slot],
+  (enum tgsi_semantic) inputSemanticName[slot],
+  inputSemanticIndex[slot],
   interp_mode, 0, interp_location, slot, tgsi_usage_mask,
   decl->array_id, decl->size);
 
@@ -6433,7 +6434,8 @@ st_translate_program(
  }
 
  dst = ureg_DECL_output_layout(ureg,
- outputSemanticName[slot], outputSemanticIndex[slot],
+ (enum tgsi_semantic) outputSemanticName[slot],
+ outputSemanticIndex[slot],
  decl->gs_out_streams,
  slot, tgsi_usage_mask, decl->array_id, decl->size);
 
@@ -6535,7 +6537,7 @@ st_translate_program(
 
   for (i = 0; sysInputs; i++) {
  if (sysInputs & (1 << i)) {
-unsigned semName = _mesa_sysval_to_semantic(i);
+enum tgsi_semantic semName = _mesa_sysval_to_semantic(i);
 
 t->systemValues[i] = ureg_DECL_system_value(ureg, semName, 0);
 
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.h 
b/src/mesa/state_tracker/st_glsl_to_tgsi.h
index 37dfdb3..f38d41d 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.h
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.h
@@ -23,6 +23,7 @@
  */
 
 #include "pipe/p_defines.h"
+#include "pipe/p_shader_tokens.h"
 #include "main/mtypes.h"
 
 #ifdef __cplusplus
@@ -66,7 +67,7 @@ st_translate_stream_output_info2(struct 
gl_transform_feedback_info *info,
 const ubyte outputMapping[],
 struct pipe_stream_output_info *so);
 
-unsigned
+enum tgsi_semantic
 _mesa_sysval_to_semantic(unsigned sysval);
 
 #ifdef __cplusplus
-- 
2.7.4

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[Mesa-dev] [PATCH 3/6] st/mesa: use TGSI enum types in st_glsl_to_tgsi.cpp

[Brian Paul]

---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index c92b1d9..5e1674c 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -191,7 +191,7 @@ public:
glsl_base_type sampler_types[PIPE_MAX_SAMPLERS];
enum tgsi_texture_type sampler_targets[PIPE_MAX_SAMPLERS];
int images_used;
-   int image_targets[PIPE_MAX_SHADER_IMAGES];
+   enum tgsi_texture_type image_targets[PIPE_MAX_SHADER_IMAGES];
enum pipe_format image_formats[PIPE_MAX_SHADER_IMAGES];
bool indirect_addr_consts;
int wpos_transform_const;
@@ -5863,7 +5863,7 @@ compile_tgsi_instruction(struct st_translate *t,
 
int num_dst;
int num_src;
-   unsigned tex_target = 0;
+   enum tgsi_texture_type tex_target;
 
num_dst = num_inst_dst_regs(inst);
num_src = num_inst_src_regs(inst);
@@ -6249,7 +6249,7 @@ sort_inout_decls_by_slot(struct inout_decl *decls,
std::sort(decls, decls + count, sorter);
 }
 
-static unsigned
+static enum tgsi_interpolate_mode
 st_translate_interp(enum glsl_interp_mode glsl_qual, GLuint varying)
 {
switch (glsl_qual) {
@@ -6367,15 +6367,15 @@ st_translate_program(
tgsi_usage_mask = TGSI_WRITEMASK_XYZW;
  }
 
- unsigned interp_mode = 0;
- unsigned interp_location = 0;
+ enum tgsi_interpolate_mode interp_mode = TGSI_INTERPOLATE_CONSTANT;
+ enum tgsi_interpolate_loc interp_location = 
TGSI_INTERPOLATE_LOC_CENTER;
  if (procType == PIPE_SHADER_FRAGMENT) {
 assert(interpMode);
 interp_mode = interpMode[slot] != TGSI_INTERPOLATE_COUNT ?
-   interpMode[slot] :
+   (enum tgsi_interpolate_mode) interpMode[slot] :
st_translate_interp(decl->interp, inputSlotToAttr[slot]);
 
-interp_location = decl->interp_loc;
+interp_location = (enum tgsi_interpolate_loc) decl->interp_loc;
  }
 
  src = ureg_DECL_fs_input_cyl_centroid_layout(ureg,
-- 
2.7.4

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[Mesa-dev] [PATCH 6/6] tgsi: use tgsi_semantic enum type in ureg code

[Brian Paul]

---
 src/gallium/auxiliary/tgsi/tgsi_ureg.c | 24 
 src/gallium/auxiliary/tgsi/tgsi_ureg.h | 22 +++---
 2 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c 
b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
index 58908ae..fefcc68 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
@@ -112,7 +112,7 @@ struct ureg_program
int next_shader_processor;
 
struct {
-  unsigned semantic_name;
+  enum tgsi_semantic semantic_name;
   unsigned semantic_index;
   enum tgsi_interpolate_mode interp;
   unsigned char cylindrical_wrap;
@@ -127,13 +127,13 @@ struct ureg_program
unsigned vs_inputs[PIPE_MAX_ATTRIBS/32];
 
struct {
-  unsigned semantic_name;
+  enum tgsi_semantic semantic_name;
   unsigned semantic_index;
} system_value[UREG_MAX_SYSTEM_VALUE];
unsigned nr_system_values;
 
struct {
-  unsigned semantic_name;
+  enum tgsi_semantic semantic_name;
   unsigned semantic_index;
   unsigned streams;
   unsigned usage_mask; /* = TGSI_WRITEMASK_* */
@@ -281,7 +281,7 @@ ureg_property(struct ureg_program *ureg, unsigned name, 
unsigned value)
 
 struct ureg_src
 ureg_DECL_fs_input_cyl_centroid_layout(struct ureg_program *ureg,
-   unsigned semantic_name,
+   enum tgsi_semantic semantic_name,
unsigned semantic_index,
enum tgsi_interpolate_mode interp_mode,
unsigned cylindrical_wrap,
@@ -334,7 +334,7 @@ out:
 
 struct ureg_src
 ureg_DECL_fs_input_cyl_centroid(struct ureg_program *ureg,
-   unsigned semantic_name,
+   enum tgsi_semantic semantic_name,
unsigned semantic_index,
enum tgsi_interpolate_mode interp_mode,
unsigned cylindrical_wrap,
@@ -363,7 +363,7 @@ ureg_DECL_vs_input( struct ureg_program *ureg,
 
 struct ureg_src
 ureg_DECL_input_layout(struct ureg_program *ureg,
-unsigned semantic_name,
+enum tgsi_semantic semantic_name,
 unsigned semantic_index,
 unsigned index,
 unsigned usage_mask,
@@ -378,7 +378,7 @@ ureg_DECL_input_layout(struct ureg_program *ureg,
 
 struct ureg_src
 ureg_DECL_input(struct ureg_program *ureg,
-unsigned semantic_name,
+enum tgsi_semantic semantic_name,
 unsigned semantic_index,
 unsigned array_id,
 unsigned array_size)
@@ -390,7 +390,7 @@ ureg_DECL_input(struct ureg_program *ureg,
 
 struct ureg_src
 ureg_DECL_system_value(struct ureg_program *ureg,
-   unsigned semantic_name,
+   enum tgsi_semantic semantic_name,
unsigned semantic_index)
 {
unsigned i;
@@ -418,7 +418,7 @@ out:
 
 struct ureg_dst
 ureg_DECL_output_layout(struct ureg_program *ureg,
-unsigned semantic_name,
+enum tgsi_semantic semantic_name,
 unsigned semantic_index,
 unsigned streams,
 unsigned index,
@@ -492,7 +492,7 @@ ureg_DECL_output(struct ureg_program *ureg,
 
 struct ureg_dst
 ureg_DECL_output_array(struct ureg_program *ureg,
-   unsigned semantic_name,
+   enum tgsi_semantic semantic_name,
unsigned semantic_index,
unsigned array_id,
unsigned array_size)
@@ -1505,7 +1505,7 @@ emit_decl_semantic(struct ureg_program *ureg,
unsigned file,
unsigned first,
unsigned last,
-   unsigned semantic_name,
+   enum tgsi_semantic semantic_name,
unsigned semantic_index,
unsigned streams,
unsigned usage_mask,
@@ -1574,7 +1574,7 @@ emit_decl_fs(struct ureg_program *ureg,
  unsigned file,
  unsigned first,
  unsigned last,
- unsigned semantic_name,
+ enum tgsi_semantic semantic_name,
  unsigned semantic_index,
  enum tgsi_interpolate_mode interpolate,
  unsigned cylindrical_wrap,
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.h 
b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
index 2bab23d..0349689 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
@@ -168,7 +168,7 @@ ureg_property(struct ureg_program *ureg, unsigned name, 
unsigned value);
 
 struct ureg_src
 ureg_DECL_fs_input_cyl_centroid_layout(struct ureg_program *,
-   unsigned semantic_name,
+   enum tgsi_semantic semantic_name,
unsigned semantic_index,
   

[Mesa-dev] [PATCH 2/6] gallium/util: replace uint with tgsi enum types

[Brian Paul]

---
 src/gallium/auxiliary/util/u_blit.c | 9 +
 src/gallium/auxiliary/util/u_blit.h | 4 ++--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_blit.c 
b/src/gallium/auxiliary/util/u_blit.c
index 3f92476..7178e89 100644
--- a/src/gallium/auxiliary/util/u_blit.c
+++ b/src/gallium/auxiliary/util/u_blit.c
@@ -178,7 +178,7 @@ set_fragment_shader(struct blit_state *ctx, uint writemask,
}
 
if (!ctx->fs[pipe_tex][writemask][idx]) {
-  unsigned tgsi_tex = util_pipe_tex_to_tgsi_tex(pipe_tex, 0);
+  enum tgsi_texture_type tgsi_tex = util_pipe_tex_to_tgsi_tex(pipe_tex, 0);
 
   /* OpenGL does not allow blits from signed to unsigned integer
* or vice versa. */
@@ -250,7 +250,7 @@ get_next_slot( struct blit_state *ctx )
  */
 static unsigned
 setup_vertex_data_tex(struct blit_state *ctx,
-  unsigned src_target,
+  enum pipe_texture_target src_target,
   unsigned src_face,
   float x0, float y0, float x1, float y1,
   float s0, float t0, float s1, float t1,
@@ -371,7 +371,8 @@ util_blit_pixels(struct blit_state *ctx,
  struct pipe_surface *dst,
  int dstX0, int dstY0,
  int dstX1, int dstY1,
- MAYBE_UNUSED float z, uint filter,
+ MAYBE_UNUSED float z,
+ enum pipe_tex_filter filter,
  uint writemask)
 {
struct pipe_context *pipe = ctx->pipe;
@@ -505,7 +506,7 @@ util_blit_pixels_tex(struct blit_state *ctx,
  struct pipe_surface *dst,
  int dstX0, int dstY0,
  int dstX1, int dstY1,
- float z, uint filter)
+ float z, enum pipe_tex_filter filter)
 {
boolean normalized = src_sampler_view->texture->target != PIPE_TEXTURE_RECT;
struct pipe_framebuffer_state fb;
diff --git a/src/gallium/auxiliary/util/u_blit.h 
b/src/gallium/auxiliary/util/u_blit.h
index b50edab..adc2173 100644
--- a/src/gallium/auxiliary/util/u_blit.h
+++ b/src/gallium/auxiliary/util/u_blit.h
@@ -60,7 +60,7 @@ util_blit_pixels(struct blit_state *ctx,
  struct pipe_surface *dst,
  int dstX0, int dstY0,
  int dstX1, int dstY1,
- float z, uint filter,
+ float z, enum pipe_tex_filter filter,
  uint writemask);
 
 extern void
@@ -72,7 +72,7 @@ util_blit_pixels_tex(struct blit_state *ctx,
  struct pipe_surface *dst,
  int dstX0, int dstY0,
  int dstX1, int dstY1,
- float z, uint filter);
+ float z, enum pipe_tex_filter filter);
 
 #ifdef __cplusplus
 }
-- 
2.7.4

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[Mesa-dev] [PATCH 4/6] tgsi: use TGSI enum types in ureg code

[Brian Paul]

---
 src/gallium/auxiliary/tgsi/tgsi_ureg.c | 62 ++
 src/gallium/auxiliary/tgsi/tgsi_ureg.h | 44 
 2 files changed, 55 insertions(+), 51 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c 
b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
index 4f3ac97..58908ae 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
@@ -114,10 +114,10 @@ struct ureg_program
struct {
   unsigned semantic_name;
   unsigned semantic_index;
-  unsigned interp;
+  enum tgsi_interpolate_mode interp;
   unsigned char cylindrical_wrap;
   unsigned char usage_mask;
-  unsigned interp_location;
+  enum tgsi_interpolate_loc interp_location;
   unsigned first;
   unsigned last;
   unsigned array_id;
@@ -159,17 +159,17 @@ struct ureg_program
 
struct {
   unsigned index;
-  unsigned target;
-  unsigned return_type_x;
-  unsigned return_type_y;
-  unsigned return_type_z;
-  unsigned return_type_w;
+  enum tgsi_texture_type target;
+  enum tgsi_return_type return_type_x;
+  enum tgsi_return_type return_type_y;
+  enum tgsi_return_type return_type_z;
+  enum tgsi_return_type return_type_w;
} sampler_view[PIPE_MAX_SHADER_SAMPLER_VIEWS];
unsigned nr_sampler_views;
 
struct {
   unsigned index;
-  unsigned target;
+  enum tgsi_texture_type target;
   unsigned format;
   boolean wr;
   boolean raw;
@@ -283,9 +283,9 @@ struct ureg_src
 ureg_DECL_fs_input_cyl_centroid_layout(struct ureg_program *ureg,
unsigned semantic_name,
unsigned semantic_index,
-   unsigned interp_mode,
+   enum tgsi_interpolate_mode interp_mode,
unsigned cylindrical_wrap,
-   unsigned interp_location,
+   enum tgsi_interpolate_loc interp_location,
unsigned index,
unsigned usage_mask,
unsigned array_id,
@@ -336,14 +336,15 @@ struct ureg_src
 ureg_DECL_fs_input_cyl_centroid(struct ureg_program *ureg,
unsigned semantic_name,
unsigned semantic_index,
-   unsigned interp_mode,
+   enum tgsi_interpolate_mode interp_mode,
unsigned cylindrical_wrap,
-   unsigned interp_location,
+   enum tgsi_interpolate_loc interp_location,
unsigned array_id,
unsigned array_size)
 {
return ureg_DECL_fs_input_cyl_centroid_layout(ureg,
- semantic_name, semantic_index, interp_mode, cylindrical_wrap, 
interp_location,
+ semantic_name, semantic_index, interp_mode,
+ cylindrical_wrap, interp_location,
  ureg->nr_input_regs, TGSI_WRITEMASK_XYZW, array_id, array_size);
 }
 
@@ -733,11 +734,11 @@ struct ureg_src ureg_DECL_sampler( struct ureg_program 
*ureg,
 struct ureg_src
 ureg_DECL_sampler_view(struct ureg_program *ureg,
unsigned index,
-   unsigned target,
-   unsigned return_type_x,
-   unsigned return_type_y,
-   unsigned return_type_z,
-   unsigned return_type_w)
+   enum tgsi_texture_type target,
+   enum tgsi_return_type return_type_x,
+   enum tgsi_return_type return_type_y,
+   enum tgsi_return_type return_type_z,
+   enum tgsi_return_type return_type_w)
 {
struct ureg_src reg = ureg_src_register(TGSI_FILE_SAMPLER_VIEW, index);
uint i;
@@ -768,7 +769,7 @@ ureg_DECL_sampler_view(struct ureg_program *ureg,
 struct ureg_src
 ureg_DECL_image(struct ureg_program *ureg,
 unsigned index,
-unsigned target,
+enum tgsi_texture_type target,
 unsigned format,
 boolean wr,
 boolean raw)
@@ -1326,7 +1327,8 @@ ureg_fixup_label(struct ureg_program *ureg,
 void
 ureg_emit_texture(struct ureg_program *ureg,
   unsigned extended_token,
-  unsigned target, unsigned return_type, unsigned num_offsets)
+  enum tgsi_texture_type target,
+  enum tgsi_return_type return_type, unsigned num_offsets)
 {
union tgsi_any_token *out, *insn;
 
@@ -1425,8 +1427,8 @@ ureg_tex_insn(struct ureg_program *ureg,
   unsigned opcode,
   const struct ureg_dst *dst,
   unsigned nr_dst,
-  unsigned target,
-  unsigned return_type,
+  enum tgsi_texture_type target,
+  enum tgsi_return_type return_type,
   const struct tgsi_texture_offset *texoffsets,
   unsigned 

[Mesa-dev] [PATCH 1/6] gallium/util: replace unsigned with tgsi enum types

[Brian Paul]

---
 src/gallium/auxiliary/util/u_simple_shaders.c | 36 ++-
 src/gallium/auxiliary/util/u_simple_shaders.h | 29 ++---
 2 files changed, 34 insertions(+), 31 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_simple_shaders.c 
b/src/gallium/auxiliary/util/u_simple_shaders.c
index 9679545..09491f4 100644
--- a/src/gallium/auxiliary/util/u_simple_shaders.c
+++ b/src/gallium/auxiliary/util/u_simple_shaders.c
@@ -202,7 +202,8 @@ void *util_make_layered_clear_geometry_shader(struct 
pipe_context *pipe)
 static void
 ureg_load_tex(struct ureg_program *ureg, struct ureg_dst out,
   struct ureg_src coord, struct ureg_src sampler,
-  unsigned tex_target, bool load_level_zero, bool use_txf)
+  enum tgsi_texture_type tex_target,
+  bool load_level_zero, bool use_txf)
 {
if (use_txf) {
   struct ureg_dst temp = ureg_DECL_temporary(ureg);
@@ -230,14 +231,14 @@ ureg_load_tex(struct ureg_program *ureg, struct ureg_dst 
out,
  *  MOV OUT[0], TEMP[0]
  *  END;
  *
- * \param tex_target  one of PIPE_TEXTURE_x
+ * \param tex_target  one of TGSI_TEXTURE_x
  * \parma interp_mode  either TGSI_INTERPOLATE_LINEAR or PERSPECTIVE
  * \param writemask  mask of TGSI_WRITEMASK_x
  */
 void *
 util_make_fragment_tex_shader_writemask(struct pipe_context *pipe,
-unsigned tex_target,
-unsigned interp_mode,
+enum tgsi_texture_type tex_target,
+enum tgsi_interpolate_mode interp_mode,
 unsigned writemask,
 enum tgsi_return_type stype,
 enum tgsi_return_type dtype,
@@ -310,11 +311,12 @@ util_make_fragment_tex_shader_writemask(struct 
pipe_context *pipe,
 /**
  * Make a simple fragment shader that sets the output color to a color
  * taken from a texture.
- * \param tex_target  one of PIPE_TEXTURE_x
+ * \param tex_target  one of TGSI_TEXTURE_x
  */
 void *
-util_make_fragment_tex_shader(struct pipe_context *pipe, unsigned tex_target,
-  unsigned interp_mode,
+util_make_fragment_tex_shader(struct pipe_context *pipe,
+  enum tgsi_texture_type tex_target,
+  enum tgsi_interpolate_mode interp_mode,
   enum tgsi_return_type stype,
   enum tgsi_return_type dtype,
   bool load_level_zero,
@@ -335,8 +337,8 @@ util_make_fragment_tex_shader(struct pipe_context *pipe, 
unsigned tex_target,
  */
 void *
 util_make_fragment_tex_shader_writedepth(struct pipe_context *pipe,
- unsigned tex_target,
- unsigned interp_mode,
+ enum tgsi_texture_type tex_target,
+ enum tgsi_interpolate_mode 
interp_mode,
  bool load_level_zero,
  bool use_txf)
 {
@@ -388,10 +390,10 @@ util_make_fragment_tex_shader_writedepth(struct 
pipe_context *pipe,
  */
 void *
 util_make_fragment_tex_shader_writedepthstencil(struct pipe_context *pipe,
-unsigned tex_target,
-unsigned interp_mode,
-bool load_level_zero,
-bool use_txf)
+ enum tgsi_texture_type tex_target,
+ enum tgsi_interpolate_mode 
interp_mode,
+ bool load_level_zero,
+ bool use_txf)
 {
struct ureg_program *ureg;
struct ureg_src depth_sampler, stencil_sampler;
@@ -452,10 +454,10 @@ util_make_fragment_tex_shader_writedepthstencil(struct 
pipe_context *pipe,
  */
 void *
 util_make_fragment_tex_shader_writestencil(struct pipe_context *pipe,
-   unsigned tex_target,
-   unsigned interp_mode,
-   bool load_level_zero,
-   bool use_txf)
+ enum tgsi_texture_type tex_target,
+ enum tgsi_interpolate_mode 
interp_mode,
+ bool load_level_zero,
+ bool use_txf)
 {
struct ureg_program *ureg;
struct ureg_src stencil_sampler;
diff --git a/src/gallium/auxiliary/util/u_simple_shaders.h 
b/src/gallium/auxiliary/util/u_simple_shaders.h
index a281f57..5c22246 100644
--- 

Re: [Mesa-dev] [PATCH 1/2] i965: perf: use drmIoctl() instead of ioctl()

[Tapani Pälli]

Both patches are
Reviewed-by: Tapani Pälli 

On 07.02.2018 01:56, Lionel Landwerlin wrote:

ioctl() might be interrupted, use drmIoctl() instead as it'll retry
automatically.

Fixes: 27ee83eaf7e "i965: perf: add support for userspace configurations"
Cc: "18.0" 
Signed-off-by: Lionel Landwerlin 
---
  src/mesa/drivers/dri/i965/brw_performance_query.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 5b8f30db2f8..f4ff858bd5d 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1842,7 +1842,7 @@ kernel_has_dynamic_config_support(struct brw_context *brw,
   config.n_mux_regs = 1;
   config.mux_regs_ptr = (uintptr_t) mux_regs;
  
- if (ioctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG, _id) < 0 &&

+ if (drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG, _id) < 0 
&&
   errno == ENOENT)
  return true;
  
@@ -1889,7 +1889,7 @@ init_oa_configs(struct brw_context *brw, const char *sysfs_dev_dir)

config.n_flex_regs = query->n_flex_regs;
config.flex_regs_ptr = (uintptr_t) query->flex_regs;
  
-  ret = ioctl(screen->fd, DRM_IOCTL_I915_PERF_ADD_CONFIG, );

+  ret = drmIoctl(screen->fd, DRM_IOCTL_I915_PERF_ADD_CONFIG, );
if (ret < 0) {
   DBG("Failed to load \"%s\" (%s) metrics set in kernel: %s\n",
   query->name, query->guid, strerror(errno));


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[Mesa-dev] [Bug 104988] Please do a mesa-demos/mesa-utils release. The last one was 2 years ago.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104988

Bug ID: 104988
   Summary: Please do a mesa-demos/mesa-utils release. The last
one was 2 years ago.
   Product: Mesa
   Version: unspecified
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Demos
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: daniel.van.v...@canonical.com
QA Contact: mesa-dev@lists.freedesktop.org

Please do a mesa-demos/mesa-utils release. The last one (8.3.0) was 2 years
ago.

See: https://cgit.freedesktop.org/mesa/demos/

I'm only waiting for one minor fix for bug 101814, but surely there are other
improvements from the last 2 years also worth releasing?

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Re: [Mesa-dev] [PATCH] i965: perf: add debug messages for loaded configs

[Tapani Pälli]

Reviewed-by: Tapani Pälli 

On 06.02.2018 19:06, Lionel Landwerlin wrote:

This helps figuring out potential problems when metrics don't show up
on frameretrace for example.

Signed-off-by: Lionel Landwerlin 
---
  src/mesa/drivers/dri/i965/brw_performance_query.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index f2aa2b8469d..5b8f30db2f8 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1871,6 +1871,7 @@ init_oa_configs(struct brw_context *brw, const char 
*sysfs_dev_dir)
  
/* Don't recreate already loaded configs. */

if (read_file_uint64(config_path, _id)) {
+ DBG("metric set: %s (already loaded)\n", query->guid);
   register_oa_config(brw, query, config_id);
   continue;
}
@@ -1896,6 +1897,7 @@ init_oa_configs(struct brw_context *brw, const char 
*sysfs_dev_dir)
}
  
register_oa_config(brw, query, config_id);

+  DBG("metric set: %s (added)\n", query->guid);
 }
  }
  


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