Re: [Mesa-dev] [PATCH] drirc: Add workaround for Divinity: Original Sin Enhanced Edition
I ended up creating a merge request for this and another patch: https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1550 On 2/8/19 10:09 am, Timothy Arceri wrote: This adds an additional work around for the game to fix the blocky shaders as reported in bug 105282 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105282 --- src/util/00-mesa-defaults.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf index ae29d8837d5..34a7993a314 100644 --- a/src/util/00-mesa-defaults.conf +++ b/src/util/00-mesa-defaults.conf @@ -146,6 +146,7 @@ TODO: document the other workarounds. + ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gallivm: fix a missing argument to CreateAtomicCmpXchg
On Fri, 2 Aug 2019 at 13:08, Brian Paul wrote: > > On 08/01/2019 04:56 PM, Charmaine Lee wrote: > > This patch fixes a missing argument to CreateAtomicCmpXchg for older > > version of LLVM. Does this pass CI? please try a pull request. We've got a bug open https://bugs.freedesktop.org/show_bug.cgi?id=02 but nobody has worked out why CI builds fine against 3.4 etc. Dave. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gallivm: fix a missing argument to CreateAtomicCmpXchg
On 08/01/2019 04:56 PM, Charmaine Lee wrote: This patch fixes a missing argument to CreateAtomicCmpXchg for older version of LLVM. --- src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp index 79d1029..8205d24 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp @@ -831,6 +831,7 @@ LLVMValueRef LLVMBuildAtomicCmpXchg(LLVMBuilderRef B, LLVMValueRef Ptr, /* LLVM 3.8 doesn't have a second ordering and uses old SynchronizationScope enum */ return llvm::wrap(llvm::unwrap(B)->CreateAtomicCmpXchg(llvm::unwrap(Ptr), llvm::unwrap(Cmp), llvm::unwrap(New), mapFromLLVMOrdering(SuccessOrdering), + mapFromLLVMOrdering(FailureOrdering), SingleThread ? llvm::SynchronizationScope::SingleThread : llvm::SynchronizationScope::CrossThread)); } #endif Reviewed-by: Brian Paul ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] egl: fix OpenGL 3.1 context creation
From the EGL_KHR_create_context spec: "* If OpenGL 3.1 is requested, the context returned may implement any of the following versions: * Version 3.1. The GL_ARB_compatibility extension may or may not be implemented, as determined by the implementation. * The core profile of version 3.2 or greater." Fixes CTS tests: dEQP-EGL.functional.create_context_ext.gl_31.rgb888_depth_stencil dEQP-EGL.functional.create_context_ext.robust_gl_31.rgb888_depth_stencil dEQP-EGL.functional.create_context_ext.gl_31.rgb888_depth_no_stencil dEQP-EGL.functional.create_context_ext.robust_gl_31.rgb888_depth_no_stencil dEQP-EGL.functional.create_context_ext.gl_31.rgba_depth_no_stencil dEQP-EGL.functional.create_context_ext.gl_31.rgb888_no_depth_no_stencil dEQP-EGL.functional.create_context_ext.robust_gl_31.rgba_depth_no_stencil dEQP-EGL.functional.create_context_ext.robust_gl_31.rgb888_no_depth_no_stencil dEQP-EGL.functional.create_context_ext.gl_31.rgba_no_depth_no_stencil dEQP-EGL.functional.create_context_ext.robust_gl_31.rgba_no_depth_no_stencil dEQP-EGL.functional.create_context_ext.gl_31.rgba_depth_stencil dEQP-EGL.functional.create_context_ext.robust_gl_31.rgba_depth_stencil --- src/egl/drivers/dri2/egl_dri2.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c index c712c106b06..918d61a1e9b 100644 --- a/src/egl/drivers/dri2/egl_dri2.c +++ b/src/egl/drivers/dri2/egl_dri2.c @@ -1245,6 +1245,9 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp, _EGLConfig *conf, && dri2_ctx->base.ClientMinorVersion >= 2)) && dri2_ctx->base.Profile == EGL_CONTEXT_OPENGL_CORE_PROFILE_BIT_KHR) api = __DRI_API_OPENGL_CORE; + else if (dri2_ctx->base.ClientMajorVersion == 3 && + dri2_ctx->base.ClientMinorVersion == 1) + api = __DRI_API_OPENGL_CORE; else api = __DRI_API_OPENGL; break; -- 2.21.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] drirc: Add workaround for Divinity: Original Sin Enhanced Edition
This adds an additional work around for the game to fix the blocky shaders as reported in bug 105282 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105282 --- src/util/00-mesa-defaults.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf index ae29d8837d5..34a7993a314 100644 --- a/src/util/00-mesa-defaults.conf +++ b/src/util/00-mesa-defaults.conf @@ -146,6 +146,7 @@ TODO: document the other workarounds. + -- 2.21.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] gallivm: fix a missing argument to CreateAtomicCmpXchg
This patch fixes a missing argument to CreateAtomicCmpXchg for older version of LLVM. --- src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp index 79d1029..8205d24 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp @@ -831,6 +831,7 @@ LLVMValueRef LLVMBuildAtomicCmpXchg(LLVMBuilderRef B, LLVMValueRef Ptr, /* LLVM 3.8 doesn't have a second ordering and uses old SynchronizationScope enum */ return llvm::wrap(llvm::unwrap(B)->CreateAtomicCmpXchg(llvm::unwrap(Ptr), llvm::unwrap(Cmp), llvm::unwrap(New), mapFromLLVMOrdering(SuccessOrdering), + mapFromLLVMOrdering(FailureOrdering), SingleThread ? llvm::SynchronizationScope::SingleThread : llvm::SynchronizationScope::CrossThread)); } #endif -- 1.8.5.6 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization
https://bugs.freedesktop.org/show_bug.cgi?id=41 --- Comment #21 from Steven Newbury --- The first one alone is enough to trigger the behaviour. It just crashes with the first disabled and the others enabled. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] intel/ir: Fix CFG corruption in opt_predicated_break().
On Tue, Jul 23, 2019 at 5:58 PM Francisco Jerez wrote: > > Specifically the optimization of a conditional BREAK + WHILE sequence > into a conditional WHILE seems pretty broken. The list of successors > of "earlier_block" (where the conditional BREAK was found) is emptied > and then re-created with the same edges for no apparent reason. On > top of that the list of predecessors of the block immediately after > the WHILE loop is emptied, but only one of the original edges will be > added back, which means that potentially several blocks that still > have it on their list of successors won't be on its list of > predecessors anymore, causing all sorts of hilarity due to the > inconsistency in the control flow graph. It's been ~5 years since I wrote the code, but I think the idea was to prevent ::combine_with from ever combining blocks that had "internal" edges -- that is, the first block cannot have outgoing edges and the second block cannot have incoming edges. That still seems to me to be a good idea. I guess it would be fine if that were relaxed to be the only The intention was to ensure that in the rare cases that we use ::combine_with that the programmer has to think hard about how they're rewiring the CFG. > The solution is to remove the code that's removing valid edges from > the CFG. cfg_t::remove_block() will already clean up after itself. > The assert in bblock_t::combine_with() also needs to be removed since > we will be merging a block with multiple children into the first one > of them. Okay, so I think you're saying that ::remove_block already does exactly what we need so we don't need to bother ensuring that the "internal" edges are removed. If that's an accurate restatement of your claim then this patch makes sense to me and is Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gitlab-ci: remove software-properties-common
On Thu, 1 Aug 2019 at 16:03, Emil Velikov wrote: > > On Thu, 1 Aug 2019 at 14:26, Michel Dänzer wrote: > > On 2019-08-01 2:32 p.m., Emil Velikov wrote: > > > > Sure I'll do that in a moment. > > > > Why don't you just follow my suggestion above? > > > That's what I was planning to do :-) > Done and dusted. Thanks for the help and extensive how-to, I've followed it literally. -Emil > -Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization
https://bugs.freedesktop.org/show_bug.cgi?id=41 --- Comment #20 from Steven Newbury --- (In reply to Jason Ekstrand from comment #10) > The undefined values appear harmless so I'm going to guess that this is > probably actually a RADV bug. Not knowing too much about RADV, how I'd go > aboug debugging it next would be to try "bisecting" nir_opt_algebraic.py by > commenting out large chunks of it and seeing if you can narrow down which > optimization triggers the problem. Fortunately, with a renderdoc trace, > it's pretty quick to test out changes (before/after shouldn't matter for the > renderdoc capture in this case) so it shouldn't take a terribly long time. > Once you've figured out which optimization is the culpret, we can see if > that optimization is buggy for some reason. If the NIR optimization looks > sound, you can try dumping the shaders out of RADV (again, I have no idea > how to do that), diff them, and see if you can figure out why it's a problem. > > For the moment, I'm going to move it over to RADV so that those people get > notified. Commenting out the bcsel@32 optimizations makes it work. I'll try enabling each one now... -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization
https://bugs.freedesktop.org/show_bug.cgi?id=41 --- Comment #19 from Steven Newbury --- (In reply to Steven Newbury from comment #18) > (In reply to Connor Abbott from comment #17) > > > One other thing you can try is to build mesa with -Dbuildtype=debug (i.e. > > with assertions enabled and no optimizations) and see if there's an > > assertion fail somewhere, or if it magically fixes itself. > > > I'll try this first since it's the easiest. > > It is perplexing what could possibly be causing my system to act > differently, especially since it didn't demonstrate anything odd prior to > the boolean change. Compiling latest llvm/mesa with debug gives the same visual result but emits continous "../mesa-/src/amd/vulkan/radv_descriptor_set.c:496: VK_ERROR_OUT_OF_POOL_MEMORY" ... probably not related. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] radv: remove radv_get_image_fmask_info()
It's unnecessary to duplicate fields in another struct.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 12 -
src/amd/vulkan/radv_image.c | 44 +++-
src/amd/vulkan/radv_meta_clear.c | 12 ++---
src/amd/vulkan/radv_private.h| 16 ++--
4 files changed, 25 insertions(+), 59 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 9aa731a252c..b9db931c309 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -4406,9 +4406,9 @@ radv_initialise_color_surface(struct radv_device *device,
if (radv_image_has_fmask(iview->image)) {
if (device->physical_device->rad_info.chip_class >=
GFX7)
- cb->cb_color_pitch |=
S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
- cb->cb_color_attrib |=
S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
- cb->cb_color_fmask_slice =
S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
+ cb->cb_color_pitch |=
S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
+ cb->cb_color_attrib |=
S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
+ cb->cb_color_fmask_slice =
S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
} else {
/* This must be set for fast clear to work without
FMASK. */
if (device->physical_device->rad_info.chip_class >=
GFX7)
@@ -4449,9 +4449,9 @@ radv_initialise_color_surface(struct radv_device *device,
}
if (radv_image_has_fmask(iview->image)) {
- va = radv_buffer_get_va(iview->bo) + iview->image->offset +
iview->image->fmask.offset;
+ va = radv_buffer_get_va(iview->bo) + iview->image->offset +
iview->image->fmask_offset;
cb->cb_color_fmask = va >> 8;
- cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
+ cb->cb_color_fmask |= surf->fmask_tile_swizzle;
} else {
cb->cb_color_fmask = cb->cb_color_base;
}
@@ -4501,7 +4501,7 @@ radv_initialise_color_surface(struct radv_device *device,
if (radv_image_has_fmask(iview->image)) {
cb->cb_color_info |= S_028C70_COMPRESSION(1);
if (device->physical_device->rad_info.chip_class == GFX6) {
- unsigned fmask_bankh =
util_logbase2(iview->image->fmask.bank_height);
+ unsigned fmask_bankh =
util_logbase2(surf->u.legacy.fmask.bankh);
cb->cb_color_attrib |=
S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
}
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index aaaf15ec8dc..efbb9de96b7 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -715,7 +715,7 @@ gfx10_make_texture_descriptor(struct radv_device *device,
assert(image->plane_count == 1);
- va = gpu_address + image->offset + image->fmask.offset;
+ va = gpu_address + image->offset + image->fmask_offset;
switch (image->info.samples) {
case 2:
@@ -879,7 +879,7 @@ si_make_texture_descriptor(struct radv_device *device,
assert(image->plane_count == 1);
- va = gpu_address + image->offset + image->fmask.offset;
+ va = gpu_address + image->offset + image->fmask_offset;
if (device->physical_device->rad_info.chip_class == GFX9) {
fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
@@ -915,7 +915,7 @@ si_make_texture_descriptor(struct radv_device *device,
}
fmask_state[0] = va >> 8;
- fmask_state[0] |= image->fmask.tile_swizzle;
+ fmask_state[0] |= image->planes[0].surface.fmask_tile_swizzle;
fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
S_008F14_DATA_FORMAT(fmask_format) |
S_008F14_NUM_FORMAT(num_format);
@@ -946,9 +946,9 @@ si_make_texture_descriptor(struct radv_device *device,
fmask_state[7] |= va >> 8;
}
} else {
- fmask_state[3] |=
S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
+ fmask_state[3] |=
S_008F1C_TILING_INDEX(image->planes[0].surface.u.legacy.fmask.tiling_index);
fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
- S_008F20_PITCH(image->fmask.pitch_in_pixels -
1);
+
S_008F20_PITCH(image->planes[0].surface.u.legacy.fmask.pitch_in_pixels - 1);
fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
[Mesa-dev] [PATCH 1/2] radv: remove radv_get_image_cmask_info()
It's unnecessary to duplicate fields in another struct.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 4 ++--
src/amd/vulkan/radv_image.c | 38 +---
src/amd/vulkan/radv_meta_clear.c | 11 +
src/amd/vulkan/radv_private.h| 13 ++-
4 files changed, 21 insertions(+), 45 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 29be192443a..9aa731a252c 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -4400,7 +4400,7 @@ radv_initialise_color_surface(struct radv_device *device,
cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
- cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
+ cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
cb->cb_color_attrib |=
S_028C74_TILE_MODE_INDEX(tile_mode_index);
@@ -4420,7 +4420,7 @@ radv_initialise_color_surface(struct radv_device *device,
/* CMASK variables */
va = radv_buffer_get_va(iview->bo) + iview->image->offset;
- va += iview->image->cmask.offset;
+ va += iview->image->cmask_offset;
cb->cb_color_cmask = va >> 8;
va = radv_buffer_get_va(iview->bo) + iview->image->offset;
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 8ff93e4344c..aaaf15ec8dc 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -939,7 +939,7 @@ si_make_texture_descriptor(struct radv_device *device,
S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
if (radv_image_is_tc_compat_cmask(image)) {
- va = gpu_address + image->offset +
image->cmask.offset;
+ va = gpu_address + image->offset +
image->cmask_offset;
fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va
>> 40);
fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
@@ -952,7 +952,7 @@ si_make_texture_descriptor(struct radv_device *device,
fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
if (radv_image_is_tc_compat_cmask(image)) {
- va = gpu_address + image->offset +
image->cmask.offset;
+ va = gpu_address + image->offset +
image->cmask_offset;
fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
fmask_state[7] |= va >> 8;
@@ -1138,45 +1138,27 @@ radv_image_alloc_fmask(struct radv_device *device,
image->alignment = MAX2(image->alignment, image->fmask.alignment);
}
-static void
-radv_image_get_cmask_info(struct radv_device *device,
- struct radv_image *image,
- struct radv_cmask_info *out)
-{
- assert(image->plane_count == 1);
-
- if (device->physical_device->rad_info.chip_class >= GFX9) {
- out->alignment = image->planes[0].surface.cmask_alignment;
- out->size = image->planes[0].surface.cmask_size;
- return;
- }
-
- out->slice_tile_max =
image->planes[0].surface.u.legacy.cmask_slice_tile_max;
- out->alignment = image->planes[0].surface.cmask_alignment;
- out->slice_size = image->planes[0].surface.cmask_slice_size;
- out->size = image->planes[0].surface.cmask_size;
-}
-
static void
radv_image_alloc_cmask(struct radv_device *device,
struct radv_image *image)
{
+ unsigned cmask_alignment = image->planes[0].surface.cmask_alignment;
+ unsigned cmask_size = image->planes[0].surface.cmask_size;
uint32_t clear_value_size = 0;
- radv_image_get_cmask_info(device, image, >cmask);
- if (!image->cmask.size)
+ if (!cmask_size)
return;
- assert(image->cmask.alignment);
+ assert(cmask_alignment);
- image->cmask.offset = align64(image->size, image->cmask.alignment);
+ image->cmask_offset = align64(image->size, cmask_alignment);
/* + 8 for storing the clear values */
if (!image->clear_value_offset) {
- image->clear_value_offset = image->cmask.offset +
image->cmask.size;
+ image->clear_value_offset = image->cmask_offset + cmask_size;
clear_value_size = 8;
}
- image->size = image->cmask.offset + image->cmask.size +
clear_value_size;
- image->alignment = MAX2(image->alignment, image->cmask.alignment);
+ image->size = image->cmask_offset + cmask_size + clear_value_size;
+ image->alignment = MAX2(image->alignment, cmask_alignment);
}
static void
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index
[Mesa-dev] [AppVeyor] mesa master #12143 completed
Build mesa 12143 completed Commit 3307c85a7d by Brian Paul on 8/1/2019 3:07 PM: st/mesa: fix MSVC compile breakage\n\nTrivial. Configure your notification preferences ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gitlab-ci: remove software-properties-common
On Thu, 1 Aug 2019 at 14:26, Michel Dänzer wrote: > On 2019-08-01 2:32 p.m., Emil Velikov wrote: > > Sure I'll do that in a moment. > > Why don't you just follow my suggestion above? > That's what I was planning to do :-) -Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/tex: ignore the diff between GL_TEXTURE_2D and GL_TEXTURE_RECTANGLE
Hi, I opened MR to fix this issue and started a discussion about the proper solution: https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1258 Thanks, Andrii. On Wed, Jul 24, 2019 at 10:32 AM Olivier Fourdan wrote: > Hi, > > On Wed, May 22, 2019 at 4:01 AM Ian Romanick wrote: > > > On Thu, Jul 19, 2018 at 12:08 PM andrey simiklit > > > > > > Jason, can we reconsider Andrii's patch? It still applies cleanly > > > (https://patchwork.freedesktop.org/patch/237490/) > > > > Looking at the patch and the "Simple reproducer" in the bug, I think > > this just papers over the issue. It seems like the problem is somewhere > > down inside the driver's handling of glXBindTexImageEXT. My best guess > > is that the texture is GL_TEXTURE_2D but the miptree backing it is > > GL_TEXTURE_RECTANGLE. It seems that the glXBindTexImageEXT handling > > should mark the miptree as GL_TEXTURE_2D when binding the image to a > > texture that is GL_TEXTURE_2D. Or is that not possible for some > > non-obvious reason? > > Sorry to be a pain, but I still get bug reports in xfce for this, for > everyone using a Mesa build with debug enabled (or a pre-release for > that matter) on Intel, the `assert()` are enabled and this bug occurs > with the xfce compositor. > > Maybe Andrii's patch is just hiding the issue, but that's already the > case without the `assert()` enabled (i.e. all stable releases of > Mesa), so I guess it's not such a big deal anyway. > > Can we agree on a fix on this? > > Cheers, > Olivier > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111053] Elite Dangerous shadows render as white.
https://bugs.freedesktop.org/show_bug.cgi?id=111053 Haxk20 changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #2 from Haxk20 --- This has been fixed multiple weeks ago. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 4/4] radv/gfx10: use the correct target machine for Wave32
r-b for patch 1,2,4
On Thu, Aug 1, 2019 at 10:40 AM Samuel Pitoiset
wrote:
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_llvm_helper.cpp | 30 +
> src/amd/vulkan/radv_shader.c| 3 ++-
> src/amd/vulkan/radv_shader_helper.h | 3 ++-
> 3 files changed, 26 insertions(+), 10 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_llvm_helper.cpp
> b/src/amd/vulkan/radv_llvm_helper.cpp
> index 2b14ddcf184..612548e4219 100644
> --- a/src/amd/vulkan/radv_llvm_helper.cpp
> +++ b/src/amd/vulkan/radv_llvm_helper.cpp
> @@ -28,8 +28,10 @@
> class radv_llvm_per_thread_info {
> public:
> radv_llvm_per_thread_info(enum radeon_family arg_family,
> - enum ac_target_machine_options arg_tm_options)
> - : family(arg_family), tm_options(arg_tm_options),
> passes(NULL) {}
> + enum ac_target_machine_options arg_tm_options,
> + unsigned arg_wave_size)
> + : family(arg_family), tm_options(arg_tm_options),
> + wave_size(arg_wave_size), passes(NULL), passes_wave32(NULL)
> {}
>
> ~radv_llvm_per_thread_info()
> {
> @@ -47,19 +49,28 @@ public:
> if (!passes)
> return false;
>
> + if (llvm_info.tm_wave32) {
> + passes_wave32 =
> ac_create_llvm_passes(llvm_info.tm_wave32);
> + if (!passes_wave32)
> + return false;
> + }
> +
> return true;
> }
>
> bool compile_to_memory_buffer(LLVMModuleRef module,
> char **pelf_buffer, size_t *pelf_size)
> {
> - return ac_compile_module_to_elf(passes, module, pelf_buffer,
> pelf_size);
> + struct ac_compiler_passes *p = wave_size == 32 ?
> passes_wave32 : passes;
> + return ac_compile_module_to_elf(p, module, pelf_buffer,
> pelf_size);
> }
>
> bool is_same(enum radeon_family arg_family,
> -enum ac_target_machine_options arg_tm_options) {
> +enum ac_target_machine_options arg_tm_options,
> +unsigned arg_wave_size) {
> if (arg_family == family &&
> - arg_tm_options == tm_options)
> + arg_tm_options == tm_options &&
> + arg_wave_size == wave_size)
> return true;
> return false;
> }
> @@ -67,7 +78,9 @@ public:
> private:
> enum radeon_family family;
> enum ac_target_machine_options tm_options;
> + unsigned wave_size;
> struct ac_compiler_passes *passes;
> + struct ac_compiler_passes *passes_wave32;
> };
>
> /* we have to store a linked list per thread due to the possiblity of
> multiple gpus being required */
> @@ -99,17 +112,18 @@ bool radv_compile_to_elf(struct ac_llvm_compiler *info,
> bool radv_init_llvm_compiler(struct ac_llvm_compiler *info,
> bool thread_compiler,
> enum radeon_family family,
> -enum ac_target_machine_options tm_options)
> +enum ac_target_machine_options tm_options,
> +unsigned wave_size)
> {
> if (thread_compiler) {
> for (auto : radv_llvm_per_thread_list) {
> - if (I.is_same(family, tm_options)) {
> + if (I.is_same(family, tm_options, wave_size)) {
> *info = I.llvm_info;
> return true;
> }
> }
>
> - radv_llvm_per_thread_list.emplace_back(family, tm_options);
> + radv_llvm_per_thread_list.emplace_back(family, tm_options,
> wave_size);
> radv_llvm_per_thread_info =
> radv_llvm_per_thread_list.back();
>
> if (!tinfo.init()) {
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index f0ab2d5e467..5e3b1378a14 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -1163,7 +1163,8 @@ shader_variant_compile(struct radv_device *device,
> radv_init_llvm_once();
> radv_init_llvm_compiler(_llvm,
> thread_compiler,
> - chip_family, tm_options);
> + chip_family, tm_options,
> +
> radv_get_shader_wave_size(device->physical_device, stage));
> if (gs_copy_shader) {
> assert(shader_count == 1);
> radv_compile_gs_copy_shader(_llvm, *shaders, ,
> diff --git a/src/amd/vulkan/radv_shader_helper.h
> b/src/amd/vulkan/radv_shader_helper.h
> index d9dace0b495..c64d2df676b 100644
> ---
Re: [Mesa-dev] [PATCH 3/4] radv/gfx10: determine correct wave size when lowering subgroups
So I'm not sure we can actually do this.
AFAIU even though we use a 32-bit wave internally we still have to
expose 64-bit externally, because with
VkPhysicalDeviceSubgroupProperties we say the subgroup size is 64
bits.
So we have to ~emulate a 64-lane wave that always has the upper bits empty.
On Thu, Aug 1, 2019 at 10:40 AM Samuel Pitoiset
wrote:
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_shader.c | 30 +-
> 1 file changed, 17 insertions(+), 13 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index 97fa80b348c..f0ab2d5e467 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -124,6 +124,17 @@ unsigned shader_io_get_unique_index(gl_varying_slot slot)
> unreachable("illegal slot in get unique index\n");
> }
>
> +static uint8_t
> +radv_get_shader_wave_size(const struct radv_physical_device *pdevice,
> + gl_shader_stage stage)
> +{
> + if (stage == MESA_SHADER_COMPUTE)
> + return pdevice->cs_wave_size;
> + else if (stage == MESA_SHADER_FRAGMENT)
> + return pdevice->ps_wave_size;
> + return pdevice->ge_wave_size;
> +}
> +
> VkResult radv_CreateShaderModule(
> VkDevice_device,
> const VkShaderModuleCreateInfo* pCreateInfo,
> @@ -422,9 +433,13 @@ radv_shader_compile_to_nir(struct radv_device *device,
>
> nir_lower_global_vars_to_local(nir);
> nir_remove_dead_variables(nir, nir_var_function_temp);
> +
> + uint8_t wave_size = radv_get_shader_wave_size(device->physical_device,
> + nir->info.stage);
> +
> nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
> - .subgroup_size = 64,
> - .ballot_bit_size = 64,
> + .subgroup_size = wave_size,
> + .ballot_bit_size = wave_size,
> .lower_to_scalar = 1,
> .lower_subgroup_masks = 1,
> .lower_shuffle = 1,
> @@ -667,17 +682,6 @@ radv_get_shader_binary_size(size_t code_size)
> return code_size + DEBUGGER_NUM_MARKERS * 4;
> }
>
> -static uint8_t
> -radv_get_shader_wave_size(const struct radv_physical_device *pdevice,
> - gl_shader_stage stage)
> -{
> - if (stage == MESA_SHADER_COMPUTE)
> - return pdevice->cs_wave_size;
> - else if (stage == MESA_SHADER_FRAGMENT)
> - return pdevice->ps_wave_size;
> - return pdevice->ge_wave_size;
> -}
> -
> static void radv_postprocess_config(const struct radv_physical_device
> *pdevice,
> const struct ac_shader_config *config_in,
> const struct radv_shader_variant_info
> *info,
> --
> 2.22.0
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] radv: only account for tile_swizzle for color surfaces with DCC
It's 0 for depth surfaces with TC compat HTILE enabled.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_image.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index f3237dd5985..221b554e73e 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -483,6 +483,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
meta_va = gpu_address + image->dcc_offset;
if (chip_class <= GFX8)
meta_va += base_level_info->dcc_offset;
+
+ meta_va |= (uint32_t)plane->surface.tile_swizzle << 8;
} else if (!is_storage_image &&
radv_image_is_tc_compat_htile(image)) {
meta_va = gpu_address + image->htile_offset;
@@ -490,10 +492,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
if (meta_va) {
state[6] |= S_008F28_COMPRESSION_EN(1);
- if (chip_class <= GFX9) {
+ if (chip_class <= GFX9)
state[7] = meta_va >> 8;
- state[7] |= plane->surface.tile_swizzle;
- }
}
}
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] radv/gfx10: add missing dcc_tile_swizzle tweak
Fixes: c90f46700dd ("radv/gfx10: mask DCC tile swizzle by alignment")
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_image.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 221b554e73e..8ff93e4344c 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -484,7 +484,9 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
if (chip_class <= GFX8)
meta_va += base_level_info->dcc_offset;
- meta_va |= (uint32_t)plane->surface.tile_swizzle << 8;
+ unsigned dcc_tile_swizzle = plane->surface.tile_swizzle
<< 8;
+ dcc_tile_swizzle &= plane->surface.dcc_alignment - 1;
+ meta_va |= dcc_tile_swizzle;
} else if (!is_storage_image &&
radv_image_is_tc_compat_htile(image)) {
meta_va = gpu_address + image->htile_offset;
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gitlab-ci: remove software-properties-common
On 2019-08-01 2:32 p.m., Emil Velikov wrote: > On Thu, 1 Aug 2019 at 09:35, Michel Dänzer wrote: >> >> On 2019-07-31 11:47 p.m., Eric Engestrom wrote: >>> On Wednesday, 2019-07-31 16:07:45 +0200, Michel Dänzer wrote: On 2019-07-31 3:26 p.m., Emil Velikov wrote: > On Wed, 31 Jul 2019 at 14:16, Michel Dänzer wrote: >> >> On 2019-07-31 3:04 p.m., Emil Velikov wrote: >>> From: Emil Velikov >>> >>> Currently we use the python package to manage repositories. At the same >>> time we also do that by hand - since it's a trivial echo to a file. >>> >>> Stay consistent, remove the package and manage things manually. >>> >>> Cc: Eric Engestrom >>> Signed-off-by: Emil Velikov >>> --- >>> .gitlab-ci/debian-install.sh | 11 +-- >>> 1 file changed, 5 insertions(+), 6 deletions(-) >>> >>> diff --git a/.gitlab-ci/debian-install.sh b/.gitlab-ci/debian-install.sh >>> index 578074ddb87..719d7830018 100644 >>> --- a/.gitlab-ci/debian-install.sh >>> +++ b/.gitlab-ci/debian-install.sh >>> @@ -16,12 +16,11 @@ apt-get install -y \ >>>curl \ >>>wget \ >>>unzip \ >>> - gnupg \ >>> - software-properties-common >>> + gnupg >>> >>> curl -fsSL https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add - >>> -add-apt-repository "deb https://apt.llvm.org/stretch/ >>> llvm-toolchain-stretch-7 main" >>> -add-apt-repository "deb https://apt.llvm.org/stretch/ >>> llvm-toolchain-stretch-8 main" >>> +echo "deb [trusted=yes] https://apt.llvm.org/stretch/ >>> llvm-toolchain-stretch-7 main" >/etc/apt/sources.list.d/llvm7.list >>> +echo "deb [trusted=yes] https://apt.llvm.org/stretch/ >>> llvm-toolchain-stretch-8 main" >/etc/apt/sources.list.d/llvm8.list >>> >>> sed -i -e 's/http:\/\/deb/https:\/\/deb/g' /etc/apt/sources.list >>> echo 'deb https://deb.debian.org/debian stretch-backports main' >>> >/etc/apt/sources.list.d/backports.list >>> @@ -46,8 +45,8 @@ apt-get install -y -t stretch-backports \ >>>clang-8 >>> >>> # Install remaining packages from Debian buster to get newer versions >>> -add-apt-repository "deb https://deb.debian.org/debian/ buster main" >>> -add-apt-repository "deb https://deb.debian.org/debian/ buster-updates >>> main" >>> +echo "deb https://deb.debian.org/debian/ buster main" >>> >/etc/apt/sources.list.d/buster.list >>> +echo "deb https://deb.debian.org/debian/ buster-updates main" >>> >/etc/apt/sources.list.d/buster-updates.list >>> apt-get update >>> apt-get install -y \ >>>bzip2 \ >>> >> >> This should be merged as part of an MR which requires the docker image >> to be re-generated for another reason, and thus bumps DEBIAN_TAG. >> > Since this is a non-functional change, I've explicitly omitted bumping > the DEBIAN_TAG. > Seemingly I forgot to mention it in the commit message though, oopsie. > > Since the image will contain practically the same artefacts, is it > worth carving out 30 minutes (or so) from the runners? No, I agree that would be wasteful for this change alone. However, merging this change without bumping the tag isn't good either, because then any issues with it would only be discovered the next time it does get bumped. Hence my request above. >>> >>> I agree with Michel here, it's better to waste a re-gen now and notice >>> any issue right away. >> >> That's not exactly what I'm saying though. :) >> >> If you don't want to merge this together with other changes which bump >> the tag, how about: >> >> * Create an MR with an additional commit which bumps the tag >> * Wait for the CI pipeline to come back green >> * Force-push to the source branch without the additional commit, and >> merge the MR >> * Remove the ephemeral docker image from >> https://gitlab.freedesktop.org/evelikov/mesa/container_registry >> >> The CI pipeline information including the log of the job which generated >> the ephemeral docker image will remain accessible. >> > if I understand you correctly, the goal is to have this explicitly tested. > Since it's a no-op, It's not a no-op, it has an observable effect, which is that the software-properties-common package will no longer be installed in the docker image. While it's unlikely that this will break anything, we have the CI pipeline to make sure changes don't break anything, so let's use it. > one might as well keep the test (and resulting extra image) downstream aka > in my repo. The image isn't needed after the test (that's why I call it ephemeral), only a record that it was successfully generated and that the CI pipeline's later stage jobs passed against it. An MR provides such a record (on the "Pipelines" tab). > Sure I'll do that in a moment. Why don't you just follow my suggestion above? --
Re: [Mesa-dev] [PATCH] gitlab-ci: remove software-properties-common
On Thu, 1 Aug 2019 at 09:35, Michel Dänzer wrote: > > On 2019-07-31 11:47 p.m., Eric Engestrom wrote: > > On Wednesday, 2019-07-31 16:07:45 +0200, Michel Dänzer wrote: > >> On 2019-07-31 3:26 p.m., Emil Velikov wrote: > >>> On Wed, 31 Jul 2019 at 14:16, Michel Dänzer wrote: > > On 2019-07-31 3:04 p.m., Emil Velikov wrote: > > From: Emil Velikov > > > > Currently we use the python package to manage repositories. At the same > > time we also do that by hand - since it's a trivial echo to a file. > > > > Stay consistent, remove the package and manage things manually. > > > > Cc: Eric Engestrom > > Signed-off-by: Emil Velikov > > --- > > .gitlab-ci/debian-install.sh | 11 +-- > > 1 file changed, 5 insertions(+), 6 deletions(-) > > > > diff --git a/.gitlab-ci/debian-install.sh b/.gitlab-ci/debian-install.sh > > index 578074ddb87..719d7830018 100644 > > --- a/.gitlab-ci/debian-install.sh > > +++ b/.gitlab-ci/debian-install.sh > > @@ -16,12 +16,11 @@ apt-get install -y \ > >curl \ > >wget \ > >unzip \ > > - gnupg \ > > - software-properties-common > > + gnupg > > > > curl -fsSL https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add - > > -add-apt-repository "deb https://apt.llvm.org/stretch/ > > llvm-toolchain-stretch-7 main" > > -add-apt-repository "deb https://apt.llvm.org/stretch/ > > llvm-toolchain-stretch-8 main" > > +echo "deb [trusted=yes] https://apt.llvm.org/stretch/ > > llvm-toolchain-stretch-7 main" >/etc/apt/sources.list.d/llvm7.list > > +echo "deb [trusted=yes] https://apt.llvm.org/stretch/ > > llvm-toolchain-stretch-8 main" >/etc/apt/sources.list.d/llvm8.list > > > > sed -i -e 's/http:\/\/deb/https:\/\/deb/g' /etc/apt/sources.list > > echo 'deb https://deb.debian.org/debian stretch-backports main' > > >/etc/apt/sources.list.d/backports.list > > @@ -46,8 +45,8 @@ apt-get install -y -t stretch-backports \ > >clang-8 > > > > # Install remaining packages from Debian buster to get newer versions > > -add-apt-repository "deb https://deb.debian.org/debian/ buster main" > > -add-apt-repository "deb https://deb.debian.org/debian/ buster-updates > > main" > > +echo "deb https://deb.debian.org/debian/ buster main" > > >/etc/apt/sources.list.d/buster.list > > +echo "deb https://deb.debian.org/debian/ buster-updates main" > > >/etc/apt/sources.list.d/buster-updates.list > > apt-get update > > apt-get install -y \ > >bzip2 \ > > > > This should be merged as part of an MR which requires the docker image > to be re-generated for another reason, and thus bumps DEBIAN_TAG. > > >>> Since this is a non-functional change, I've explicitly omitted bumping > >>> the DEBIAN_TAG. > >>> Seemingly I forgot to mention it in the commit message though, oopsie. > >>> > >>> Since the image will contain practically the same artefacts, is it > >>> worth carving out 30 minutes (or so) from the runners? > >> > >> No, I agree that would be wasteful for this change alone. > >> > >> However, merging this change without bumping the tag isn't good either, > >> because then any issues with it would only be discovered the next time > >> it does get bumped. Hence my request above. > > > > I agree with Michel here, it's better to waste a re-gen now and notice > > any issue right away. > > That's not exactly what I'm saying though. :) > > If you don't want to merge this together with other changes which bump > the tag, how about: > > * Create an MR with an additional commit which bumps the tag > * Wait for the CI pipeline to come back green > * Force-push to the source branch without the additional commit, and > merge the MR > * Remove the ephemeral docker image from > https://gitlab.freedesktop.org/evelikov/mesa/container_registry > > The CI pipeline information including the log of the job which generated > the ephemeral docker image will remain accessible. > if I understand you correctly, the goal is to have this explicitly tested. Since it's a no-op, one might as well keep the test (and resulting extra image) downstream aka in my repo. Sure I'll do that in a moment. Thanks Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v6 4/5] st/dri2: Implement DRI2bufferDamageExtension
+Marek (looks like I forgot to Cc you on this v6 :-/).
On Mon, 22 Jul 2019 09:49:31 +0200
Boris Brezillon wrote:
> Hi Qiang,
>
> On Sun, 21 Jul 2019 17:02:54 +0800
> Qiang Yu wrote:
>
> > On Mon, Jul 15, 2019 at 8:50 PM Boris Brezillon
> > wrote:
> > >
> > > From: Daniel Stone
> > >
> > > Add a pipe_screen->set_damage_region() hook to propagate
> > > set-damage-region requests to the driver, it's then up to the driver to
> > > decide what to do with this piece of information.
> > >
> > > If the hook is left unassigned, the buffer-damage extension is
> > > considered unsupported.
> > >
> > > Signed-off-by: Daniel Stone
> > > Signed-off-by: Boris Brezillon
> > > Reviewed-by: Alyssa Rosenzweig
> > > ---
> > > Hello Qiang,
> > >
> > > I intentionally dropped your R-b/T-b on this patch since the
> > > ->set_damage_region() prototype has changed. Feel free to add it back.
> > >
> > > Regards,
> > >
> > > Boris
> > >
> > > Changes in v6:
> > > * Pass pipe_box objects instead ints
> > > * Document the set_damage_region() hook
> > >
> > > Changes in v5:
> > > * Add Alyssa's R-b
> > > ---
> > > src/gallium/include/pipe/p_screen.h | 17 ++
> > > src/gallium/state_trackers/dri/dri2.c | 34 +++
> > > 2 files changed, 51 insertions(+)
> > >
> > > diff --git a/src/gallium/include/pipe/p_screen.h
> > > b/src/gallium/include/pipe/p_screen.h
> > > index 3f9bad470950..11a6aa939124 100644
> > > --- a/src/gallium/include/pipe/p_screen.h
> > > +++ b/src/gallium/include/pipe/p_screen.h
> > > @@ -464,6 +464,23 @@ struct pipe_screen {
> > > bool (*is_parallel_shader_compilation_finished)(struct pipe_screen
> > > *screen,
> > > void *shader,
> > > unsigned shader_type);
> > > +
> > > + /**
> > > +* Set the damage region (called when KHR_partial_update() is
> > > invoked).
> > > +* This function is passed an array of rectangles encoding the damage
> > > area.
> > > +* rects are using the bottom-left origin convention.
> > > +* nrects = 0 means 'reset the damage region'. What 'reset' implies
> > > is HW
> > > +* specific. For tile-based renderers, the damage extent is typically
> > > set
> > > +* to cover the whole resource with no damage rect (or a 0-size damage
> > > +* rect). This way, the existing resource content is reloaded into the
> > > +* local tile buffer for every tile thus making partial tile update
> > > +* possible. For HW operating in immediate mode, this reset operation
> > > is
> > > +* likely to be a NOOP.
> > > +*/
> > > + void (*set_damage_region)(struct pipe_screen *screen,
> > > + struct pipe_resource *resource,
> > > + unsigned int nrects,
> > > + const struct pipe_box *rects);
> > > };
> > >
> > >
> > > diff --git a/src/gallium/state_trackers/dri/dri2.c
> > > b/src/gallium/state_trackers/dri/dri2.c
> > > index 5a7ec878bab0..5273b95cd5fb 100644
> > > --- a/src/gallium/state_trackers/dri/dri2.c
> > > +++ b/src/gallium/state_trackers/dri/dri2.c
> > > @@ -1807,6 +1807,35 @@ static const __DRI2interopExtension
> > > dri2InteropExtension = {
> > > .export_object = dri2_interop_export_object
> > > };
> > >
> > > +/**
> > > + * \brief the DRI2bufferDamageExtension set_damage_region method
> > > + */
> > > +static void
> > > +dri2_set_damage_region(__DRIdrawable *dPriv, unsigned int nrects, int
> > > *rects)
> > > +{
> > > + struct dri_drawable *drawable = dri_drawable(dPriv);
> > > + struct pipe_resource *resource =
> > > drawable->textures[ST_ATTACHMENT_BACK_LEFT];
> > > + struct pipe_screen *screen = resource->screen;
> > > + struct pipe_box *boxes = NULL;
> > > +
> > > + if (nrects) {
> > > + boxes = CALLOC(nrects, sizeof(*boxes));
> > > + assert(boxes);
> >
> > Where does this boxes array get freed? I can't find in your patch 6 either.
> >
>
> Indeed, the FREE() is missing.
>
> > In fact I prefer the v5 way which just uses `int *rects` to avoid
> > unnecessary
> > conversion.
>
> Well, Erik suggested to pass an array of pipe_boxe objects to make
> things clearer, and I can of agree with him. Moreover, I'd expect the
*kind of
> extra allocation + pipe_box init overhead to be negligible.
Erik, Qiang, Marek,
Any comment on this v5. Should I send a v6 adding the missing FREE()
call. Anything else you'd like me to change?
Thanks,
Boris
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] Re mesa/st: add tgsi-lowering code for depth-clamp
Hey Gert, I'm looking at https://cgit.freedesktop.org/mesa/mesa/commit/?id=b048d8bf8f056759d1845a799d4ba2ac84bce30f , which attempts to implement depth clamping (rather than clipping) with shader tricks. You're forcing the final vertex stage's position's depth to 0, and then making up for it in the frag shader with an extra varying. However won't this screw up the barycentric coordinates for perspective interpolation? i.e. won't you effectively always just get noperspective interp everywhere as a result? -ilia ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/4] radv/gfx10: determine correct wave size when lowering subgroups
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_shader.c | 30 +-
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 97fa80b348c..f0ab2d5e467 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -124,6 +124,17 @@ unsigned shader_io_get_unique_index(gl_varying_slot slot)
unreachable("illegal slot in get unique index\n");
}
+static uint8_t
+radv_get_shader_wave_size(const struct radv_physical_device *pdevice,
+ gl_shader_stage stage)
+{
+ if (stage == MESA_SHADER_COMPUTE)
+ return pdevice->cs_wave_size;
+ else if (stage == MESA_SHADER_FRAGMENT)
+ return pdevice->ps_wave_size;
+ return pdevice->ge_wave_size;
+}
+
VkResult radv_CreateShaderModule(
VkDevice_device,
const VkShaderModuleCreateInfo* pCreateInfo,
@@ -422,9 +433,13 @@ radv_shader_compile_to_nir(struct radv_device *device,
nir_lower_global_vars_to_local(nir);
nir_remove_dead_variables(nir, nir_var_function_temp);
+
+ uint8_t wave_size = radv_get_shader_wave_size(device->physical_device,
+ nir->info.stage);
+
nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
- .subgroup_size = 64,
- .ballot_bit_size = 64,
+ .subgroup_size = wave_size,
+ .ballot_bit_size = wave_size,
.lower_to_scalar = 1,
.lower_subgroup_masks = 1,
.lower_shuffle = 1,
@@ -667,17 +682,6 @@ radv_get_shader_binary_size(size_t code_size)
return code_size + DEBUGGER_NUM_MARKERS * 4;
}
-static uint8_t
-radv_get_shader_wave_size(const struct radv_physical_device *pdevice,
- gl_shader_stage stage)
-{
- if (stage == MESA_SHADER_COMPUTE)
- return pdevice->cs_wave_size;
- else if (stage == MESA_SHADER_FRAGMENT)
- return pdevice->ps_wave_size;
- return pdevice->ge_wave_size;
-}
-
static void radv_postprocess_config(const struct radv_physical_device *pdevice,
const struct ac_shader_config *config_in,
const struct radv_shader_variant_info *info,
--
2.22.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 4/4] radv/gfx10: use the correct target machine for Wave32
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_llvm_helper.cpp | 30 +
src/amd/vulkan/radv_shader.c| 3 ++-
src/amd/vulkan/radv_shader_helper.h | 3 ++-
3 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/src/amd/vulkan/radv_llvm_helper.cpp
b/src/amd/vulkan/radv_llvm_helper.cpp
index 2b14ddcf184..612548e4219 100644
--- a/src/amd/vulkan/radv_llvm_helper.cpp
+++ b/src/amd/vulkan/radv_llvm_helper.cpp
@@ -28,8 +28,10 @@
class radv_llvm_per_thread_info {
public:
radv_llvm_per_thread_info(enum radeon_family arg_family,
- enum ac_target_machine_options arg_tm_options)
- : family(arg_family), tm_options(arg_tm_options), passes(NULL)
{}
+ enum ac_target_machine_options arg_tm_options,
+ unsigned arg_wave_size)
+ : family(arg_family), tm_options(arg_tm_options),
+ wave_size(arg_wave_size), passes(NULL), passes_wave32(NULL) {}
~radv_llvm_per_thread_info()
{
@@ -47,19 +49,28 @@ public:
if (!passes)
return false;
+ if (llvm_info.tm_wave32) {
+ passes_wave32 =
ac_create_llvm_passes(llvm_info.tm_wave32);
+ if (!passes_wave32)
+ return false;
+ }
+
return true;
}
bool compile_to_memory_buffer(LLVMModuleRef module,
char **pelf_buffer, size_t *pelf_size)
{
- return ac_compile_module_to_elf(passes, module, pelf_buffer,
pelf_size);
+ struct ac_compiler_passes *p = wave_size == 32 ? passes_wave32
: passes;
+ return ac_compile_module_to_elf(p, module, pelf_buffer,
pelf_size);
}
bool is_same(enum radeon_family arg_family,
-enum ac_target_machine_options arg_tm_options) {
+enum ac_target_machine_options arg_tm_options,
+unsigned arg_wave_size) {
if (arg_family == family &&
- arg_tm_options == tm_options)
+ arg_tm_options == tm_options &&
+ arg_wave_size == wave_size)
return true;
return false;
}
@@ -67,7 +78,9 @@ public:
private:
enum radeon_family family;
enum ac_target_machine_options tm_options;
+ unsigned wave_size;
struct ac_compiler_passes *passes;
+ struct ac_compiler_passes *passes_wave32;
};
/* we have to store a linked list per thread due to the possiblity of multiple
gpus being required */
@@ -99,17 +112,18 @@ bool radv_compile_to_elf(struct ac_llvm_compiler *info,
bool radv_init_llvm_compiler(struct ac_llvm_compiler *info,
bool thread_compiler,
enum radeon_family family,
-enum ac_target_machine_options tm_options)
+enum ac_target_machine_options tm_options,
+unsigned wave_size)
{
if (thread_compiler) {
for (auto : radv_llvm_per_thread_list) {
- if (I.is_same(family, tm_options)) {
+ if (I.is_same(family, tm_options, wave_size)) {
*info = I.llvm_info;
return true;
}
}
- radv_llvm_per_thread_list.emplace_back(family, tm_options);
+ radv_llvm_per_thread_list.emplace_back(family, tm_options,
wave_size);
radv_llvm_per_thread_info =
radv_llvm_per_thread_list.back();
if (!tinfo.init()) {
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index f0ab2d5e467..5e3b1378a14 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -1163,7 +1163,8 @@ shader_variant_compile(struct radv_device *device,
radv_init_llvm_once();
radv_init_llvm_compiler(_llvm,
thread_compiler,
- chip_family, tm_options);
+ chip_family, tm_options,
+
radv_get_shader_wave_size(device->physical_device, stage));
if (gs_copy_shader) {
assert(shader_count == 1);
radv_compile_gs_copy_shader(_llvm, *shaders, ,
diff --git a/src/amd/vulkan/radv_shader_helper.h
b/src/amd/vulkan/radv_shader_helper.h
index d9dace0b495..c64d2df676b 100644
--- a/src/amd/vulkan/radv_shader_helper.h
+++ b/src/amd/vulkan/radv_shader_helper.h
@@ -29,7 +29,8 @@ extern "C" {
bool radv_init_llvm_compiler(struct ac_llvm_compiler *info,
bool thread_compiler,
enum radeon_family family,
-enum
[Mesa-dev] [PATCH 1/4] radv/gfx10: add Wave32 support for fragment shaders
It can be enabled with RADV_PERFTEST=pswave32.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_debug.h | 1 +
src/amd/vulkan/radv_device.c | 6 ++
src/amd/vulkan/radv_nir_to_llvm.c | 2 ++
src/amd/vulkan/radv_pipeline.c| 3 ++-
src/amd/vulkan/radv_private.h | 1 +
src/amd/vulkan/radv_shader.c | 4 +++-
src/amd/vulkan/radv_shader.h | 1 +
7 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index 6414e882676..65dbec6e90d 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -65,6 +65,7 @@ enum {
RADV_PERFTEST_SHADER_BALLOT = 0x40,
RADV_PERFTEST_TC_COMPAT_CMASK = 0x80,
RADV_PERFTEST_CS_WAVE_32 = 0x100,
+ RADV_PERFTEST_PS_WAVE_32 = 0x200,
};
bool
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 29be192443a..b66b15edf73 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -385,10 +385,15 @@ radv_physical_device_init(struct radv_physical_device
*device,
/* Determine the number of threads per wave for all stages. */
device->cs_wave_size = 64;
+ device->ps_wave_size = 64;
if (device->rad_info.chip_class >= GFX10) {
if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
device->cs_wave_size = 32;
+
+ /* For pixel shaders, wave64 is recommanded. */
+ if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
+ device->ps_wave_size = 32;
}
radv_physical_device_init_mem_types(device);
@@ -503,6 +508,7 @@ static const struct debug_control radv_perftest_options[] =
{
{"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
{"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
{"cswave32", RADV_PERFTEST_CS_WAVE_32},
+ {"pswave32", RADV_PERFTEST_PS_WAVE_32},
{NULL, 0}
};
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index bb78bcccf0e..bba5849b152 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -4323,6 +4323,8 @@ radv_nir_shader_wave_size(struct nir_shader *const
*shaders, int shader_count,
{
if (shaders[0]->info.stage == MESA_SHADER_COMPUTE)
return options->cs_wave_size;
+ else if (shaders[0]->info.stage == MESA_SHADER_FRAGMENT)
+ return options->ps_wave_size;
return 64;
}
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index d62066cbee4..dbfe261c982 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4060,7 +4060,8 @@ radv_pipeline_generate_fragment_shader(struct
radeon_cmdbuf *ctx_cs,
ps->config.spi_ps_input_addr);
radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
- S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
+ S_0286D8_NUM_INTERP(ps->info.fs.num_interp) |
+
S_0286D8_PS_W32_EN(pipeline->device->physical_device->ps_wave_size == 32));
radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL,
pipeline->graphics.spi_baryc_cntl);
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 143c09811c8..a1347060190 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -302,6 +302,7 @@ struct radv_physical_device {
bool has_dcc_constant_encode;
/* Number of threads per wave. */
+ uint8_t ps_wave_size;
uint8_t cs_wave_size;
/* This is the drivers on-disk cache used as a fallback as opposed to
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 9c88ab551bb..48ed86c99b1 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -673,7 +673,8 @@ radv_get_shader_wave_size(const struct radv_physical_device
*pdevice,
{
if (stage == MESA_SHADER_COMPUTE)
return pdevice->cs_wave_size;
-
+ else if (stage == MESA_SHADER_FRAGMENT)
+ return pdevice->ps_wave_size;
return 64;
}
@@ -1142,6 +1143,7 @@ shader_variant_compile(struct radv_device *device,
options->tess_offchip_block_dw_size =
device->tess_offchip_block_dw_size;
options->address32_hi = device->physical_device->rad_info.address32_hi;
options->cs_wave_size = device->physical_device->cs_wave_size;
+ options->ps_wave_size = device->physical_device->ps_wave_size;
if (options->supports_spill)
tm_options |= AC_TM_SUPPORTS_SPILL;
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 92ae2a7259d..0ef49628b5d 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -129,6 +129,7 @@ struct radv_nir_compiler_options {
uint32_t
[Mesa-dev] [PATCH 2/4] radv/gfx10: add Wave32 support for vertex, tessellation and geometry shaders
It can be enabled with RADV_PERFTEST=gewave32.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_debug.h | 1 +
src/amd/vulkan/radv_device.c | 5 +
src/amd/vulkan/radv_nir_to_llvm.c | 13 +++--
src/amd/vulkan/radv_pipeline.c| 10 +-
src/amd/vulkan/radv_private.h | 1 +
src/amd/vulkan/radv_shader.c | 3 ++-
src/amd/vulkan/radv_shader.h | 1 +
7 files changed, 26 insertions(+), 8 deletions(-)
diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index 65dbec6e90d..ef5b331d188 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -66,6 +66,7 @@ enum {
RADV_PERFTEST_TC_COMPAT_CMASK = 0x80,
RADV_PERFTEST_CS_WAVE_32 = 0x100,
RADV_PERFTEST_PS_WAVE_32 = 0x200,
+ RADV_PERFTEST_GE_WAVE_32 = 0x400,
};
bool
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index b66b15edf73..fc961040b6e 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -386,6 +386,7 @@ radv_physical_device_init(struct radv_physical_device
*device,
/* Determine the number of threads per wave for all stages. */
device->cs_wave_size = 64;
device->ps_wave_size = 64;
+ device->ge_wave_size = 64;
if (device->rad_info.chip_class >= GFX10) {
if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
@@ -394,6 +395,9 @@ radv_physical_device_init(struct radv_physical_device
*device,
/* For pixel shaders, wave64 is recommanded. */
if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
device->ps_wave_size = 32;
+
+ if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
+ device->ge_wave_size = 32;
}
radv_physical_device_init_mem_types(device);
@@ -509,6 +513,7 @@ static const struct debug_control radv_perftest_options[] =
{
{"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
{"cswave32", RADV_PERFTEST_CS_WAVE_32},
{"pswave32", RADV_PERFTEST_PS_WAVE_32},
+ {"gewave32", RADV_PERFTEST_GE_WAVE_32},
{NULL, 0}
};
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index bba5849b152..91251aa69bd 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -295,7 +295,7 @@ get_tcs_num_patches(struct radv_shader_context *ctx)
/* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
if (ctx->options->chip_class == GFX6) {
- unsigned one_wave = 64 / MAX2(num_tcs_input_cp,
num_tcs_output_cp);
+ unsigned one_wave = ctx->options->ge_wave_size /
MAX2(num_tcs_input_cp, num_tcs_output_cp);
num_patches = MIN2(num_patches, one_wave);
}
return num_patches;
@@ -3038,7 +3038,8 @@ handle_es_outputs_post(struct radv_shader_context *ctx,
LLVMValueRef wave_idx = ac_unpack_param(>ac,
ctx->merged_wave_info, 24, 4);
vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
LLVMBuildMul(ctx->ac.builder, wave_idx,
- LLVMConstInt(ctx->ac.i32,
64, false), ""), "");
+ LLVMConstInt(ctx->ac.i32,
+
ctx->ac.wave_size, false), ""), "");
lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
LLVMConstInt(ctx->ac.i32, itemsize_dw,
0), "");
}
@@ -3140,7 +3141,7 @@ static LLVMValueRef get_thread_id_in_tg(struct
radv_shader_context *ctx)
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef tmp;
tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
- LLVMConstInt(ctx->ac.i32, 64, false), "");
+ LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false),
"");
return LLVMBuildAdd(builder, tmp, ac_get_thread_id(>ac), "");
}
@@ -4190,7 +4191,7 @@ ac_setup_rings(struct radv_shader_context *ctx)
*/
LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
uint64_t stream_offset = 0;
- unsigned num_records = 64;
+ unsigned num_records = ctx->ac.wave_size;
LLVMValueRef base_ring;
base_ring =
@@ -4223,7 +4224,7 @@ ac_setup_rings(struct radv_shader_context *ctx)
ring = LLVMBuildInsertElement(ctx->ac.builder,
ring, tmp, ctx->ac.i32_0,
"");
- stream_offset += stride * 64;
+ stream_offset += stride * ctx->ac.wave_size;
ring = LLVMBuildBitCast(ctx->ac.builder, ring,
Re: [Mesa-dev] [PATCH] gitlab-ci: remove software-properties-common
On 2019-07-31 11:47 p.m., Eric Engestrom wrote: > On Wednesday, 2019-07-31 16:07:45 +0200, Michel Dänzer wrote: >> On 2019-07-31 3:26 p.m., Emil Velikov wrote: >>> On Wed, 31 Jul 2019 at 14:16, Michel Dänzer wrote: On 2019-07-31 3:04 p.m., Emil Velikov wrote: > From: Emil Velikov > > Currently we use the python package to manage repositories. At the same > time we also do that by hand - since it's a trivial echo to a file. > > Stay consistent, remove the package and manage things manually. > > Cc: Eric Engestrom > Signed-off-by: Emil Velikov > --- > .gitlab-ci/debian-install.sh | 11 +-- > 1 file changed, 5 insertions(+), 6 deletions(-) > > diff --git a/.gitlab-ci/debian-install.sh b/.gitlab-ci/debian-install.sh > index 578074ddb87..719d7830018 100644 > --- a/.gitlab-ci/debian-install.sh > +++ b/.gitlab-ci/debian-install.sh > @@ -16,12 +16,11 @@ apt-get install -y \ >curl \ >wget \ >unzip \ > - gnupg \ > - software-properties-common > + gnupg > > curl -fsSL https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add - > -add-apt-repository "deb https://apt.llvm.org/stretch/ > llvm-toolchain-stretch-7 main" > -add-apt-repository "deb https://apt.llvm.org/stretch/ > llvm-toolchain-stretch-8 main" > +echo "deb [trusted=yes] https://apt.llvm.org/stretch/ > llvm-toolchain-stretch-7 main" >/etc/apt/sources.list.d/llvm7.list > +echo "deb [trusted=yes] https://apt.llvm.org/stretch/ > llvm-toolchain-stretch-8 main" >/etc/apt/sources.list.d/llvm8.list > > sed -i -e 's/http:\/\/deb/https:\/\/deb/g' /etc/apt/sources.list > echo 'deb https://deb.debian.org/debian stretch-backports main' > >/etc/apt/sources.list.d/backports.list > @@ -46,8 +45,8 @@ apt-get install -y -t stretch-backports \ >clang-8 > > # Install remaining packages from Debian buster to get newer versions > -add-apt-repository "deb https://deb.debian.org/debian/ buster main" > -add-apt-repository "deb https://deb.debian.org/debian/ buster-updates > main" > +echo "deb https://deb.debian.org/debian/ buster main" > >/etc/apt/sources.list.d/buster.list > +echo "deb https://deb.debian.org/debian/ buster-updates main" > >/etc/apt/sources.list.d/buster-updates.list > apt-get update > apt-get install -y \ >bzip2 \ > This should be merged as part of an MR which requires the docker image to be re-generated for another reason, and thus bumps DEBIAN_TAG. >>> Since this is a non-functional change, I've explicitly omitted bumping >>> the DEBIAN_TAG. >>> Seemingly I forgot to mention it in the commit message though, oopsie. >>> >>> Since the image will contain practically the same artefacts, is it >>> worth carving out 30 minutes (or so) from the runners? >> >> No, I agree that would be wasteful for this change alone. >> >> However, merging this change without bumping the tag isn't good either, >> because then any issues with it would only be discovered the next time >> it does get bumped. Hence my request above. > > I agree with Michel here, it's better to waste a re-gen now and notice > any issue right away. That's not exactly what I'm saying though. :) If you don't want to merge this together with other changes which bump the tag, how about: * Create an MR with an additional commit which bumps the tag * Wait for the CI pipeline to come back green * Force-push to the source branch without the additional commit, and merge the MR * Remove the ephemeral docker image from https://gitlab.freedesktop.org/evelikov/mesa/container_registry The CI pipeline information including the log of the job which generated the ephemeral docker image will remain accessible. -- Earthling Michel Dänzer | https://www.amd.com Libre software enthusiast | Mesa and X developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [AppVeyor] mesa master #12142 failed
Build mesa 12142 failed Commit 9de00e74fe by Gert Wollny on 7/25/2019 8:45 AM: virgl: Enable depth_clamp by lowering if the host is new enough.\n\nSigned-off-by: Gert Wollny \nReviewed-by: Reviewed-by: Marek Olšák Configure your notification preferences ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
