On Tue, 2016-09-13 at 22:12 -0700, Francisco Jerez wrote:
> Iago Toral writes:
>
> >
> > On Mon, 2016-09-12 at 14:05 -0700, Francisco Jerez wrote:
> > >
> > > Iago Toral Quiroga writes:
> > >
> > > >
> > > >
> > > > We will use this in cases where we want to force the vstride of
> > > > a
>
Just looking at the channel enables is not sufficient, at least not on Sky
Lake. Channels that are disabled by the sample_mask may show up in the
channel enable register as being enabled even if they are not executing.
This can cause FIND_LIVE_CHANNEL to return a channel that isn't actually
execut
On Mon, Sep 12, 2016 at 05:58:20PM -0700, Jason Ekstrand wrote:
> Compressed 1-D textures are a well-defined thing in both GL and Vulkan.
Looks correct to me:
Reviewed-by: Topi Pohjolainen
> ---
> src/intel/isl/isl.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git
so that the texture is rendered to back buffer before calling
flush_frontbuffer and can be copied to a different buffer in
the function
Signed-off-by: Nayan Deshmukh
---
src/gallium/state_trackers/vdpau/presentation.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src
so that the texture is rendered to back buffer before calling
flush_frontbuffer and can be copied to a different buffer in
the function
Signed-off-by: Nayan Deshmukh
---
src/gallium/state_trackers/va/surface.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/gallium/st
In case of prime when rendering is done on GPU other then the
server GPU, use a seprate linear buffer for each back buffer
which will be displayed using present extension.
v2: Use a seprate linear buffer for each back buffer (Michel)
v3: Change variable names and fix coding style (Leo and Emil)
v4
Iago Toral writes:
> On Mon, 2016-09-12 at 14:19 -0700, Francisco Jerez wrote:
>> Iago Toral Quiroga writes:
>>
>> >
>> > SIMD4x2 64bit data is stored in register space like this:
>> >
>> > r0.0:DF x0 y0 z0 w0
>> > r0.1:DF x1 y1 z1 w1
>> >
>> > When we need to write data such as this to me
Iago Toral writes:
> On Mon, 2016-09-12 at 14:05 -0700, Francisco Jerez wrote:
>> Iago Toral Quiroga writes:
>>
>> >
>> > We will use this in cases where we want to force the vstride of a
>> > src_reg
>> > to 0 to exploit a particular behavior of the hardware. It will come
>> > in
>> > handy t
Kenneth Graunke writes:
> This is mandatory.
This series is:
Reviewed-by: Eric Anholt
signature.asc
Description: PGP signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
On 14 September 2016 at 14:26, Jason Ekstrand wrote:
> Signed-off-by: Jason Ekstrand
After writing my own version, I now understand the code enough to review it,
The only thing I did different was to set a flag in the first switch
to avoid the second switch,
but otherwise this looks how it shou
We already support all of the decorations that require this capability.
Signed-off-by: Jason Ekstrand
---
src/compiler/spirv/spirv_to_nir.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 7e7a026..0c
Signed-off-by: Jason Ekstrand
---
src/compiler/spirv/vtn_glsl450.c | 54 +++-
1 file changed, 53 insertions(+), 1 deletion(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index e05d28f..cb0570d 100644
--- a/src/compiler/spir
On 14/09/16 02:53 AM, Marek Olšák wrote:
>
> cmake .. -G Ninja -DCMAKE_INSTALL_PREFIX=/usr/llvm/x86_64-linux-gnu
> -DLLVM_TARGETS_TO_BUILD="X86;AMDGPU" -DLLVM_ENABLE_ASSERTIONS=O
> -DCMAKE_BUILD_TYPE=RelWithDebInfo
> -DLLVM_BUILD_LLVM_DYLIB=ON -DLLVM_LINK_LLVM_DYLIB=ON \
>
Note that ASTC support is not actually mandated for this extension to be
exposed.
Signed-off-by: Ilia Mirkin
---
Also note that it doesn't seem required for the driver to simultaneously be
exposing an actual ES 3.2 context. The ext does, however, nominally require
GL 4.5. I think that can be ign
Seems reasonable. Perhaps it'd be worth figuring out what the deal
with CHV's ASTC support is, since that's probably a more likely
Android target. In the meanwhile, this is
Reviewed-by: Ilia Mirkin
On Tue, Sep 13, 2016 at 9:06 PM, Kenneth Graunke wrote:
> AEP requires ASTC, which is only suppor
AEP requires ASTC, which is only supported on Skylake and later.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index
For now that's never since advanced blend hasn't been piped through.
Signed-off-by: Ilia Mirkin
---
src/mesa/state_tracker/st_extensions.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
inde
Signed-off-by: Ilia Mirkin
---
src/mesa/state_tracker/st_extensions.c | 20
1 file changed, 20 insertions(+)
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 4d54928..55019d7 100644
--- a/src/mesa/state_tracker/st_extensions
Signed-off-by: Kenneth Graunke
---
src/compiler/nir/nir.h | 2 +-
src/compiler/nir/nir_lower_phis_to_scalar.c | 20 +++-
src/gallium/drivers/freedreno/ir3/ir3_nir.c | 2 +-
src/gallium/drivers/vc4/vc4_program.c | 3 +--
src/mesa/drivers/dri/i965/brw_n
Signed-off-by: Kenneth Graunke
---
src/compiler/nir/nir.h | 2 +-
src/compiler/nir/nir_lower_alu_to_scalar.c | 42 ++---
src/gallium/drivers/freedreno/ir3/ir3_nir.c | 2 +-
src/gallium/drivers/vc4/vc4_program.c | 2 +-
src/mesa/drivers/dri/i9
This is mandatory.
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke
---
src/compiler/nir/nir_lower_alu_to_scalar.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/compiler/nir/nir_lower_alu_to_scalar.c
b/src/compiler/nir/nir_lower_alu_to_scalar.c
index 4f72cf7..a8
Patches 2,3 and 5 are easy enough and so,
Reviewed-by: Edward O'Callaghan
Those numbers do look good but I think I'll leave the rest up to other
folks to review.
Kind Regards,
Edward.
On 09/14/2016 03:13 AM, Marek Olšák wrote:
> This is quite easy because we just have to get rid of all of
> the
On Tuesday, September 13, 2016 7:10:57 PM PDT Ilia Mirkin wrote:
> This also exposes them for ARB_ES3_2_compatibility.
>
> While both specs refer to the new MS line width parameters being
> separate from the existing AA line widths, reality begs to differ. It's
> the same on all hardware currently
On Tuesday, September 13, 2016 4:19:28 PM PDT Sirisha Gandikota wrote:
> From: Sirisha Gandikota
>
> This patch set simplifies parts of code in the aubinator tool
> as per review comments from Ken (Wed Aug 24 04:51:47 UTC 2016)
>
> v2 of the earlier patches simplifying code further as per Ken's
From: Sirisha Gandikota
This patch set simplifies parts of code in the aubinator tool
as per review comments from Ken (Wed Aug 24 04:51:47 UTC 2016)
v2 of the earlier patches simplifying code further as per Ken's comments
Sirisha Gandikota (3):
aubinator: Simplify print_dword_val() method
a
From: Sirisha Gandikota
Earlier, the loop pretends to loop over instructions from "start" to "end",
but the callers always pass 8192 for end, which is some huge bogus
value. The real loop termination condition is send-with-EOT or 0. (Ken)
v2: no change
Signed-off-by: Sirisha Gandikota
---
src
From: Sirisha Gandikota
Skylake adds new SENDS and SENDSC opcodes, which should be
handled in the send-with-EOT check. Make an is_send() helper
that checks if the opcode is SEND/SENDC/SENDS/SENDSC (Ken)
v2: Make is_send() much more crispier, Mix declaration and
code to make the code compact (Ken
From: Sirisha Gandikota
Remove the float/dword union and use the iter->p[f->start / 32]
directly as printf formatter %08x expects uint32_t (Ken)
v2: Make the cleanup much more crispier (Ken)
Signed-off-by: Sirisha Gandikota
---
src/intel/tools/aubinator.c | 12
1 file changed, 4
Signed-off-by: Ilia Mirkin
---
src/compiler/glsl/glsl_parser_extras.cpp | 58 +++-
src/compiler/glsl/glsl_parser_extras.h | 2 ++
src/mesa/main/extensions_table.h | 2 ++
src/mesa/main/mtypes.h | 1 +
4 files changed, 47 insertions(+), 16
This requires a bit of rejiggering, since normally ES entrypoints alias
core ones, not vice-versa.
Signed-off-by: Ilia Mirkin
Reviewed-by: Ian Romanick
---
src/mapi/glapi/gen/es_EXT.xml | 19 -
src/mapi/glapi/gen/gl_API.xml | 37 ++
This also exposes them for ARB_ES3_2_compatibility.
While both specs refer to the new MS line width parameters being
separate from the existing AA line widths, reality begs to differ. It's
the same on all hardware currently supported by mesa. Should hardware
come along that wants these to be diffe
On 09/13/2016 02:21 PM, Steven Toth wrote:
V3: Flatten the entire patchset ready for the ML
V2: Additional seperate patches based on feedback
a) configure.ac: Add a comment related to libsensors
b) HUD: Disable Block/NIC I/O stats by default.
Implement configuration option --enable-gallium-extr
On 09/13/2016 02:42 PM, Adam Jackson wrote:
On Tue, 2016-09-13 at 14:14 -0600, Kyle Brenneman wrote:
On 09/13/2016 11:57 AM, Adam Jackson wrote:
@@ -37,7 +39,7 @@
/* This should be kept in sync with _eglInitThreadInfo() */
#define _EGL_THREAD_INFO_INITIALIZER \
- { EGL_SUCCESS, NUL
Yes please, thanks!
On Tue, Sep 13, 2016 at 4:22 PM, Brian Paul wrote:
> On 09/13/2016 01:08 PM, Lars Hamre wrote:
>>
>> Fixes the following piglit test (for softpipe):
>> /spec/glsl-1.10/execution/fs-loop-return
>>
>> Signed-off-by: Lars Hamre
>>
>> ---
>> src/gallium/auxiliary/tgsi/tgsi_exec
On Tue, 2016-09-13 at 14:14 -0600, Kyle Brenneman wrote:
> On 09/13/2016 11:57 AM, Adam Jackson wrote:
> > @@ -37,7 +39,7 @@
> >
> > /* This should be kept in sync with _eglInitThreadInfo() */
> > #define _EGL_THREAD_INFO_INITIALIZER \
> > - { EGL_SUCCESS, NULL, 0, NULL, NULL, NULL }
> > +
> V3: Flatten the entire patchset ready for the ML
Compile tested on Windows via AppVeyor
Patches tested in various ./configure disable/enable modes on Ubuntu
16.04, 4.5.7 kernel on 32bit.
Many thanks to everyone who provided feedback.
--
Steven Toth - Kernel Labs
http://www.kernellabs.com
+1.6
From: Marek Olšák
26011 shaders in 14651 tests
Totals:
SGPRS: 1251920 -> 1152636 (-7.93 %)
VGPRS: 728421 -> 728198 (-0.03 %)
Spilled SGPRs: 16644 -> 3776 (-77.31 %)
Spilled VGPRs: 369 -> 369 (0.00 %)
Scratch VGPRs: 1344 -> 1344 (0.00 %) dwords per thread
Code Size: 36001064 -> 35835152 (-0.46 %)
From: Marek Olšák
v2: inline the code and remove the conditional that's a no-op now
---
src/gallium/drivers/radeonsi/si_shader.c | 47 ++--
1 file changed, 14 insertions(+), 33 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/
V3: Flatten the entire patchset ready for the ML
V2: Additional seperate patches based on feedback
a) configure.ac: Add a comment related to libsensors
b) HUD: Disable Block/NIC I/O stats by default.
Implement configuration option --enable-gallium-extra-hud=yes
and enable both statistics when thi
On 09/13/2016 01:08 PM, Lars Hamre wrote:
Fixes the following piglit test (for softpipe):
/spec/glsl-1.10/execution/fs-loop-return
Signed-off-by: Lars Hamre
---
src/gallium/auxiliary/tgsi/tgsi_exec.c | 4
1 file changed, 4 insertions(+)
NOTE: Someone with access will need to commit th
From: Marek Olšák
The LLVM compiler can CSE interp intrinsics thanks to
LLVMReadNoneAttribute.
26011 shaders in 14651 tests
Totals:
SGPRS: 1146340 -> 1132676 (-1.19 %)
VGPRS: 727371 -> 711730 (-2.15 %)
Spilled SGPRs: 2218 -> 2078 (-6.31 %)
Spilled VGPRs: 369 -> 369 (0.00 %)
Scratch VGPRs: 1344 -
On 09/13/2016 11:57 AM, Adam Jackson wrote:
From: Kyle Brenneman
This decorates every EGL entrypoint with _EGL_FUNC_START, which records
the function name and primary dispatch object label in the current
thread state. It also adds debug report functions and calls them when
appropriate.
This wo
On Tue, Sep 13, 2016 at 4:05 PM, Eric Anholt wrote:
> Ilia Mirkin writes:
>
>> On Mon, Sep 12, 2016 at 11:55 AM, Emil Velikov
>> wrote:
>>> On 12 September 2016 at 15:35, Ilia Mirkin wrote:
On Mon, Sep 12, 2016 at 10:10 AM, Emil Velikov
wrote:
> Keeping diff/patches in git alwa
Ilia Mirkin writes:
> On Mon, Sep 12, 2016 at 11:55 AM, Emil Velikov
> wrote:
>> On 12 September 2016 at 15:35, Ilia Mirkin wrote:
>>> On Mon, Sep 12, 2016 at 10:10 AM, Emil Velikov
>>> wrote:
Keeping diff/patches in git always felt like a hack, imho. Plus
most/all(?) distros rely
https://bugs.freedesktop.org/show_bug.cgi?id=97261
Andy Furniss changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
With OP_ADD3, we might want to swap sources 2 and 1.
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 29 ++
1 file changed, 29 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/n
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index fe815e3..ecde364
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 55 ++
1 file changed, 55 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index f212eba..fe8
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 8
1 file changed, 8 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index ecde364..246cdff 10064
Signed-off-by: Samuel Pitoiset
---
.../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 34 ++
1 file changed, 34 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index cfde66c.
And ADD3(d, a, 0x0, c) to ADD(d, a, c) as well.
v2: - use moveSources()
- allow ADD3 -> ADD when srcFlags is set
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/gallium/
This instruction is new since SM50 (Maxwell) and allows to perform
an add with three sources. Unfortunately, it only supports integers.
v3: - set commutative flag for OP_ADD3
- move OP_ADD3 after arithmetic ops
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h
This is similar to what we already do for MAD/FMA.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/d
And ADD3(d, a, b, c) to ADD(d, b, a + c) as well.
Very modest effect because OP_ADD3 only supports integers, but can
reduce the number of instructions in some shaders.
total instructions in shared programs :2594754 -> 2594686 (-0.00%)
total gprs used in shared programs:366893 -> 366919 (0.01%
Fixes the following piglit test (for softpipe):
/spec/glsl-1.10/execution/fs-loop-return
Signed-off-by: Lars Hamre
---
src/gallium/auxiliary/tgsi/tgsi_exec.c | 4
1 file changed, 4 insertions(+)
NOTE: Someone with access will need to commit this
after the review process
diff --git
https://bugs.freedesktop.org/show_bug.cgi?id=94627
--- Comment #9 from Heiko Ernst ---
Bug is closed in mesa 12.0.2
--
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the bug.___
mesa-dev mailing list
This patch switches non-TGSI compute shaders over to using the HSA
ABI described here:
https://github.com/RadeonOpenCompute/ROCm-Docs/blob/master/AMDGPU-ABI.md
The HSA ABI provides a much cleaner interface for compute shaders and allows
us to share more code in the compiler with the HSA stack.
T
---
src/gallium/drivers/radeonsi/si_compute.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_compute.c
b/src/gallium/drivers/radeonsi/si_compute.c
index 5041761..a79c224 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeon
Andy Furniss wrote:
Leo Liu wrote:
mpv --vo-vaapi all is apparently OK when playing say a 25fps vid,
but I've found that if I push the framerate to refresh rate and
do something that draws OSD than image is corrupted, possible many
VM faults logged followed by a segfault in u_copy_yv12_img_to_
On Tue, Sep 13, 2016 at 8:16 PM, Nicolai Hähnle wrote:
>
> On 13.09.2016 19:13, Marek Olšák wrote:
>>
>> This is quite easy because we just have to get rid of all of
>> the preloading at the beginning of shaders.
>>
>> I also removed preloading of PS inputs with literal indexing, which
>> has almo
Thanks a lot! I'll try that tonight!
I have a 64-bit distrib, I don't think so but do I need to compile the 32-bit
version of llvm as well (is it because Steam is using 32-bit libraries?).
2016-09-13 13:53 GMT-04:00 Marek Olšák :
> LLVM 64-bit:
>
> mkdir -p build
> cd build
> cmake .. -G Ninja -D
On Tue, 2016-09-13 at 19:18 +0100, Emil Velikov wrote:
> For the series as a whole ?
> Two words which contradict any software's stable scheme - new feature.
Disagree, but I'm not the one running Mesa's stable branch, so my
opinion doesn't count here.
- ajax
_
From: Marc-André Lureau
When updating the sampler views, virgl might need to flush. After
flushing, the resources are reattached, however, the sampler
enabled_mask isn't yet updated, and some views could be in the process
of being removed, which lead to the following crash:
Thread 1 "heaven_x64
On 13 September 2016 at 19:14, Adam Jackson wrote:
> On Tue, 2016-09-13 at 17:22 +0100, Emil Velikov wrote:
>
>> Actually, current code has a bunch of such bugs which this series addresses.
>> Considering there's only a couple of those and they are pretty hard to
>> hit I won't bother with respinn
Leo Liu wrote:
On 09/13/2016 01:29 PM, Andy Furniss wrote:
Leo Liu wrote:
Hi Andy,
On 09/13/2016 06:22 AM, Andy Furniss wrote:
Zhang, Boyuan wrote:
Hi Leo, Christian and Julien,
I tested the patch with Vaapi Encoding and Transcoding, it seems
working fine. We are using "VAAPI_DISABLE_INTE
On 13.09.2016 19:13, Marek Olšák wrote:
This is quite easy because we just have to get rid of all of
the preloading at the beginning of shaders.
I also removed preloading of PS inputs with literal indexing, which
has almost the same effect as sinking interp instructions.
I'm slightly concerned
On 13 September 2016 at 18:55, Adam Jackson wrote:
> On Tue, 2016-09-13 at 17:17 +0100, Emil Velikov wrote:
>
>> > + } else {
>> > + _eglDebugReportFull(EGL_BAD_ALLOC, __func__, __func__,
>> > + EGL_DEBUG_MSG_CRITICAL_KHR, NULL, NULL);
>> > + return EGL_BAD_ALLOC
On Tue, 2016-09-13 at 17:22 +0100, Emil Velikov wrote:
> Actually, current code has a bunch of such bugs which this series addresses.
> Considering there's only a couple of those and they are pretty hard to
> hit I won't bother with respinning the patches.
>
> That is unless we want them for stab
On 13.09.2016 19:13, Marek Olšák wrote:
From: Marek Olšák
The LLVM compiler can CSE interp intrinsics thanks to
LLVMReadNoneAttribute.
26011 shaders in 14651 tests
Totals:
SGPRS: 1146340 -> 1132676 (-1.19 %)
VGPRS: 727371 -> 711730 (-2.15 %)
Spilled SGPRs: 2218 -> 2078 (-6.31 %)
Spilled VGPRs:
Marek Olšák wrote on 13.09.2016 19:53:
> LLVM 64-bit:
>
> mkdir -p build
> cd build
> cmake .. -G Ninja -DCMAKE_INSTALL_PREFIX=/usr/llvm/x86_64-linux-gnu
> -DLLVM_TARGETS_TO_BUILD="X86;AMDGPU" -DLLVM_ENABLE_ASSERTIONS=O
> -DCMAKE_BUILD_TYPE=RelWithDebInfo
> -DLLVM_BUILD_LLVM_DYLI
On 13.09.2016 19:13, Marek Olšák wrote:
From: Marek Olšák
26011 shaders in 14651 tests
Totals:
SGPRS: 1251920 -> 1152636 (-7.93 %)
VGPRS: 728421 -> 728198 (-0.03 %)
Spilled SGPRs: 16644 -> 3776 (-77.31 %)
Spilled VGPRs: 369 -> 369 (0.00 %)
Scratch VGPRs: 1344 -> 1344 (0.00 %) dwords per thread
On 09/13/2016 01:29 PM, Andy Furniss wrote:
Leo Liu wrote:
Hi Andy,
On 09/13/2016 06:22 AM, Andy Furniss wrote:
Zhang, Boyuan wrote:
Hi Leo, Christian and Julien,
I tested the patch with Vaapi Encoding and Transcoding, it seems
working fine. We are using "VAAPI_DISABLE_INTERLACE" env, so
i
On Mon, Sep 12, 2016 at 3:50 PM, Jason Ekstrand wrote:
> The Vulkan driver sets 3DSTATE_DRAWING_RECTANGLE once to MAX_INT x MAX_INT
> at the GPU initialization time and never sets it again. The GL driver sets
> it every time the framebuffer changes. Originally, blorp set it to the
> size of the
On 13.09.2016 19:13, Marek Olšák wrote:
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 67
1 file changed, 34 insertions(+), 33 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
ind
From: Kyle Brenneman
v2:
- Pass disp to RETURN_EGL_ERROR so we unlock the display
---
src/egl/main/eglapi.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index a74e5e4..ba4826a 100644
--- a/src/egl/main/eglap
From: Kyle Brenneman
Wire up the debug entrypoints to EGL dispatch, and add the extension
string to the client extension list.
v2:
- Lots of style fixes
- Fix missing EGLAPIENTRYs
- Factor out valid attribute check
- Lock display in eglLabelObjectKHR as needed, and use RETURN_EGL_*
- Move "EGL_K
From: Kyle Brenneman
This decorates every EGL entrypoint with _EGL_FUNC_START, which records
the function name and primary dispatch object label in the current
thread state. It also adds debug report functions and calls them when
appropriate.
This would be useful enough for debugging on its own,
On Tue, 2016-09-13 at 17:17 +0100, Emil Velikov wrote:
> > + } else {
> > + _eglDebugReportFull(EGL_BAD_ALLOC, __func__, __func__,
> > + EGL_DEBUG_MSG_CRITICAL_KHR, NULL, NULL);
> > + return EGL_BAD_ALLOC;
> > + }
>
> Nit: Please use the same style as the "
LLVM 64-bit:
mkdir -p build
cd build
cmake .. -G Ninja -DCMAKE_INSTALL_PREFIX=/usr/llvm/x86_64-linux-gnu
-DLLVM_TARGETS_TO_BUILD="X86;AMDGPU" -DLLVM_ENABLE_ASSERTIONS=O
-DCMAKE_BUILD_TYPE=RelWithDebInfo
-DLLVM_BUILD_LLVM_DYLIB=ON -DLLVM_LINK_LLVM_DYLIB=ON \
-DCM
On Tue, Sep 13, 2016 at 10:46 AM, Chad Versace
wrote:
> On Thu 08 Sep 2016, Jason Ekstrand wrote:
> > ---
> > src/intel/isl/isl_surface_state.c | 15 ++-
> > 1 file changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/src/intel/isl/isl_surface_state.c
> b/src/intel/isl/isl_s
On Thu 08 Sep 2016, Jason Ekstrand wrote:
> ---
> src/intel/isl/isl_surface_state.c | 15 ++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/isl/isl_surface_state.c
> b/src/intel/isl/isl_surface_state.c
> index f8ea122..22fef3d 100644
> --- a/src/intel/i
On Thu 08 Sep 2016, Jason Ekstrand wrote:
> ---
> src/intel/isl/isl_surface_state.c | 17 -
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/isl/isl_surface_state.c
> b/src/intel/isl/isl_surface_state.c
> index 979e140..f8ea122 100644
> --- a/src/intel
On Tue 13 Sep 2016, Jason Ekstrand wrote:
> The time we want to restrict the Z range of a 3-D surface is when rendering
> to it. For storage surfaces, we always want he full range. However, we
Typo --^^
> still need to set MinimumArrayElement and RenderTarg
On 09/13/2016 10:17 AM, Emil Velikov wrote:
Hi guys,
There's a bunch of outstanding style nitpicks (come to think of it
13/14 could use the same)
Those aside: there's a bunch of serious suggestions which I missed last time.
On 12 September 2016 at 23:19, Adam Jackson wrote:
From: Kyle Brenne
The comment for the commutative flags was wrong because OP_MUL is
before OP_MAD. While we are at it add missing opcodes, and fix
the comment about the short forms.
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 5 +++--
1 file changed, 3 insertio
2016-09-13 12:41 GMT-04:00 Marek Olšák :
>
> BTW, If you update LLVM to a newer version, you also have to re-build
> Mesa, because the LLVM version used by Mesa is determined while Mesa
> is being built.
>
> Also, the chance to rage-quit while building LLVM+Mesa is pretty high
> if you've never don
On Tue 13 Sep 2016, Nanley Chery wrote:
> On Wed, Sep 07, 2016 at 03:51:14PM -0700, Chad Versace wrote:
> > On Wed 07 Sep 2016, Nanley Chery wrote:
> > > On Fri, Sep 02, 2016 at 11:42:24AM -0700, Chad Versace wrote:
> > > > On Thu 01 Sep 2016, Jason Ekstrand wrote:
> > > > > On Wed, Aug 31, 2016 at
>> It looks like the winflexbison URL changed some time ago. But this
>> didn't cause any build failures because the ZIP was being recovered from
>> the cache.
>>
>> I'll look into it.
>>
>> Jose
>
>
> It looks the archive was moved into a old_versions subdir.
>
> The attached patch should fix it.
Leo Liu wrote:
Hi Andy,
On 09/13/2016 06:22 AM, Andy Furniss wrote:
Zhang, Boyuan wrote:
Hi Leo, Christian and Julien,
I tested the patch with Vaapi Encoding and Transcoding, it seems
working fine. We are using "VAAPI_DISABLE_INTERLACE" env, so
interlaced is always disabled.
Though I notice
On Mon, Sep 12, 2016 at 3:50 PM, Jason Ekstrand wrote:
> Signed-off-by: Jason Ekstrand
> ---
> .../genX_multisample.h => common/gen_sample_positions.h} | 10 +-
> src/intel/vulkan/genX_blorp_exec.c | 10 +-
> src/intel/vulkan/genX_pipeline_util.h
This patchset makes eglExportDMABUFImageMESA return corresponding offset
of EGLImage instead of 0 on intel platfrom with classic dri driver(i965).
v2: Add version check of __DRIimageExtension implementation in egl loader
(Suggested by Axel Davy).
v3: Don't add version check of __DRIimageExtension
The offset should not always be 0. For example, if EGLImage is
created from a 2D texture with EGL_GL_TEXTURE_LEVEL=1, then the
offset should be the actual start of miplevel 1 in bo.
v2: Add version check of __DRIimageExtension implementation
(Suggested by Axel Davy).
v3: Don't add version check o
Offset is useful for buffer sharing with other components, so add
it to queryImage attributes.
Signed-off-by: Chuanbo Weng
---
include/GL/internal/dri_interface.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/GL/internal/dri_interface.h
b/include/GL/internal/dri
Implement querying this attribute in intelImageExtension and bump
version of intelImageExtension.
Signed-off-by: Chuanbo Weng
---
src/mesa/drivers/dri/i965/intel_screen.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 696f67b..3f77714 100644
--- a/src/gallium/drivers
From: Marek Olšák
26011 shaders in 14651 tests
Totals:
SGPRS: 1251920 -> 1152636 (-7.93 %)
VGPRS: 728421 -> 728198 (-0.03 %)
Spilled SGPRs: 16644 -> 3776 (-77.31 %)
Spilled VGPRs: 369 -> 369 (0.00 %)
Scratch VGPRs: 1344 -> 1344 (0.00 %) dwords per thread
Code Size: 36001064 -> 35835152 (-0.46 %)
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 67
1 file changed, 34 insertions(+), 33 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index be6fae7..b9ad4be 100644
--- a/src/galli
From: Marek Olšák
The LLVM compiler can CSE interp intrinsics thanks to
LLVMReadNoneAttribute.
26011 shaders in 14651 tests
Totals:
SGPRS: 1146340 -> 1132676 (-1.19 %)
VGPRS: 727371 -> 711730 (-2.15 %)
Spilled SGPRs: 2218 -> 2078 (-6.31 %)
Spilled VGPRs: 369 -> 369 (0.00 %)
Scratch VGPRs: 1344 -
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index b9ad4be..696f67b 100644
--- a/src/gallium/drivers/radeonsi/si_shad
From: Marek Olšák
26011 shaders in 14651 tests
Totals:
SGPRS: 1152636 -> 1146340 (-0.55 %)
VGPRS: 728198 -> 727371 (-0.11 %)
Spilled SGPRs: 3776 -> 2218 (-41.26 %)
Spilled VGPRs: 369 -> 369 (0.00 %)
Scratch VGPRs: 1344 -> 1344 (0.00 %) dwords per thread
Code Size: 35835152 -> 35841268 (0.02 %) by
1 - 100 of 160 matches
Mail list logo
