Re: [Mesa-dev] [PATCH 23/34] i965: Add logic for allocating BO with CCS

On 17-01-31 13:03:52, Jason Ekstrand wrote: On Wed, Jan 25, 2017 at 10:36 AM, Pohjolainen, Topi < topi.pohjolai...@gmail.com> wrote: On Mon, Jan 23, 2017 at 10:21:46PM -0800, Ben Widawsky wrote: > This patch provides the support (and comments) for allocating the BO > with space for the CCS

[Mesa-dev] [PATCH v2] i965: Allocate tile aligned height

This patch shouldn't actually do anything because the libdrm function should already do this alignment. However, it preps us for a future patch where we add in the CCS AUX size, and in the process it serves as a good place to find bisectable issues if libdrm or kernel does something incorrectly.

Re: [Mesa-dev] [PATCH] gbm: add support for loading third-party backend

On 06/02/17 03:48 PM, Yu, Qiang wrote: > > Dose this mean if the amdgpu_dri.so is compatible with GBM DRI backend, > it will also compatible with libGL.so and xserver libglx.so (do these use > same loader/DRI-ABI as GBM DRI backend)? Yes, they do. -- Earthling Michel Dänzer |

Re: [Mesa-dev] [PATCH] gbm: add support for loading third-party backend

Dose this mean if the amdgpu_dri.so is compatible with GBM DRI backend, it will also compatible with libGL.so and xserver libglx.so (do these use same loader/DRI-ABI as GBM DRI backend)? Regards, Qiang From: Michel Dänzer Sent:

Re: [Mesa-dev] [PATCH 20/34] i965: Restructure CCS disable

On 17-01-25 20:53:44, Topi Pohjolainen Topi Pohjolainen wrote: On Mon, Jan 23, 2017 at 10:21:43PM -0800, Ben Widawsky wrote: Make the code only disable CCS when it has to, unlike before where it disabled CCS and enabled it when it could. This is much more inline with how it should work in a few

Re: [Mesa-dev] [PATCH] gbm: add support for loading third-party backend

On 06/02/17 02:58 PM, Yu, Qiang wrote: > >> * The ImgTec guys were able to tweak their binary which combined with >> a bit of mesa glue produces a DRI module. >> This in itself lead of a number of nice improvements and fixes that >> landed in Mesa. Have you/others considered that option ? > [yuq]

Re: [Mesa-dev] [PATCH] gbm: add support for loading third-party backend

+ David Hi Emil, > * With the discussion(s) about liballoc/libgbm2 in motion wouldn't it > be better to focus/target it ? [yuq] I think this small improvement won't conflict with libgbm2 work which is not my current focus. My purpose is getting current mesa co-exist with amdgpu-pro. BTW. will

Re: [Mesa-dev] [PATCH] gbm: add support for loading third-party backend

Thanks Nicolai, I'll address the gbmint.h and ABI version next version. Regards, Qiang From: Nicolai Hähnle Sent: Tuesday, January 24, 2017 6:12:06 PM To: Yu, Qiang; mesa-dev@lists.freedesktop.org Subject: Re: [Mesa-dev] [PATCH] gbm:

Re: [Mesa-dev] [PATCH 18/34] i965/miptree: Add a helper functions for image creation

On 17-01-31 12:54:33, Jason Ekstrand wrote: On Wed, Jan 25, 2017 at 10:58 AM, Pohjolainen, Topi < topi.pohjolai...@gmail.com> wrote: On Mon, Jan 23, 2017 at 10:21:41PM -0800, Ben Widawsky wrote: > This provides a common function or creating miptrees when there is an > existing DRIimage to use.

[Mesa-dev] [Bug 99591] Segmentation fault when running vulkaninfo with RADV Radeon Vulkan driver

https://bugs.freedesktop.org/show_bug.cgi?id=99591 Petr Cervinka changed: What|Removed |Added CC||p...@cervinka.net --

Re: [Mesa-dev] [PATCH 16/34] i965: Separate image allocation with modifiers

On 17-01-31 13:01:11, Jason Ekstrand wrote: On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky wrote: Since the code doesn't support modifiers yet, this patch should do nothing other than prepare for more patches. Signed-off-by: Ben Widawsky Acked-by:

Re: [Mesa-dev] [PATCH 12/34] i965: Handle Y-tile modifier

On 17-01-31 12:10:11, Jason Ekstrand wrote: On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky wrote: This patch begins introducing how we'll actually handle the potentially many modifiers coming in from the API, how we'll store them, and the structure in the code to support

[Mesa-dev] [PATCH v5] gbm: Introduce modifiers into surface/bo creation

The idea behind modifiers like this is that the user of GBM will have some mechanism to query what properties the hardware supports for its BO or surface. This information is directly passed in (and stored) so that the DRI implementation can create an image with the appropriate attributes. A

Re: [Mesa-dev] [PATCH 10/34] gbm: Introduce modifiers into surface/bo creation

On 17-01-31 11:52:38, Jason Ekstrand wrote: On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky wrote: The idea behind modifiers like this is that the user of GBM will have some mechanism to query what properties the hardware supports for its BO or surface. This information is

[Mesa-dev] [PATCH v3] gbm: Export a per plane getter for offset

Unlike stride, there was no previous offset getter, so it can be right on the first try. v2: Return EINVAL when plane is greater than total planes to make it match the similar APIs. Avoid leak after fromPlanar (Daniel) Make sure when getting offsets we consider dumb images (Daniel) v3: Use

[Mesa-dev] [PATCH v3] gbm: Export a per plane getter for stride

v2: Preserve legacy behavior when plane is 0 (Jason Ekstrand) EINVAL when input plane is greater than total planes (Jason Ekstrand) Don't leak the image after fromPlanar (Daniel) Move bo->image check below plane count preventing bad index succeeding (Daniel) v3: Fix DRIimage leak (using Jason's

[Mesa-dev] [PATCH] radv/ac: avoid the fmask path when doing txs.

From: Dave Airlie This fixes the vulkan samples deferredmultisampling test. Cc: "17.0" Signed-off-by: Dave Airlie --- src/amd/common/ac_nir_to_llvm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git

Re: [Mesa-dev] [PATCH] glsl: binding qualifier must match with opaque-uniforms only

Reviewed-by: Edward O'Callaghan On 02/06/2017 05:53 AM, Andres Gomez wrote: > The binding point is a valid layout qualifier for Uniform Blocks, > Shader Storage Blocks and Opaque-Uniforms. > > From page 60 (page 66 of the PDF) of the GLSL 4.20 spec, v11: > > " A

Re: [Mesa-dev] [Freedreno] WebProcess crash on DB410c

Thanks Rob for your inputs. Yes, you are looking at the right place. But the HiKey which takes same pbuffer path and it working with Mali is the reference now. I'm trying to write a simple egl app that uses pbuffer to confirm the support with Mesa. Does it sounds correct or you have any

Re: [Mesa-dev] [Freedreno] WebProcess crash on DB410c

One more point is westeros always return null window for offscreen target, that why WPE falls back to pbuffer on HiKey and DB410c cases. On 3 February 2017 at 11:30, Sivasubramanian Patchaiperumal < sivasubramanian.patchaiperu...@linaro.org> wrote: > Thanks Rob for your inputs. Yes, you are

[Mesa-dev] Time to merge threaded GL dispatch? (aka glthread)

Hi, Back in 2012-2013, then-Intel employees Eric Anholt and Paul Berry wrote this threaded GL dispatch where GL calls are queued and executed in a different thread. It was supposed to deal with high CPU overhead of Mesa, but at the time most games used the compatibility profile and Steam didn't

[Mesa-dev] [Bug 97967] glsl/tests/cache-test regression

https://bugs.freedesktop.org/show_bug.cgi?id=97967 --- Comment #11 from Timothy Arceri --- FRom the gentoo bug: "This only happens with ABI_X86=32, the test passes for native abi." -- You are receiving this mail because: You are the assignee for the bug. You are the QA

Re: [Mesa-dev] [PATCH 14/34] gbm: Get modifiers from DRI

On 17-01-31 12:38:44, Jason Ekstrand wrote: On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky wrote: Replace the naive, 'save all the modifiers' with a proper query for just the modifier that was selected. To accomplish this, two new query tokens are added to the extension:

[Mesa-dev] [Bug 99591] Segmentation fault when running vulkaninfo with RADV Radeon Vulkan driver

https://bugs.freedesktop.org/show_bug.cgi?id=99591 --- Comment #3 from Petr Cervinka --- (In reply to Vedran Miletić from comment #1) > Can you try newer vulkaninfo? Some segfaults were fixed recently. I tested it on openSUSE with vulkan info 1.0.39.1, but the results are the

[Mesa-dev] [PATCH] glsl: binding qualifier must match with opaque-uniforms only

The binding point is a valid layout qualifier for Uniform Blocks, Shader Storage Blocks and Opaque-Uniforms. From page 60 (page 66 of the PDF) of the GLSL 4.20 spec, v11: " A link error will result if two compilation units in a program specify different integer-constant bindings for the

[Mesa-dev] [PATCH 8/8] nvc0: expose int64 on pre-maxwell

Everything should be ready to go on maxwell as well, but the sched code calculator ends up causing a lot of failures with the generated code. Since this is a fringe feature, leave it out until the sched code logic is improved. Signed-off-by: Ilia Mirkin ---

[Mesa-dev] [PATCH 7/8] nvc0/ir: add support for 64-bit shift lowering on SM20/SM30

Unfortunately there is no SHF.L/SHF.R instruction pre-SM35. So we have to do a bit more work to get the job done. Signed-off-by: Ilia Mirkin --- .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 68 -- 1 file changed, 62 insertions(+), 6 deletions(-)

[Mesa-dev] [PATCH 4/8] nvc0/ir: add a "high" subop for shifts, emit shf.l/shf.r for 64-bit

Note that this is not available for SM20/SM30. Signed-off-by: Ilia Mirkin --- src/gallium/drivers/nouveau/codegen/nv50_ir.h | 1 + .../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 24 +- .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 52

[Mesa-dev] [PATCH 6/8] nvc0/ir: add support for all the new int64 tgsi opcodes

Signed-off-by: Ilia Mirkin --- .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 222 - .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 67 ++- .../nouveau/codegen/nv50_ir_lowering_nvc0.h| 2 +

[Mesa-dev] [PATCH 5/8] nv50/ir: Split 64-bit integer MAD/MUL operations

From: Pierre Moreau Hardware does not support 64-bit integers MAD and MUL operations, so we need to transform them in 32-bit operations. Signed-off-by: Pierre Moreau --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 116

[Mesa-dev] [PATCH 3/8] nvc0/ir: fix SET and SLCT emission

We were never emitting a .X flag for consuming condition code on SET, and weren't emitting a signed type for SLCT comparison. Discovered while working on int64 logic. Signed-off-by: Ilia Mirkin --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 4

[Mesa-dev] [PATCH 2/8] nvc0/ir: add support for emitting partial min/max ops for int64

These operations allow you to compute min/max on arbitrary-width integers, 32 bits at a time. Note that the low/med ops implicitly set the condition code, and the med/high ops implicitly consume it. Signed-off-by: Ilia Mirkin ---

[Mesa-dev] [PATCH 1/8] gallium: add separate PIPE_CAP_INT64_DIVMOD

Nouveau does not currently have logic to implement this as a library function. Even though such a library could be written, there's no big advantage to do it that way for now given that int64 is a very uncommon use-case. Allow a driver to expose INT64 without supporting division and modulo

[Mesa-dev] [Bug 97879] [amdgpu] Rocket League: long hangs (several seconds) when loading assets (models/textures/shaders?)

https://bugs.freedesktop.org/show_bug.cgi?id=97879 andrei.demin1...@gmail.com changed: What|Removed |Added CC||andrei.demin1...@gmail.com

Re: [Mesa-dev] [PATCH 06/34] gbm: Export a per plane getter for stride

Hi, On 4 February 2017 at 05:29, Ben Widawsky wrote: > On 17-01-31 11:33:39, Jason Ekstrand wrote: >> On Mon, Jan 23, 2017 at 10:19 PM, Ben Widawsky wrote: >>> + /* Preserve legacy behavior if plane is 0 */ >>> + if (plane == 0) >>> + return

Re: [Mesa-dev] [RFC PATCH 1/1] st/dri: add a new driconf option override_glsl_version for ARK games

On 02/03/2017 07:48 PM, Bas Nieuwenhuizen wrote: On Fri, Feb 3, 2017, at 19:24, Jason Ekstrand wrote: On Fri, Feb 3, 2017 at 9:23 AM, Samuel Pitoiset > wrote: This is similar to the MESA_GLSL_VERSION_OVERRIDE envvar (mainly

Re: [Mesa-dev] [RFC PATCH 1/1] st/dri: add a new driconf option override_glsl_version for ARK games

On 02/03/2017 07:24 PM, Jason Ekstrand wrote: On Fri, Feb 3, 2017 at 9:23 AM, Samuel Pitoiset > wrote: This is similar to the MESA_GLSL_VERSION_OVERRIDE envvar (mainly for developers). But this one has the advantage to be

Re: [Mesa-dev] [PATCH 0/8] radv: implement sparseBinding

From what I understand this series is, Reviewed-by: Edward O'Callaghan A few rather trivial style bits to be fixed pertaining of space before '(', e.g., 'if(..)' -> 'if ('. On 02/05/2017 10:43 PM, Bas Nieuwenhuizen wrote: > This implements the sparseBinding feature

[Mesa-dev] [PATCH 7/8] radv/amdgpu: Use reference counting for bos.

Per the Vulkan spec, memory objects may be deleted before the buffers and images using them are deleted, although those resources then cannot be used except for deletion themselves. For the virtual buffers, we need to access them on resource destruction to unmap the regions, so this results in a

[Mesa-dev] [PATCH 6/8] radv: Implement sparse memory binding.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 75 +--- 1 file changed, 71 insertions(+), 4 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 1e92046d62c..d501be3793f 100644

[Mesa-dev] [PATCH 5/8] radv: Implement sparse image creation.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_image.c | 23 +-- src/amd/vulkan/radv_private.h | 1 + 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index

[Mesa-dev] [PATCH 8/8] radv: Enable sparseBinding feature.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index d501be3793f..4db58929a42 100644 ---

[Mesa-dev] [PATCH 1/8] radv/amdgpu: Allow submitting 0 command buffers.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 7 +-- src/amd/vulkan/radv_radeon_winsys.h | 1 + src/amd/vulkan/radv_wsi.c | 3 ++- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 12 4

[Mesa-dev] [PATCH 3/8] radv/amdgpu: Add winsys implementation of virtual buffers.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_radeon_winsys.h | 5 + src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 218 +++--- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.h | 35 - src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c |

[Mesa-dev] [PATCH 2/8] radv: Better handle submitting 0 command buffers.

If we had submitCount >0, but each submit had zero command buffers, then we still wouldn't signal the fence. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 18 +- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH 4/8] radv: Implement sparse buffer creation.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 22 -- src/amd/vulkan/radv_private.h | 1 + 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index

[Mesa-dev] [PATCH 0/8] radv: implement sparseBinding

This implements the sparseBinding feature radv. The feature name is a misnomer, as all the resources still have to be completely backed by memore. However, that can be done independently of descriptor generation, so we have to work with blocks of address space already. This feature does not need

[Mesa-dev] [Bug 99517] [TRACKER] Mesa 17.0 release tracker

https://bugs.freedesktop.org/show_bug.cgi?id=99517 Mark Janes changed: What|Removed |Added Depends on|96907 | Referenced Bugs: