[Mesa-dev] [PATCH V4 4/4] r600/radeonsi: enable glsl/tgsi on-disk cache

[Timothy Arceri]

For gpu generations that use LLVM we create a timestamp string
containing both the LLVM and Mesa build times, otherwise we just
use the Mesa build time.

V2: share code in r600_pipe_common as suggested by Marek.

V3: send the correct revision of V2

V4: rework the order we check chip_class so that we don't append
llvm timestamp when not needed and also don't fallback to a mesa only
timestamp when we must have the llvm timestamp but generation failed.
---
 src/gallium/drivers/radeon/r600_pipe_common.c | 43 +++
 src/gallium/drivers/radeon/r600_pipe_common.h |  3 ++
 2 files changed, 46 insertions(+)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 1781584..bae6d6f 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -43,6 +43,10 @@
 #define HAVE_LLVM 0
 #endif
 
+#if HAVE_LLVM
+#include 
+#endif
+
 #ifndef MESA_LLVM_VERSION_PATCH
 #define MESA_LLVM_VERSION_PATCH 0
 #endif
@@ -779,6 +783,41 @@ static const char* r600_get_chip_name(struct 
r600_common_screen *rscreen)
}
 }
 
+static void r600_disk_cache_create(struct r600_common_screen *rscreen)
+{
+   uint32_t mesa_timestamp;
+   if (disk_cache_get_function_timestamp(r600_disk_cache_create,
+ _timestamp)) {
+   char *timestamp_str;
+   int res = -1;
+   if (rscreen->chip_class < SI) {
+   res = asprintf(_str, "%u",mesa_timestamp);
+   }
+#if HAVE_LLVM
+   else {
+   uint32_t llvm_timestamp;
+   if 
(disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
+ _timestamp)) 
{
+   res = asprintf(_str, "%u_%u",
+  mesa_timestamp, llvm_timestamp);
+   }
+   }
+#endif
+   if (res != -1) {
+   rscreen->disk_shader_cache =
+   disk_cache_create(r600_get_chip_name(rscreen),
+ timestamp_str);
+   free(timestamp_str);
+   }
+   }
+}
+
+static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen 
*pscreen)
+{
+   struct r600_common_screen *rscreen = (struct 
r600_common_screen*)pscreen;
+   return rscreen->disk_shader_cache;
+}
+
 static const char* r600_get_name(struct pipe_screen* pscreen)
 {
struct r600_common_screen *rscreen = (struct 
r600_common_screen*)pscreen;
@@ -1234,6 +1273,7 @@ bool r600_common_screen_init(struct r600_common_screen 
*rscreen,
rscreen->b.get_name = r600_get_name;
rscreen->b.get_vendor = r600_get_vendor;
rscreen->b.get_device_vendor = r600_get_device_vendor;
+   rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
rscreen->b.get_compute_param = r600_get_compute_param;
rscreen->b.get_paramf = r600_get_paramf;
rscreen->b.get_timestamp = r600_get_timestamp;
@@ -1259,6 +1299,8 @@ bool r600_common_screen_init(struct r600_common_screen 
*rscreen,
rscreen->chip_class = rscreen->info.chip_class;
rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", 
common_debug_options, 0);
 
+   r600_disk_cache_create(rscreen);
+
slab_create_parent(>pool_transfers, sizeof(struct 
r600_transfer), 64);
 
rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", 
-1));
@@ -1324,6 +1366,7 @@ void r600_destroy_common_screen(struct r600_common_screen 
*rscreen)
 
slab_destroy_parent(>pool_transfers);
 
+   disk_cache_destroy(rscreen->disk_shader_cache);
rscreen->ws->destroy(rscreen->ws);
FREE(rscreen);
 }
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index e8dbf5d..92b9532 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -36,6 +36,7 @@
 
 #include "radeon/radeon_winsys.h"
 
+#include "util/disk_cache.h"
 #include "util/u_blitter.h"
 #include "util/list.h"
 #include "util/u_range.h"
@@ -404,6 +405,8 @@ struct r600_common_screen {
boolhas_cp_dma;
boolhas_streamout;
 
+   struct disk_cache   *disk_shader_cache;
+
struct slab_parent_pool pool_transfers;
 
/* Texture filter settings. */
-- 
2.9.3

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[Mesa-dev] [PATCH] util/disk_cache: create timestamp and gpu_id dirs when MESA_GLSL_CACHE_DIR is used

[Timothy Arceri]

The make check test is also updated to make sure these dirs are created.
---
 src/compiler/glsl/tests/cache_test.c | 40 
 src/util/disk_cache.c| 10 +++--
 2 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/src/compiler/glsl/tests/cache_test.c 
b/src/compiler/glsl/tests/cache_test.c
index ba56441..c4e6e36 100644
--- a/src/compiler/glsl/tests/cache_test.c
+++ b/src/compiler/glsl/tests/cache_test.c
@@ -31,6 +31,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include "util/mesa-sha1.h"
 #include "util/disk_cache.h"
@@ -40,6 +42,16 @@ bool error = false;
 #ifdef ENABLE_SHADER_CACHE
 
 static void
+expect_true(bool result, const char *test)
+{
+   if (!result) {
+  fprintf(stderr, "Error: Test '%s' failed: Expected=true"
+  ", Actual=false\n", test);
+  error = true;
+   }
+}
+
+static void
 expect_equal(uint64_t actual, uint64_t expected, const char *test)
 {
if (actual != expected) {
@@ -114,6 +126,26 @@ rmrf_local(const char *path)
return nftw(path, remove_entry, 64, FTW_DEPTH | FTW_PHYS | FTW_MOUNT);
 }
 
+static void
+check_timestamp_and_gpu_id_directories_created(const char *cache_dir)
+{
+   bool sub_dirs_created = false;
+
+   char buf[PATH_MAX];
+   if (getcwd(buf, PATH_MAX)) {
+  char *full_path = NULL;
+  if (asprintf(_path, "%s%s", buf, ++cache_dir) != -1 ) {
+ struct stat sb;
+ if (stat(full_path, ) != -1 && S_ISDIR(sb.st_mode))
+sub_dirs_created = true;
+
+ free(full_path);
+  }
+   }
+
+   expect_true(sub_dirs_created, "create timestamp and gpu ip sub dirs");
+}
+
 #define CACHE_TEST_TMP "./cache-test-tmp"
 
 static void
@@ -152,6 +184,10 @@ test_disk_cache_create(void)
cache = disk_cache_create("test", "make_check");
expect_non_null(cache, "disk_cache_create with XDG_CACHE_HOME set");
 
+   check_timestamp_and_gpu_id_directories_created(CACHE_TEST_TMP
+  "/xdg-cache-home"
+  "/mesa/make_check/test");
+
disk_cache_destroy(cache);
 
/* Test with MESA_GLSL_CACHE_DIR set */
@@ -167,6 +203,10 @@ test_disk_cache_create(void)
cache = disk_cache_create("test", "make_check");
expect_non_null(cache, "disk_cache_create with MESA_GLSL_CACHE_DIR set");
 
+   check_timestamp_and_gpu_id_directories_created(CACHE_TEST_TMP
+  "/mesa-glsl-cache-dir"
+  "/mesa/make_check/test");
+
disk_cache_destroy(cache);
 }
 
diff --git a/src/util/disk_cache.c b/src/util/disk_cache.c
index 6618a24..2f138da 100644
--- a/src/util/disk_cache.c
+++ b/src/util/disk_cache.c
@@ -225,8 +225,14 @@ disk_cache_create(const char *gpu_name, const char 
*timestamp)
 *   /.cache/mesa
 */
path = getenv("MESA_GLSL_CACHE_DIR");
-   if (path && mkdir_if_needed(path) == -1) {
-  goto fail;
+   if (path) {
+  if (mkdir_if_needed(path) == -1)
+ goto fail;
+
+  path = create_mesa_cache_dir(local, path, timestamp,
+   gpu_name);
+  if (path == NULL)
+ goto fail;
}
 
if (path == NULL) {
-- 
2.9.3

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[Mesa-dev] [PATCH] st/nine: make use of common uploaders v4

[Constantine Charlamov]

Make use of common uploaders that landed recently to Mesa

v2: fixed formatting, broken due to thunderbird configuration

v3: per Axel comment: added a comment into NineDevice9_DrawPrimitiveUP

v4: per Axel comment: changed style of the comment

---
 src/gallium/state_trackers/nine/device9.c| 50 +---
 src/gallium/state_trackers/nine/device9.h|  5 ---
 src/gallium/state_trackers/nine/nine_ff.c|  8 ++---
 src/gallium/state_trackers/nine/nine_state.c | 48 +-
 4 files changed, 37 insertions(+), 74 deletions(-)

diff --git a/src/gallium/state_trackers/nine/device9.c 
b/src/gallium/state_trackers/nine/device9.c
index b9b7a637d7..86c8e38535 100644
--- a/src/gallium/state_trackers/nine/device9.c
+++ b/src/gallium/state_trackers/nine/device9.c
@@ -477,31 +477,8 @@ NineDevice9_ctor( struct NineDevice9 *This,
 This->driver_caps.user_cbufs = GET_PCAP(USER_CONSTANT_BUFFERS);
 This->driver_caps.user_sw_vbufs = 
This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_VERTEX_BUFFERS);
 This->driver_caps.user_sw_cbufs = 
This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_CONSTANT_BUFFERS);
-
-/* Implicit use of context pipe for vertex and index uploaded when
- * csmt is not active. Does not need to sync since csmt is unactive,
- * thus no need to call NineDevice9_GetPipe at each upload. */
-if (!This->driver_caps.user_vbufs)
-This->vertex_uploader = u_upload_create(This->csmt_active ?
-This->pipe_secondary : 
This->context.pipe,
-65536,
-PIPE_BIND_VERTEX_BUFFER, 
PIPE_USAGE_STREAM);
-This->vertex_sw_uploader = u_upload_create(This->pipe_sw, 65536,
-PIPE_BIND_VERTEX_BUFFER, 
PIPE_USAGE_STREAM);
-if (!This->driver_caps.user_ibufs)
-This->index_uploader = u_upload_create(This->csmt_active ?
-This->pipe_secondary : 
This->context.pipe,
-   128 * 1024,
-   PIPE_BIND_INDEX_BUFFER, 
PIPE_USAGE_STREAM);
-if (!This->driver_caps.user_cbufs) {
+if (!This->driver_caps.user_cbufs)
 This->constbuf_alignment = GET_PCAP(CONSTANT_BUFFER_OFFSET_ALIGNMENT);
-This->constbuf_uploader = u_upload_create(This->context.pipe, 
This->vs_const_size,
-  PIPE_BIND_CONSTANT_BUFFER, 
PIPE_USAGE_STREAM);
-}
-
-This->constbuf_sw_uploader = u_upload_create(This->pipe_sw, 128 * 1024,
- PIPE_BIND_CONSTANT_BUFFER, 
PIPE_USAGE_STREAM);
-
 This->driver_caps.window_space_position_support = 
GET_PCAP(TGSI_VS_WINDOW_SPACE_POSITION);
 This->driver_caps.vs_integer = pScreen->get_shader_param(pScreen, 
PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS);
 This->driver_caps.ps_integer = pScreen->get_shader_param(pScreen, 
PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_INTEGERS);
@@ -552,17 +529,6 @@ NineDevice9_dtor( struct NineDevice9 *This )
 nine_state_clear(>state, TRUE);
 nine_context_clear(This);
 
-if (This->vertex_uploader)
-u_upload_destroy(This->vertex_uploader);
-if (This->index_uploader)
-u_upload_destroy(This->index_uploader);
-if (This->constbuf_uploader)
-u_upload_destroy(This->constbuf_uploader);
-if (This->vertex_sw_uploader)
-u_upload_destroy(This->vertex_sw_uploader);
-if (This->constbuf_sw_uploader)
-u_upload_destroy(This->constbuf_sw_uploader);
-
 nine_bind(>record, NULL);
 
 pipe_sampler_view_reference(>dummy_sampler_view, NULL);
@@ -2852,15 +2818,17 @@ NineDevice9_DrawPrimitiveUP( struct NineDevice9 *This,
 vtxbuf.buffer = NULL;
 vtxbuf.user_buffer = pVertexStreamZeroData;
 
+/* csmt is unactive when user vertex or index buffers are used, thus no
+ * need to call NineDevice9_GetPipe. */
 if (!This->driver_caps.user_vbufs) {
-u_upload_data(This->vertex_uploader,
+u_upload_data(This->context.pipe->stream_uploader,
   0,
   (prim_count_to_vertex_count(PrimitiveType, 
PrimitiveCount)) * VertexStreamZeroStride, /* XXX */
   4,
   vtxbuf.user_buffer,
   _offset,
   );
-u_upload_unmap(This->vertex_uploader);
+u_upload_unmap(This->context.pipe->stream_uploader);
 vtxbuf.user_buffer = NULL;
 }
 
@@ -2916,27 +2884,27 @@ NineDevice9_DrawIndexedPrimitiveUP( struct NineDevice9 
*This,
 
 if (!This->driver_caps.user_vbufs) {
 const unsigned base = MinVertexIndex * VertexStreamZeroStride;
-u_upload_data(This->vertex_uploader,
+u_upload_data(This->context.pipe->stream_uploader,
   base,
  

[Mesa-dev] [PATCH 2/3] radv/ac: pass clips properly from vertex->geometry shader stages.

[Dave Airlie]

From: Dave Airlie 

This works out the geometry shader clip/cull inputs separately
to the outputs, and uses that information to read from the ES->GS
ring buffer. It stores the clip/cull distances packed into one
or two slots. It fixes the es output emission and gs input
reading to match.

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 46 +++--
 1 file changed, 40 insertions(+), 6 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 6c6a1d1..43d5295 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -141,6 +141,8 @@ struct nir_to_llvm_context {
int num_locals;
LLVMValueRef *locals;
bool has_ddxy;
+   uint8_t num_input_clips;
+   uint8_t num_input_culls;
uint8_t num_output_clips;
uint8_t num_output_culls;
 
@@ -172,9 +174,11 @@ static unsigned shader_io_get_unique_index(gl_varying_slot 
slot)
return 0;
if (slot == VARYING_SLOT_PSIZ)
return 1;
-   if (slot == VARYING_SLOT_CLIP_DIST0)
+   if (slot == VARYING_SLOT_CLIP_DIST0 ||
+   slot == VARYING_SLOT_CULL_DIST0)
return 2;
-   if (slot == VARYING_SLOT_CLIP_DIST1)
+   if (slot == VARYING_SLOT_CLIP_DIST1 ||
+   slot == VARYING_SLOT_CULL_DIST1)
return 3;
if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
return 4 + (slot - VARYING_SLOT_VAR0);
@@ -2089,6 +2093,7 @@ load_gs_input(struct nir_to_llvm_context *ctx,
unsigned param, vtx_offset_param;
LLVMValueRef value[4], result;
unsigned vertex_index;
+   unsigned cull_offset = 0;
radv_get_deref_offset(ctx, >variables[0]->deref,
  false, _index,
  _index, _index);
@@ -2097,11 +2102,14 @@ load_gs_input(struct nir_to_llvm_context *ctx,
vtx_offset = LLVMBuildMul(ctx->builder, 
ctx->gs_vtx_offset[vtx_offset_param],
  LLVMConstInt(ctx->i32, 4, false), "");
 
+   param = 
shader_io_get_unique_index(instr->variables[0]->var->data.location);
+   if (instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
+   cull_offset += ctx->num_input_clips;
for (unsigned i = 0; i < instr->num_components; i++) {
-   param = 
shader_io_get_unique_index(instr->variables[0]->var->data.location);
+
args[0] = ctx->esgs_ring;
args[1] = vtx_offset;
-   args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index) 
* 256, false);
+   args[2] = LLVMConstInt(ctx->i32, (param * 4 + i + const_index + 
cull_offset) * 256, false);
args[3] = ctx->i32zero;
args[4] = ctx->i32one; /* OFFEN */
args[5] = ctx->i32zero; /* IDXEN */
@@ -3942,6 +3950,21 @@ handle_vs_input_decl(struct nir_to_llvm_context *ctx,
}
 }
 
+static void
+handle_gs_input_decl(struct nir_to_llvm_context *ctx,
+struct nir_variable *variable)
+{
+   int idx = variable->data.location;
+
+   if (idx == VARYING_SLOT_CLIP_DIST0 ||
+   idx == VARYING_SLOT_CULL_DIST0) {
+   int length = 
glsl_get_length(glsl_get_array_element(variable->type));
+   if (idx == VARYING_SLOT_CLIP_DIST0)
+   ctx->num_input_clips = length;
+   else
+   ctx->num_input_culls = length;
+   }
+}
 
 static void interp_fs_input(struct nir_to_llvm_context *ctx,
unsigned attr,
@@ -4035,6 +4058,9 @@ handle_shader_input_decl(struct nir_to_llvm_context *ctx,
case MESA_SHADER_FRAGMENT:
handle_fs_input_decl(ctx, variable);
break;
+   case MESA_SHADER_GEOMETRY:
+   handle_gs_input_decl(ctx, variable);
+   break;
default:
break;
}
@@ -4520,15 +4546,23 @@ handle_es_outputs_post(struct nir_to_llvm_context *ctx)
for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
LLVMValueRef *out_ptr = >outputs[i * 4];
int param_index;
+   int length = 4;
+   int start = 0;
if (!(ctx->output_mask & (1ull << i)))
continue;
 
+   if (i == VARYING_SLOT_CLIP_DIST0) {
+   length = ctx->num_output_clips;
+   } else if (i == VARYING_SLOT_CULL_DIST0) {
+   start = ctx->num_output_clips;
+   length = ctx->num_output_culls;
+   }
param_index = shader_io_get_unique_index(i);
 
if (param_index > max_output_written)
max_output_written = param_index;
 
-   for (j = 0; j < 4; j++) {
+   for (j = 0; j 

[Mesa-dev] [PATCH 1/3] radv/ac: rename num clips/cull to output clips/culls

[Dave Airlie]

From: Dave Airlie 

As geom shaders can have different ones on entry and exit.

also move to uint8_t as these are never that big.

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 20 ++--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index b3dc63c..6c6a1d1 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -141,8 +141,8 @@ struct nir_to_llvm_context {
int num_locals;
LLVMValueRef *locals;
bool has_ddxy;
-   unsigned num_clips;
-   unsigned num_culls;
+   uint8_t num_output_clips;
+   uint8_t num_output_culls;
 
bool has_ds_bpermute;
 
@@ -4132,10 +4132,10 @@ handle_shader_output_decl(struct nir_to_llvm_context 
*ctx,
if (ctx->stage == MESA_SHADER_VERTEX) {
if (idx == VARYING_SLOT_CLIP_DIST0) {
ctx->shader_info->vs.clip_dist_mask = 
(1 << length) - 1;
-   ctx->num_clips = length;
+   ctx->num_output_clips = length;
} else if (idx == VARYING_SLOT_CULL_DIST0) {
ctx->shader_info->vs.cull_dist_mask = 
(1 << length) - 1;
-   ctx->num_culls = length;
+   ctx->num_output_culls = length;
}
}
if (length > 4)
@@ -4372,21 +4372,21 @@ handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
unsigned j;
 
if (ctx->shader_info->vs.cull_dist_mask)
-   ctx->shader_info->vs.cull_dist_mask <<= ctx->num_clips;
+   ctx->shader_info->vs.cull_dist_mask <<= 
ctx->num_output_clips;
 
i = VARYING_SLOT_CLIP_DIST0;
-   for (j = 0; j < ctx->num_clips; j++)
+   for (j = 0; j < ctx->num_output_clips; j++)
slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
   
ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
i = VARYING_SLOT_CULL_DIST0;
-   for (j = 0; j < ctx->num_culls; j++)
-   slots[ctx->num_clips + j] = to_float(ctx, 
LLVMBuildLoad(ctx->builder,
+   for (j = 0; j < ctx->num_output_culls; j++)
+   slots[ctx->num_output_clips + j] = to_float(ctx, 
LLVMBuildLoad(ctx->builder,
   
ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
 
-   for (i = ctx->num_clips + ctx->num_culls; i < 8; i++)
+   for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; 
i++)
slots[i] = LLVMGetUndef(ctx->f32);
 
-   if (ctx->num_clips + ctx->num_culls > 4) {
+   if (ctx->num_output_clips + ctx->num_output_culls > 4) {
target = V_008DFC_SQ_EXP_POS + 3;
si_llvm_init_export_args(ctx, [4], target, args);
memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
-- 
2.9.3

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[Mesa-dev] [PATCH 3/3] radv/ac: handle gs->copy shader clip distances.

[Dave Airlie]

From: Dave Airlie 

This fixes up the clip distance passing between the geometry
shader and the copy shader. It packs the clip and cull distances
into one or two consecutive slots, and avoids wasting space and
make sure the gs output and copy shader input agree on where
things are stored.

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 81 ++---
 1 file changed, 68 insertions(+), 13 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 43d5295..a74b906 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2980,7 +2980,7 @@ visit_emit_vertex(struct nir_to_llvm_context *ctx,
LLVMValueRef gs_next_vertex;
LLVMValueRef can_emit, kill;
int idx;
-
+   int clip_cull_slot = -1;
assert(instr->const_index[0] == 0);
/* Write vertex attribute values to GSVS ring */
gs_next_vertex = LLVMBuildLoad(ctx->builder,
@@ -3005,13 +3005,40 @@ visit_emit_vertex(struct nir_to_llvm_context *ctx,
idx = 0;
for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
LLVMValueRef *out_ptr = >outputs[i * 4];
+   int length = 4;
+   int start = 0;
+   int slot = idx;
+   int slot_inc = 1;
+
if (!(ctx->output_mask & (1ull << i)))
continue;
 
-   for (unsigned j = 0; j < 4; j++) {
+   if (i == VARYING_SLOT_CLIP_DIST1 ||
+   i == VARYING_SLOT_CULL_DIST1)
+   continue;
+
+   if (i == VARYING_SLOT_CLIP_DIST0 ||
+   i == VARYING_SLOT_CULL_DIST0) {
+   /* pack clip and cull into a single set of slots */
+   if (clip_cull_slot == -1) {
+   clip_cull_slot = idx;
+   if (ctx->num_output_clips + 
ctx->num_output_culls > 4)
+   slot_inc = 2;
+   } else {
+   slot = clip_cull_slot;
+   slot_inc = 0;
+   }
+   if (i == VARYING_SLOT_CLIP_DIST0)
+   length = ctx->num_output_clips;
+   if (i == VARYING_SLOT_CULL_DIST0) {
+   start = ctx->num_output_clips;
+   length = ctx->num_output_culls;
+   }
+   }
+   for (unsigned j = 0; j < length; j++) {
LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
 out_ptr[j], "");
-   LLVMValueRef voffset = LLVMConstInt(ctx->i32, (idx * 4 
+ j) * ctx->gs_max_out_vertices, false);
+   LLVMValueRef voffset = LLVMConstInt(ctx->i32, (slot * 4 
+ j + start) * ctx->gs_max_out_vertices, false);
voffset = LLVMBuildAdd(ctx->builder, voffset, 
gs_next_vertex, "");
voffset = LLVMBuildMul(ctx->builder, voffset, 
LLVMConstInt(ctx->i32, 4, false), "");
 
@@ -3024,7 +3051,7 @@ visit_emit_vertex(struct nir_to_llvm_context *ctx,
   V_008F0C_BUF_NUM_FORMAT_UINT,
   1, 0, 1, 1, 0);
}
-   idx++;
+   idx += slot_inc;
}
 
gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
@@ -4155,14 +4182,14 @@ handle_shader_output_decl(struct nir_to_llvm_context 
*ctx,
if (idx == VARYING_SLOT_CLIP_DIST0 ||
idx == VARYING_SLOT_CULL_DIST0) {
int length = glsl_get_length(variable->type);
-   if (ctx->stage == MESA_SHADER_VERTEX) {
-   if (idx == VARYING_SLOT_CLIP_DIST0) {
+   if (idx == VARYING_SLOT_CLIP_DIST0) {
+   if (ctx->stage == MESA_SHADER_VERTEX)
ctx->shader_info->vs.clip_dist_mask = 
(1 << length) - 1;
-   ctx->num_output_clips = length;
-   } else if (idx == VARYING_SLOT_CULL_DIST0) {
+   ctx->num_output_clips = length;
+   } else if (idx == VARYING_SLOT_CULL_DIST0) {
+   if (ctx->stage == MESA_SHADER_VERTEX)
ctx->shader_info->vs.cull_dist_mask = 
(1 << length) - 1;
-   ctx->num_output_culls = length;
-   }
+   ctx->num_output_culls = length;
}
if (length > 4)
attrib_count = 2;
@@ 

Re: [Mesa-dev] Gallium: Removal of set_index_buffer (discussion)

[Roland Scheidegger]

Am 20.02.2017 um 21:58 schrieb Marek Olšák:
> On Mon, Feb 20, 2017 at 9:28 PM, Roland Scheidegger  
> wrote:
>> Am 20.02.2017 um 20:56 schrieb Marek Olšák:
>>> On Mon, Feb 20, 2017 at 8:29 PM, Axel Davy  wrote:
 On 20/02/2017 20:11, Ilia Mirkin wrote:
>
> On Mon, Feb 20, 2017 at 2:01 PM, Marek Olšák  wrote:
>>
>> Hi,
>>
>> I'd like to remove pipe_context::set_index_buffer. It's not useful to
>> most drivers and the interface is inconvenient for Mesa/OpenGL,
>> because it's a draw state that is set with a separate driver callback,
>> which is an unnecessary driver roundtrip taking some CPU cycles. I'd
>> prefer to pass the index buffer via pipe_draw_info.
>>
>> I'm aware that the interface was inherited from DX10, but I don't
>> think that makes any difference here. DX10 state trackers can pass the
>> index buffer via pipe_draw_info too.
>>
>> This is my proposal:
>>
>> iff --git a/src/gallium/include/pipe/p_state.h
>> b/src/gallium/include/pipe/p_state.h
>> index ce19b92..cffbb33 100644
>> --- a/src/gallium/include/pipe/p_state.h
>> +++ b/src/gallium/include/pipe/p_state.h
>> @@ -635,7 +635,7 @@ struct pipe_index_buffer
>>*/
>>   struct pipe_draw_info
>>   {
>> -   boolean indexed;  /**< use index buffer */
>> +   ubyte index_size;  /**< 0 = non-indexed */

 Isn't that enough to say non-index when index_buffer and user_indices are
 NULL ?
>>>
>>> We still need index_size and it's only 8 bits as opposed to 64 bits.
>> FWIW at least in d3d10 you can actually have indexed rendering without
>> an index buffer bound. This is perfectly valid, you're just expected to
>> return always zero for all indices... Albeit I believe we actually deal
>> with this with a dummy buffer.
>>
>>>
>>
>>  enum pipe_prim_type mode;  /**< the mode of the primitive */
>>  boolean primitive_restart;
>>  ubyte vertices_per_patch; /**< the number of vertices per patch */
>> @@ -666,12 +666,18 @@ struct pipe_draw_info
>>
>>  unsigned indirect_params_offset; /**< must be 4 byte aligned */
>>
>> +   /**
>> +* Index buffer. Only one can be non-NULL.
>> +*/
>> +   struct pipe_resource *index_buffer; /* "start" is the offset */
>
> Works for me. Is start the offset in bytes or is start * index_size
> the offset in bytes?

 Same question here. My understanding is that start is in terms of start *
 index_size bytes.
>>>
>>> offset = start * index_size;
>>>
 But we really want to have a byte offset.
>>>
>>> The offset should be aligned to index_size, otherwise hardware won't work.
>> Are you sure of that? d3d10 doesn't seem to have such a requirement, or
>> if it has I can't find it now (so, the startIndex really is in terms of
>> index units, but the offset of the buffer is in terms of bytes, and the
>> docs don't seem to mention it's limited to index alignment).
>> I don't actually see such a limitation in GL neither, albeit some quick
>> googling seems to suggest YMMV (e.g.
>> https://urldefense.proofpoint.com/v2/url?u=http-3A__irrlicht.sourceforge.net_forum_viewtopic.php-3Ff-3D7-26t-3D51444=DwIFaQ=uilaK90D4TOVoH58JNXRgQ=_QIjpv-UJ77xEQY8fIYoQtr5qv8wKrPJc7v7_-CYAb0=_nDDEb8aspFcYmYCdx9G-Pfs4rRVzx4rodfxnJNkNyc=XPduNXrH7SGk7lVUD2izbWAOfERG60bJWTsI600UWCg=
>>  ).
>> So, I can't quite tell right now if we really need byte offsets...
> 
> It's a natural requirement of hardware. It doesn't have to be
> documented IMO. CPUs might not support it either.
I did some quick tests and I believe d3d10 doesn't actually require
offsets not aligned to index size, but don't quote me on that.
Nevertheless, I've got the feeling this might be expected to work with
GL - doesn't look like it would be an error if your indices "pointer" in
glDrawElements() isn't aligned, and if it's not an error I don't see why
it wouldn't be well defined?
(FWIW x86 supports this fine, but indeed not all cpu archs might. Even
AVX2 gather supports non-aligned lookups - of course just for uint
indices since gather doesn't support smaller than 32bit gathers.)


> 
>>
>> Otherwise we should be able to deal with the interface change (that
>> said, arguably the old one is quite consistent with the analogous
>> set_vertex_buffers call - vulkan also has two analogous entry points for
>> setting vertex and index buffers, so it can't be all that wrong).
>> Do you have some evidence this really saves some measurable cpu cycles?
> 
> Yes it can be measurable, but it's not massive. setup_index_buffer is
> close to 1% in torcs. We can also lose time elsewhere due to cache
> evictions. It's never just about CPU time in one function.
> 
> My plan is:
> - get rid of pipe_index_buffer
> - get rid of _mesa_index_buffer
> - make _mesa_prim the same as pipe_draw_info
> - pretty much set pipe_draw_info in the vbo module
> 

Re: [Mesa-dev] [PATCH v2] radeonsi, r600g: Alias 'R600_DEBUG' with 'RADEON_DEBUG'

[Michel Dänzer]

On 20/02/17 07:15 PM, Edward O'Callaghan wrote:
> The name has become a little misleading now that it applies
> to both r600g and radeonsi.
> 
> V.2: Michel Dänzer - R600_DEBUG must continue to work.
> 
> Signed-off-by: Edward O'Callaghan 

In addition to others' comments:


> diff --git a/src/gallium/drivers/radeonsi/glsl_tests/amdgcn_glslc.c 
> b/src/gallium/drivers/radeonsi/glsl_tests/amdgcn_glslc.c
> index 3f52188..947736b 100644
> --- a/src/gallium/drivers/radeonsi/glsl_tests/amdgcn_glslc.c
> +++ b/src/gallium/drivers/radeonsi/glsl_tests/amdgcn_glslc.c
> @@ -207,6 +207,7 @@ main(int argc, char **argv)
>  }
>  
>  addenv("R600_DEBUG", "precompile,vs,tcs,tes,gs,ps,cs,noir,notgsi");
> +addenv("RADEON_DEBUG", "precompile,vs,tcs,tes,gs,ps,cs,noir,notgsi");

This doesn't need to set both environment variables.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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[Mesa-dev] [PATCH V2 3.5/4] st/mesa: get on-disk shader cache

[Timothy Arceri]

V2: make sure callback exists before calling it
---
 src/mesa/state_tracker/st_context.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/state_tracker/st_context.c 
b/src/mesa/state_tracker/st_context.c
index f4ad6d8..6321309 100644
--- a/src/mesa/state_tracker/st_context.c
+++ b/src/mesa/state_tracker/st_context.c
@@ -538,6 +538,9 @@ struct st_context *st_create_context(gl_api api, struct 
pipe_context *pipe,
   return NULL;
}
 
+   if (pipe->screen->get_disk_shader_cache)
+  ctx->Cache = pipe->screen->get_disk_shader_cache(pipe->screen);
+
st_init_driver_flags(>DriverFlags);
 
/* XXX: need a capability bit in gallium to query if the pipe
-- 
2.9.3

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Re: [Mesa-dev] [PATCH 3.5/4] st/mesa: get on-disk shader cache

[Timothy Arceri]

On 21/02/17 13:20, Michel Dänzer wrote:

On 21/02/17 08:23 AM, Timothy Arceri wrote:

---
 src/mesa/state_tracker/st_context.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/state_tracker/st_context.c 
b/src/mesa/state_tracker/st_context.c
index f4ad6d8..153f01c 100644
--- a/src/mesa/state_tracker/st_context.c
+++ b/src/mesa/state_tracker/st_context.c
@@ -538,6 +538,8 @@ struct st_context *st_create_context(gl_api api, struct 
pipe_context *pipe,
   return NULL;
}

+   ctx->Cache = pipe->screen->get_disk_shader_cache(pipe->screen);


You probably want to guard this by

   if (pipe->screen->get_disk_shader_cache)


Of course. Thanks.



otherwise you'd need to make sure that every driver sets
pipe_screen::get_disk_shader_cache.


Speaking of which, you probably need to add a get_disk_shader_cache
implementation to all the wrapper drivers (ddebug, rbug, trace).



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Re: [Mesa-dev] [PATCH 2/2] vulkan/wsi/radv: add initial prime support

[Mike Lothian]

Feel free to add my "Tested by" to these

Tested with vulkaninfo, vulkancube, vulkanscene and The Talos
Principle 32bit & 64bit

Cheers

Mike

On 21 February 2017 at 02:26, Dave Airlie  wrote:
> From: Dave Airlie 
>
> This is a complete rewrite of my previous rfc patches.
>
> This adds the ability to present to a different GPU that rendering
> using a driver side operation that can copy from the tiled to
> linear shared image.
>
> This does prime support completely in the swapchain present code,
> and each queue has a precreated command buffer for each image
> and for the each queue family. This means presenting should work
> on graphics and compute queues and transfer in the future.
>
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/vulkan/radv_meta.h  |   3 +
>  src/amd/vulkan/radv_meta_copy.c |  20 ++
>  src/amd/vulkan/radv_wsi.c   | 136 
> +---
>  src/amd/vulkan/radv_wsi_x11.c   |   4 +-
>  src/intel/vulkan/anv_wsi.c  |   5 +-
>  src/intel/vulkan/anv_wsi_x11.c  |   4 +-
>  src/vulkan/wsi/wsi_common.h |   8 +++
>  src/vulkan/wsi/wsi_common_wayland.c |   4 ++
>  src/vulkan/wsi/wsi_common_x11.c |  59 ++--
>  src/vulkan/wsi/wsi_common_x11.h |   1 +
>  10 files changed, 223 insertions(+), 21 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
> index 8eb3df3..d70fef1 100644
> --- a/src/amd/vulkan/radv_meta.h
> +++ b/src/amd/vulkan/radv_meta.h
> @@ -208,6 +208,9 @@ void radv_meta_resolve_compute_image(struct 
> radv_cmd_buffer *cmd_buffer,
>  uint32_t region_count,
>  const VkImageResolve *regions);
>
> +void radv_blit_to_prime_linear(struct radv_cmd_buffer *cmd_buffer,
> +  struct radv_image *image,
> +  struct radv_image *linear_image);
>  #ifdef __cplusplus
>  }
>  #endif
> diff --git a/src/amd/vulkan/radv_meta_copy.c b/src/amd/vulkan/radv_meta_copy.c
> index 2bd20b5..5473764 100644
> --- a/src/amd/vulkan/radv_meta_copy.c
> +++ b/src/amd/vulkan/radv_meta_copy.c
> @@ -430,3 +430,23 @@ void radv_CmdCopyImage(
> meta_copy_image(cmd_buffer, src_image, dest_image,
> regionCount, pRegions);
>  }
> +
> +void radv_blit_to_prime_linear(struct radv_cmd_buffer *cmd_buffer,
> +  struct radv_image *image,
> +  struct radv_image *linear_image)
> +{
> +   struct VkImageCopy image_copy = { 0 };
> +
> +   image_copy.srcSubresource.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
> +   image_copy.srcSubresource.layerCount = 1;
> +
> +   image_copy.dstSubresource.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
> +   image_copy.dstSubresource.layerCount = 1;
> +
> +   image_copy.extent.width = image->extent.width;
> +   image_copy.extent.height = image->extent.height;
> +   image_copy.extent.depth = 1;
> +
> +   meta_copy_image(cmd_buffer, image, linear_image,
> +   1, _copy);
> +}
> diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
> index ea8e784..4d0168f 100644
> --- a/src/amd/vulkan/radv_wsi.c
> +++ b/src/amd/vulkan/radv_wsi.c
> @@ -24,6 +24,7 @@
>   */
>
>  #include "radv_private.h"
> +#include "radv_meta.h"
>  #include "wsi_common.h"
>
>  static const struct wsi_callbacks wsi_cbs = {
> @@ -92,7 +93,7 @@ VkResult radv_GetPhysicalDeviceSurfaceSupportKHR(
>
> return iface->get_support(surface, >wsi_device,
>   >instance->alloc,
> - queueFamilyIndex, device->local_fd, 
> pSupported);
> + queueFamilyIndex, device->local_fd, true, 
> pSupported);
>  }
>
>  VkResult radv_GetPhysicalDeviceSurfaceCapabilitiesKHR(
> @@ -139,6 +140,8 @@ static VkResult
>  radv_wsi_image_create(VkDevice device_h,
>   const VkSwapchainCreateInfoKHR *pCreateInfo,
>   const VkAllocationCallbacks* pAllocator,
> + bool needs_linear_copy,
> + bool linear,
>   VkImage *image_p,
>   VkDeviceMemory *memory_p,
>   uint32_t *size,
> @@ -169,7 +172,7 @@ radv_wsi_image_create(VkDevice device_h,
>.arrayLayers = 1,
>.samples = 1,
>/* FIXME: Need a way to 
> use X tiling to allow scanout */
> -  .tiling = 
> VK_IMAGE_TILING_OPTIMAL,
> +  .tiling = linear ? 
> VK_IMAGE_TILING_LINEAR : VK_IMAGE_TILING_OPTIMAL,
>.usage = 
> VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT,
> 

Re: [Mesa-dev] [PATCH 1/2] vulkan/wsi: move image count to shared structure.

[Jason Ekstrand]

Fine by me

Reviewed-by: Jason Ekstrand 

On Mon, Feb 20, 2017 at 6:26 PM, Dave Airlie  wrote:

> From: Dave Airlie 
>
> For prime support I need to access this, so move it in advance.
>
> Signed-off-by: Dave Airlie 
> ---
>  src/vulkan/wsi/wsi_common.h |  1 +
>  src/vulkan/wsi/wsi_common_wayland.c | 20 +---
>  src/vulkan/wsi/wsi_common_x11.c | 29 ++---
>  3 files changed, 24 insertions(+), 26 deletions(-)
>
> diff --git a/src/vulkan/wsi/wsi_common.h b/src/vulkan/wsi/wsi_common.h
> index ae9e587..1a22935 100644
> --- a/src/vulkan/wsi/wsi_common.h
> +++ b/src/vulkan/wsi/wsi_common.h
> @@ -54,6 +54,7 @@ struct wsi_swapchain {
> const struct wsi_image_fns *image_fns;
> VkFence fences[3];
> VkPresentModeKHR present_mode;
> +   int image_count;
>
> VkResult (*destroy)(struct wsi_swapchain *swapchain,
> const VkAllocationCallbacks *pAllocator);
> diff --git a/src/vulkan/wsi/wsi_common_wayland.c
> b/src/vulkan/wsi/wsi_common_wayland.c
> index 4489736..e6490ee 100644
> --- a/src/vulkan/wsi/wsi_common_wayland.c
> +++ b/src/vulkan/wsi/wsi_common_wayland.c
> @@ -495,7 +495,6 @@ struct wsi_wl_swapchain {
> VkPresentModeKHR present_mode;
> bool fifo_ready;
>
> -   uint32_t image_count;
> struct wsi_wl_image  images[0];
>  };
>
> @@ -508,13 +507,13 @@ wsi_wl_swapchain_get_images(struct wsi_swapchain
> *wsi_chain,
> VkResult result;
>
> if (pSwapchainImages == NULL) {
> -  *pCount = chain->image_count;
> +  *pCount = chain->base.image_count;
>return VK_SUCCESS;
> }
>
> result = VK_SUCCESS;
> -   ret_count = chain->image_count;
> -   if (chain->image_count > *pCount) {
> +   ret_count = chain->base.image_count;
> +   if (chain->base.image_count > *pCount) {
>   ret_count = *pCount;
>   result = VK_INCOMPLETE;
> }
> @@ -543,7 +542,7 @@ wsi_wl_swapchain_acquire_next_image(struct
> wsi_swapchain *wsi_chain,
>return VK_ERROR_OUT_OF_DATE_KHR;
>
> while (1) {
> -  for (uint32_t i = 0; i < chain->image_count; i++) {
> +  for (uint32_t i = 0; i < chain->base.image_count; i++) {
>   if (!chain->images[i].busy) {
>  /* We found a non-busy image */
>  *image_index = i;
> @@ -591,7 +590,7 @@ wsi_wl_swapchain_queue_present(struct wsi_swapchain
> *wsi_chain,
>}
> }
>
> -   assert(image_index < chain->image_count);
> +   assert(image_index < chain->base.image_count);
> wl_surface_attach(chain->surface, chain->images[image_index].buffer,
> 0, 0);
> wl_surface_damage(chain->surface, 0, 0, INT32_MAX, INT32_MAX);
>
> @@ -679,7 +678,7 @@ wsi_wl_swapchain_destroy(struct wsi_swapchain
> *wsi_chain,
>  {
> struct wsi_wl_swapchain *chain = (struct wsi_wl_swapchain *)wsi_chain;
>
> -   for (uint32_t i = 0; i < chain->image_count; i++) {
> +   for (uint32_t i = 0; i < chain->base.image_count; i++) {
>if (chain->images[i].buffer)
>   chain->base.image_fns->free_wsi_image(chain->base.device,
> pAllocator,
> chain->images[i].image,
> @@ -724,6 +723,7 @@ wsi_wl_surface_create_swapchain(VkIcdSurfaceBase
> *icd_surface,
> chain->base.queue_present = wsi_wl_swapchain_queue_present;
> chain->base.image_fns = image_fns;
> chain->base.present_mode = pCreateInfo->presentMode;
> +   chain->base.image_count = num_images;
> chain->surface = surface->surface;
> chain->extent = pCreateInfo->imageExtent;
> chain->vk_format = pCreateInfo->imageFormat;
> @@ -731,12 +731,10 @@ wsi_wl_surface_create_swapchain(VkIcdSurfaceBase
> *icd_surface,
>
> chain->fifo_ready = true;
>
> -   chain->image_count = num_images;
> -
> /* Mark a bunch of stuff as NULL.  This way we can just call
>  * destroy_swapchain for cleanup.
>  */
> -   for (uint32_t i = 0; i < chain->image_count; i++)
> +   for (uint32_t i = 0; i < chain->base.image_count; i++)
>chain->images[i].buffer = NULL;
> chain->queue = NULL;
>
> @@ -753,7 +751,7 @@ wsi_wl_surface_create_swapchain(VkIcdSurfaceBase
> *icd_surface,
>goto fail;
> }
>
> -   for (uint32_t i = 0; i < chain->image_count; i++) {
> +   for (uint32_t i = 0; i < chain->base.image_count; i++) {
>result = wsi_wl_image_init(chain, >images[i],
>   pCreateInfo, pAllocator);
>if (result != VK_SUCCESS)
> diff --git a/src/vulkan/wsi/wsi_common_x11.c b/src/vulkan/wsi/wsi_common_
> x11.c
> index bec4907..9e19b10 100644
> --- a/src/vulkan/wsi/wsi_common_x11.c
> +++ b/src/vulkan/wsi/wsi_common_x11.c
> @@ -565,7 +565,6 @@ struct x11_swapchain {
> xcb_gc_t gc;
> uint32_t depth;
> 

[Mesa-dev] [PATCH 2/2] vulkan/wsi/radv: add initial prime support

[Dave Airlie]

From: Dave Airlie 

This is a complete rewrite of my previous rfc patches.

This adds the ability to present to a different GPU that rendering
using a driver side operation that can copy from the tiled to
linear shared image.

This does prime support completely in the swapchain present code,
and each queue has a precreated command buffer for each image
and for the each queue family. This means presenting should work
on graphics and compute queues and transfer in the future.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_meta.h  |   3 +
 src/amd/vulkan/radv_meta_copy.c |  20 ++
 src/amd/vulkan/radv_wsi.c   | 136 +---
 src/amd/vulkan/radv_wsi_x11.c   |   4 +-
 src/intel/vulkan/anv_wsi.c  |   5 +-
 src/intel/vulkan/anv_wsi_x11.c  |   4 +-
 src/vulkan/wsi/wsi_common.h |   8 +++
 src/vulkan/wsi/wsi_common_wayland.c |   4 ++
 src/vulkan/wsi/wsi_common_x11.c |  59 ++--
 src/vulkan/wsi/wsi_common_x11.h |   1 +
 10 files changed, 223 insertions(+), 21 deletions(-)

diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 8eb3df3..d70fef1 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -208,6 +208,9 @@ void radv_meta_resolve_compute_image(struct radv_cmd_buffer 
*cmd_buffer,
 uint32_t region_count,
 const VkImageResolve *regions);
 
+void radv_blit_to_prime_linear(struct radv_cmd_buffer *cmd_buffer,
+  struct radv_image *image,
+  struct radv_image *linear_image);
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/amd/vulkan/radv_meta_copy.c b/src/amd/vulkan/radv_meta_copy.c
index 2bd20b5..5473764 100644
--- a/src/amd/vulkan/radv_meta_copy.c
+++ b/src/amd/vulkan/radv_meta_copy.c
@@ -430,3 +430,23 @@ void radv_CmdCopyImage(
meta_copy_image(cmd_buffer, src_image, dest_image,
regionCount, pRegions);
 }
+
+void radv_blit_to_prime_linear(struct radv_cmd_buffer *cmd_buffer,
+  struct radv_image *image,
+  struct radv_image *linear_image)
+{
+   struct VkImageCopy image_copy = { 0 };
+
+   image_copy.srcSubresource.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
+   image_copy.srcSubresource.layerCount = 1;
+
+   image_copy.dstSubresource.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
+   image_copy.dstSubresource.layerCount = 1;
+
+   image_copy.extent.width = image->extent.width;
+   image_copy.extent.height = image->extent.height;
+   image_copy.extent.depth = 1;
+
+   meta_copy_image(cmd_buffer, image, linear_image,
+   1, _copy);
+}
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index ea8e784..4d0168f 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -24,6 +24,7 @@
  */
 
 #include "radv_private.h"
+#include "radv_meta.h"
 #include "wsi_common.h"
 
 static const struct wsi_callbacks wsi_cbs = {
@@ -92,7 +93,7 @@ VkResult radv_GetPhysicalDeviceSurfaceSupportKHR(
 
return iface->get_support(surface, >wsi_device,
  >instance->alloc,
- queueFamilyIndex, device->local_fd, 
pSupported);
+ queueFamilyIndex, device->local_fd, true, 
pSupported);
 }
 
 VkResult radv_GetPhysicalDeviceSurfaceCapabilitiesKHR(
@@ -139,6 +140,8 @@ static VkResult
 radv_wsi_image_create(VkDevice device_h,
  const VkSwapchainCreateInfoKHR *pCreateInfo,
  const VkAllocationCallbacks* pAllocator,
+ bool needs_linear_copy,
+ bool linear,
  VkImage *image_p,
  VkDeviceMemory *memory_p,
  uint32_t *size,
@@ -169,7 +172,7 @@ radv_wsi_image_create(VkDevice device_h,
   .arrayLayers = 1,
   .samples = 1,
   /* FIXME: Need a way to use 
X tiling to allow scanout */
-  .tiling = 
VK_IMAGE_TILING_OPTIMAL,
+  .tiling = linear ? 
VK_IMAGE_TILING_LINEAR : VK_IMAGE_TILING_OPTIMAL,
   .usage = 
VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT,
   .flags = 0,
   },
@@ -180,14 +183,14 @@ radv_wsi_image_create(VkDevice device_h,
return result;
 
image = radv_image_from_handle(image_h);
-
VkDeviceMemory memory_h;
struct radv_device_memory *memory;
+
result = radv_AllocateMemory(device_h,
 

[Mesa-dev] [PATCH 1/2] vulkan/wsi: move image count to shared structure.

[Dave Airlie]

From: Dave Airlie 

For prime support I need to access this, so move it in advance.

Signed-off-by: Dave Airlie 
---
 src/vulkan/wsi/wsi_common.h |  1 +
 src/vulkan/wsi/wsi_common_wayland.c | 20 +---
 src/vulkan/wsi/wsi_common_x11.c | 29 ++---
 3 files changed, 24 insertions(+), 26 deletions(-)

diff --git a/src/vulkan/wsi/wsi_common.h b/src/vulkan/wsi/wsi_common.h
index ae9e587..1a22935 100644
--- a/src/vulkan/wsi/wsi_common.h
+++ b/src/vulkan/wsi/wsi_common.h
@@ -54,6 +54,7 @@ struct wsi_swapchain {
const struct wsi_image_fns *image_fns;
VkFence fences[3];
VkPresentModeKHR present_mode;
+   int image_count;
 
VkResult (*destroy)(struct wsi_swapchain *swapchain,
const VkAllocationCallbacks *pAllocator);
diff --git a/src/vulkan/wsi/wsi_common_wayland.c 
b/src/vulkan/wsi/wsi_common_wayland.c
index 4489736..e6490ee 100644
--- a/src/vulkan/wsi/wsi_common_wayland.c
+++ b/src/vulkan/wsi/wsi_common_wayland.c
@@ -495,7 +495,6 @@ struct wsi_wl_swapchain {
VkPresentModeKHR present_mode;
bool fifo_ready;
 
-   uint32_t image_count;
struct wsi_wl_image  images[0];
 };
 
@@ -508,13 +507,13 @@ wsi_wl_swapchain_get_images(struct wsi_swapchain 
*wsi_chain,
VkResult result;
 
if (pSwapchainImages == NULL) {
-  *pCount = chain->image_count;
+  *pCount = chain->base.image_count;
   return VK_SUCCESS;
}
 
result = VK_SUCCESS;
-   ret_count = chain->image_count;
-   if (chain->image_count > *pCount) {
+   ret_count = chain->base.image_count;
+   if (chain->base.image_count > *pCount) {
  ret_count = *pCount;
  result = VK_INCOMPLETE;
}
@@ -543,7 +542,7 @@ wsi_wl_swapchain_acquire_next_image(struct wsi_swapchain 
*wsi_chain,
   return VK_ERROR_OUT_OF_DATE_KHR;
 
while (1) {
-  for (uint32_t i = 0; i < chain->image_count; i++) {
+  for (uint32_t i = 0; i < chain->base.image_count; i++) {
  if (!chain->images[i].busy) {
 /* We found a non-busy image */
 *image_index = i;
@@ -591,7 +590,7 @@ wsi_wl_swapchain_queue_present(struct wsi_swapchain 
*wsi_chain,
   }
}
 
-   assert(image_index < chain->image_count);
+   assert(image_index < chain->base.image_count);
wl_surface_attach(chain->surface, chain->images[image_index].buffer, 0, 0);
wl_surface_damage(chain->surface, 0, 0, INT32_MAX, INT32_MAX);
 
@@ -679,7 +678,7 @@ wsi_wl_swapchain_destroy(struct wsi_swapchain *wsi_chain,
 {
struct wsi_wl_swapchain *chain = (struct wsi_wl_swapchain *)wsi_chain;
 
-   for (uint32_t i = 0; i < chain->image_count; i++) {
+   for (uint32_t i = 0; i < chain->base.image_count; i++) {
   if (chain->images[i].buffer)
  chain->base.image_fns->free_wsi_image(chain->base.device, pAllocator,
chain->images[i].image,
@@ -724,6 +723,7 @@ wsi_wl_surface_create_swapchain(VkIcdSurfaceBase 
*icd_surface,
chain->base.queue_present = wsi_wl_swapchain_queue_present;
chain->base.image_fns = image_fns;
chain->base.present_mode = pCreateInfo->presentMode;
+   chain->base.image_count = num_images;
chain->surface = surface->surface;
chain->extent = pCreateInfo->imageExtent;
chain->vk_format = pCreateInfo->imageFormat;
@@ -731,12 +731,10 @@ wsi_wl_surface_create_swapchain(VkIcdSurfaceBase 
*icd_surface,
 
chain->fifo_ready = true;
 
-   chain->image_count = num_images;
-
/* Mark a bunch of stuff as NULL.  This way we can just call
 * destroy_swapchain for cleanup.
 */
-   for (uint32_t i = 0; i < chain->image_count; i++)
+   for (uint32_t i = 0; i < chain->base.image_count; i++)
   chain->images[i].buffer = NULL;
chain->queue = NULL;
 
@@ -753,7 +751,7 @@ wsi_wl_surface_create_swapchain(VkIcdSurfaceBase 
*icd_surface,
   goto fail;
}
 
-   for (uint32_t i = 0; i < chain->image_count; i++) {
+   for (uint32_t i = 0; i < chain->base.image_count; i++) {
   result = wsi_wl_image_init(chain, >images[i],
  pCreateInfo, pAllocator);
   if (result != VK_SUCCESS)
diff --git a/src/vulkan/wsi/wsi_common_x11.c b/src/vulkan/wsi/wsi_common_x11.c
index bec4907..9e19b10 100644
--- a/src/vulkan/wsi/wsi_common_x11.c
+++ b/src/vulkan/wsi/wsi_common_x11.c
@@ -565,7 +565,6 @@ struct x11_swapchain {
xcb_gc_t gc;
uint32_t depth;
VkExtent2D   extent;
-   uint32_t image_count;
 
xcb_present_event_t  event_id;
xcb_special_event_t *special_event;
@@ -591,13 +590,13 @@ x11_get_images(struct wsi_swapchain *anv_chain,
VkResult result;
 
if (pSwapchainImages == 

Re: [Mesa-dev] [PATCH 3.5/4] st/mesa: get on-disk shader cache

[Michel Dänzer]

On 21/02/17 08:23 AM, Timothy Arceri wrote:
> ---
>  src/mesa/state_tracker/st_context.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/src/mesa/state_tracker/st_context.c 
> b/src/mesa/state_tracker/st_context.c
> index f4ad6d8..153f01c 100644
> --- a/src/mesa/state_tracker/st_context.c
> +++ b/src/mesa/state_tracker/st_context.c
> @@ -538,6 +538,8 @@ struct st_context *st_create_context(gl_api api, struct 
> pipe_context *pipe,
>return NULL;
> }
>  
> +   ctx->Cache = pipe->screen->get_disk_shader_cache(pipe->screen);

You probably want to guard this by

   if (pipe->screen->get_disk_shader_cache)

otherwise you'd need to make sure that every driver sets
pipe_screen::get_disk_shader_cache.


Speaking of which, you probably need to add a get_disk_shader_cache
implementation to all the wrapper drivers (ddebug, rbug, trace).


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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[Mesa-dev] [Bug 99849] Dashed lines (drawn via GLAMOR) are not rendered correctly

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99849

--- Comment #5 from Michel Dänzer  ---
Xephyr -glamor is basically an OpenGL application like any other. E.g. you can
create an apitrace reproducing the problem, if that helps.

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Re: [Mesa-dev] [PATCH] glx/glvnd: Fix GLXdispatchIndex sorting

[Hans de Goede]

Hi Emil,

On 16-02-17 16:38, Emil Velikov wrote:

Hi Hans,

On 6 February 2017 at 13:09, Hans de Goede  wrote:

Commit 8bca8d89ef3b ("glx/glvnd: Fix dispatch function names and indices")
fixed the sorting of the array initializers in g_glxglvnddispatchfuncs.c
because FindGLXFunction's binary search needs these to be sorted
alphabetically.

That commit also mostly fixed the sorting of the DI_foo defines in
g_glxglvnddispatchindices.h, which is what actually matters as the
arrays are initialized using "[DI_foo] = glXfoo," but a small error
crept in which at least causes glXGetVisualFromFBConfigSGIX to not
resolve, breaking games such as "The Binding of Isaac: Rebirth" and
"Crypt of the NecroDancer" from Steam not working and possible causes
other problems too.

This commit fixes the last of the sorting errors, fixing these mentioned
games not working.

Fixes: 8bca8d89ef3b ("glx/glvnd: Fix dispatch function names and indices")
Cc: "13.0" 
Cc: "17.0" 
Cc: Adam Jackson 
Signed-off-by: Hans de Goede 
---

A while back as Adam did a similar thing, it was suggested that we get
an actual test so that things don't break.

I was stupid^Wkind enough to opt for "we can have such patch as
follow-up", only that it never came.
As you can imagine not cool...


Sorry, but for me this was sort of a drive by patch and I don't really
have time to work on a test for this. But it looks like ajax owes you
a test-case for this, ajax ?

Also Kyle Brenneman (added to the CC) who helped me pinpoint the issue
to the sorting problem mentioned that he was working on a patch to
autogenerate the files in question to avoid breakage like this,
Kyle what is the status of that ?

Regards,

Hans
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Re: [Mesa-dev] [PATCH V3] r600/radeonsi: enable glsl/tgsi on-disk cache

[Timothy Arceri]

On 21/02/17 10:35, Marek Olšák wrote:

v2 looked better, because HAVE_LLVM can be > 0, but r600g doesn't need
llvm_timestamp. (note that drivers/radeon is a static lib used by
r600g and radeonsi)


Sure but my thinking was that it wouldn't hurt much to append llvm 
anyway, but if disk_cache_get_function_timestamp() failed for SI we 
would want to skip cache creation completely to avoid issues.


Maybe I should just do:

   if (rscreen->chip_class < SI) {
  res = asprintf(_str, "%u",mesa_timestamp);
   }
#if HAVE_LLVM
   else {
  uint32_t llvm_timestamp;
  if (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
_timestamp)) {

 res = asprintf(_str, "%u_%u", mesa_timestamp,
llvm_timestamp);
  }
   }
#endif




Marek

On Tue, Feb 21, 2017 at 12:31 AM, Timothy Arceri  wrote:

For gpu generations that use LLVM we create a timestamp string
containing both the LLVM and Mesa build times, otherwise we just
use the Mesa build time.

V2: share code in r600_pipe_common as suggested by Marek.

V3: send the correct revision of V2
---
 src/gallium/drivers/radeon/r600_pipe_common.c | 51 +++
 src/gallium/drivers/radeon/r600_pipe_common.h |  3 ++
 2 files changed, 54 insertions(+)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 1781584..614eef1 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -43,6 +43,10 @@
 #define HAVE_LLVM 0
 #endif

+#if HAVE_LLVM
+#include 
+#endif
+
 #ifndef MESA_LLVM_VERSION_PATCH
 #define MESA_LLVM_VERSION_PATCH 0
 #endif
@@ -779,6 +783,49 @@ static const char* r600_get_chip_name(struct 
r600_common_screen *rscreen)
}
 }

+static void r600_disk_cache_create(struct r600_common_screen *rscreen)
+{
+   uint32_t mesa_timestamp;
+   if (disk_cache_get_function_timestamp(r600_disk_cache_create,
+ _timestamp)) {
+   char *timestamp_str;
+   int res = -1;
+#if HAVE_LLVM
+   uint32_t llvm_timestamp;
+   if 
(disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
+ _timestamp)) {
+
+   res = asprintf(_str, "%u_%u", mesa_timestamp,
+  llvm_timestamp);
+   } else {
+#endif
+   /* We only use a Mesa only timestamp if less than SI
+* because we must have an LLVM identifier to avoid
+* shaders not being rebuild when the LLVM version
+* changes.
+*/
+   if (rscreen->chip_class < SI) {
+   res = asprintf(_str, "%u",
+  mesa_timestamp);
+   }
+#if HAVE_LLVM
+   }
+#endif
+   if (res != -1) {
+   rscreen->disk_shader_cache =
+   disk_cache_create(r600_get_chip_name(rscreen),
+ timestamp_str);
+   free(timestamp_str);
+   }
+   }
+}
+
+static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen 
*pscreen)
+{
+   struct r600_common_screen *rscreen = (struct 
r600_common_screen*)pscreen;
+   return rscreen->disk_shader_cache;
+}
+
 static const char* r600_get_name(struct pipe_screen* pscreen)
 {
struct r600_common_screen *rscreen = (struct 
r600_common_screen*)pscreen;
@@ -1234,6 +1281,7 @@ bool r600_common_screen_init(struct r600_common_screen 
*rscreen,
rscreen->b.get_name = r600_get_name;
rscreen->b.get_vendor = r600_get_vendor;
rscreen->b.get_device_vendor = r600_get_device_vendor;
+   rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
rscreen->b.get_compute_param = r600_get_compute_param;
rscreen->b.get_paramf = r600_get_paramf;
rscreen->b.get_timestamp = r600_get_timestamp;
@@ -1243,6 +1291,8 @@ bool r600_common_screen_init(struct r600_common_screen 
*rscreen,
rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
rscreen->b.query_memory_info = r600_query_memory_info;

+   r600_disk_cache_create(rscreen);
+
if (rscreen->info.has_uvd) {
rscreen->b.get_video_param = rvid_get_video_param;
rscreen->b.is_video_format_supported = rvid_is_format_supported;
@@ -1324,6 +1374,7 @@ void r600_destroy_common_screen(struct r600_common_screen 
*rscreen)

slab_destroy_parent(>pool_transfers);

+   disk_cache_destroy(rscreen->disk_shader_cache);
rscreen->ws->destroy(rscreen->ws);
FREE(rscreen);
 }
diff --git 

[Mesa-dev] [PATCH v2 1/5] intel/blorp: Explicitly flush all allocated state

[Jason Ekstrand]

Found by inspection.  However, I expect it fixes real bugs when using
blorp from Vulkan on little-core platforms.

Cc: "13.0 17.0" 
---
 src/intel/blorp/blorp_genX_exec.h   | 17 -
 src/intel/vulkan/genX_blorp_exec.c  |  8 
 src/mesa/drivers/dri/i965/genX_blorp_exec.c |  8 
 3 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index a673ab8..1e6b05c 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -66,6 +66,10 @@ blorp_alloc_binding_table(struct blorp_batch *batch, 
unsigned num_entries,
   unsigned state_size, unsigned state_alignment,
   uint32_t *bt_offset, uint32_t *surface_offsets,
   void **surface_maps);
+
+static void
+blorp_flush_range(struct blorp_batch *batch, void *start, size_t size);
+
 static void
 blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
 struct blorp_address address, uint32_t delta);
@@ -182,6 +186,7 @@ blorp_emit_vertex_data(struct blorp_batch *batch,
void *data = blorp_alloc_vertex_buffer(batch, sizeof(vertices), addr);
memcpy(data, vertices, sizeof(vertices));
*size = sizeof(vertices);
+   blorp_flush_range(batch, data, *size);
 }
 
 static void
@@ -199,7 +204,8 @@ blorp_emit_input_varying_data(struct blorp_batch *batch,
*size = 16 + num_varyings * vec4_size_in_bytes;
 
const uint32_t *const inputs_src = (const uint32_t *)>wm_inputs;
-   uint32_t *inputs = blorp_alloc_vertex_buffer(batch, *size, addr);
+   void *data = blorp_alloc_vertex_buffer(batch, *size, addr);
+   uint32_t *inputs = data;
 
/* Copy in the VS inputs */
assert(sizeof(params->vs_inputs) == 16);
@@ -223,6 +229,8 @@ blorp_emit_input_varying_data(struct blorp_batch *batch,
  inputs += 4;
   }
}
+
+   blorp_flush_range(batch, data, *size);
 }
 
 static void
@@ -906,6 +914,7 @@ blorp_emit_blend_state(struct blorp_batch *batch,
GENX(BLEND_STATE_length) * 4,
64, );
GENX(BLEND_STATE_pack)(NULL, state, );
+   blorp_flush_range(batch, state, GENX(BLEND_STATE_length) * 4);
 
 #if GEN_GEN >= 7
blorp_emit(batch, GENX(3DSTATE_BLEND_STATE_POINTERS), sp) {
@@ -940,6 +949,7 @@ blorp_emit_color_calc_state(struct blorp_batch *batch,
GENX(COLOR_CALC_STATE_length) * 4,
64, );
GENX(COLOR_CALC_STATE_pack)(NULL, state, );
+   blorp_flush_range(batch, state, GENX(COLOR_CALC_STATE_length) * 4);
 
 #if GEN_GEN >= 7
blorp_emit(batch, GENX(3DSTATE_CC_STATE_POINTERS), sp) {
@@ -1016,6 +1026,7 @@ blorp_emit_depth_stencil_state(struct blorp_batch *batch,
GENX(DEPTH_STENCIL_STATE_length) * 
4,
64, );
GENX(DEPTH_STENCIL_STATE_pack)(NULL, state, );
+   blorp_flush_range(batch, state, GENX(DEPTH_STENCIL_STATE_length) * 4);
 #endif
 
 #if GEN_GEN == 7
@@ -1068,6 +1079,8 @@ blorp_emit_surface_state(struct blorp_batch *batch,
   blorp_surface_reloc(batch, state_offset + isl_dev->ss.aux_addr_offset,
   surface->aux_addr, *aux_addr);
}
+
+   blorp_flush_range(batch, state, GENX(RENDER_SURFACE_STATE_length) * 4);
 }
 
 static void
@@ -1181,6 +1194,7 @@ blorp_emit_sampler_state(struct blorp_batch *batch,
GENX(SAMPLER_STATE_length) * 4,
32, );
GENX(SAMPLER_STATE_pack)(NULL, state, );
+   blorp_flush_range(batch, state, GENX(SAMPLER_STATE_length) * 4);
 
 #if GEN_GEN >= 7
blorp_emit(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS), ssp) {
@@ -1333,6 +1347,7 @@ blorp_emit_viewport_state(struct blorp_batch *batch,
  .MinimumDepth = 0.0,
  .MaximumDepth = 1.0,
   });
+   blorp_flush_range(batch, state, GENX(CC_VIEWPORT_length) * 4);
 
 #if GEN_GEN >= 7
blorp_emit(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), vsp) {
diff --git a/src/intel/vulkan/genX_blorp_exec.c 
b/src/intel/vulkan/genX_blorp_exec.c
index 6f0b063..2e78bab 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -119,6 +119,14 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, 
uint32_t size,
 }
 
 static void
+blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
+{
+   struct anv_device *device = batch->blorp->driver_ctx;
+   if (!device->info.has_llc)
+  anv_clflush_range(start, size);
+}
+
+static void
 blorp_emit_urb_config(struct blorp_batch *batch, unsigned vs_entry_size)
 {
struct anv_device *device = batch->blorp->driver_ctx;
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c 
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 

Re: [Mesa-dev] [PATCH] r300g: only allow byteswapped formats on big endian

[Marek Olšák]

Pushed.

Marek

On Mon, Feb 20, 2017 at 11:40 PM, Grazvydas Ignotas  wrote:
> So, as there are no better solutions in sight, can somebody please
> push this patch?
>
> Gražvydas
>
> On Wed, Feb 15, 2017 at 5:33 AM, Alex Deucher  wrote:
>> On Tue, Feb 14, 2017 at 10:27 PM, Michel Dänzer  wrote:
>>> On 14/02/17 08:25 PM, Marek Olšák wrote:
 I've changed my mind. The patch can be merged if nobody disagrees.
>>>
>>> It would be nice to better understand what exactly the problem is. It
>>> seems unlikely that it's actually an endianness specific problem in the
>>> driver code, more likely an endianness specific problem in state tracker
>>> code, or maybe a non-endianness-specific problem in the driver code
>>> (which may or may not be possible to hit on big endian hosts as well).
>>>
>>> In other words, I suspect this isn't a fix for the actual problem, but
>>> just a workaround. That said, if you guys are happy with that, I'm not
>>> holding it up.
>>
>> I tend to agree, but OTOH, r300 is pretty old and BE systems are
>> pretty few and far between these days.  Neither of which are conducive
>> to spending much time on them.  Someone with an interest in BE systems
>> really needs to step up and fix up endian handling in mesa for real.
>>
>> Alex
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Re: [Mesa-dev] [PATCH V3] r600/radeonsi: enable glsl/tgsi on-disk cache

[Marek Olšák]

v2 looked better, because HAVE_LLVM can be > 0, but r600g doesn't need
llvm_timestamp. (note that drivers/radeon is a static lib used by
r600g and radeonsi)

Marek

On Tue, Feb 21, 2017 at 12:31 AM, Timothy Arceri  wrote:
> For gpu generations that use LLVM we create a timestamp string
> containing both the LLVM and Mesa build times, otherwise we just
> use the Mesa build time.
>
> V2: share code in r600_pipe_common as suggested by Marek.
>
> V3: send the correct revision of V2
> ---
>  src/gallium/drivers/radeon/r600_pipe_common.c | 51 
> +++
>  src/gallium/drivers/radeon/r600_pipe_common.h |  3 ++
>  2 files changed, 54 insertions(+)
>
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
> b/src/gallium/drivers/radeon/r600_pipe_common.c
> index 1781584..614eef1 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.c
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.c
> @@ -43,6 +43,10 @@
>  #define HAVE_LLVM 0
>  #endif
>
> +#if HAVE_LLVM
> +#include 
> +#endif
> +
>  #ifndef MESA_LLVM_VERSION_PATCH
>  #define MESA_LLVM_VERSION_PATCH 0
>  #endif
> @@ -779,6 +783,49 @@ static const char* r600_get_chip_name(struct 
> r600_common_screen *rscreen)
> }
>  }
>
> +static void r600_disk_cache_create(struct r600_common_screen *rscreen)
> +{
> +   uint32_t mesa_timestamp;
> +   if (disk_cache_get_function_timestamp(r600_disk_cache_create,
> + _timestamp)) {
> +   char *timestamp_str;
> +   int res = -1;
> +#if HAVE_LLVM
> +   uint32_t llvm_timestamp;
> +   if 
> (disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
> + _timestamp)) {
> +
> +   res = asprintf(_str, "%u_%u", 
> mesa_timestamp,
> +  llvm_timestamp);
> +   } else {
> +#endif
> +   /* We only use a Mesa only timestamp if less than SI
> +* because we must have an LLVM identifier to avoid
> +* shaders not being rebuild when the LLVM version
> +* changes.
> +*/
> +   if (rscreen->chip_class < SI) {
> +   res = asprintf(_str, "%u",
> +  mesa_timestamp);
> +   }
> +#if HAVE_LLVM
> +   }
> +#endif
> +   if (res != -1) {
> +   rscreen->disk_shader_cache =
> +   disk_cache_create(r600_get_chip_name(rscreen),
> + timestamp_str);
> +   free(timestamp_str);
> +   }
> +   }
> +}
> +
> +static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen 
> *pscreen)
> +{
> +   struct r600_common_screen *rscreen = (struct 
> r600_common_screen*)pscreen;
> +   return rscreen->disk_shader_cache;
> +}
> +
>  static const char* r600_get_name(struct pipe_screen* pscreen)
>  {
> struct r600_common_screen *rscreen = (struct 
> r600_common_screen*)pscreen;
> @@ -1234,6 +1281,7 @@ bool r600_common_screen_init(struct r600_common_screen 
> *rscreen,
> rscreen->b.get_name = r600_get_name;
> rscreen->b.get_vendor = r600_get_vendor;
> rscreen->b.get_device_vendor = r600_get_device_vendor;
> +   rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
> rscreen->b.get_compute_param = r600_get_compute_param;
> rscreen->b.get_paramf = r600_get_paramf;
> rscreen->b.get_timestamp = r600_get_timestamp;
> @@ -1243,6 +1291,8 @@ bool r600_common_screen_init(struct r600_common_screen 
> *rscreen,
> rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
> rscreen->b.query_memory_info = r600_query_memory_info;
>
> +   r600_disk_cache_create(rscreen);
> +
> if (rscreen->info.has_uvd) {
> rscreen->b.get_video_param = rvid_get_video_param;
> rscreen->b.is_video_format_supported = 
> rvid_is_format_supported;
> @@ -1324,6 +1374,7 @@ void r600_destroy_common_screen(struct 
> r600_common_screen *rscreen)
>
> slab_destroy_parent(>pool_transfers);
>
> +   disk_cache_destroy(rscreen->disk_shader_cache);
> rscreen->ws->destroy(rscreen->ws);
> FREE(rscreen);
>  }
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
> b/src/gallium/drivers/radeon/r600_pipe_common.h
> index e8dbf5d..92b9532 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -36,6 +36,7 @@
>
>  #include "radeon/radeon_winsys.h"
>
> +#include "util/disk_cache.h"
>  #include "util/u_blitter.h"
>  #include "util/list.h"
>  #include "util/u_range.h"
> @@ -404,6 +405,8 @@ struct r600_common_screen {
> bool  

[Mesa-dev] [PATCH V3] r600/radeonsi: enable glsl/tgsi on-disk cache

[Timothy Arceri]

For gpu generations that use LLVM we create a timestamp string
containing both the LLVM and Mesa build times, otherwise we just
use the Mesa build time.

V2: share code in r600_pipe_common as suggested by Marek.

V3: send the correct revision of V2
---
 src/gallium/drivers/radeon/r600_pipe_common.c | 51 +++
 src/gallium/drivers/radeon/r600_pipe_common.h |  3 ++
 2 files changed, 54 insertions(+)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 1781584..614eef1 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -43,6 +43,10 @@
 #define HAVE_LLVM 0
 #endif
 
+#if HAVE_LLVM
+#include 
+#endif
+
 #ifndef MESA_LLVM_VERSION_PATCH
 #define MESA_LLVM_VERSION_PATCH 0
 #endif
@@ -779,6 +783,49 @@ static const char* r600_get_chip_name(struct 
r600_common_screen *rscreen)
}
 }
 
+static void r600_disk_cache_create(struct r600_common_screen *rscreen)
+{
+   uint32_t mesa_timestamp;
+   if (disk_cache_get_function_timestamp(r600_disk_cache_create,
+ _timestamp)) {
+   char *timestamp_str;
+   int res = -1;
+#if HAVE_LLVM
+   uint32_t llvm_timestamp;
+   if 
(disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
+ _timestamp)) {
+
+   res = asprintf(_str, "%u_%u", mesa_timestamp,
+  llvm_timestamp);
+   } else {
+#endif
+   /* We only use a Mesa only timestamp if less than SI
+* because we must have an LLVM identifier to avoid
+* shaders not being rebuild when the LLVM version
+* changes.
+*/
+   if (rscreen->chip_class < SI) {
+   res = asprintf(_str, "%u",
+  mesa_timestamp);
+   }
+#if HAVE_LLVM
+   }
+#endif
+   if (res != -1) {
+   rscreen->disk_shader_cache =
+   disk_cache_create(r600_get_chip_name(rscreen),
+ timestamp_str);
+   free(timestamp_str);
+   }
+   }
+}
+
+static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen 
*pscreen)
+{
+   struct r600_common_screen *rscreen = (struct 
r600_common_screen*)pscreen;
+   return rscreen->disk_shader_cache;
+}
+
 static const char* r600_get_name(struct pipe_screen* pscreen)
 {
struct r600_common_screen *rscreen = (struct 
r600_common_screen*)pscreen;
@@ -1234,6 +1281,7 @@ bool r600_common_screen_init(struct r600_common_screen 
*rscreen,
rscreen->b.get_name = r600_get_name;
rscreen->b.get_vendor = r600_get_vendor;
rscreen->b.get_device_vendor = r600_get_device_vendor;
+   rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
rscreen->b.get_compute_param = r600_get_compute_param;
rscreen->b.get_paramf = r600_get_paramf;
rscreen->b.get_timestamp = r600_get_timestamp;
@@ -1243,6 +1291,8 @@ bool r600_common_screen_init(struct r600_common_screen 
*rscreen,
rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
rscreen->b.query_memory_info = r600_query_memory_info;
 
+   r600_disk_cache_create(rscreen);
+
if (rscreen->info.has_uvd) {
rscreen->b.get_video_param = rvid_get_video_param;
rscreen->b.is_video_format_supported = rvid_is_format_supported;
@@ -1324,6 +1374,7 @@ void r600_destroy_common_screen(struct r600_common_screen 
*rscreen)
 
slab_destroy_parent(>pool_transfers);
 
+   disk_cache_destroy(rscreen->disk_shader_cache);
rscreen->ws->destroy(rscreen->ws);
FREE(rscreen);
 }
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index e8dbf5d..92b9532 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -36,6 +36,7 @@
 
 #include "radeon/radeon_winsys.h"
 
+#include "util/disk_cache.h"
 #include "util/u_blitter.h"
 #include "util/list.h"
 #include "util/u_range.h"
@@ -404,6 +405,8 @@ struct r600_common_screen {
boolhas_cp_dma;
boolhas_streamout;
 
+   struct disk_cache   *disk_shader_cache;
+
struct slab_parent_pool pool_transfers;
 
/* Texture filter settings. */
-- 
2.9.3

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Re: [Mesa-dev] [Mesa-stable] [PATCH 1/2] radeonsi: handle MultiDrawIndirect in si_get_draw_start_count

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Mon, Feb 20, 2017 at 12:21 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> Also handle the GL_ARB_indirect_parameters case where the count itself
> is in a buffer.
>
> Use transfers rather than mapping the buffers directly. This anticipates
> the possibility that the buffers are sparse (once ARB_sparse_buffer is
> implemented), in which case they cannot be mapped directly.
>
> Fixes GL45-CTS.gtf43.GL3Tests.multi_draw_indirect.multi_draw_indirect_type
> on <= CIK.
>
> Cc: mesa-sta...@lists.freedesktop.org
> ---
>  src/gallium/drivers/radeonsi/si_state_draw.c | 54 
> 
>  1 file changed, 47 insertions(+), 7 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
> b/src/gallium/drivers/radeonsi/si_state_draw.c
> index 141dd8f..e022d5c 100644
> --- a/src/gallium/drivers/radeonsi/si_state_draw.c
> +++ b/src/gallium/drivers/radeonsi/si_state_draw.c
> @@ -914,13 +914,53 @@ static void si_get_draw_start_count(struct si_context 
> *sctx,
> unsigned *start, unsigned *count)
>  {
> if (info->indirect) {
> -   struct r600_resource *indirect =
> -   (struct r600_resource*)info->indirect;
> -   int *data = r600_buffer_map_sync_with_rings(>b,
> -   indirect, PIPE_TRANSFER_READ);
> -data += info->indirect_offset/sizeof(int);
> -   *start = data[2];
> -   *count = data[0];
> +   unsigned indirect_count;
> +   struct pipe_transfer *transfer;
> +   unsigned begin, end;
> +   unsigned map_size;
> +   unsigned *data;
> +
> +   if (info->indirect_params) {
> +   data = pipe_buffer_map_range(>b.b,
> +   info->indirect_params,
> +   info->indirect_params_offset,
> +   sizeof(unsigned),
> +   PIPE_TRANSFER_READ, );
> +
> +   indirect_count = *data;
> +
> +   pipe_buffer_unmap(>b.b, transfer);
> +   } else {
> +   indirect_count = info->indirect_count;
> +   }
> +
> +   if (!indirect_count) {
> +   *start = *count = 0;
> +   return;
> +   }
> +
> +   map_size = (indirect_count - 1) * info->indirect_stride + 3 * 
> sizeof(unsigned);
> +   data = pipe_buffer_map_range(>b.b, info->indirect,
> +info->indirect_offset, map_size,
> +PIPE_TRANSFER_READ, );
> +
> +   begin = UINT_MAX;
> +   end = 0;
> +
> +   for (unsigned i = 0; i < indirect_count; ++i) {
> +   unsigned count = data[0];
> +   unsigned start = data[2];
> +
> +   if (count > 0) {
> +   begin = MIN2(begin, start);
> +   end = MAX2(end, start + count);
> +   }
> +
> +   data += info->indirect_stride / sizeof(unsigned);
> +   }
> +
> +   *start = begin;
> +   *count = end - begin;
> } else {
> *start = info->start;
> *count = info->count;
> --
> 2.9.3
>
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[Mesa-dev] [PATCH v2 4/4] r600/radeonsi: enable glsl/tgsi on-disk cache

[Timothy Arceri]

For gpu generations that use LLVM we create a timestamp string
containing both the LLVM and Mesa build times, otherwise we just
use the Mesa build time.

V2: share code in r600_pipe_common as suggested by Marek.
---
 src/gallium/drivers/radeon/r600_pipe_common.c | 44 +++
 src/gallium/drivers/radeon/r600_pipe_common.h |  3 ++
 2 files changed, 47 insertions(+)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 1781584..4057058 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -43,6 +43,10 @@
 #define HAVE_LLVM 0
 #endif
 
+#if HAVE_LLVM
+#include 
+#endif
+
 #ifndef MESA_LLVM_VERSION_PATCH
 #define MESA_LLVM_VERSION_PATCH 0
 #endif
@@ -779,6 +783,42 @@ static const char* r600_get_chip_name(struct 
r600_common_screen *rscreen)
}
 }
 
+static void r600_disk_cache_create(struct r600_common_screen *rscreen)
+{
+   uint32_t mesa_timestamp;
+   if (disk_cache_get_function_timestamp(r600_disk_cache_create,
+ _timestamp)) {
+   char *timestamp_str;
+   int res;
+#if HAVE_LLVM
+   uint32_t llvm_timestamp;
+   if (rscreen->chip_class >= SI &&
+   
disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
+ _timestamp)) {
+
+   res = asprintf(_str, "%u_%u", mesa_timestamp,
+  llvm_timestamp);
+   } else {
+#endif
+   res = asprintf(_str, "%u", mesa_timestamp);
+#if HAVE_LLVM
+   }
+#endif
+   if (res != -1) {
+   rscreen->disk_shader_cache =
+   disk_cache_create(r600_get_chip_name(rscreen),
+ timestamp_str);
+   free(timestamp_str);
+   }
+   }
+}
+
+static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen 
*pscreen)
+{
+   struct r600_common_screen *rscreen = (struct 
r600_common_screen*)pscreen;
+   return rscreen->disk_shader_cache;
+}
+
 static const char* r600_get_name(struct pipe_screen* pscreen)
 {
struct r600_common_screen *rscreen = (struct 
r600_common_screen*)pscreen;
@@ -1234,6 +1274,7 @@ bool r600_common_screen_init(struct r600_common_screen 
*rscreen,
rscreen->b.get_name = r600_get_name;
rscreen->b.get_vendor = r600_get_vendor;
rscreen->b.get_device_vendor = r600_get_device_vendor;
+   rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
rscreen->b.get_compute_param = r600_get_compute_param;
rscreen->b.get_paramf = r600_get_paramf;
rscreen->b.get_timestamp = r600_get_timestamp;
@@ -1243,6 +1284,8 @@ bool r600_common_screen_init(struct r600_common_screen 
*rscreen,
rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
rscreen->b.query_memory_info = r600_query_memory_info;
 
+   r600_disk_cache_create(rscreen);
+
if (rscreen->info.has_uvd) {
rscreen->b.get_video_param = rvid_get_video_param;
rscreen->b.is_video_format_supported = rvid_is_format_supported;
@@ -1324,6 +1367,7 @@ void r600_destroy_common_screen(struct r600_common_screen 
*rscreen)
 
slab_destroy_parent(>pool_transfers);
 
+   disk_cache_destroy(rscreen->disk_shader_cache);
rscreen->ws->destroy(rscreen->ws);
FREE(rscreen);
 }
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index e8dbf5d..92b9532 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -36,6 +36,7 @@
 
 #include "radeon/radeon_winsys.h"
 
+#include "util/disk_cache.h"
 #include "util/u_blitter.h"
 #include "util/list.h"
 #include "util/u_range.h"
@@ -404,6 +405,8 @@ struct r600_common_screen {
boolhas_cp_dma;
boolhas_streamout;
 
+   struct disk_cache   *disk_shader_cache;
+
struct slab_parent_pool pool_transfers;
 
/* Texture filter settings. */
-- 
2.9.3

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[Mesa-dev] [PATCH 3.5/4] st/mesa: get on-disk shader cache

[Timothy Arceri]

---
 src/mesa/state_tracker/st_context.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/state_tracker/st_context.c 
b/src/mesa/state_tracker/st_context.c
index f4ad6d8..153f01c 100644
--- a/src/mesa/state_tracker/st_context.c
+++ b/src/mesa/state_tracker/st_context.c
@@ -538,6 +538,8 @@ struct st_context *st_create_context(gl_api api, struct 
pipe_context *pipe,
   return NULL;
}
 
+   ctx->Cache = pipe->screen->get_disk_shader_cache(pipe->screen);
+
st_init_driver_flags(>DriverFlags);
 
/* XXX: need a capability bit in gallium to query if the pipe
-- 
2.9.3

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Re: [Mesa-dev] [PATCH v2] radeonsi: handle MultiDrawIndirect in si_get_draw_start_count

[Edward O'Callaghan]

v2 is,
Acked-by: Edward O'Callaghan 

On 02/21/2017 09:05 AM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle 
> 
> Also handle the GL_ARB_indirect_parameters case where the count itself
> is in a buffer.
> 
> Use transfers rather than mapping the buffers directly. This anticipates
> the possibility that the buffers are sparse (once ARB_sparse_buffer is
> implemented), in which case they cannot be mapped directly.
> 
> Fixes GL45-CTS.gtf43.GL3Tests.multi_draw_indirect.multi_draw_indirect_type
> on <= CIK.
> 
> v2:
> - unmap the indirect buffer correctly
> - handle the corner case where we have indirect draws, but all of them
>   have count 0.
> 
> Cc: mesa-sta...@lists.freedesktop.org
> Reviewed-by: Marek Olšák  (v1)
> ---
>  src/gallium/drivers/radeonsi/si_state_draw.c | 60 
> 
>  1 file changed, 53 insertions(+), 7 deletions(-)
> 
> diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
> b/src/gallium/drivers/radeonsi/si_state_draw.c
> index 141dd8f..1ff1547 100644
> --- a/src/gallium/drivers/radeonsi/si_state_draw.c
> +++ b/src/gallium/drivers/radeonsi/si_state_draw.c
> @@ -907,27 +907,73 @@ void si_emit_cache_flush(struct si_context *sctx)
>   }
>  
>   rctx->flags = 0;
>  }
>  
>  static void si_get_draw_start_count(struct si_context *sctx,
>   const struct pipe_draw_info *info,
>   unsigned *start, unsigned *count)
>  {
>   if (info->indirect) {
> - struct r600_resource *indirect =
> - (struct r600_resource*)info->indirect;
> - int *data = r600_buffer_map_sync_with_rings(>b,
> - indirect, PIPE_TRANSFER_READ);
> -data += info->indirect_offset/sizeof(int);
> - *start = data[2];
> - *count = data[0];
> + unsigned indirect_count;
> + struct pipe_transfer *transfer;
> + unsigned begin, end;
> + unsigned map_size;
> + unsigned *data;
> +
> + if (info->indirect_params) {
> + data = pipe_buffer_map_range(>b.b,
> + info->indirect_params,
> + info->indirect_params_offset,
> + sizeof(unsigned),
> + PIPE_TRANSFER_READ, );
> +
> + indirect_count = *data;
> +
> + pipe_buffer_unmap(>b.b, transfer);
> + } else {
> + indirect_count = info->indirect_count;
> + }
> +
> + if (!indirect_count) {
> + *start = *count = 0;
> + return;
> + }
> +
> + map_size = (indirect_count - 1) * info->indirect_stride + 3 * 
> sizeof(unsigned);
> + data = pipe_buffer_map_range(>b.b, info->indirect,
> +  info->indirect_offset, map_size,
> +  PIPE_TRANSFER_READ, );
> +
> + begin = UINT_MAX;
> + end = 0;
> +
> + for (unsigned i = 0; i < indirect_count; ++i) {
> + unsigned count = data[0];
> + unsigned start = data[2];
> +
> + if (count > 0) {
> + begin = MIN2(begin, start);
> + end = MAX2(end, start + count);
> + }
> +
> + data += info->indirect_stride / sizeof(unsigned);
> + }
> +
> + pipe_buffer_unmap(>b.b, transfer);
> +
> + if (begin < end) {
> + *start = begin;
> + *count = end - begin;
> + } else {
> + *start = *count = 0;
> + }
>   } else {
>   *start = info->start;
>   *count = info->count;
>   }
>  }
>  
>  void si_ce_pre_draw_synchronization(struct si_context *sctx)
>  {
>   if (sctx->ce_need_synchronization) {
>   radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
> 



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Re: [Mesa-dev] [PATCH] r300g: only allow byteswapped formats on big endian

[Grazvydas Ignotas]

So, as there are no better solutions in sight, can somebody please
push this patch?

Gražvydas

On Wed, Feb 15, 2017 at 5:33 AM, Alex Deucher  wrote:
> On Tue, Feb 14, 2017 at 10:27 PM, Michel Dänzer  wrote:
>> On 14/02/17 08:25 PM, Marek Olšák wrote:
>>> I've changed my mind. The patch can be merged if nobody disagrees.
>>
>> It would be nice to better understand what exactly the problem is. It
>> seems unlikely that it's actually an endianness specific problem in the
>> driver code, more likely an endianness specific problem in state tracker
>> code, or maybe a non-endianness-specific problem in the driver code
>> (which may or may not be possible to hit on big endian hosts as well).
>>
>> In other words, I suspect this isn't a fix for the actual problem, but
>> just a workaround. That said, if you guys are happy with that, I'm not
>> holding it up.
>
> I tend to agree, but OTOH, r300 is pretty old and BE systems are
> pretty few and far between these days.  Neither of which are conducive
> to spending much time on them.  Someone with an interest in BE systems
> really needs to step up and fix up endian handling in mesa for real.
>
> Alex
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[Mesa-dev] [PATCH v2] radeonsi: handle MultiDrawIndirect in si_get_draw_start_count

[Nicolai Hähnle]

From: Nicolai Hähnle 

Also handle the GL_ARB_indirect_parameters case where the count itself
is in a buffer.

Use transfers rather than mapping the buffers directly. This anticipates
the possibility that the buffers are sparse (once ARB_sparse_buffer is
implemented), in which case they cannot be mapped directly.

Fixes GL45-CTS.gtf43.GL3Tests.multi_draw_indirect.multi_draw_indirect_type
on <= CIK.

v2:
- unmap the indirect buffer correctly
- handle the corner case where we have indirect draws, but all of them
  have count 0.

Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák  (v1)
---
 src/gallium/drivers/radeonsi/si_state_draw.c | 60 
 1 file changed, 53 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 141dd8f..1ff1547 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -907,27 +907,73 @@ void si_emit_cache_flush(struct si_context *sctx)
}
 
rctx->flags = 0;
 }
 
 static void si_get_draw_start_count(struct si_context *sctx,
const struct pipe_draw_info *info,
unsigned *start, unsigned *count)
 {
if (info->indirect) {
-   struct r600_resource *indirect =
-   (struct r600_resource*)info->indirect;
-   int *data = r600_buffer_map_sync_with_rings(>b,
-   indirect, PIPE_TRANSFER_READ);
-data += info->indirect_offset/sizeof(int);
-   *start = data[2];
-   *count = data[0];
+   unsigned indirect_count;
+   struct pipe_transfer *transfer;
+   unsigned begin, end;
+   unsigned map_size;
+   unsigned *data;
+
+   if (info->indirect_params) {
+   data = pipe_buffer_map_range(>b.b,
+   info->indirect_params,
+   info->indirect_params_offset,
+   sizeof(unsigned),
+   PIPE_TRANSFER_READ, );
+
+   indirect_count = *data;
+
+   pipe_buffer_unmap(>b.b, transfer);
+   } else {
+   indirect_count = info->indirect_count;
+   }
+
+   if (!indirect_count) {
+   *start = *count = 0;
+   return;
+   }
+
+   map_size = (indirect_count - 1) * info->indirect_stride + 3 * 
sizeof(unsigned);
+   data = pipe_buffer_map_range(>b.b, info->indirect,
+info->indirect_offset, map_size,
+PIPE_TRANSFER_READ, );
+
+   begin = UINT_MAX;
+   end = 0;
+
+   for (unsigned i = 0; i < indirect_count; ++i) {
+   unsigned count = data[0];
+   unsigned start = data[2];
+
+   if (count > 0) {
+   begin = MIN2(begin, start);
+   end = MAX2(end, start + count);
+   }
+
+   data += info->indirect_stride / sizeof(unsigned);
+   }
+
+   pipe_buffer_unmap(>b.b, transfer);
+
+   if (begin < end) {
+   *start = begin;
+   *count = end - begin;
+   } else {
+   *start = *count = 0;
+   }
} else {
*start = info->start;
*count = info->count;
}
 }
 
 void si_ce_pre_draw_synchronization(struct si_context *sctx)
 {
if (sctx->ce_need_synchronization) {
radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
-- 
2.9.3

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Re: [Mesa-dev] [PATCH] st/nine: make use of common uploaders v3

[Axel Davy]

On 20/02/2017 21:30, Constantine Charlamov wrote:

Make use of common uploaders that landed recently to Mesa

v2: fixed formatting, broken due to thunderbird configuration

v3: per Axel comment: added a comment into NineDevice9_DrawPrimitiveUP

---
  src/gallium/state_trackers/nine/device9.c| 50 +---
  src/gallium/state_trackers/nine/device9.h|  5 ---
  src/gallium/state_trackers/nine/nine_ff.c|  8 ++---
  src/gallium/state_trackers/nine/nine_state.c | 48 +-
  4 files changed, 37 insertions(+), 74 deletions(-)

diff --git a/src/gallium/state_trackers/nine/device9.c 
b/src/gallium/state_trackers/nine/device9.c
index b9b7a637d7..86c8e38535 100644
--- a/src/gallium/state_trackers/nine/device9.c
+++ b/src/gallium/state_trackers/nine/device9.c
@@ -477,31 +477,8 @@ NineDevice9_ctor( struct NineDevice9 *This,
  This->driver_caps.user_cbufs = GET_PCAP(USER_CONSTANT_BUFFERS);
  This->driver_caps.user_sw_vbufs = 
This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_VERTEX_BUFFERS);
  This->driver_caps.user_sw_cbufs = 
This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_CONSTANT_BUFFERS);
-
-/* Implicit use of context pipe for vertex and index uploaded when
- * csmt is not active. Does not need to sync since csmt is unactive,
- * thus no need to call NineDevice9_GetPipe at each upload. */
-if (!This->driver_caps.user_vbufs)
-This->vertex_uploader = u_upload_create(This->csmt_active ?
-This->pipe_secondary : 
This->context.pipe,
-65536,
-PIPE_BIND_VERTEX_BUFFER, 
PIPE_USAGE_STREAM);
-This->vertex_sw_uploader = u_upload_create(This->pipe_sw, 65536,
-PIPE_BIND_VERTEX_BUFFER, 
PIPE_USAGE_STREAM);
-if (!This->driver_caps.user_ibufs)
-This->index_uploader = u_upload_create(This->csmt_active ?
-This->pipe_secondary : 
This->context.pipe,
-   128 * 1024,
-   PIPE_BIND_INDEX_BUFFER, 
PIPE_USAGE_STREAM);
-if (!This->driver_caps.user_cbufs) {
+if (!This->driver_caps.user_cbufs)
  This->constbuf_alignment = GET_PCAP(CONSTANT_BUFFER_OFFSET_ALIGNMENT);
-This->constbuf_uploader = u_upload_create(This->context.pipe, 
This->vs_const_size,
-  PIPE_BIND_CONSTANT_BUFFER, 
PIPE_USAGE_STREAM);
-}
-
-This->constbuf_sw_uploader = u_upload_create(This->pipe_sw, 128 * 1024,
- PIPE_BIND_CONSTANT_BUFFER, 
PIPE_USAGE_STREAM);
-
  This->driver_caps.window_space_position_support = 
GET_PCAP(TGSI_VS_WINDOW_SPACE_POSITION);
  This->driver_caps.vs_integer = pScreen->get_shader_param(pScreen, 
PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS);
  This->driver_caps.ps_integer = pScreen->get_shader_param(pScreen, 
PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_INTEGERS);
@@ -552,17 +529,6 @@ NineDevice9_dtor( struct NineDevice9 *This )
  nine_state_clear(>state, TRUE);
  nine_context_clear(This);
  
-if (This->vertex_uploader)

-u_upload_destroy(This->vertex_uploader);
-if (This->index_uploader)
-u_upload_destroy(This->index_uploader);
-if (This->constbuf_uploader)
-u_upload_destroy(This->constbuf_uploader);
-if (This->vertex_sw_uploader)
-u_upload_destroy(This->vertex_sw_uploader);
-if (This->constbuf_sw_uploader)
-u_upload_destroy(This->constbuf_sw_uploader);
-
  nine_bind(>record, NULL);
  
  pipe_sampler_view_reference(>dummy_sampler_view, NULL);

@@ -2852,15 +2818,17 @@ NineDevice9_DrawPrimitiveUP( struct NineDevice9 *This,
  vtxbuf.buffer = NULL;
  vtxbuf.user_buffer = pVertexStreamZeroData;
  
+// csmt is unactive when user vertex or index buffers are used, thus no

+// need to call NineDevice9_GetPipe.

Comments in gallium nine are C style.

Axel

  if (!This->driver_caps.user_vbufs) {
-u_upload_data(This->vertex_uploader,
+u_upload_data(This->context.pipe->stream_uploader,
0,
(prim_count_to_vertex_count(PrimitiveType, 
PrimitiveCount)) * VertexStreamZeroStride, /* XXX */
4,
vtxbuf.user_buffer,
_offset,
);
-u_upload_unmap(This->vertex_uploader);
+u_upload_unmap(This->context.pipe->stream_uploader);
  vtxbuf.user_buffer = NULL;
  }
  
@@ -2916,27 +2884,27 @@ NineDevice9_DrawIndexedPrimitiveUP( struct NineDevice9 *This,
  
  if (!This->driver_caps.user_vbufs) {

  const unsigned base = MinVertexIndex * VertexStreamZeroStride;
-u_upload_data(This->vertex_uploader,
+

Re: [Mesa-dev] [PATCH] st/nine: make use of common uploaders v2

[Constantine Charlamov]

Version 3 sent. Sorry, I haven't figured out — I ought to add you to CC.


On 20.02.2017 22:49, Axel Davy wrote:
> On 20/02/2017 20:22, Constantine Charlamov wrote:
>> Make use of common uploaders that landed recently to Mesa
>>
>> v2: fixed formatting, broken due to thunderbird configuration
>>
>> ---
>>  src/gallium/state_trackers/nine/device9.c| 48 
>> 
>>  src/gallium/state_trackers/nine/device9.h|  5 ---
>>  src/gallium/state_trackers/nine/nine_ff.c|  8 ++---
>>  src/gallium/state_trackers/nine/nine_state.c | 48 
>> ++--
>>  4 files changed, 35 insertions(+), 74 deletions(-)
>>
>> diff --git a/src/gallium/state_trackers/nine/device9.c 
>> b/src/gallium/state_trackers/nine/device9.c
>> index b9b7a637d7..2ae8678c31 100644
>> --- a/src/gallium/state_trackers/nine/device9.c
>> +++ b/src/gallium/state_trackers/nine/device9.c
>> @@ -477,31 +477,8 @@ NineDevice9_ctor( struct NineDevice9 *This,
>>  This->driver_caps.user_cbufs = GET_PCAP(USER_CONSTANT_BUFFERS);
>>  This->driver_caps.user_sw_vbufs = 
>> This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_VERTEX_BUFFERS);
>>  This->driver_caps.user_sw_cbufs = 
>> This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_CONSTANT_BUFFERS);
>> -
>> -/* Implicit use of context pipe for vertex and index uploaded when
>> - * csmt is not active. Does not need to sync since csmt is unactive,
>> - * thus no need to call NineDevice9_GetPipe at each upload. */
> I'd like to have this comment kept somehow (though the use of context pipe is 
> not implicit anymore).
>
> I guess it should be in NineDevice9_DrawPrimitiveUP just before if 
> (!This->driver_caps.user_vbufs).
>
> It could be: csmt is unactive when user vertex or index buffers are used, 
> thus no need to call NineDevice8_GetPipe.
>
> Axel
>> -if (!This->driver_caps.user_vbufs)
>> -This->vertex_uploader = u_upload_create(This->csmt_active ?
>> -This->pipe_secondary : 
>> This->context.pipe,
>> -65536,
>> -PIPE_BIND_VERTEX_BUFFER, 
>> PIPE_USAGE_STREAM);
>> -This->vertex_sw_uploader = u_upload_create(This->pipe_sw, 65536,
>> -PIPE_BIND_VERTEX_BUFFER, 
>> PIPE_USAGE_STREAM);
>> -if (!This->driver_caps.user_ibufs)
>> -This->index_uploader = u_upload_create(This->csmt_active ?
>> -This->pipe_secondary : 
>> This->context.pipe,
>> -   128 * 1024,
>> -   PIPE_BIND_INDEX_BUFFER, 
>> PIPE_USAGE_STREAM);
>> -if (!This->driver_caps.user_cbufs) {
>> +if (!This->driver_caps.user_cbufs)
>>  This->constbuf_alignment = 
>> GET_PCAP(CONSTANT_BUFFER_OFFSET_ALIGNMENT);
>> -This->constbuf_uploader = u_upload_create(This->context.pipe, 
>> This->vs_const_size,
>> -  
>> PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
>> -}
>> -
>> -This->constbuf_sw_uploader = u_upload_create(This->pipe_sw, 128 * 1024,
>> - PIPE_BIND_CONSTANT_BUFFER, 
>> PIPE_USAGE_STREAM);
>> -
>>  This->driver_caps.window_space_position_support = 
>> GET_PCAP(TGSI_VS_WINDOW_SPACE_POSITION);
>>  This->driver_caps.vs_integer = pScreen->get_shader_param(pScreen, 
>> PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS);
>>  This->driver_caps.ps_integer = pScreen->get_shader_param(pScreen, 
>> PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_INTEGERS);
>> @@ -552,17 +529,6 @@ NineDevice9_dtor( struct NineDevice9 *This )
>>  nine_state_clear(>state, TRUE);
>>  nine_context_clear(This);
>>  
>> -if (This->vertex_uploader)
>> -u_upload_destroy(This->vertex_uploader);
>> -if (This->index_uploader)
>> -u_upload_destroy(This->index_uploader);
>> -if (This->constbuf_uploader)
>> -u_upload_destroy(This->constbuf_uploader);
>> -if (This->vertex_sw_uploader)
>> -u_upload_destroy(This->vertex_sw_uploader);
>> -if (This->constbuf_sw_uploader)
>> -u_upload_destroy(This->constbuf_sw_uploader);
>> -
>>  nine_bind(>record, NULL);
>>  
>>  pipe_sampler_view_reference(>dummy_sampler_view, NULL);
>> @@ -2853,14 +2819,14 @@ NineDevice9_DrawPrimitiveUP( struct NineDevice9 
>> *This,
>>  vtxbuf.user_buffer = pVertexStreamZeroData;
>>  
>>  if (!This->driver_caps.user_vbufs) {
>> -u_upload_data(This->vertex_uploader,
>> +u_upload_data(This->context.pipe->stream_uploader,
>>0,
>>(prim_count_to_vertex_count(PrimitiveType, 
>> PrimitiveCount)) * VertexStreamZeroStride, /* XXX */
>>4,
>>vtxbuf.user_buffer,
>>

Re: [Mesa-dev] Gallium: Removal of set_index_buffer (discussion)

[Marek Olšák]

On Mon, Feb 20, 2017 at 9:28 PM, Roland Scheidegger  wrote:
> Am 20.02.2017 um 20:56 schrieb Marek Olšák:
>> On Mon, Feb 20, 2017 at 8:29 PM, Axel Davy  wrote:
>>> On 20/02/2017 20:11, Ilia Mirkin wrote:

 On Mon, Feb 20, 2017 at 2:01 PM, Marek Olšák  wrote:
>
> Hi,
>
> I'd like to remove pipe_context::set_index_buffer. It's not useful to
> most drivers and the interface is inconvenient for Mesa/OpenGL,
> because it's a draw state that is set with a separate driver callback,
> which is an unnecessary driver roundtrip taking some CPU cycles. I'd
> prefer to pass the index buffer via pipe_draw_info.
>
> I'm aware that the interface was inherited from DX10, but I don't
> think that makes any difference here. DX10 state trackers can pass the
> index buffer via pipe_draw_info too.
>
> This is my proposal:
>
> iff --git a/src/gallium/include/pipe/p_state.h
> b/src/gallium/include/pipe/p_state.h
> index ce19b92..cffbb33 100644
> --- a/src/gallium/include/pipe/p_state.h
> +++ b/src/gallium/include/pipe/p_state.h
> @@ -635,7 +635,7 @@ struct pipe_index_buffer
>*/
>   struct pipe_draw_info
>   {
> -   boolean indexed;  /**< use index buffer */
> +   ubyte index_size;  /**< 0 = non-indexed */
>>>
>>> Isn't that enough to say non-index when index_buffer and user_indices are
>>> NULL ?
>>
>> We still need index_size and it's only 8 bits as opposed to 64 bits.
> FWIW at least in d3d10 you can actually have indexed rendering without
> an index buffer bound. This is perfectly valid, you're just expected to
> return always zero for all indices... Albeit I believe we actually deal
> with this with a dummy buffer.
>
>>
>
>  enum pipe_prim_type mode;  /**< the mode of the primitive */
>  boolean primitive_restart;
>  ubyte vertices_per_patch; /**< the number of vertices per patch */
> @@ -666,12 +666,18 @@ struct pipe_draw_info
>
>  unsigned indirect_params_offset; /**< must be 4 byte aligned */
>
> +   /**
> +* Index buffer. Only one can be non-NULL.
> +*/
> +   struct pipe_resource *index_buffer; /* "start" is the offset */

 Works for me. Is start the offset in bytes or is start * index_size
 the offset in bytes?
>>>
>>> Same question here. My understanding is that start is in terms of start *
>>> index_size bytes.
>>
>> offset = start * index_size;
>>
>>> But we really want to have a byte offset.
>>
>> The offset should be aligned to index_size, otherwise hardware won't work.
> Are you sure of that? d3d10 doesn't seem to have such a requirement, or
> if it has I can't find it now (so, the startIndex really is in terms of
> index units, but the offset of the buffer is in terms of bytes, and the
> docs don't seem to mention it's limited to index alignment).
> I don't actually see such a limitation in GL neither, albeit some quick
> googling seems to suggest YMMV (e.g.
> http://irrlicht.sourceforge.net/forum/viewtopic.php?f=7=51444).
> So, I can't quite tell right now if we really need byte offsets...

It's a natural requirement of hardware. It doesn't have to be
documented IMO. CPUs might not support it either.

>
> Otherwise we should be able to deal with the interface change (that
> said, arguably the old one is quite consistent with the analogous
> set_vertex_buffers call - vulkan also has two analogous entry points for
> setting vertex and index buffers, so it can't be all that wrong).
> Do you have some evidence this really saves some measurable cpu cycles?

Yes it can be measurable, but it's not massive. setup_index_buffer is
close to 1% in torcs. We can also lose time elsewhere due to cache
evictions. It's never just about CPU time in one function.

My plan is:
- get rid of pipe_index_buffer
- get rid of _mesa_index_buffer
- make _mesa_prim the same as pipe_draw_info
- pretty much set pipe_draw_info in the vbo module

In light of that, the performance question of set_index_buffer has
little relevance.

Marek
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Re: [Mesa-dev] [PATCH v2 1/3] i965/fs: fix indirect load DF uniforms on BSW/BXT

[Francisco Jerez]

Samuel Iglesias Gonsálvez  writes:

> On Mon, 2017-02-20 at 08:58 +0100, Samuel Iglesias Gonsálvez wrote:
>> On Sat, 2017-02-18 at 18:58 -0800, Francisco Jerez wrote:
>> > Samuel Iglesias Gonsálvez  writes:
>> > 
>> > > The lowered BSW/BXT indirect move instructions had incorrect
>> > > source types, which luckily wasn't causing incorrect assembly to
>> > > be
>> > > generated due to the bug fixed in the next patch, but would have
>> > > confused the remaining back-end IR infrastructure due to the
>> > > mismatch
>> > > between the IR source types and the emitted machine code.
>> > > 
>> > > v2:
>> > > - Improve commit log (Curro)
>> > > - Fix read_size (Curro)
>> > > - Fix DF uniform array detection in assign_constant_locations()
>> > > when
>> > >   it is acceded with 32-bit MOV_INDIRECTs in BSW/BXT.
>> > > 
>> > > Signed-off-by: Samuel Iglesias Gonsálvez 
>> > > Cc: "17.0" 
>> > > ---
>> > >  src/mesa/drivers/dri/i965/brw_fs.cpp | 11 -
>> > >  src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 41 --
>> > > --
>> > >  2 files changed, 30 insertions(+), 22 deletions(-)
>> > > 
>> > > diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
>> > > b/src/mesa/drivers/dri/i965/brw_fs.cpp
>> > > index c348bc7138d..93ab84b5845 100644
>> > > --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
>> > > +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
>> > > @@ -1944,10 +1944,19 @@ fs_visitor::assign_constant_locations()
>> > >  unsigned last = constant_nr + (inst->src[2].ud / 4)
>> > > -
>> > > 1;
>> > >  assert(last < uniforms);
>> > >  
>> > > +bool supports_64bit_indirects =
>> > > +   !devinfo->is_cherryview && !devinfo->is_broxton;
>> > > +/* Detect if this is as a result 64-bit MOV
>> > > INDIRECT.
>> > > In case
>> > > + * of BSW/BXT, we substitute each DF MOV INDIRECT by
>> > > two 32-bit MOV
>> > > + * INDIRECT.
>> > > + */
>> > > +bool mov_indirect_64bit = (type_sz(inst-
>> > > >src[i].type)
>> > > == 8) ||
>> > > +   (!supports_64bit_indirects && inst->dst.type ==
>> > > BRW_REGISTER_TYPE_UD &&
>> > > +inst->src[0].type == BRW_REGISTER_TYPE_UD &&
>> > > inst-
>> > > > dst.stride == 2);
>> > 
>> > This seems kind of fragile, I don't think the optimizer gives you
>> > any
>> > guarantees that the stride of a lowered 64-bit indirect move will
>> > remain
>> > equal to two, or that the destination stride of an actual 32-bit
>> > indirect uniform load will never end up being two as well.  That
>> > said,
>> > because you access these with 32-bit indirect moves, I don't see
>> > why
>> > you'd need to treat them as 64-bit uniforms here, the usual
>> > alignment
>> > requirements for 64-bit uniforms no longer apply, so you can treat
>> > them
>> > as regular 32-bit uniforms AFAICT.  Why did you add this hunk?
>> > 
>> 
>> I added it because of this case: if we access to one DF uniform array
>> element with a normal MOV and the rest with MOV INDIRECT, we will
>> mark
>> the former as a live 64bit variable. Then we have the array scattered
>> as part of it is uploaded as a 64-bits uniform and the other as 32-
>> bits. Even if we avoid this by uploading everything together as 32-
>> bits, then the access to that DF could not be aligned to 64-bits.
>> 
>> So my idea was to find a way to identify somehow those MOV INDIRECT
>> in
>> BSW to mark all the array as a 64-bit one.
>> 
>
> Mmm, maybe I can fix this case without the hack I did. I can add the
> following code after marking all live variables accessed by the
> instructions.
>
> It is very similar to the one to detect live variables but it is fixing
> the case where any MOV INDIRECT in BSW is accessing to an uniform array
> of DF elements where one of these elements is directly accessed by
> another instruction.
>
> What do you think?
>

Looks somewhat better, but I don't think this is correct if you have
multiple overlapping indirect loads of the same uniform array and only
one of them overlaps with a direct 64-bit load.  Apparently
assign_constant_locations() already has code to attempt to push
indirectly accessed uniform sections contiguously, but the logic seems
broken in multiple ways, even on platforms other than CHV/BXT...  The
first is_live_64bit location assignment loop doesn't consider non-64bit
uniforms even if they're marked as contiguous with a 64-bit uniform,
because the contiguous block tracking is done from within
set_push_pull_constant_loc() which may not be called at all if the
continue condition evaluates to true at the top of the loop.  Also
AFAICT this could potentially lead to a very large amount of data being
considered as contiguous if you have a contiguous 64-bit block, then
random unrelated 32-bit data, and then another contiguous 64-bit block,
because the very last element of a MOV_INDIRECT 

[Mesa-dev] [PATCH] st/nine: make use of common uploaders v3

[Constantine Charlamov]

Make use of common uploaders that landed recently to Mesa

v2: fixed formatting, broken due to thunderbird configuration

v3: per Axel comment: added a comment into NineDevice9_DrawPrimitiveUP

---
 src/gallium/state_trackers/nine/device9.c| 50 +---
 src/gallium/state_trackers/nine/device9.h|  5 ---
 src/gallium/state_trackers/nine/nine_ff.c|  8 ++---
 src/gallium/state_trackers/nine/nine_state.c | 48 +-
 4 files changed, 37 insertions(+), 74 deletions(-)

diff --git a/src/gallium/state_trackers/nine/device9.c 
b/src/gallium/state_trackers/nine/device9.c
index b9b7a637d7..86c8e38535 100644
--- a/src/gallium/state_trackers/nine/device9.c
+++ b/src/gallium/state_trackers/nine/device9.c
@@ -477,31 +477,8 @@ NineDevice9_ctor( struct NineDevice9 *This,
 This->driver_caps.user_cbufs = GET_PCAP(USER_CONSTANT_BUFFERS);
 This->driver_caps.user_sw_vbufs = 
This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_VERTEX_BUFFERS);
 This->driver_caps.user_sw_cbufs = 
This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_CONSTANT_BUFFERS);
-
-/* Implicit use of context pipe for vertex and index uploaded when
- * csmt is not active. Does not need to sync since csmt is unactive,
- * thus no need to call NineDevice9_GetPipe at each upload. */
-if (!This->driver_caps.user_vbufs)
-This->vertex_uploader = u_upload_create(This->csmt_active ?
-This->pipe_secondary : 
This->context.pipe,
-65536,
-PIPE_BIND_VERTEX_BUFFER, 
PIPE_USAGE_STREAM);
-This->vertex_sw_uploader = u_upload_create(This->pipe_sw, 65536,
-PIPE_BIND_VERTEX_BUFFER, 
PIPE_USAGE_STREAM);
-if (!This->driver_caps.user_ibufs)
-This->index_uploader = u_upload_create(This->csmt_active ?
-This->pipe_secondary : 
This->context.pipe,
-   128 * 1024,
-   PIPE_BIND_INDEX_BUFFER, 
PIPE_USAGE_STREAM);
-if (!This->driver_caps.user_cbufs) {
+if (!This->driver_caps.user_cbufs)
 This->constbuf_alignment = GET_PCAP(CONSTANT_BUFFER_OFFSET_ALIGNMENT);
-This->constbuf_uploader = u_upload_create(This->context.pipe, 
This->vs_const_size,
-  PIPE_BIND_CONSTANT_BUFFER, 
PIPE_USAGE_STREAM);
-}
-
-This->constbuf_sw_uploader = u_upload_create(This->pipe_sw, 128 * 1024,
- PIPE_BIND_CONSTANT_BUFFER, 
PIPE_USAGE_STREAM);
-
 This->driver_caps.window_space_position_support = 
GET_PCAP(TGSI_VS_WINDOW_SPACE_POSITION);
 This->driver_caps.vs_integer = pScreen->get_shader_param(pScreen, 
PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS);
 This->driver_caps.ps_integer = pScreen->get_shader_param(pScreen, 
PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_INTEGERS);
@@ -552,17 +529,6 @@ NineDevice9_dtor( struct NineDevice9 *This )
 nine_state_clear(>state, TRUE);
 nine_context_clear(This);
 
-if (This->vertex_uploader)
-u_upload_destroy(This->vertex_uploader);
-if (This->index_uploader)
-u_upload_destroy(This->index_uploader);
-if (This->constbuf_uploader)
-u_upload_destroy(This->constbuf_uploader);
-if (This->vertex_sw_uploader)
-u_upload_destroy(This->vertex_sw_uploader);
-if (This->constbuf_sw_uploader)
-u_upload_destroy(This->constbuf_sw_uploader);
-
 nine_bind(>record, NULL);
 
 pipe_sampler_view_reference(>dummy_sampler_view, NULL);
@@ -2852,15 +2818,17 @@ NineDevice9_DrawPrimitiveUP( struct NineDevice9 *This,
 vtxbuf.buffer = NULL;
 vtxbuf.user_buffer = pVertexStreamZeroData;
 
+// csmt is unactive when user vertex or index buffers are used, thus no
+// need to call NineDevice9_GetPipe.
 if (!This->driver_caps.user_vbufs) {
-u_upload_data(This->vertex_uploader,
+u_upload_data(This->context.pipe->stream_uploader,
   0,
   (prim_count_to_vertex_count(PrimitiveType, 
PrimitiveCount)) * VertexStreamZeroStride, /* XXX */
   4,
   vtxbuf.user_buffer,
   _offset,
   );
-u_upload_unmap(This->vertex_uploader);
+u_upload_unmap(This->context.pipe->stream_uploader);
 vtxbuf.user_buffer = NULL;
 }
 
@@ -2916,27 +2884,27 @@ NineDevice9_DrawIndexedPrimitiveUP( struct NineDevice9 
*This,
 
 if (!This->driver_caps.user_vbufs) {
 const unsigned base = MinVertexIndex * VertexStreamZeroStride;
-u_upload_data(This->vertex_uploader,
+u_upload_data(This->context.pipe->stream_uploader,
   base,
   NumVertices * VertexStreamZeroStride, 

Re: [Mesa-dev] Gallium: Removal of set_index_buffer (discussion)

[Roland Scheidegger]

Am 20.02.2017 um 20:56 schrieb Marek Olšák:
> On Mon, Feb 20, 2017 at 8:29 PM, Axel Davy  wrote:
>> On 20/02/2017 20:11, Ilia Mirkin wrote:
>>>
>>> On Mon, Feb 20, 2017 at 2:01 PM, Marek Olšák  wrote:

 Hi,

 I'd like to remove pipe_context::set_index_buffer. It's not useful to
 most drivers and the interface is inconvenient for Mesa/OpenGL,
 because it's a draw state that is set with a separate driver callback,
 which is an unnecessary driver roundtrip taking some CPU cycles. I'd
 prefer to pass the index buffer via pipe_draw_info.

 I'm aware that the interface was inherited from DX10, but I don't
 think that makes any difference here. DX10 state trackers can pass the
 index buffer via pipe_draw_info too.

 This is my proposal:

 iff --git a/src/gallium/include/pipe/p_state.h
 b/src/gallium/include/pipe/p_state.h
 index ce19b92..cffbb33 100644
 --- a/src/gallium/include/pipe/p_state.h
 +++ b/src/gallium/include/pipe/p_state.h
 @@ -635,7 +635,7 @@ struct pipe_index_buffer
*/
   struct pipe_draw_info
   {
 -   boolean indexed;  /**< use index buffer */
 +   ubyte index_size;  /**< 0 = non-indexed */
>>
>> Isn't that enough to say non-index when index_buffer and user_indices are
>> NULL ?
> 
> We still need index_size and it's only 8 bits as opposed to 64 bits.
FWIW at least in d3d10 you can actually have indexed rendering without
an index buffer bound. This is perfectly valid, you're just expected to
return always zero for all indices... Albeit I believe we actually deal
with this with a dummy buffer.

> 

  enum pipe_prim_type mode;  /**< the mode of the primitive */
  boolean primitive_restart;
  ubyte vertices_per_patch; /**< the number of vertices per patch */
 @@ -666,12 +666,18 @@ struct pipe_draw_info

  unsigned indirect_params_offset; /**< must be 4 byte aligned */

 +   /**
 +* Index buffer. Only one can be non-NULL.
 +*/
 +   struct pipe_resource *index_buffer; /* "start" is the offset */
>>>
>>> Works for me. Is start the offset in bytes or is start * index_size
>>> the offset in bytes?
>>
>> Same question here. My understanding is that start is in terms of start *
>> index_size bytes.
> 
> offset = start * index_size;
> 
>> But we really want to have a byte offset.
> 
> The offset should be aligned to index_size, otherwise hardware won't work.
Are you sure of that? d3d10 doesn't seem to have such a requirement, or
if it has I can't find it now (so, the startIndex really is in terms of
index units, but the offset of the buffer is in terms of bytes, and the
docs don't seem to mention it's limited to index alignment).
I don't actually see such a limitation in GL neither, albeit some quick
googling seems to suggest YMMV (e.g.
http://irrlicht.sourceforge.net/forum/viewtopic.php?f=7=51444).
So, I can't quite tell right now if we really need byte offsets...

Otherwise we should be able to deal with the interface change (that
said, arguably the old one is quite consistent with the analogous
set_vertex_buffers call - vulkan also has two analogous entry points for
setting vertex and index buffers, so it can't be all that wrong).
Do you have some evidence this really saves some measurable cpu cycles?

Roland






> 

 +   void *user_indices;
 +
  /* Pointers must be at the end for an optimal structure layout on
 64-bit. */


 Comments welcome,

 Marek
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>>>
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>>> https://urldefense.proofpoint.com/v2/url?u=https-3A__lists.freedesktop.org_mailman_listinfo_mesa-2Ddev=DwIGaQ=uilaK90D4TOVoH58JNXRgQ=_QIjpv-UJ77xEQY8fIYoQtr5qv8wKrPJc7v7_-CYAb0=VuVSYjOwW2vK7aFDJK8g1jjWk4YikjJ6y3TJ5mFdkl0=2zbVOE2ZE3M8z7z3IKYDRHx9SPh81WhmgilHm2qrPZ8=
>>>  
>>
>>
>> My understanding of the current interface is that setting the index buffer
>> may be costly. Thus you want to set once, and use for several draw calls
>> with different start or other changes.
> 
> Not true. It's there only because the interface is based on DX10.
> 
> Marek
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[Mesa-dev] [Bug 98502] Delay when starting firefox, thunderbird or chromium and dmesg spam

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98502

--- Comment #10 from Emil Velikov  ---
Guys, the kernel (v4.10) has been updated to provide the revision field [1], at
the same time libdrm (v2.4.75) has API which does not fetch it [2] and the mesa
patches [3] to us the new API has been updated.

Sadly applying [3] triggers a libtool bug^Wfeature where linking fails on the
Intel CI. Once we get a workaround for that I'll apply [3].


[1]
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=702ed3be1b1bf4dea05954168321741c0910c645
[2]
https://cgit.freedesktop.org/mesa/drm/commit/?id=11687bf4180f7e21045ed9c4730533c40fe01ea5
[3] https://patchwork.freedesktop.org/series/19714/

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Re: [Mesa-dev] [PATCH] gallium: reorder fields in pipe_draw_info

[Marek Olšák]

On Mon, Feb 20, 2017 at 8:36 PM, Roland Scheidegger  wrote:
> Am 20.02.2017 um 20:08 schrieb Marek Olšák:
>> On Mon, Feb 20, 2017 at 8:03 PM, Roland Scheidegger  
>> wrote:
>>> This doesn't quite just do what the commit log says, since at least one
>>> parameter is changed from unsigned to ubyte (I hope vertices_per_patch
>>> can't exceed that for any driver...)
>>
>> vertices_per_patch must be in [1, 32]. Only 5 bits are necessary to
>> represent it.
>
> Well as far as I can tell at a very quick glance this is an
> implementation dependent limit.
> But I don't have any objections making it a ubyte if no implementations
> could handle more than 32 (or even 64, 128,...) anyway (should just
> mention it in the log that it's changed to ubyte).

Yeah, I've already updated the commit message.

Marek
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Re: [Mesa-dev] Gallium: Removal of set_index_buffer (discussion)

[Marek Olšák]

On Mon, Feb 20, 2017 at 8:29 PM, Axel Davy  wrote:
> On 20/02/2017 20:11, Ilia Mirkin wrote:
>>
>> On Mon, Feb 20, 2017 at 2:01 PM, Marek Olšák  wrote:
>>>
>>> Hi,
>>>
>>> I'd like to remove pipe_context::set_index_buffer. It's not useful to
>>> most drivers and the interface is inconvenient for Mesa/OpenGL,
>>> because it's a draw state that is set with a separate driver callback,
>>> which is an unnecessary driver roundtrip taking some CPU cycles. I'd
>>> prefer to pass the index buffer via pipe_draw_info.
>>>
>>> I'm aware that the interface was inherited from DX10, but I don't
>>> think that makes any difference here. DX10 state trackers can pass the
>>> index buffer via pipe_draw_info too.
>>>
>>> This is my proposal:
>>>
>>> iff --git a/src/gallium/include/pipe/p_state.h
>>> b/src/gallium/include/pipe/p_state.h
>>> index ce19b92..cffbb33 100644
>>> --- a/src/gallium/include/pipe/p_state.h
>>> +++ b/src/gallium/include/pipe/p_state.h
>>> @@ -635,7 +635,7 @@ struct pipe_index_buffer
>>>*/
>>>   struct pipe_draw_info
>>>   {
>>> -   boolean indexed;  /**< use index buffer */
>>> +   ubyte index_size;  /**< 0 = non-indexed */
>
> Isn't that enough to say non-index when index_buffer and user_indices are
> NULL ?

We still need index_size and it's only 8 bits as opposed to 64 bits.

>>>
>>>  enum pipe_prim_type mode;  /**< the mode of the primitive */
>>>  boolean primitive_restart;
>>>  ubyte vertices_per_patch; /**< the number of vertices per patch */
>>> @@ -666,12 +666,18 @@ struct pipe_draw_info
>>>
>>>  unsigned indirect_params_offset; /**< must be 4 byte aligned */
>>>
>>> +   /**
>>> +* Index buffer. Only one can be non-NULL.
>>> +*/
>>> +   struct pipe_resource *index_buffer; /* "start" is the offset */
>>
>> Works for me. Is start the offset in bytes or is start * index_size
>> the offset in bytes?
>
> Same question here. My understanding is that start is in terms of start *
> index_size bytes.

offset = start * index_size;

> But we really want to have a byte offset.

The offset should be aligned to index_size, otherwise hardware won't work.

>>>
>>> +   void *user_indices;
>>> +
>>>  /* Pointers must be at the end for an optimal structure layout on
>>> 64-bit. */
>>>
>>>
>>> Comments welcome,
>>>
>>> Marek
>>> ___
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>>
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>
>
> My understanding of the current interface is that setting the index buffer
> may be costly. Thus you want to set once, and use for several draw calls
> with different start or other changes.

Not true. It's there only because the interface is based on DX10.

Marek
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Re: [Mesa-dev] [PATCH v2 0/6] anv: Query cleanups and fixes

[Lionel Landwerlin]

This series is :

Reviewed-by: Lionel Landwerlin 

On 20/02/17 19:25, Jason Ekstrand wrote:

This series is a v2 of some of the patches I sent out on Saturday to fix
queries.  I've incorporated the review feedback from Lionel.  All but the
last two patches are CC'd to stable for both 13.0 and 17.0 as queries are
pretty well busted without them.  This series fixes some rendering errors
in The Talos Principle due to occlusion queries not working correctly.

Jason Ekstrand (6):
   anv: Add an invalidate_range helper
   anv/query: clflush the bo map on non-LLC platforms
   genxml: Make MI_STORE_DATA_IMM more consistent
   anv/query: Perform CmdResetQueryPool on the GPU
   anv/Makefile: alphabetize
   anv: Put everything about queries in genX_query.c

  src/intel/genxml/gen6.xml  |   2 +-
  src/intel/genxml/gen7.xml  |   2 +-
  src/intel/genxml/gen75.xml |   2 +-
  src/intel/vulkan/Makefile.sources  |  13 +-
  src/intel/vulkan/anv_private.h |  13 +
  src/intel/vulkan/anv_query.c   | 190 ---
  src/intel/vulkan/genX_cmd_buffer.c | 276 -
  src/intel/vulkan/genX_query.c  | 480 +
  8 files changed, 504 insertions(+), 474 deletions(-)
  delete mode 100644 src/intel/vulkan/anv_query.c
  create mode 100644 src/intel/vulkan/genX_query.c



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Re: [Mesa-dev] [PATCH] gallium: reorder fields in pipe_draw_info

[Roland Scheidegger]

Am 20.02.2017 um 20:08 schrieb Marek Olšák:
> On Mon, Feb 20, 2017 at 8:03 PM, Roland Scheidegger  
> wrote:
>> This doesn't quite just do what the commit log says, since at least one
>> parameter is changed from unsigned to ubyte (I hope vertices_per_patch
>> can't exceed that for any driver...)
> 
> vertices_per_patch must be in [1, 32]. Only 5 bits are necessary to
> represent it.

Well as far as I can tell at a very quick glance this is an
implementation dependent limit.
But I don't have any objections making it a ubyte if no implementations
could handle more than 32 (or even 64, 128,...) anyway (should just
mention it in the log that it's changed to ubyte).

Roland

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Re: [Mesa-dev] [PATCH mesa 7/8] eglapi: make sure list is always sorted

[Emil Velikov]

On 19 February 2017 at 23:23, Eric Engestrom  wrote:
> Starting with the next commit, badly sorting this list will break the
> eglGetProcAddress().
>
> Signed-off-by: Eric Engestrom 
> ---
>  src/egl/Makefile.am  | 3 ++-
>  src/egl/egl-entrypoint-check | 4 
>  2 files changed, 6 insertions(+), 1 deletion(-)
>  create mode 100755 src/egl/egl-entrypoint-check
>
> diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
> index bd8903f666..6c0548d856 100644
> --- a/src/egl/Makefile.am
> +++ b/src/egl/Makefile.am
> @@ -126,7 +126,8 @@ egl_HEADERS = \
> $(top_srcdir)/include/EGL/eglmesaext.h \
> $(top_srcdir)/include/EGL/eglplatform.h
>
> -TESTS = egl-symbols-check
> +TESTS = egl-symbols-check \
> +   egl-entrypoint-check
>
>  EXTRA_DIST = \
> egl-symbols-check \
Maybe:

- egl-symbols-check \
+$(TESTS) \

> diff --git a/src/egl/egl-entrypoint-check b/src/egl/egl-entrypoint-check
> new file mode 100755
> index 00..d3757aae3c
> --- /dev/null
> +++ b/src/egl/egl-entrypoint-check
> @@ -0,0 +1,4 @@
> +#!/bin/bash
Please add a blank line.

> +entrypoints=$(grep EGL_ENTRYPOINT "$srcdir"/main/eglentrypoint.def)
> +sorted=$(sort <<< "$entrypoints")
> +test "$entrypoints" = "$sorted"
Cannot spot any bashisms here. checkbashisms also cannot find any.
s|bash|sh| in the shebang ?

Thanks to the cleanup Eric !
Emil
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Re: [Mesa-dev] [PATCH] st/nine: make use of common uploaders v2

[Axel Davy]

On 20/02/2017 20:22, Constantine Charlamov wrote:

Make use of common uploaders that landed recently to Mesa

v2: fixed formatting, broken due to thunderbird configuration

---
  src/gallium/state_trackers/nine/device9.c| 48 
  src/gallium/state_trackers/nine/device9.h|  5 ---
  src/gallium/state_trackers/nine/nine_ff.c|  8 ++---
  src/gallium/state_trackers/nine/nine_state.c | 48 ++--
  4 files changed, 35 insertions(+), 74 deletions(-)

diff --git a/src/gallium/state_trackers/nine/device9.c 
b/src/gallium/state_trackers/nine/device9.c
index b9b7a637d7..2ae8678c31 100644
--- a/src/gallium/state_trackers/nine/device9.c
+++ b/src/gallium/state_trackers/nine/device9.c
@@ -477,31 +477,8 @@ NineDevice9_ctor( struct NineDevice9 *This,
  This->driver_caps.user_cbufs = GET_PCAP(USER_CONSTANT_BUFFERS);
  This->driver_caps.user_sw_vbufs = 
This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_VERTEX_BUFFERS);
  This->driver_caps.user_sw_cbufs = 
This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_CONSTANT_BUFFERS);
-
-/* Implicit use of context pipe for vertex and index uploaded when
- * csmt is not active. Does not need to sync since csmt is unactive,
- * thus no need to call NineDevice9_GetPipe at each upload. */
I'd like to have this comment kept somehow (though the use of context 
pipe is not implicit anymore).


I guess it should be in NineDevice9_DrawPrimitiveUP just before if 
(!This->driver_caps.user_vbufs).


It could be: csmt is unactive when user vertex or index buffers are 
used, thus no need to call NineDevice8_GetPipe.


Axel

-if (!This->driver_caps.user_vbufs)
-This->vertex_uploader = u_upload_create(This->csmt_active ?
-This->pipe_secondary : 
This->context.pipe,
-65536,
-PIPE_BIND_VERTEX_BUFFER, 
PIPE_USAGE_STREAM);
-This->vertex_sw_uploader = u_upload_create(This->pipe_sw, 65536,
-PIPE_BIND_VERTEX_BUFFER, 
PIPE_USAGE_STREAM);
-if (!This->driver_caps.user_ibufs)
-This->index_uploader = u_upload_create(This->csmt_active ?
-This->pipe_secondary : 
This->context.pipe,
-   128 * 1024,
-   PIPE_BIND_INDEX_BUFFER, 
PIPE_USAGE_STREAM);
-if (!This->driver_caps.user_cbufs) {
+if (!This->driver_caps.user_cbufs)
  This->constbuf_alignment = GET_PCAP(CONSTANT_BUFFER_OFFSET_ALIGNMENT);
-This->constbuf_uploader = u_upload_create(This->context.pipe, 
This->vs_const_size,
-  PIPE_BIND_CONSTANT_BUFFER, 
PIPE_USAGE_STREAM);
-}
-
-This->constbuf_sw_uploader = u_upload_create(This->pipe_sw, 128 * 1024,
- PIPE_BIND_CONSTANT_BUFFER, 
PIPE_USAGE_STREAM);
-
  This->driver_caps.window_space_position_support = 
GET_PCAP(TGSI_VS_WINDOW_SPACE_POSITION);
  This->driver_caps.vs_integer = pScreen->get_shader_param(pScreen, 
PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS);
  This->driver_caps.ps_integer = pScreen->get_shader_param(pScreen, 
PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_INTEGERS);
@@ -552,17 +529,6 @@ NineDevice9_dtor( struct NineDevice9 *This )
  nine_state_clear(>state, TRUE);
  nine_context_clear(This);
  
-if (This->vertex_uploader)

-u_upload_destroy(This->vertex_uploader);
-if (This->index_uploader)
-u_upload_destroy(This->index_uploader);
-if (This->constbuf_uploader)
-u_upload_destroy(This->constbuf_uploader);
-if (This->vertex_sw_uploader)
-u_upload_destroy(This->vertex_sw_uploader);
-if (This->constbuf_sw_uploader)
-u_upload_destroy(This->constbuf_sw_uploader);
-
  nine_bind(>record, NULL);
  
  pipe_sampler_view_reference(>dummy_sampler_view, NULL);

@@ -2853,14 +2819,14 @@ NineDevice9_DrawPrimitiveUP( struct NineDevice9 *This,
  vtxbuf.user_buffer = pVertexStreamZeroData;
  
  if (!This->driver_caps.user_vbufs) {

-u_upload_data(This->vertex_uploader,
+u_upload_data(This->context.pipe->stream_uploader,
0,
(prim_count_to_vertex_count(PrimitiveType, 
PrimitiveCount)) * VertexStreamZeroStride, /* XXX */
4,
vtxbuf.user_buffer,
_offset,
);
-u_upload_unmap(This->vertex_uploader);
+u_upload_unmap(This->context.pipe->stream_uploader);
  vtxbuf.user_buffer = NULL;
  }
  
@@ -2916,27 +2882,27 @@ NineDevice9_DrawIndexedPrimitiveUP( struct NineDevice9 *This,
  
  if (!This->driver_caps.user_vbufs) {

  const unsigned base = MinVertexIndex * 

Re: [Mesa-dev] [PATCH 3/3] anv: Enable MSAA compression

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin 

On 20/02/17 18:09, Jason Ekstrand wrote:

This just enables basic MSAA compression (no fast clears) for all
multisampled surfaces.  This improves the framerate of the Sascha
"multisampling" demo by 76% on my Sky Lake laptop.  Running Talos on
medium settings with 8x MSAA, this improves the framerate in the
benchmark by 80%.
---
  src/intel/vulkan/TODO  |  2 +-
  src/intel/vulkan/anv_blorp.c   |  3 ++-
  src/intel/vulkan/anv_image.c   |  9 +
  src/intel/vulkan/anv_pipeline.c| 19 +++
  src/intel/vulkan/genX_cmd_buffer.c |  5 +
  5 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/TODO b/src/intel/vulkan/TODO
index f8b73a1..daab39f 100644
--- a/src/intel/vulkan/TODO
+++ b/src/intel/vulkan/TODO
@@ -9,7 +9,7 @@ Missing Features:
  
  Performance:

   - Multi-{sampled/gen8,LOD} HiZ
- - Compressed multisample support
+ - MSAA fast clears
   - Pushing pieces of UBOs?
   - Enable guardband clipping
   - Use soft-pin to avoid relocations
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 4e7078b..902d9af 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1397,7 +1397,8 @@ ccs_resolve_attachment(struct anv_cmd_buffer *cmd_buffer,
 struct anv_attachment_state *att_state =
_buffer->state.attachments[att];
  
-   if (att_state->aux_usage == ISL_AUX_USAGE_NONE)

+   if (att_state->aux_usage == ISL_AUX_USAGE_NONE ||
+   att_state->aux_usage == ISL_AUX_USAGE_MCS)
return; /* Nothing to resolve */
  
 assert(att_state->aux_usage == ISL_AUX_USAGE_CCS_E ||

diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 7eb0f8f..e4be2e5 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -238,6 +238,15 @@ make_surface(const struct anv_device *dev,
  }
   }
}
+   } else if (aspect == VK_IMAGE_ASPECT_COLOR_BIT && vk_info->samples > 1) {
+  assert(image->aux_surface.isl.size == 0);
+  assert(!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT));
+  ok = isl_surf_get_mcs_surf(>isl_dev, _surf->isl,
+ >aux_surface.isl);
+  if (ok) {
+ add_surface(image, >aux_surface);
+ image->aux_usage = ISL_AUX_USAGE_MCS;
+  }
 }
  
 return VK_SUCCESS;

diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 4410103..708b05a 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -228,6 +228,25 @@ static void
  populate_sampler_prog_key(const struct gen_device_info *devinfo,
struct brw_sampler_prog_key_data *key)
  {
+   /* Almost all multisampled textures are compressed.  The only time when we
+* don't compress a multisampled texture is for 16x MSAA with a surface
+* width greater than 8k which is a bit of an edge case.  Since the sampler
+* just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
+* to tell the compiler to always assume compression.
+*/
+   key->compressed_multisample_layout_mask = ~0;
+
+   /* SkyLake added support for 16x MSAA.  With this came a new message for
+* reading from a 16x MSAA surface with compression.  The new message was
+* needed because now the MCS data is 64 bits instead of 32 or lower as is
+* the case for 8x, 4x, and 2x.  The key->msaa_16 bit-field controls which
+* message we use.  Fortunately, the 16x message works for 8x, 4x, and 2x
+* so we can just use it unconditionally.  This may not be quite as
+* efficient but it saves us from recompiling.
+*/
+   if (devinfo->gen >= 9)
+  key->msaa_16 = ~0;
+
 /* XXX: Handle texture swizzle on HSW- */
 for (int i = 0; i < MAX_SAMPLERS; i++) {
/* Assume color sampler, no swizzling. (Works for BDW+) */
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 40a72f4..5d8c3ea 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -222,6 +222,11 @@ color_attachment_compute_aux_usage(struct anv_device 
*device,
att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
att_state->fast_clear = false;
return;
+   } else if (iview->image->aux_usage == ISL_AUX_USAGE_MCS) {
+  att_state->aux_usage = ISL_AUX_USAGE_MCS;
+  att_state->input_aux_usage = ISL_AUX_USAGE_MCS;
+  att_state->fast_clear = false;
+  return;
 }
  
 assert(iview->image->aux_surface.isl.usage & ISL_SURF_USAGE_CCS_BIT);



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Re: [Mesa-dev] [PATCH] docs/releasing.html: reword "distro breaking changes" hunk

[Nayan Deshmukh]

Reviewed-by: Nayan Deshmukh 

On Tue, Feb 21, 2017 at 12:57 AM, Emil Velikov  wrote:
> From: Emil Velikov 
>
> Suggested-by: Eric Engestrom 
> Signed-off-by: Emil Velikov 
> ---
>  docs/releasing.html | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/docs/releasing.html b/docs/releasing.html
> index 048aa1f7a4..26daf505a5 100644
> --- a/docs/releasing.html
> +++ b/docs/releasing.html
> @@ -171,9 +171,9 @@ Now go to
>   href="https://bugs.freedesktop.org/editversions.cgi?action=addproduct=Mesa;
>  target="_parent">Bugzilla and add the new Mesa version X.Y.
>  
>  
> -Check for rare that there are no distribution breaking changes and revert 
> them
> -if needed. Extremely rare - we had only one case so far (see
> -commit 2ced8eb136528914e1bf4e000dea06a9d53c7e04).
> +Check that there are no distribution breaking changes and revert them if 
> needed.
> +For example: files being overwritten on install, etc. Happens extremely rare 
> -
> +we had only one case so far (see commit 
> 2ced8eb136528914e1bf4e000dea06a9d53c7e04).
>  
>  
>  Proceed to release -rc1.
> --
> 2.11.0
>
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Re: [Mesa-dev] [PATCH v2] softpipe: implement clear_texture

[Roland Scheidegger]

Am 20.02.2017 um 18:01 schrieb Lars Hamre:
> v2: rework util clear functions such that they operate on a resource
> instead of a surface (Roland Scheidegger)
> 
> Implements the ARB_clear_texture extension for softpipe.
> Passes all corresponding piglit tests.
> 
> Signed-off-by: Lars Hamre 
> 
> ---
> 
> CC: Roland Scheidegger 
> 
> NOTE: someone with access will need to commit this post
>   review process
> 
>  src/gallium/auxiliary/util/u_surface.c| 339 
> +-
>  src/gallium/auxiliary/util/u_surface.h|  17 ++
>  src/gallium/drivers/softpipe/sp_screen.c  |   3 +-
>  src/gallium/drivers/softpipe/sp_texture.c |  51 +
>  4 files changed, 262 insertions(+), 148 deletions(-)
> 
> diff --git a/src/gallium/auxiliary/util/u_surface.c 
> b/src/gallium/auxiliary/util/u_surface.c
> index a9ed006..1ec168f 100644
> --- a/src/gallium/auxiliary/util/u_surface.c
> +++ b/src/gallium/auxiliary/util/u_surface.c
> @@ -388,7 +388,66 @@ no_src_map:
> ;
>  }
>  
> +static void
> +util_clear_texture_helper(struct pipe_transfer *dst_trans,
> +  ubyte *dst_map,
> +  enum pipe_format format,
> +  const union pipe_color_union *color,
> +  unsigned width, unsigned height, unsigned depth)
> +{
> +   union util_color uc;
> +
> +   assert(dst_trans->stride > 0);
> +
> +   if (util_format_is_pure_integer(format)) {
> +  /*
> +   * We expect int/uint clear values here, though some APIs
> +   * might disagree (but in any case util_pack_color()
> +   * couldn't handle it)...
> +   */
> +  if (util_format_is_pure_sint(format)) {
> + util_format_write_4i(format, color->i, 0, , 0, 0, 0, 1, 1);
> +  } else {
> + assert(util_format_is_pure_uint(format));
> + util_format_write_4ui(format, color->ui, 0, , 0, 0, 0, 1, 1);
> +  }
> +   } else {
> +  util_pack_color(color->f, format, );
> +   }
> +
> +   util_fill_box(dst_map, format,
> + dst_trans->stride, dst_trans->layer_stride,
> + 0, 0, 0, width, height, depth, );
> +}
> +
> +void
> +util_clear_texture(struct pipe_context *pipe,
> +   struct pipe_resource *texture,
> +   const union pipe_color_union *color,
> +   unsigned level,
> +   unsigned dstx, unsigned dsty, unsigned dstz,
> +   unsigned width, unsigned height, unsigned depth)
> +{
> +   struct pipe_transfer *dst_trans;
> +   ubyte *dst_map;
> +   enum pipe_format format = texture->format;
>  
> +   dst_map = pipe_transfer_map_3d(pipe,
> +  texture,
> +  level,
> +  PIPE_TRANSFER_WRITE,
> +  dstx, dsty, dstz,
> +  width, height, depth,
> +  _trans);
> +   if (!dst_map)
> +  return;
> +
> +   if (dst_trans->stride > 0) {
> +  util_clear_texture_helper(dst_trans, dst_map, format, color,
> +width, height, depth);
> +   }
> +   pipe->transfer_unmap(pipe, dst_trans);
> +}
>  
>  #define UBYTE_TO_USHORT(B) ((B) | ((B) << 8))
>  
> @@ -410,8 +469,6 @@ util_clear_render_target(struct pipe_context *pipe,
>  {
> struct pipe_transfer *dst_trans;
> ubyte *dst_map;
> -   union util_color uc;
> -   unsigned max_layer;
>  
> assert(dst->texture);
> if (!dst->texture)
> @@ -426,54 +483,150 @@ util_clear_render_target(struct pipe_context *pipe,
>unsigned pixstride = util_format_get_blocksize(dst->format);
>dx = (dst->u.buf.first_element + dstx) * pixstride;
>w = width * pixstride;
> -  max_layer = 0;
>dst_map = pipe_transfer_map(pipe,
>dst->texture,
>0, 0,
>PIPE_TRANSFER_WRITE,
>dx, 0, w, 1,
>_trans);
> +  if (dst_map) {
> + util_clear_texture_helper(dst_trans, dst_map, dst->format, color,
> +   width, height, 1);
> + pipe->transfer_unmap(pipe, dst_trans);
> +  }
> }
> else {
> -  max_layer = dst->u.tex.last_layer - dst->u.tex.first_layer;
> -  dst_map = pipe_transfer_map_3d(pipe,
> - dst->texture,
> - dst->u.tex.level,
> - PIPE_TRANSFER_WRITE,
> - dstx, dsty, dst->u.tex.first_layer,
> - width, height, max_layer + 1, 
> _trans);
> +  unsigned depth = dst->u.tex.last_layer - dst->u.tex.first_layer + 1;
> +  util_clear_texture(pipe, dst->texture, color, dst->u.tex.level,
> + 

Re: [Mesa-dev] [PATCH mesa 6/8] eglapi: move list out to its own file

[Emil Velikov]

2017-02-19 23:23 GMT+00:00 Eric Engestrom :
> This will allow us to make sure the list is always sorted in the next
> commit.
>
> Signed-off-by: Eric Engestrom 
> ---
>  src/egl/main/eglapi.c  | 78 
> +-
>  src/egl/main/eglentrypoint.def | 77 +
I'd rename that to .h and throw it in src/egl/Makefile.sources' LIBEGL_C_FILES

Thanks
Emil
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Re: [Mesa-dev] [PATCH 2/3] isl: add MCS width constraint 16 samples

[Lionel Landwerlin]

On 20/02/17 19:12, Jason Ekstrand wrote:
On Mon, Feb 20, 2017 at 10:33 AM, Lionel Landwerlin 
> 
wrote:


On 20/02/17 18:09, Jason Ekstrand wrote:

From: Lionel Landwerlin >

v3 (Jason Ekstrand): Add a comment explaining why

Signed-off-by: Lionel Landwerlin
>
Reviewed-by: Jason Ekstrand >
---
  src/intel/isl/isl.c | 10 ++
  1 file changed, 10 insertions(+)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 1a47da5..6979063 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1417,6 +1417,16 @@ isl_surf_get_mcs_surf(const struct
isl_device *dev,
 assert(surf->levels == 1);
 assert(surf->logical_level0_px.depth == 1);
  +   /* The "Auxiliary Surface Pitch" field in
RENDER_SURFACE_STATE is only 9
+* bits which means the maximum pitch of a compression
surface is 512
+* tiles or 64KB (since MCS is always Y-tiled). Since a
16x MCS buffer is
+* 64bpp, this gives us a maximum width of 8192 pixels. 
We can create

+* larger multisampled surfaces, we just can't compress
them.   For 2x, 4x,
+* and 8x, we have enough room for the full 16k supported
by the hardware.
+*/
+   if (surf->samples == 16 && surf->width > 8192)
+  return false;
+


I was about to write something like this :

   struct isl_tile_info tile_info;
   isl_surf_get_tile_info(dev, surf, _info);
   if ((surf->row_pitch / tile_info.phys_extent_B.width) > 512)
  return false;


That would work too and it is a bit more general. However, ISL 
currently doesn't touch the isl_surf if creation fails.  I wouldn't 
mind keeping that.  Also, I like that the end result of the 
restriction is clearly spelled out with the old check.  I can't say 
that I care all that much one way or the other so long as both the 
effect (16x 16k surfaces not working) and the reason (pitch) are 
documented.


Whichever :)

Reviewed-by: Lionel Landwerlin 


 enum isl_format mcs_format;
 switch (surf->samples) {
 case 2:  mcs_format = ISL_FORMAT_MCS_2X; break;






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Re: [Mesa-dev] [PATCH mesa 3/8] eglapi: add entrypoint for eglClientWaitSyncKHR

[Emil Velikov]

On 20 February 2017 at 00:03, Eric Engestrom  wrote:
> On Sunday, 2017-02-19 18:54:51 -0500, Ilia Mirkin wrote:
>> On Sun, Feb 19, 2017 at 6:51 PM, Eric Engestrom  wrote:
>> > On Sunday, 2017-02-19 18:33:16 -0500, Ilia Mirkin wrote:
>> >> Why are patches 1-3 necessary?
>> >
>> > They allow patch #4, which makes use of a macro to simplify the list,
>> > (requires a 1:1 mapping of entrypoint to function) which also allows for
>> > the simple sorting test script in patch #7.
>> > I could do without, but honestly I just thought this looked cleaner.
>>
>> I'd rather have a ENTRYPOINT2 macro that allows different external an
>> internal names than duplicating functions. Perhaps others disagree.
>
> Easy enough to change, I'll do a v2 with that if someone else wants it
> as well :)
>
>>
>> >
>> > Also, I think the debug extension would print the wrong function names
>> > before these patches? Not tested though, maybe it somehow worked.
>>
>> Is that important?
>
> Probably not, which is why I didn't mention it at first.
>
Fwiw I'm in favour of 1-3. The extra 35 LoC is nothing - we already
have the *Common pattern throughout eglapi.c.

-Emil
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[Mesa-dev] [PATCH] docs/releasing.html: reword "distro breaking changes" hunk

[Emil Velikov]

From: Emil Velikov 

Suggested-by: Eric Engestrom 
Signed-off-by: Emil Velikov 
---
 docs/releasing.html | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/docs/releasing.html b/docs/releasing.html
index 048aa1f7a4..26daf505a5 100644
--- a/docs/releasing.html
+++ b/docs/releasing.html
@@ -171,9 +171,9 @@ Now go to
 https://bugs.freedesktop.org/editversions.cgi?action=addproduct=Mesa;
 target="_parent">Bugzilla and add the new Mesa version X.Y.
 
 
-Check for rare that there are no distribution breaking changes and revert them
-if needed. Extremely rare - we had only one case so far (see
-commit 2ced8eb136528914e1bf4e000dea06a9d53c7e04).
+Check that there are no distribution breaking changes and revert them if 
needed.
+For example: files being overwritten on install, etc. Happens extremely rare -
+we had only one case so far (see commit 
2ced8eb136528914e1bf4e000dea06a9d53c7e04).
 
 
 Proceed to release -rc1.
-- 
2.11.0

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Re: [Mesa-dev] Gallium: Removal of set_index_buffer (discussion)

[Axel Davy]

On 20/02/2017 20:11, Ilia Mirkin wrote:

On Mon, Feb 20, 2017 at 2:01 PM, Marek Olšák  wrote:

Hi,

I'd like to remove pipe_context::set_index_buffer. It's not useful to
most drivers and the interface is inconvenient for Mesa/OpenGL,
because it's a draw state that is set with a separate driver callback,
which is an unnecessary driver roundtrip taking some CPU cycles. I'd
prefer to pass the index buffer via pipe_draw_info.

I'm aware that the interface was inherited from DX10, but I don't
think that makes any difference here. DX10 state trackers can pass the
index buffer via pipe_draw_info too.

This is my proposal:

iff --git a/src/gallium/include/pipe/p_state.h
b/src/gallium/include/pipe/p_state.h
index ce19b92..cffbb33 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -635,7 +635,7 @@ struct pipe_index_buffer
   */
  struct pipe_draw_info
  {
-   boolean indexed;  /**< use index buffer */
+   ubyte index_size;  /**< 0 = non-indexed */
Isn't that enough to say non-index when index_buffer and user_indices 
are NULL ?

 enum pipe_prim_type mode;  /**< the mode of the primitive */
 boolean primitive_restart;
 ubyte vertices_per_patch; /**< the number of vertices per patch */
@@ -666,12 +666,18 @@ struct pipe_draw_info

 unsigned indirect_params_offset; /**< must be 4 byte aligned */

+   /**
+* Index buffer. Only one can be non-NULL.
+*/
+   struct pipe_resource *index_buffer; /* "start" is the offset */

Works for me. Is start the offset in bytes or is start * index_size
the offset in bytes?
Same question here. My understanding is that start is in terms of start 
* index_size bytes.

But we really want to have a byte offset.

+   void *user_indices;
+
 /* Pointers must be at the end for an optimal structure layout on 64-bit. 
*/


Comments welcome,

Marek
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My understanding of the current interface is that setting the index 
buffer may be costly. Thus you want to set once, and use for several 
draw calls with different start or other changes.


If setting the index buffer is indeed costly, and independant of the 
draw calls, the proposed change makes it a bit harder for the driver 
(it's as if we are setting the index buffer ever draw call, even if it 
didn't really change). For the state tracker, it doesn't make much 
difference.



Axel


Axel

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[Mesa-dev] [PATCH v2 5/6] anv/Makefile: alphabetize

[Jason Ekstrand]

---
 src/intel/vulkan/Makefile.sources | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/intel/vulkan/Makefile.sources 
b/src/intel/vulkan/Makefile.sources
index bd78805..b99 100644
--- a/src/intel/vulkan/Makefile.sources
+++ b/src/intel/vulkan/Makefile.sources
@@ -63,33 +63,33 @@ VULKAN_GENERATED_FILES := \
 
 
 GEN7_FILES := \
+   gen7_cmd_buffer.c \
genX_cmd_buffer.c \
genX_blorp_exec.c \
genX_gpu_memcpy.c \
genX_pipeline.c \
-   gen7_cmd_buffer.c \
genX_state.c
 
 GEN75_FILES := \
+   gen7_cmd_buffer.c \
genX_cmd_buffer.c \
genX_blorp_exec.c \
genX_gpu_memcpy.c \
genX_pipeline.c \
-   gen7_cmd_buffer.c \
genX_state.c
 
 GEN8_FILES := \
+   gen8_cmd_buffer.c \
genX_cmd_buffer.c \
genX_blorp_exec.c \
genX_gpu_memcpy.c \
genX_pipeline.c \
-   gen8_cmd_buffer.c \
genX_state.c
 
 GEN9_FILES := \
+   gen8_cmd_buffer.c \
genX_cmd_buffer.c \
genX_blorp_exec.c \
genX_gpu_memcpy.c \
genX_pipeline.c \
-   gen8_cmd_buffer.c \
genX_state.c
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 6/6] anv: Put everything about queries in genX_query.c

[Jason Ekstrand]

---
 src/intel/vulkan/Makefile.sources  |   5 +-
 src/intel/vulkan/anv_query.c   | 171 -
 src/intel/vulkan/genX_cmd_buffer.c | 306 ---
 src/intel/vulkan/genX_query.c  | 480 +
 4 files changed, 484 insertions(+), 478 deletions(-)
 delete mode 100644 src/intel/vulkan/anv_query.c
 create mode 100644 src/intel/vulkan/genX_query.c

diff --git a/src/intel/vulkan/Makefile.sources 
b/src/intel/vulkan/Makefile.sources
index b99..21c04cd 100644
--- a/src/intel/vulkan/Makefile.sources
+++ b/src/intel/vulkan/Makefile.sources
@@ -40,7 +40,6 @@ VULKAN_FILES := \
anv_pipeline.c \
anv_pipeline_cache.c \
anv_private.h \
-   anv_query.c \
anv_util.c \
anv_wsi.c \
vk_format_info.h
@@ -68,6 +67,7 @@ GEN7_FILES := \
genX_blorp_exec.c \
genX_gpu_memcpy.c \
genX_pipeline.c \
+   genX_query.c \
genX_state.c
 
 GEN75_FILES := \
@@ -76,6 +76,7 @@ GEN75_FILES := \
genX_blorp_exec.c \
genX_gpu_memcpy.c \
genX_pipeline.c \
+   genX_query.c \
genX_state.c
 
 GEN8_FILES := \
@@ -84,6 +85,7 @@ GEN8_FILES := \
genX_blorp_exec.c \
genX_gpu_memcpy.c \
genX_pipeline.c \
+   genX_query.c \
genX_state.c
 
 GEN9_FILES := \
@@ -92,4 +94,5 @@ GEN9_FILES := \
genX_blorp_exec.c \
genX_gpu_memcpy.c \
genX_pipeline.c \
+   genX_query.c \
genX_state.c
diff --git a/src/intel/vulkan/anv_query.c b/src/intel/vulkan/anv_query.c
deleted file mode 100644
index 6fe94b0..000
--- a/src/intel/vulkan/anv_query.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright © 2015 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "anv_private.h"
-
-VkResult anv_CreateQueryPool(
-VkDevice_device,
-const VkQueryPoolCreateInfo*pCreateInfo,
-const VkAllocationCallbacks*pAllocator,
-VkQueryPool*pQueryPool)
-{
-   ANV_FROM_HANDLE(anv_device, device, _device);
-   struct anv_query_pool *pool;
-   VkResult result;
-   uint32_t slot_size;
-   uint64_t size;
-
-   assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_QUERY_POOL_CREATE_INFO);
-
-   switch (pCreateInfo->queryType) {
-   case VK_QUERY_TYPE_OCCLUSION:
-   case VK_QUERY_TYPE_TIMESTAMP:
-  break;
-   case VK_QUERY_TYPE_PIPELINE_STATISTICS:
-  return VK_ERROR_INCOMPATIBLE_DRIVER;
-   default:
-  assert(!"Invalid query type");
-   }
-
-   slot_size = sizeof(struct anv_query_pool_slot);
-   pool = vk_alloc2(>alloc, pAllocator, sizeof(*pool), 8,
- VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
-   if (pool == NULL)
-  return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
-
-   pool->type = pCreateInfo->queryType;
-   pool->slots = pCreateInfo->queryCount;
-
-   size = pCreateInfo->queryCount * slot_size;
-   result = anv_bo_init_new(>bo, device, size);
-   if (result != VK_SUCCESS)
-  goto fail;
-
-   pool->bo.map = anv_gem_mmap(device, pool->bo.gem_handle, 0, size, 0);
-
-   *pQueryPool = anv_query_pool_to_handle(pool);
-
-   return VK_SUCCESS;
-
- fail:
-   vk_free2(>alloc, pAllocator, pool);
-
-   return result;
-}
-
-void anv_DestroyQueryPool(
-VkDevice_device,
-VkQueryPool _pool,
-const VkAllocationCallbacks*pAllocator)
-{
-   ANV_FROM_HANDLE(anv_device, device, _device);
-   ANV_FROM_HANDLE(anv_query_pool, pool, _pool);
-
-   if (!pool)
-  return;
-
-   anv_gem_munmap(pool->bo.map, pool->bo.size);
-   anv_gem_close(device, pool->bo.gem_handle);
-   vk_free2(>alloc, pAllocator, pool);
-}
-
-VkResult anv_GetQueryPoolResults(
-VkDevice

[Mesa-dev] [PATCH v2 1/6] anv: Add an invalidate_range helper

[Jason Ekstrand]

This is similar to clflush_range except that it puts the mfence on the
other side to ensure caches are flushed prior to reading.

Cc: "13.0 17.0" 
---
 src/intel/vulkan/anv_private.h | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index da1ca29..5344f07 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -452,6 +452,19 @@ anv_clflush_range(void *start, size_t size)
}
 }
 
+static inline void
+anv_invalidate_range(void *start, size_t size)
+{
+   void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
+   void *end = start + size;
+
+   while (p < end) {
+  __builtin_ia32_clflush(p);
+  p += CACHELINE_SIZE;
+   }
+   __builtin_ia32_mfence();
+}
+
 static void inline
 anv_state_clflush(struct anv_state state)
 {
-- 
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[Mesa-dev] [PATCH v2 2/6] anv/query: clflush the bo map on non-LLC platforms

[Jason Ekstrand]

Found by inspection

Cc: "13.0 17.0" 
---
 src/intel/vulkan/anv_query.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/intel/vulkan/anv_query.c b/src/intel/vulkan/anv_query.c
index 293257b..da0deb8 100644
--- a/src/intel/vulkan/anv_query.c
+++ b/src/intel/vulkan/anv_query.c
@@ -129,6 +129,9 @@ VkResult anv_GetQueryPoolResults(
void *data_end = pData + dataSize;
struct anv_query_pool_slot *slot = pool->bo.map;
 
+   if (!device->info.has_llc)
+  anv_invalidate_range(slot, MIN2(queryCount * sizeof(*slot), 
pool->bo.size));
+
for (uint32_t i = 0; i < queryCount; i++) {
   switch (pool->type) {
   case VK_QUERY_TYPE_OCCLUSION: {
-- 
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[Mesa-dev] [PATCH v2 4/6] anv/query: Perform CmdResetQueryPool on the GPU

[Jason Ekstrand]

This fixes a some rendering corruption in The Talos Principle

Cc: "13.0 17.0" 
---
 src/intel/vulkan/anv_query.c   | 22 --
 src/intel/vulkan/genX_cmd_buffer.c | 30 ++
 2 files changed, 30 insertions(+), 22 deletions(-)

diff --git a/src/intel/vulkan/anv_query.c b/src/intel/vulkan/anv_query.c
index da0deb8..6fe94b0 100644
--- a/src/intel/vulkan/anv_query.c
+++ b/src/intel/vulkan/anv_query.c
@@ -169,25 +169,3 @@ VkResult anv_GetQueryPoolResults(
 
return VK_SUCCESS;
 }
-
-void anv_CmdResetQueryPool(
-VkCommandBuffer commandBuffer,
-VkQueryPool queryPool,
-uint32_tfirstQuery,
-uint32_tqueryCount)
-{
-   ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
-
-   for (uint32_t i = 0; i < queryCount; i++) {
-  switch (pool->type) {
-  case VK_QUERY_TYPE_OCCLUSION:
-  case VK_QUERY_TYPE_TIMESTAMP: {
- struct anv_query_pool_slot *slot = pool->bo.map;
- slot[firstQuery + i].available = 0;
- break;
-  }
-  default:
- assert(!"Invalid query type");
-  }
-   }
-}
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 40a72f4..12ff410 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2510,6 +2510,36 @@ emit_query_availability(struct anv_cmd_buffer 
*cmd_buffer,
}
 }
 
+void genX(CmdResetQueryPool)(
+VkCommandBuffer commandBuffer,
+VkQueryPool queryPool,
+uint32_tfirstQuery,
+uint32_tqueryCount)
+{
+   ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
+   ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
+
+   for (uint32_t i = 0; i < queryCount; i++) {
+  switch (pool->type) {
+  case VK_QUERY_TYPE_OCCLUSION:
+  case VK_QUERY_TYPE_TIMESTAMP: {
+ anv_batch_emit(_buffer->batch, GENX(MI_STORE_DATA_IMM), sdm) {
+sdm.Address = (struct anv_address) {
+   .bo = >bo,
+   .offset = (firstQuery + i) * sizeof(struct anv_query_pool_slot) 
+
+ offsetof(struct anv_query_pool_slot, available),
+};
+sdm.DataDWord0 = 0;
+sdm.DataDWord1 = 0;
+ }
+ break;
+  }
+  default:
+ assert(!"Invalid query type");
+  }
+   }
+}
+
 void genX(CmdBeginQuery)(
 VkCommandBuffer commandBuffer,
 VkQueryPool queryPool,
-- 
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[Mesa-dev] [PATCH v2 0/6] anv: Query cleanups and fixes

[Jason Ekstrand]

This series is a v2 of some of the patches I sent out on Saturday to fix
queries.  I've incorporated the review feedback from Lionel.  All but the
last two patches are CC'd to stable for both 13.0 and 17.0 as queries are
pretty well busted without them.  This series fixes some rendering errors
in The Talos Principle due to occlusion queries not working correctly.

Jason Ekstrand (6):
  anv: Add an invalidate_range helper
  anv/query: clflush the bo map on non-LLC platforms
  genxml: Make MI_STORE_DATA_IMM more consistent
  anv/query: Perform CmdResetQueryPool on the GPU
  anv/Makefile: alphabetize
  anv: Put everything about queries in genX_query.c

 src/intel/genxml/gen6.xml  |   2 +-
 src/intel/genxml/gen7.xml  |   2 +-
 src/intel/genxml/gen75.xml |   2 +-
 src/intel/vulkan/Makefile.sources  |  13 +-
 src/intel/vulkan/anv_private.h |  13 +
 src/intel/vulkan/anv_query.c   | 190 ---
 src/intel/vulkan/genX_cmd_buffer.c | 276 -
 src/intel/vulkan/genX_query.c  | 480 +
 8 files changed, 504 insertions(+), 474 deletions(-)
 delete mode 100644 src/intel/vulkan/anv_query.c
 create mode 100644 src/intel/vulkan/genX_query.c

-- 
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[Mesa-dev] [PATCH v2 3/6] genxml: Make MI_STORE_DATA_IMM more consistent

[Jason Ekstrand]

Cc: "13.0 17.0" 
---
 src/intel/genxml/gen6.xml  | 2 +-
 src/intel/genxml/gen7.xml  | 2 +-
 src/intel/genxml/gen75.xml | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 575ba86..6a9b090 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1803,7 +1803,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 57c3013..7368b5b 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2314,7 +2314,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 8260974..ed82236 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2707,7 +2707,7 @@
 
 
 
-
+
 
 
 
-- 
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[Mesa-dev] [PATCH] st/nine: make use of common uploaders v2

[Constantine Charlamov]

Make use of common uploaders that landed recently to Mesa

v2: fixed formatting, broken due to thunderbird configuration

---
 src/gallium/state_trackers/nine/device9.c| 48 
 src/gallium/state_trackers/nine/device9.h|  5 ---
 src/gallium/state_trackers/nine/nine_ff.c|  8 ++---
 src/gallium/state_trackers/nine/nine_state.c | 48 ++--
 4 files changed, 35 insertions(+), 74 deletions(-)

diff --git a/src/gallium/state_trackers/nine/device9.c 
b/src/gallium/state_trackers/nine/device9.c
index b9b7a637d7..2ae8678c31 100644
--- a/src/gallium/state_trackers/nine/device9.c
+++ b/src/gallium/state_trackers/nine/device9.c
@@ -477,31 +477,8 @@ NineDevice9_ctor( struct NineDevice9 *This,
 This->driver_caps.user_cbufs = GET_PCAP(USER_CONSTANT_BUFFERS);
 This->driver_caps.user_sw_vbufs = 
This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_VERTEX_BUFFERS);
 This->driver_caps.user_sw_cbufs = 
This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_CONSTANT_BUFFERS);
-
-/* Implicit use of context pipe for vertex and index uploaded when
- * csmt is not active. Does not need to sync since csmt is unactive,
- * thus no need to call NineDevice9_GetPipe at each upload. */
-if (!This->driver_caps.user_vbufs)
-This->vertex_uploader = u_upload_create(This->csmt_active ?
-This->pipe_secondary : 
This->context.pipe,
-65536,
-PIPE_BIND_VERTEX_BUFFER, 
PIPE_USAGE_STREAM);
-This->vertex_sw_uploader = u_upload_create(This->pipe_sw, 65536,
-PIPE_BIND_VERTEX_BUFFER, 
PIPE_USAGE_STREAM);
-if (!This->driver_caps.user_ibufs)
-This->index_uploader = u_upload_create(This->csmt_active ?
-This->pipe_secondary : 
This->context.pipe,
-   128 * 1024,
-   PIPE_BIND_INDEX_BUFFER, 
PIPE_USAGE_STREAM);
-if (!This->driver_caps.user_cbufs) {
+if (!This->driver_caps.user_cbufs)
 This->constbuf_alignment = GET_PCAP(CONSTANT_BUFFER_OFFSET_ALIGNMENT);
-This->constbuf_uploader = u_upload_create(This->context.pipe, 
This->vs_const_size,
-  PIPE_BIND_CONSTANT_BUFFER, 
PIPE_USAGE_STREAM);
-}
-
-This->constbuf_sw_uploader = u_upload_create(This->pipe_sw, 128 * 1024,
- PIPE_BIND_CONSTANT_BUFFER, 
PIPE_USAGE_STREAM);
-
 This->driver_caps.window_space_position_support = 
GET_PCAP(TGSI_VS_WINDOW_SPACE_POSITION);
 This->driver_caps.vs_integer = pScreen->get_shader_param(pScreen, 
PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS);
 This->driver_caps.ps_integer = pScreen->get_shader_param(pScreen, 
PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_INTEGERS);
@@ -552,17 +529,6 @@ NineDevice9_dtor( struct NineDevice9 *This )
 nine_state_clear(>state, TRUE);
 nine_context_clear(This);
 
-if (This->vertex_uploader)
-u_upload_destroy(This->vertex_uploader);
-if (This->index_uploader)
-u_upload_destroy(This->index_uploader);
-if (This->constbuf_uploader)
-u_upload_destroy(This->constbuf_uploader);
-if (This->vertex_sw_uploader)
-u_upload_destroy(This->vertex_sw_uploader);
-if (This->constbuf_sw_uploader)
-u_upload_destroy(This->constbuf_sw_uploader);
-
 nine_bind(>record, NULL);
 
 pipe_sampler_view_reference(>dummy_sampler_view, NULL);
@@ -2853,14 +2819,14 @@ NineDevice9_DrawPrimitiveUP( struct NineDevice9 *This,
 vtxbuf.user_buffer = pVertexStreamZeroData;
 
 if (!This->driver_caps.user_vbufs) {
-u_upload_data(This->vertex_uploader,
+u_upload_data(This->context.pipe->stream_uploader,
   0,
   (prim_count_to_vertex_count(PrimitiveType, 
PrimitiveCount)) * VertexStreamZeroStride, /* XXX */
   4,
   vtxbuf.user_buffer,
   _offset,
   );
-u_upload_unmap(This->vertex_uploader);
+u_upload_unmap(This->context.pipe->stream_uploader);
 vtxbuf.user_buffer = NULL;
 }
 
@@ -2916,27 +2882,27 @@ NineDevice9_DrawIndexedPrimitiveUP( struct NineDevice9 
*This,
 
 if (!This->driver_caps.user_vbufs) {
 const unsigned base = MinVertexIndex * VertexStreamZeroStride;
-u_upload_data(This->vertex_uploader,
+u_upload_data(This->context.pipe->stream_uploader,
   base,
   NumVertices * VertexStreamZeroStride, /* XXX */
   4,
   (const uint8_t *)vbuf.user_buffer + base,
   _offset,
   );
-u_upload_unmap(This->vertex_uploader);
+

[Mesa-dev] [PATCH 3/5] anv: Remove the unused state_pool_emit macro

[Jason Ekstrand]

---
 src/intel/vulkan/anv_private.h | 14 --
 1 file changed, 14 deletions(-)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 7bdbfab..73a3f29 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -791,20 +791,6 @@ _anv_combine_address(struct anv_batch *batch, void 
*location,
_dst = NULL; \
  }))
 
-#define anv_state_pool_emit(pool, cmd, align, ...) ({   \
-  const uint32_t __size = __anv_cmd_length(cmd) * 4;\
-  struct anv_state __state =\
- anv_state_pool_alloc((pool), __size, align);   \
-  struct cmd __template = { \
- __VA_ARGS__\
-  };\
-  __anv_cmd_pack(cmd)(NULL, __state.map, &__template);  \
-  VG(VALGRIND_CHECK_MEM_IS_DEFINED(__state.map, __anv_cmd_length(cmd) * 
4)); \
-  if (!(pool)->block_pool->device->info.has_llc)\
- anv_state_clflush(__state);\
-  __state;  \
-   })
-
 #define GEN7_MOCS (struct GEN7_MEMORY_OBJECT_CONTROL_STATE) {  \
.GraphicsDataTypeGFDT= 0,   \
.LLCCacheabilityControlLLCCC = 0,   \
-- 
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[Mesa-dev] [PATCH 5/5] anv: Take a device parameter in anv_state_flush

[Jason Ekstrand]

This allows the helper to check for llc instead of having to do it
manually at all the call sites.
---
 src/intel/vulkan/anv_cmd_buffer.c  | 12 
 src/intel/vulkan/anv_device.c  |  6 ++
 src/intel/vulkan/anv_image.c   |  9 +++--
 src/intel/vulkan/anv_private.h | 15 +--
 src/intel/vulkan/gen7_cmd_buffer.c |  6 ++
 src/intel/vulkan/gen8_cmd_buffer.c | 12 
 src/intel/vulkan/genX_cmd_buffer.c | 18 ++
 src/intel/vulkan/genX_pipeline.c   |  3 +--
 8 files changed, 31 insertions(+), 50 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index e82cfd2..d7e50db 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -587,8 +587,7 @@ anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer 
*cmd_buffer,
state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
memcpy(state.map, data, size);
 
-   if (!cmd_buffer->device->info.has_llc)
-  anv_state_flush(state);
+   anv_state_flush(cmd_buffer->device, state);
 
VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, size));
 
@@ -609,8 +608,7 @@ anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer 
*cmd_buffer,
for (uint32_t i = 0; i < dwords; i++)
   p[i] = a[i] | b[i];
 
-   if (!cmd_buffer->device->info.has_llc)
-  anv_state_flush(state);
+   anv_state_flush(cmd_buffer->device, state);
 
VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
 
@@ -646,8 +644,7 @@ anv_cmd_buffer_push_constants(struct anv_cmd_buffer 
*cmd_buffer,
   u32_map[i] = *(uint32_t *)((uint8_t *)data + offset);
}
 
-   if (!cmd_buffer->device->info.has_llc)
-  anv_state_flush(state);
+   anv_state_flush(cmd_buffer->device, state);
 
return state;
 }
@@ -706,8 +703,7 @@ anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer 
*cmd_buffer)
   }
}
 
-   if (!cmd_buffer->device->info.has_llc)
-  anv_state_flush(state);
+   anv_state_flush(cmd_buffer->device, state);
 
return state;
 }
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 258a25f..9628137 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -862,8 +862,7 @@ anv_state_pool_emit_data(struct anv_state_pool *pool, 
size_t size, size_t align,
state = anv_state_pool_alloc(pool, size, align);
memcpy(state.map, p, size);
 
-   if (!pool->block_pool->device->info.has_llc)
-  anv_state_flush(state);
+   anv_state_flush(pool->block_pool->device, state);
 
return state;
 }
@@ -2056,8 +2055,7 @@ anv_fill_buffer_surface_state(struct anv_device *device, 
struct anv_state state,
  .format = format,
  .stride = stride);
 
-   if (!device->info.has_llc)
-  anv_state_flush(state);
+   anv_state_flush(device, state);
 }
 
 void anv_DestroySampler(
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index c0142c8..e2f7ca3 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -574,8 +574,7 @@ anv_CreateImageView(VkDevice _device,
   .aux_usage = surf_usage,
   .mocs = device->default_mocs);
 
-  if (!device->info.has_llc)
- anv_state_flush(iview->sampler_surface_state);
+  anv_state_flush(device, iview->sampler_surface_state);
} else {
   iview->sampler_surface_state.alloc_size = 0;
}
@@ -626,10 +625,8 @@ anv_CreateImageView(VkDevice _device,
 >storage_image_param,
 >isl, >isl);
 
-  if (!device->info.has_llc) {
- anv_state_flush(iview->storage_surface_state);
- anv_state_flush(iview->writeonly_storage_surface_state);
-  }
+  anv_state_flush(device, iview->storage_surface_state);
+  anv_state_flush(device, iview->writeonly_storage_surface_state);
} else {
   iview->storage_surface_state.alloc_size = 0;
   iview->writeonly_storage_surface_state.alloc_size = 0;
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 39b1235..6a00e55 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -465,12 +465,6 @@ anv_invalidate_range(void *start, size_t size)
__builtin_ia32_mfence();
 }
 
-static void inline
-anv_state_flush(struct anv_state state)
-{
-   anv_flush_range(state.map, state.alloc_size);
-}
-
 VkResult anv_block_pool_init(struct anv_block_pool *pool,
  struct anv_device *device, uint32_t block_size);
 void anv_block_pool_finish(struct anv_block_pool *pool);
@@ -635,6 +629,15 @@ struct anv_device {
 pthread_cond_t  queue_submit;
 };
 
+static void inline
+anv_state_flush(struct anv_device *device, struct anv_state state)
+{
+   if (device->info.has_llc)
+  return;
+
+   anv_flush_range(state.map, state.alloc_size);
+}
+
 void anv_device_init_blorp(struct anv_device *device);
 

[Mesa-dev] [PATCH 4/5] anv: Pull all clflushing into a clflush_range helper

[Jason Ekstrand]

All this cache line address calculation stuff is tricky.  Let's not
duplicate it more places than we have to.
---
 src/intel/vulkan/anv_device.c  | 15 ---
 src/intel/vulkan/anv_private.h | 18 +-
 2 files changed, 13 insertions(+), 20 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index c8277cb..258a25f 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1487,18 +1487,11 @@ clflush_mapped_ranges(struct anv_device *device,
 {
for (uint32_t i = 0; i < count; i++) {
   ANV_FROM_HANDLE(anv_device_memory, mem, ranges[i].memory);
-  void *p = mem->map + (ranges[i].offset & ~CACHELINE_MASK);
-  void *end;
+  if (ranges[i].offset >= mem->map_size)
+ continue;
 
-  if (ranges[i].offset + ranges[i].size > mem->map_size)
- end = mem->map + mem->map_size;
-  else
- end = mem->map + ranges[i].offset + ranges[i].size;
-
-  while (p < end) {
- __builtin_ia32_clflush(p);
- p += CACHELINE_SIZE;
-  }
+  anv_clflush_range(mem->map + ranges[i].offset,
+MIN2(ranges[i].size, mem->map_size - 
ranges[i].offset));
}
 }
 
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 73a3f29..39b1235 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -440,12 +440,11 @@ struct anv_state_stream {
 #define CACHELINE_MASK 63
 
 static inline void
-anv_flush_range(void *start, size_t size)
+anv_clflush_range(void *start, size_t size)
 {
void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
void *end = start + size;
 
-   __builtin_ia32_mfence();
while (p < end) {
   __builtin_ia32_clflush(p);
   p += CACHELINE_SIZE;
@@ -453,15 +452,16 @@ anv_flush_range(void *start, size_t size)
 }
 
 static inline void
-anv_invalidate_range(void *start, size_t size)
+anv_flush_range(void *start, size_t size)
 {
-   void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
-   void *end = start + size;
+   __builtin_ia32_mfence();
+   anv_clflush_range(start, size);
+}
 
-   while (p < end) {
-  __builtin_ia32_clflush(p);
-  p += CACHELINE_SIZE;
-   }
+static inline void
+anv_invalidate_range(void *start, size_t size)
+{
+   anv_clflush_range(start, size);
__builtin_ia32_mfence();
 }
 
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 2/5] anv: Rename clflush_range and state_clflush

[Jason Ekstrand]

It's a bit shorter and easier to work with.  Also, we're about to add a
helper called clflush which does the clflush but without any memory
fencing.
---
 src/intel/vulkan/anv_batch_chain.c |  2 +-
 src/intel/vulkan/anv_cmd_buffer.c  |  8 
 src/intel/vulkan/anv_device.c  |  6 +++---
 src/intel/vulkan/anv_image.c   |  6 +++---
 src/intel/vulkan/anv_private.h |  6 +++---
 src/intel/vulkan/gen7_cmd_buffer.c |  4 ++--
 src/intel/vulkan/gen8_cmd_buffer.c |  8 
 src/intel/vulkan/genX_blorp_exec.c |  2 +-
 src/intel/vulkan/genX_cmd_buffer.c | 12 ++--
 src/intel/vulkan/genX_pipeline.c   |  2 +-
 10 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/src/intel/vulkan/anv_batch_chain.c 
b/src/intel/vulkan/anv_batch_chain.c
index f585946..3f6039e 100644
--- a/src/intel/vulkan/anv_batch_chain.c
+++ b/src/intel/vulkan/anv_batch_chain.c
@@ -1063,7 +1063,7 @@ write_reloc(const struct anv_device *device, void *p, 
uint64_t v, bool flush)
}
 
if (flush && !device->info.has_llc)
-  anv_clflush_range(p, reloc_size);
+  anv_flush_range(p, reloc_size);
 }
 
 static void
diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index 8c08f8d..e82cfd2 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -588,7 +588,7 @@ anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer 
*cmd_buffer,
memcpy(state.map, data, size);
 
if (!cmd_buffer->device->info.has_llc)
-  anv_state_clflush(state);
+  anv_state_flush(state);
 
VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, size));
 
@@ -610,7 +610,7 @@ anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer 
*cmd_buffer,
   p[i] = a[i] | b[i];
 
if (!cmd_buffer->device->info.has_llc)
-  anv_state_clflush(state);
+  anv_state_flush(state);
 
VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
 
@@ -647,7 +647,7 @@ anv_cmd_buffer_push_constants(struct anv_cmd_buffer 
*cmd_buffer,
}
 
if (!cmd_buffer->device->info.has_llc)
-  anv_state_clflush(state);
+  anv_state_flush(state);
 
return state;
 }
@@ -707,7 +707,7 @@ anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer 
*cmd_buffer)
}
 
if (!cmd_buffer->device->info.has_llc)
-  anv_state_clflush(state);
+  anv_state_flush(state);
 
return state;
 }
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index cae5fef..c8277cb 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -863,7 +863,7 @@ anv_state_pool_emit_data(struct anv_state_pool *pool, 
size_t size, size_t align,
memcpy(state.map, p, size);
 
if (!pool->block_pool->device->info.has_llc)
-  anv_state_clflush(state);
+  anv_state_flush(state);
 
return state;
 }
@@ -914,7 +914,7 @@ anv_device_submit_simple_batch(struct anv_device *device,
 
memcpy(bo.map, batch->start, size);
if (!device->info.has_llc)
-  anv_clflush_range(bo.map, size);
+  anv_flush_range(bo.map, size);
 
exec_bos[0] = 
exec2_objects[0].handle = bo.gem_handle;
@@ -2064,7 +2064,7 @@ anv_fill_buffer_surface_state(struct anv_device *device, 
struct anv_state state,
  .stride = stride);
 
if (!device->info.has_llc)
-  anv_state_clflush(state);
+  anv_state_flush(state);
 }
 
 void anv_DestroySampler(
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index cf4304a..c0142c8 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -575,7 +575,7 @@ anv_CreateImageView(VkDevice _device,
   .mocs = device->default_mocs);
 
   if (!device->info.has_llc)
- anv_state_clflush(iview->sampler_surface_state);
+ anv_state_flush(iview->sampler_surface_state);
} else {
   iview->sampler_surface_state.alloc_size = 0;
}
@@ -627,8 +627,8 @@ anv_CreateImageView(VkDevice _device,
 >isl, >isl);
 
   if (!device->info.has_llc) {
- anv_state_clflush(iview->storage_surface_state);
- anv_state_clflush(iview->writeonly_storage_surface_state);
+ anv_state_flush(iview->storage_surface_state);
+ anv_state_flush(iview->writeonly_storage_surface_state);
   }
} else {
   iview->storage_surface_state.alloc_size = 0;
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 5344f07..7bdbfab 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -440,7 +440,7 @@ struct anv_state_stream {
 #define CACHELINE_MASK 63
 
 static inline void
-anv_clflush_range(void *start, size_t size)
+anv_flush_range(void *start, size_t size)
 {
void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
void *end = start + size;
@@ -466,9 +466,9 @@ anv_invalidate_range(void *start, size_t size)
 }
 
 static void inline
-anv_state_clflush(struct anv_state state)
+anv_state_flush(struct anv_state state)
 {
-   

[Mesa-dev] [PATCH 0/5] anv: Fix and rework flushing

[Jason Ekstrand]

The first patch in this little series should fix actual bugs on little-core
platforms because it makes BLORP properly clflush it's dynamic state in
Vulkan.  The GL driver is fine because it allocates it all out of the batch
which gets implicitly flushed when it's submitted.

The other patches just clean things up in the Vulkan driver a bit.  Whether
or not they're actually cleanups is a bit subjective, but I think I like it
better.  The last one certainly makes for less typing.

Jason Ekstrand (5):
  intel/blorp: Explicitly flush all allocated state
  anv: Rename clflush_range and state_clflush
  anv: Remove the unused state_pool_emit macro
  anv: Pull all clflushing into a clflush_range helper
  anv: Take a device parameter in anv_state_flush

 src/intel/blorp/blorp_genX_exec.h   | 17 +++-
 src/intel/vulkan/anv_batch_chain.c  |  2 +-
 src/intel/vulkan/anv_cmd_buffer.c   | 12 +++--
 src/intel/vulkan/anv_device.c   | 23 +---
 src/intel/vulkan/anv_image.c|  9 +++
 src/intel/vulkan/anv_private.h  | 41 +++--
 src/intel/vulkan/gen7_cmd_buffer.c  |  6 ++---
 src/intel/vulkan/gen8_cmd_buffer.c  | 12 +++--
 src/intel/vulkan/genX_blorp_exec.c  |  8 ++
 src/intel/vulkan/genX_cmd_buffer.c  | 18 +
 src/intel/vulkan/genX_pipeline.c|  3 +--
 src/mesa/drivers/dri/i965/genX_blorp_exec.c |  8 ++
 12 files changed, 75 insertions(+), 84 deletions(-)

-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 1/5] intel/blorp: Explicitly flush all allocated state

[Jason Ekstrand]

Found by inspection.  However, I expect it fixes real bugs when using
blorp from Vulkan on little-core platforms.

Cc: "13.0 17.0" 
---
 src/intel/blorp/blorp_genX_exec.h   | 17 -
 src/intel/vulkan/genX_blorp_exec.c  |  8 
 src/mesa/drivers/dri/i965/genX_blorp_exec.c |  8 
 3 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index a673ab8..1e6b05c 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -66,6 +66,10 @@ blorp_alloc_binding_table(struct blorp_batch *batch, 
unsigned num_entries,
   unsigned state_size, unsigned state_alignment,
   uint32_t *bt_offset, uint32_t *surface_offsets,
   void **surface_maps);
+
+static void
+blorp_flush_range(struct blorp_batch *batch, void *start, size_t size);
+
 static void
 blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
 struct blorp_address address, uint32_t delta);
@@ -182,6 +186,7 @@ blorp_emit_vertex_data(struct blorp_batch *batch,
void *data = blorp_alloc_vertex_buffer(batch, sizeof(vertices), addr);
memcpy(data, vertices, sizeof(vertices));
*size = sizeof(vertices);
+   blorp_flush_range(batch, data, *size);
 }
 
 static void
@@ -199,7 +204,8 @@ blorp_emit_input_varying_data(struct blorp_batch *batch,
*size = 16 + num_varyings * vec4_size_in_bytes;
 
const uint32_t *const inputs_src = (const uint32_t *)>wm_inputs;
-   uint32_t *inputs = blorp_alloc_vertex_buffer(batch, *size, addr);
+   void *data = blorp_alloc_vertex_buffer(batch, *size, addr);
+   uint32_t *inputs = data;
 
/* Copy in the VS inputs */
assert(sizeof(params->vs_inputs) == 16);
@@ -223,6 +229,8 @@ blorp_emit_input_varying_data(struct blorp_batch *batch,
  inputs += 4;
   }
}
+
+   blorp_flush_range(batch, data, *size);
 }
 
 static void
@@ -906,6 +914,7 @@ blorp_emit_blend_state(struct blorp_batch *batch,
GENX(BLEND_STATE_length) * 4,
64, );
GENX(BLEND_STATE_pack)(NULL, state, );
+   blorp_flush_range(batch, state, GENX(BLEND_STATE_length) * 4);
 
 #if GEN_GEN >= 7
blorp_emit(batch, GENX(3DSTATE_BLEND_STATE_POINTERS), sp) {
@@ -940,6 +949,7 @@ blorp_emit_color_calc_state(struct blorp_batch *batch,
GENX(COLOR_CALC_STATE_length) * 4,
64, );
GENX(COLOR_CALC_STATE_pack)(NULL, state, );
+   blorp_flush_range(batch, state, GENX(COLOR_CALC_STATE_length) * 4);
 
 #if GEN_GEN >= 7
blorp_emit(batch, GENX(3DSTATE_CC_STATE_POINTERS), sp) {
@@ -1016,6 +1026,7 @@ blorp_emit_depth_stencil_state(struct blorp_batch *batch,
GENX(DEPTH_STENCIL_STATE_length) * 
4,
64, );
GENX(DEPTH_STENCIL_STATE_pack)(NULL, state, );
+   blorp_flush_range(batch, state, GENX(DEPTH_STENCIL_STATE_length) * 4);
 #endif
 
 #if GEN_GEN == 7
@@ -1068,6 +1079,8 @@ blorp_emit_surface_state(struct blorp_batch *batch,
   blorp_surface_reloc(batch, state_offset + isl_dev->ss.aux_addr_offset,
   surface->aux_addr, *aux_addr);
}
+
+   blorp_flush_range(batch, state, GENX(RENDER_SURFACE_STATE_length) * 4);
 }
 
 static void
@@ -1181,6 +1194,7 @@ blorp_emit_sampler_state(struct blorp_batch *batch,
GENX(SAMPLER_STATE_length) * 4,
32, );
GENX(SAMPLER_STATE_pack)(NULL, state, );
+   blorp_flush_range(batch, state, GENX(SAMPLER_STATE_length) * 4);
 
 #if GEN_GEN >= 7
blorp_emit(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS), ssp) {
@@ -1333,6 +1347,7 @@ blorp_emit_viewport_state(struct blorp_batch *batch,
  .MinimumDepth = 0.0,
  .MaximumDepth = 1.0,
   });
+   blorp_flush_range(batch, state, GENX(CC_VIEWPORT_length) * 4);
 
 #if GEN_GEN >= 7
blorp_emit(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), vsp) {
diff --git a/src/intel/vulkan/genX_blorp_exec.c 
b/src/intel/vulkan/genX_blorp_exec.c
index 6f0b063..f7969e5 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -119,6 +119,14 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, 
uint32_t size,
 }
 
 static void
+blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
+{
+   struct anv_device *device = batch->blorp->driver_ctx;
+   if (device->info.has_llc)
+  anv_clflush_range(start, size);
+}
+
+static void
 blorp_emit_urb_config(struct blorp_batch *batch, unsigned vs_entry_size)
 {
struct anv_device *device = batch->blorp->driver_ctx;
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c 
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 

Re: [Mesa-dev] [PATCH 2/3] isl: add MCS width constraint 16 samples

[Jason Ekstrand]

On Mon, Feb 20, 2017 at 10:33 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> On 20/02/17 18:09, Jason Ekstrand wrote:
>
>> From: Lionel Landwerlin 
>>
>> v3 (Jason Ekstrand): Add a comment explaining why
>>
>> Signed-off-by: Lionel Landwerlin 
>> Reviewed-by: Jason Ekstrand 
>> ---
>>   src/intel/isl/isl.c | 10 ++
>>   1 file changed, 10 insertions(+)
>>
>> diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
>> index 1a47da5..6979063 100644
>> --- a/src/intel/isl/isl.c
>> +++ b/src/intel/isl/isl.c
>> @@ -1417,6 +1417,16 @@ isl_surf_get_mcs_surf(const struct isl_device *dev,
>>  assert(surf->levels == 1);
>>  assert(surf->logical_level0_px.depth == 1);
>>   +   /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is
>> only 9
>> +* bits which means the maximum pitch of a compression surface is 512
>> +* tiles or 64KB (since MCS is always Y-tiled).  Since a 16x MCS
>> buffer is
>> +* 64bpp, this gives us a maximum width of 8192 pixels.  We can create
>> +* larger multisampled surfaces, we just can't compress them.   For
>> 2x, 4x,
>> +* and 8x, we have enough room for the full 16k supported by the
>> hardware.
>> +*/
>> +   if (surf->samples == 16 && surf->width > 8192)
>> +  return false;
>> +
>>
>
> I was about to write something like this :
>
>struct isl_tile_info tile_info;
>isl_surf_get_tile_info(dev, surf, _info);
>if ((surf->row_pitch / tile_info.phys_extent_B.width) > 512)
>   return false;
>

That would work too and it is a bit more general.  However, ISL currently
doesn't touch the isl_surf if creation fails.  I wouldn't mind keeping
that.  Also, I like that the end result of the restriction is clearly
spelled out with the old check.  I can't say that I care all that much one
way or the other so long as both the effect (16x 16k surfaces not working)
and the reason (pitch) are documented.


>  enum isl_format mcs_format;
>>  switch (surf->samples) {
>>  case 2:  mcs_format = ISL_FORMAT_MCS_2X;  break;
>>
>
>
>
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Re: [Mesa-dev] Gallium: Removal of set_index_buffer (discussion)

[Ilia Mirkin]

On Mon, Feb 20, 2017 at 2:01 PM, Marek Olšák  wrote:
> Hi,
>
> I'd like to remove pipe_context::set_index_buffer. It's not useful to
> most drivers and the interface is inconvenient for Mesa/OpenGL,
> because it's a draw state that is set with a separate driver callback,
> which is an unnecessary driver roundtrip taking some CPU cycles. I'd
> prefer to pass the index buffer via pipe_draw_info.
>
> I'm aware that the interface was inherited from DX10, but I don't
> think that makes any difference here. DX10 state trackers can pass the
> index buffer via pipe_draw_info too.
>
> This is my proposal:
>
> iff --git a/src/gallium/include/pipe/p_state.h
> b/src/gallium/include/pipe/p_state.h
> index ce19b92..cffbb33 100644
> --- a/src/gallium/include/pipe/p_state.h
> +++ b/src/gallium/include/pipe/p_state.h
> @@ -635,7 +635,7 @@ struct pipe_index_buffer
>   */
>  struct pipe_draw_info
>  {
> -   boolean indexed;  /**< use index buffer */
> +   ubyte index_size;  /**< 0 = non-indexed */
> enum pipe_prim_type mode;  /**< the mode of the primitive */
> boolean primitive_restart;
> ubyte vertices_per_patch; /**< the number of vertices per patch */
> @@ -666,12 +666,18 @@ struct pipe_draw_info
>
> unsigned indirect_params_offset; /**< must be 4 byte aligned */
>
> +   /**
> +* Index buffer. Only one can be non-NULL.
> +*/
> +   struct pipe_resource *index_buffer; /* "start" is the offset */

Works for me. Is start the offset in bytes or is start * index_size
the offset in bytes?

> +   void *user_indices;
> +
> /* Pointers must be at the end for an optimal structure layout on 64-bit. 
> */
>
>
> Comments welcome,
>
> Marek
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Re: [Mesa-dev] [PATCH] gallium: reorder fields in pipe_draw_info

[Marek Olšák]

On Mon, Feb 20, 2017 at 8:03 PM, Roland Scheidegger  wrote:
> This doesn't quite just do what the commit log says, since at least one
> parameter is changed from unsigned to ubyte (I hope vertices_per_patch
> can't exceed that for any driver...)

vertices_per_patch must be in [1, 32]. Only 5 bits are necessary to
represent it.

Marek
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[Mesa-dev] [Bug 99849] Dashed lines (drawn via GLAMOR) are not rendered correctly

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99849

--- Comment #4 from Roland Scheidegger  ---
Looks like this isn't using line stippling or anything like that, but just
drawing a line with a texture attached, with a shader which discards pixel
based on the texture value (I think using a A8 texture, I hope that works,
since the fs is using the .w value - I have no idea there how pixmaps get
converted into textures).
discard obviously is something that is known to work usually, as is ordinary
line drawing (it's using GL_LINE_STRIP).
I'm not familiar enough with glamor to easily debug this though...

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Re: [Mesa-dev] [PATCH] gallium: reorder fields in pipe_draw_info

[Roland Scheidegger]

This doesn't quite just do what the commit log says, since at least one
parameter is changed from unsigned to ubyte (I hope vertices_per_patch
can't exceed that for any driver...)

Otherwise seems reasonable.

Roland



Am 20.02.2017 um 19:35 schrieb Marek Olšák:
> From: Marek Olšák 
> 
> sizeof(struct pipe_draw_info) = 104 -> 88
> ---
>  src/gallium/include/pipe/p_state.h | 49 
> --
>  1 file changed, 26 insertions(+), 23 deletions(-)
> 
> diff --git a/src/gallium/include/pipe/p_state.h 
> b/src/gallium/include/pipe/p_state.h
> index cb72310..ce19b92 100644
> --- a/src/gallium/include/pipe/p_state.h
> +++ b/src/gallium/include/pipe/p_state.h
> @@ -629,60 +629,51 @@ struct pipe_index_buffer
> const void *user_buffer;  /**< pointer to a user buffer if buffer == NULL 
> */
>  };
>  
>  
>  /**
>   * Information to describe a draw_vbo call.
>   */
>  struct pipe_draw_info
>  {
> boolean indexed;  /**< use index buffer */
> -
> enum pipe_prim_type mode;  /**< the mode of the primitive */
> +   boolean primitive_restart;
> +   ubyte vertices_per_patch; /**< the number of vertices per patch */
> +
> unsigned start;  /**< the index of the first vertex */
> unsigned count;  /**< number of vertices */
>  
> unsigned start_instance; /**< first instance id */
> unsigned instance_count; /**< number of instances */
>  
> unsigned drawid; /**< id of this draw in a multidraw */
>  
> -   unsigned vertices_per_patch; /**< the number of vertices per patch */
> -
> /**
>  * For indexed drawing, these fields apply after index lookup.
>  */
> int index_bias; /**< a bias to be added to each index */
> unsigned min_index; /**< the min index */
> unsigned max_index; /**< the max index */
>  
> /**
>  * Primitive restart enable/index (only applies to indexed drawing)
>  */
> -   boolean primitive_restart;
> unsigned restart_index;
>  
> -   /**
> -* Stream output target. If not NULL, it's used to provide the 'count'
> -* parameter based on the number vertices captured by the stream output
> -* stage. (or generally, based on the number of bytes captured)
> -*
> -* Only 'mode', 'start_instance', and 'instance_count' are taken into
> -* account, all the other variables from pipe_draw_info are ignored.
> -*
> -* 'start' is implicitly 0 and 'count' is set as discussed above.
> -* The draw command is non-indexed.
> -*
> -* Note that this only provides the count. The vertex buffers must
> -* be set via set_vertex_buffers manually.
> -*/
> -   struct pipe_stream_output_target *count_from_stream_output;
> +   unsigned indirect_offset; /**< must be 4 byte aligned */
> +   unsigned indirect_stride; /**< must be 4 byte aligned */
> +   unsigned indirect_count; /**< number of indirect draws */
> +
> +   unsigned indirect_params_offset; /**< must be 4 byte aligned */
> +
> +   /* Pointers must be at the end for an optimal structure layout on 64-bit. 
> */
>  
> /* Indirect draw parameters resource: If not NULL, most values are taken
>  * from this buffer instead, which is laid out as follows:
>  *
>  * if indexed is TRUE:
>  *  struct {
>  * uint32_t count;
>  * uint32_t instance_count;
>  * uint32_t start;
>  * int32_t index_bias;
> @@ -690,30 +681,42 @@ struct pipe_draw_info
>  *  };
>  * otherwise:
>  *  struct {
>  * uint32_t count;
>  * uint32_t instance_count;
>  * uint32_t start;
>  * uint32_t start_instance;
>  *  };
>  */
> struct pipe_resource *indirect;
> -   unsigned indirect_offset; /**< must be 4 byte aligned */
> -   unsigned indirect_stride; /**< must be 4 byte aligned */
> -   unsigned indirect_count; /**< number of indirect draws */
>  
> /* Indirect draw count resource: If not NULL, contains a 32-bit value 
> which
>  * is to be used as the real indirect_count. In that case indirect_count
>  * becomes the maximum possible value.
>  */
> struct pipe_resource *indirect_params;
> -   unsigned indirect_params_offset; /**< must be 4 byte aligned */
> +
> +   /**
> +* Stream output target. If not NULL, it's used to provide the 'count'
> +* parameter based on the number vertices captured by the stream output
> +* stage. (or generally, based on the number of bytes captured)
> +*
> +* Only 'mode', 'start_instance', and 'instance_count' are taken into
> +* account, all the other variables from pipe_draw_info are ignored.
> +*
> +* 'start' is implicitly 0 and 'count' is set as discussed above.
> +* The draw command is non-indexed.
> +*
> +* Note that this only provides the count. The vertex buffers must
> +* be set via set_vertex_buffers manually.
> +*/
> +   struct pipe_stream_output_target *count_from_stream_output;
>  };
>  
>  
>  /**
>   * Information to describe a blit call.

[Mesa-dev] Gallium: Removal of set_index_buffer (discussion)

[Marek Olšák]

Hi,

I'd like to remove pipe_context::set_index_buffer. It's not useful to
most drivers and the interface is inconvenient for Mesa/OpenGL,
because it's a draw state that is set with a separate driver callback,
which is an unnecessary driver roundtrip taking some CPU cycles. I'd
prefer to pass the index buffer via pipe_draw_info.

I'm aware that the interface was inherited from DX10, but I don't
think that makes any difference here. DX10 state trackers can pass the
index buffer via pipe_draw_info too.

This is my proposal:

iff --git a/src/gallium/include/pipe/p_state.h
b/src/gallium/include/pipe/p_state.h
index ce19b92..cffbb33 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -635,7 +635,7 @@ struct pipe_index_buffer
  */
 struct pipe_draw_info
 {
-   boolean indexed;  /**< use index buffer */
+   ubyte index_size;  /**< 0 = non-indexed */
enum pipe_prim_type mode;  /**< the mode of the primitive */
boolean primitive_restart;
ubyte vertices_per_patch; /**< the number of vertices per patch */
@@ -666,12 +666,18 @@ struct pipe_draw_info

unsigned indirect_params_offset; /**< must be 4 byte aligned */

+   /**
+* Index buffer. Only one can be non-NULL.
+*/
+   struct pipe_resource *index_buffer; /* "start" is the offset */
+   void *user_indices;
+
/* Pointers must be at the end for an optimal structure layout on 64-bit. */


Comments welcome,

Marek
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[Mesa-dev] [PATCH] st/nine: make use of common uploaders

[Constantine Charlamov]

Make use of common uploaders that landed recently to Mesa
---
 src/gallium/state_trackers/nine/device9.c| 48 


 src/gallium/state_trackers/nine/device9.h|  5 ---
 src/gallium/state_trackers/nine/nine_ff.c|  8 ++---
 src/gallium/state_trackers/nine/nine_state.c | 48 
++--

 4 files changed, 35 insertions(+), 74 deletions(-)

diff --git a/src/gallium/state_trackers/nine/device9.c 
b/src/gallium/state_trackers/nine/device9.c

index b9b7a637d7..2ae8678c31 100644
--- a/src/gallium/state_trackers/nine/device9.c
+++ b/src/gallium/state_trackers/nine/device9.c
@@ -477,31 +477,8 @@ NineDevice9_ctor( struct NineDevice9 *This,
 This->driver_caps.user_cbufs = GET_PCAP(USER_CONSTANT_BUFFERS);
 This->driver_caps.user_sw_vbufs = 
This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_VERTEX_BUFFERS);
 This->driver_caps.user_sw_cbufs = 
This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_CONSTANT_BUFFERS);

-
-/* Implicit use of context pipe for vertex and index uploaded when
- * csmt is not active. Does not need to sync since csmt is unactive,
- * thus no need to call NineDevice9_GetPipe at each upload. */
-if (!This->driver_caps.user_vbufs)
-This->vertex_uploader = u_upload_create(This->csmt_active ?
- This->pipe_secondary : This->context.pipe,
-65536,
- PIPE_BIND_VERTEX_BUFFER, PIPE_USAGE_STREAM);
-This->vertex_sw_uploader = u_upload_create(This->pipe_sw, 65536,
- PIPE_BIND_VERTEX_BUFFER, PIPE_USAGE_STREAM);
-if (!This->driver_caps.user_ibufs)
-This->index_uploader = u_upload_create(This->csmt_active ?
- This->pipe_secondary : This->context.pipe,
-   128 * 1024,
- PIPE_BIND_INDEX_BUFFER, PIPE_USAGE_STREAM);
-if (!This->driver_caps.user_cbufs) {
+if (!This->driver_caps.user_cbufs)
 This->constbuf_alignment = 
GET_PCAP(CONSTANT_BUFFER_OFFSET_ALIGNMENT);
-This->constbuf_uploader = u_upload_create(This->context.pipe, 
This->vs_const_size,

- PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
-}
-
-This->constbuf_sw_uploader = u_upload_create(This->pipe_sw, 128 * 1024,
- PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
-
 This->driver_caps.window_space_position_support = 
GET_PCAP(TGSI_VS_WINDOW_SPACE_POSITION);
 This->driver_caps.vs_integer = pScreen->get_shader_param(pScreen, 
PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS);
 This->driver_caps.ps_integer = pScreen->get_shader_param(pScreen, 
PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_INTEGERS);

@@ -552,17 +529,6 @@ NineDevice9_dtor( struct NineDevice9 *This )
 nine_state_clear(>state, TRUE);
 nine_context_clear(This);

-if (This->vertex_uploader)
-u_upload_destroy(This->vertex_uploader);
-if (This->index_uploader)
-u_upload_destroy(This->index_uploader);
-if (This->constbuf_uploader)
-u_upload_destroy(This->constbuf_uploader);
-if (This->vertex_sw_uploader)
-u_upload_destroy(This->vertex_sw_uploader);
-if (This->constbuf_sw_uploader)
-u_upload_destroy(This->constbuf_sw_uploader);
-
 nine_bind(>record, NULL);

 pipe_sampler_view_reference(>dummy_sampler_view, NULL);
@@ -2853,14 +2819,14 @@ NineDevice9_DrawPrimitiveUP( struct NineDevice9 
*This,

 vtxbuf.user_buffer = pVertexStreamZeroData;

 if (!This->driver_caps.user_vbufs) {
-u_upload_data(This->vertex_uploader,
+u_upload_data(This->context.pipe->stream_uploader,
   0,
   (prim_count_to_vertex_count(PrimitiveType, 
PrimitiveCount)) * VertexStreamZeroStride, /* XXX */

   4,
   vtxbuf.user_buffer,
   _offset,
   );
-u_upload_unmap(This->vertex_uploader);
+u_upload_unmap(This->context.pipe->stream_uploader);
 vtxbuf.user_buffer = NULL;
 }

@@ -2916,27 +2882,27 @@ NineDevice9_DrawIndexedPrimitiveUP( struct 
NineDevice9 *This,


 if (!This->driver_caps.user_vbufs) {
 const unsigned base = MinVertexIndex * VertexStreamZeroStride;
-u_upload_data(This->vertex_uploader,
+u_upload_data(This->context.pipe->stream_uploader,
   base,
   NumVertices * VertexStreamZeroStride, /* XXX */
   4,
   (const uint8_t *)vbuf.user_buffer + base,
   _offset,
   );
-u_upload_unmap(This->vertex_uploader);
+u_upload_unmap(This->context.pipe->stream_uploader);
 /* Won't be used: */
 vbuf.buffer_offset -= base;
 vbuf.user_buffer = NULL;
 }
 if (!This->driver_caps.user_ibufs) {
-u_upload_data(This->index_uploader,
+u_upload_data(This->context.pipe->stream_uploader,
   0,
   

Re: [Mesa-dev] [PATCH 4/4] anv: Put everything about queries in genX_query.c

[Jason Ekstrand]

On Mon, Feb 20, 2017 at 10:35 AM, Emil Velikov 
wrote:

> On 18 February 2017 at 23:59, Jason Ekstrand  wrote:
> > ---
> >  src/intel/vulkan/Makefile.sources  |   5 +-
> >  src/intel/vulkan/anv_query.c   | 171 -
> Won't this lead to this [albeit trivial] code built 4 times instead of
> once ? Worth mentioning in the commit message (build time should be
> the same afaict).
>

Yes it would and I did think about that.  I briefly considered just picking
an arbitrary gen and only building the 3 common functions once but I
figured that was probably more hassle than it was worth.


> Regardless, I've verified that nothing sneaked in during the move and
> the makefile changes seem good.
> For 3 and 4:
> Reviewed-by: Emil Velikov 
>
> -Emil
>
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[Mesa-dev] [PATCH] gallium: reorder fields in pipe_draw_info

[Marek Olšák]

From: Marek Olšák 

sizeof(struct pipe_draw_info) = 104 -> 88
---
 src/gallium/include/pipe/p_state.h | 49 --
 1 file changed, 26 insertions(+), 23 deletions(-)

diff --git a/src/gallium/include/pipe/p_state.h 
b/src/gallium/include/pipe/p_state.h
index cb72310..ce19b92 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -629,60 +629,51 @@ struct pipe_index_buffer
const void *user_buffer;  /**< pointer to a user buffer if buffer == NULL */
 };
 
 
 /**
  * Information to describe a draw_vbo call.
  */
 struct pipe_draw_info
 {
boolean indexed;  /**< use index buffer */
-
enum pipe_prim_type mode;  /**< the mode of the primitive */
+   boolean primitive_restart;
+   ubyte vertices_per_patch; /**< the number of vertices per patch */
+
unsigned start;  /**< the index of the first vertex */
unsigned count;  /**< number of vertices */
 
unsigned start_instance; /**< first instance id */
unsigned instance_count; /**< number of instances */
 
unsigned drawid; /**< id of this draw in a multidraw */
 
-   unsigned vertices_per_patch; /**< the number of vertices per patch */
-
/**
 * For indexed drawing, these fields apply after index lookup.
 */
int index_bias; /**< a bias to be added to each index */
unsigned min_index; /**< the min index */
unsigned max_index; /**< the max index */
 
/**
 * Primitive restart enable/index (only applies to indexed drawing)
 */
-   boolean primitive_restart;
unsigned restart_index;
 
-   /**
-* Stream output target. If not NULL, it's used to provide the 'count'
-* parameter based on the number vertices captured by the stream output
-* stage. (or generally, based on the number of bytes captured)
-*
-* Only 'mode', 'start_instance', and 'instance_count' are taken into
-* account, all the other variables from pipe_draw_info are ignored.
-*
-* 'start' is implicitly 0 and 'count' is set as discussed above.
-* The draw command is non-indexed.
-*
-* Note that this only provides the count. The vertex buffers must
-* be set via set_vertex_buffers manually.
-*/
-   struct pipe_stream_output_target *count_from_stream_output;
+   unsigned indirect_offset; /**< must be 4 byte aligned */
+   unsigned indirect_stride; /**< must be 4 byte aligned */
+   unsigned indirect_count; /**< number of indirect draws */
+
+   unsigned indirect_params_offset; /**< must be 4 byte aligned */
+
+   /* Pointers must be at the end for an optimal structure layout on 64-bit. */
 
/* Indirect draw parameters resource: If not NULL, most values are taken
 * from this buffer instead, which is laid out as follows:
 *
 * if indexed is TRUE:
 *  struct {
 * uint32_t count;
 * uint32_t instance_count;
 * uint32_t start;
 * int32_t index_bias;
@@ -690,30 +681,42 @@ struct pipe_draw_info
 *  };
 * otherwise:
 *  struct {
 * uint32_t count;
 * uint32_t instance_count;
 * uint32_t start;
 * uint32_t start_instance;
 *  };
 */
struct pipe_resource *indirect;
-   unsigned indirect_offset; /**< must be 4 byte aligned */
-   unsigned indirect_stride; /**< must be 4 byte aligned */
-   unsigned indirect_count; /**< number of indirect draws */
 
/* Indirect draw count resource: If not NULL, contains a 32-bit value which
 * is to be used as the real indirect_count. In that case indirect_count
 * becomes the maximum possible value.
 */
struct pipe_resource *indirect_params;
-   unsigned indirect_params_offset; /**< must be 4 byte aligned */
+
+   /**
+* Stream output target. If not NULL, it's used to provide the 'count'
+* parameter based on the number vertices captured by the stream output
+* stage. (or generally, based on the number of bytes captured)
+*
+* Only 'mode', 'start_instance', and 'instance_count' are taken into
+* account, all the other variables from pipe_draw_info are ignored.
+*
+* 'start' is implicitly 0 and 'count' is set as discussed above.
+* The draw command is non-indexed.
+*
+* Note that this only provides the count. The vertex buffers must
+* be set via set_vertex_buffers manually.
+*/
+   struct pipe_stream_output_target *count_from_stream_output;
 };
 
 
 /**
  * Information to describe a blit call.
  */
 struct pipe_blit_info
 {
struct {
   struct pipe_resource *resource;
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 4/4] anv: Put everything about queries in genX_query.c

[Emil Velikov]

On 18 February 2017 at 23:59, Jason Ekstrand  wrote:
> ---
>  src/intel/vulkan/Makefile.sources  |   5 +-
>  src/intel/vulkan/anv_query.c   | 171 -
Won't this lead to this [albeit trivial] code built 4 times instead of
once ? Worth mentioning in the commit message (build time should be
the same afaict).

Regardless, I've verified that nothing sneaked in during the move and
the makefile changes seem good.
For 3 and 4:
Reviewed-by: Emil Velikov 

-Emil
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[Mesa-dev] [PATCH] vbo: kill primitive restart lowering in glDrawArrays

[Marek Olšák]

From: Marek Olšák 

---
 src/mesa/vbo/vbo_exec_array.c | 56 ++-
 1 file changed, 7 insertions(+), 49 deletions(-)

diff --git a/src/mesa/vbo/vbo_exec_array.c b/src/mesa/vbo/vbo_exec_array.c
index 6a96167..30c52d5 100644
--- a/src/mesa/vbo/vbo_exec_array.c
+++ b/src/mesa/vbo/vbo_exec_array.c
@@ -404,77 +404,35 @@ vbo_bind_arrays(struct gl_context *ctx)
  */
 static void
 vbo_draw_arrays(struct gl_context *ctx, GLenum mode, GLint start,
 GLsizei count, GLuint numInstances, GLuint baseInstance)
 {
struct vbo_context *vbo = vbo_context(ctx);
struct _mesa_prim prim[2];
 
vbo_bind_arrays(ctx);
 
-   /* init most fields to zero */
+   /* OpenGL 4.5 says that primitive restart is ignored with non-indexed
+* draws.
+*/
memset(prim, 0, sizeof(prim));
prim[0].begin = 1;
prim[0].end = 1;
prim[0].mode = mode;
prim[0].num_instances = numInstances;
prim[0].base_instance = baseInstance;
prim[0].is_indirect = 0;
+   prim[0].start = start;
+   prim[0].count = count;
 
-   /* Implement the primitive restart index */
-   if (ctx->Array.PrimitiveRestart &&
-   !ctx->Array.PrimitiveRestartFixedIndex &&
-   ctx->Array.RestartIndex < count) {
-  GLuint primCount = 0;
-
-  if (ctx->Array.RestartIndex == start) {
- /* special case: RestartIndex at beginning */
- if (count > 1) {
-prim[0].start = start + 1;
-prim[0].count = count - 1;
-primCount = 1;
- }
-  }
-  else if (ctx->Array.RestartIndex == start + count - 1) {
- /* special case: RestartIndex at end */
- if (count > 1) {
-prim[0].start = start;
-prim[0].count = count - 1;
-primCount = 1;
- }
-  }
-  else {
- /* general case: RestartIndex in middle, split into two prims */
- prim[0].start = start;
- prim[0].count = ctx->Array.RestartIndex - start;
-
- prim[1] = prim[0];
- prim[1].start = ctx->Array.RestartIndex + 1;
- prim[1].count = count - prim[1].start;
-
- primCount = 2;
-  }
-
-  if (primCount > 0) {
- /* draw one or two prims */
- vbo->draw_prims(ctx, prim, primCount, NULL,
- GL_TRUE, start, start + count - 1, NULL, 0, NULL);
-  }
-   }
-   else {
-  /* no prim restart */
-  prim[0].start = start;
-  prim[0].count = count;
-
-  vbo->draw_prims(ctx, prim, 1, NULL,
-  GL_TRUE, start, start + count - 1, NULL, 0, NULL);
-   }
+   vbo->draw_prims(ctx, prim, 1, NULL,
+   GL_TRUE, start, start + count - 1, NULL, 0, NULL);
 
if (MESA_DEBUG_FLAGS & DEBUG_ALWAYS_FLUSH) {
   _mesa_flush(ctx);
}
 }
 
 
 /**
  * Execute a glRectf() function.
  */
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 2/3] isl: add MCS width constraint 16 samples

[Lionel Landwerlin]

On 20/02/17 18:09, Jason Ekstrand wrote:

From: Lionel Landwerlin 

v3 (Jason Ekstrand): Add a comment explaining why

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Jason Ekstrand 
---
  src/intel/isl/isl.c | 10 ++
  1 file changed, 10 insertions(+)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 1a47da5..6979063 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1417,6 +1417,16 @@ isl_surf_get_mcs_surf(const struct isl_device *dev,
 assert(surf->levels == 1);
 assert(surf->logical_level0_px.depth == 1);
  
+   /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9

+* bits which means the maximum pitch of a compression surface is 512
+* tiles or 64KB (since MCS is always Y-tiled).  Since a 16x MCS buffer is
+* 64bpp, this gives us a maximum width of 8192 pixels.  We can create
+* larger multisampled surfaces, we just can't compress them.   For 2x, 4x,
+* and 8x, we have enough room for the full 16k supported by the hardware.
+*/
+   if (surf->samples == 16 && surf->width > 8192)
+  return false;
+


I was about to write something like this :

   struct isl_tile_info tile_info;
   isl_surf_get_tile_info(dev, surf, _info);
   if ((surf->row_pitch / tile_info.phys_extent_B.width) > 512)
  return false;



 enum isl_format mcs_format;
 switch (surf->samples) {
 case 2:  mcs_format = ISL_FORMAT_MCS_2X;  break;



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[Mesa-dev] [Bug 99849] Dashed lines (drawn via GLAMOR) are not rendered correctly

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99849

--- Comment #3 from Max Staudt  ---
I've also reproduced this on the most recent openSUSE Tumbleweed snapshot,
which includes Mesa 17.0.0 and Xorg 1.19.1.

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[Mesa-dev] [PATCH 2/3] isl: add MCS width constraint 16 samples

[Jason Ekstrand]

From: Lionel Landwerlin 

v3 (Jason Ekstrand): Add a comment explaining why

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Jason Ekstrand 
---
 src/intel/isl/isl.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 1a47da5..6979063 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1417,6 +1417,16 @@ isl_surf_get_mcs_surf(const struct isl_device *dev,
assert(surf->levels == 1);
assert(surf->logical_level0_px.depth == 1);
 
+   /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
+* bits which means the maximum pitch of a compression surface is 512
+* tiles or 64KB (since MCS is always Y-tiled).  Since a 16x MCS buffer is
+* 64bpp, this gives us a maximum width of 8192 pixels.  We can create
+* larger multisampled surfaces, we just can't compress them.   For 2x, 4x,
+* and 8x, we have enough room for the full 16k supported by the hardware.
+*/
+   if (surf->samples == 16 && surf->width > 8192)
+  return false;
+
enum isl_format mcs_format;
switch (surf->samples) {
case 2:  mcs_format = ISL_FORMAT_MCS_2X;  break;
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 1/3] isl: Return surface creation success from aux helpers

[Jason Ekstrand]

The isl_surf_init call that each of these helpers make can, in theory,
fail.  We should propagate that up to the caller rather than just
silently ignoring it.

Reviewed-by: Topi Pohjolainen 
---
 src/intel/isl/isl.c  | 72 +---
 src/intel/isl/isl.h  |  4 +--
 src/intel/vulkan/anv_image.c |  5 +--
 3 files changed, 40 insertions(+), 41 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 82ab68d..1a47da5 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1323,7 +1323,7 @@ isl_surf_get_tile_info(const struct isl_device *dev,
isl_tiling_get_info(dev, surf->tiling, fmtl->bpb, tile_info);
 }
 
-void
+bool
 isl_surf_get_hiz_surf(const struct isl_device *dev,
   const struct isl_surf *surf,
   struct isl_surf *hiz_surf)
@@ -1391,20 +1391,20 @@ isl_surf_get_hiz_surf(const struct isl_device *dev,
 */
const unsigned samples = ISL_DEV_GEN(dev) >= 9 ? 1 : surf->samples;
 
-   isl_surf_init(dev, hiz_surf,
- .dim = surf->dim,
- .format = ISL_FORMAT_HIZ,
- .width = surf->logical_level0_px.width,
- .height = surf->logical_level0_px.height,
- .depth = surf->logical_level0_px.depth,
- .levels = surf->levels,
- .array_len = surf->logical_level0_px.array_len,
- .samples = samples,
- .usage = ISL_SURF_USAGE_HIZ_BIT,
- .tiling_flags = ISL_TILING_HIZ_BIT);
+   return isl_surf_init(dev, hiz_surf,
+.dim = surf->dim,
+.format = ISL_FORMAT_HIZ,
+.width = surf->logical_level0_px.width,
+.height = surf->logical_level0_px.height,
+.depth = surf->logical_level0_px.depth,
+.levels = surf->levels,
+.array_len = surf->logical_level0_px.array_len,
+.samples = samples,
+.usage = ISL_SURF_USAGE_HIZ_BIT,
+.tiling_flags = ISL_TILING_HIZ_BIT);
 }
 
-void
+bool
 isl_surf_get_mcs_surf(const struct isl_device *dev,
   const struct isl_surf *surf,
   struct isl_surf *mcs_surf)
@@ -1427,17 +1427,17 @@ isl_surf_get_mcs_surf(const struct isl_device *dev,
   unreachable("Invalid sample count");
}
 
-   isl_surf_init(dev, mcs_surf,
- .dim = ISL_SURF_DIM_2D,
- .format = mcs_format,
- .width = surf->logical_level0_px.width,
- .height = surf->logical_level0_px.height,
- .depth = 1,
- .levels = 1,
- .array_len = surf->logical_level0_px.array_len,
- .samples = 1, /* MCS surfaces are really single-sampled */
- .usage = ISL_SURF_USAGE_MCS_BIT,
- .tiling_flags = ISL_TILING_Y0_BIT);
+   return isl_surf_init(dev, mcs_surf,
+.dim = ISL_SURF_DIM_2D,
+.format = mcs_format,
+.width = surf->logical_level0_px.width,
+.height = surf->logical_level0_px.height,
+.depth = 1,
+.levels = 1,
+.array_len = surf->logical_level0_px.array_len,
+.samples = 1, /* MCS surfaces are really 
single-sampled */
+.usage = ISL_SURF_USAGE_MCS_BIT,
+.tiling_flags = ISL_TILING_Y0_BIT);
 }
 
 bool
@@ -1491,19 +1491,17 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
   return false;
}
 
-   isl_surf_init(dev, ccs_surf,
- .dim = surf->dim,
- .format = ccs_format,
- .width = surf->logical_level0_px.width,
- .height = surf->logical_level0_px.height,
- .depth = surf->logical_level0_px.depth,
- .levels = surf->levels,
- .array_len = surf->logical_level0_px.array_len,
- .samples = 1,
- .usage = ISL_SURF_USAGE_CCS_BIT,
- .tiling_flags = ISL_TILING_CCS_BIT);
-
-   return true;
+   return isl_surf_init(dev, ccs_surf,
+.dim = surf->dim,
+.format = ccs_format,
+.width = surf->logical_level0_px.width,
+.height = surf->logical_level0_px.height,
+.depth = surf->logical_level0_px.depth,
+.levels = surf->levels,
+.array_len = surf->logical_level0_px.array_len,
+.samples = 1,
+.usage = ISL_SURF_USAGE_CCS_BIT,
+.tiling_flags = ISL_TILING_CCS_BIT);
 }
 
 void
diff --git a/src/intel/isl/isl.h 

[Mesa-dev] [PATCH 3/3] anv: Enable MSAA compression

[Jason Ekstrand]

This just enables basic MSAA compression (no fast clears) for all
multisampled surfaces.  This improves the framerate of the Sascha
"multisampling" demo by 76% on my Sky Lake laptop.  Running Talos on
medium settings with 8x MSAA, this improves the framerate in the
benchmark by 80%.
---
 src/intel/vulkan/TODO  |  2 +-
 src/intel/vulkan/anv_blorp.c   |  3 ++-
 src/intel/vulkan/anv_image.c   |  9 +
 src/intel/vulkan/anv_pipeline.c| 19 +++
 src/intel/vulkan/genX_cmd_buffer.c |  5 +
 5 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/TODO b/src/intel/vulkan/TODO
index f8b73a1..daab39f 100644
--- a/src/intel/vulkan/TODO
+++ b/src/intel/vulkan/TODO
@@ -9,7 +9,7 @@ Missing Features:
 
 Performance:
  - Multi-{sampled/gen8,LOD} HiZ
- - Compressed multisample support
+ - MSAA fast clears
  - Pushing pieces of UBOs?
  - Enable guardband clipping
  - Use soft-pin to avoid relocations
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 4e7078b..902d9af 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1397,7 +1397,8 @@ ccs_resolve_attachment(struct anv_cmd_buffer *cmd_buffer,
struct anv_attachment_state *att_state =
   _buffer->state.attachments[att];
 
-   if (att_state->aux_usage == ISL_AUX_USAGE_NONE)
+   if (att_state->aux_usage == ISL_AUX_USAGE_NONE ||
+   att_state->aux_usage == ISL_AUX_USAGE_MCS)
   return; /* Nothing to resolve */
 
assert(att_state->aux_usage == ISL_AUX_USAGE_CCS_E ||
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 7eb0f8f..e4be2e5 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -238,6 +238,15 @@ make_surface(const struct anv_device *dev,
 }
  }
   }
+   } else if (aspect == VK_IMAGE_ASPECT_COLOR_BIT && vk_info->samples > 1) {
+  assert(image->aux_surface.isl.size == 0);
+  assert(!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT));
+  ok = isl_surf_get_mcs_surf(>isl_dev, _surf->isl,
+ >aux_surface.isl);
+  if (ok) {
+ add_surface(image, >aux_surface);
+ image->aux_usage = ISL_AUX_USAGE_MCS;
+  }
}
 
return VK_SUCCESS;
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 4410103..708b05a 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -228,6 +228,25 @@ static void
 populate_sampler_prog_key(const struct gen_device_info *devinfo,
   struct brw_sampler_prog_key_data *key)
 {
+   /* Almost all multisampled textures are compressed.  The only time when we
+* don't compress a multisampled texture is for 16x MSAA with a surface
+* width greater than 8k which is a bit of an edge case.  Since the sampler
+* just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
+* to tell the compiler to always assume compression.
+*/
+   key->compressed_multisample_layout_mask = ~0;
+
+   /* SkyLake added support for 16x MSAA.  With this came a new message for
+* reading from a 16x MSAA surface with compression.  The new message was
+* needed because now the MCS data is 64 bits instead of 32 or lower as is
+* the case for 8x, 4x, and 2x.  The key->msaa_16 bit-field controls which
+* message we use.  Fortunately, the 16x message works for 8x, 4x, and 2x
+* so we can just use it unconditionally.  This may not be quite as
+* efficient but it saves us from recompiling.
+*/
+   if (devinfo->gen >= 9)
+  key->msaa_16 = ~0;
+
/* XXX: Handle texture swizzle on HSW- */
for (int i = 0; i < MAX_SAMPLERS; i++) {
   /* Assume color sampler, no swizzling. (Works for BDW+) */
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 40a72f4..5d8c3ea 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -222,6 +222,11 @@ color_attachment_compute_aux_usage(struct anv_device 
*device,
   att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
   att_state->fast_clear = false;
   return;
+   } else if (iview->image->aux_usage == ISL_AUX_USAGE_MCS) {
+  att_state->aux_usage = ISL_AUX_USAGE_MCS;
+  att_state->input_aux_usage = ISL_AUX_USAGE_MCS;
+  att_state->fast_clear = false;
+  return;
}
 
assert(iview->image->aux_surface.isl.usage & ISL_SURF_USAGE_CCS_BIT);
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 1/5] etnaviv: add support for user index buffers

[Marek Olšák]

From: Marek Olšák 

v2: fix a bug in u_helpers
---
 src/gallium/auxiliary/util/u_helpers.c| 29 +++
 src/gallium/auxiliary/util/u_helpers.h|  5 +
 src/gallium/drivers/etnaviv/etnaviv_context.c | 12 +++
 src/gallium/drivers/etnaviv/etnaviv_screen.c  |  2 +-
 4 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/util/u_helpers.c 
b/src/gallium/auxiliary/util/u_helpers.c
index 09020b0..e195576 100644
--- a/src/gallium/auxiliary/util/u_helpers.c
+++ b/src/gallium/auxiliary/util/u_helpers.c
@@ -20,20 +20,21 @@
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  * IN NO EVENT SHALL THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
  **/
 
 #include "util/u_helpers.h"
 #include "util/u_inlines.h"
+#include "util/u_upload_mgr.h"
 
 /**
  * This function is used to copy an array of pipe_vertex_buffer structures,
  * while properly referencing the pipe_vertex_buffer::buffer member.
  *
  * enabled_buffers is updated such that the bits corresponding to the indices
  * of disabled buffers are set to 0 and the enabled ones are set to 1.
  *
  * \sa util_copy_framebuffer_state
  */
@@ -102,10 +103,38 @@ util_set_index_buffer(struct pipe_index_buffer *dst,
 {
if (src) {
   pipe_resource_reference(>buffer, src->buffer);
   memcpy(dst, src, sizeof(*dst));
}
else {
   pipe_resource_reference(>buffer, NULL);
   memset(dst, 0, sizeof(*dst));
}
 }
+
+/**
+ * Given a user index buffer, save the structure to "saved", and upload it.
+ */
+bool
+util_save_and_upload_index_buffer(struct pipe_context *pipe,
+  const struct pipe_draw_info *info,
+  const struct pipe_index_buffer *ib,
+  struct pipe_index_buffer *out_saved)
+{
+   struct pipe_index_buffer new_ib = {0};
+   unsigned start_offset = info->start * ib->index_size;
+
+   u_upload_data(pipe->stream_uploader, start_offset,
+ info->count * ib->index_size, 4,
+ (char*)ib->user_buffer + start_offset,
+ _ib.offset, _ib.buffer);
+   if (!new_ib.buffer)
+  return false;
+   u_upload_unmap(pipe->stream_uploader);
+
+   new_ib.offset -= start_offset;
+   new_ib.index_size = ib->index_size;
+
+   util_set_index_buffer(out_saved, ib);
+   pipe->set_index_buffer(pipe, _ib);
+   return true;
+}
diff --git a/src/gallium/auxiliary/util/u_helpers.h 
b/src/gallium/auxiliary/util/u_helpers.h
index a9a53e4..7de960b 100644
--- a/src/gallium/auxiliary/util/u_helpers.h
+++ b/src/gallium/auxiliary/util/u_helpers.h
@@ -40,15 +40,20 @@ void util_set_vertex_buffers_mask(struct pipe_vertex_buffer 
*dst,
   unsigned start_slot, unsigned count);
 
 void util_set_vertex_buffers_count(struct pipe_vertex_buffer *dst,
unsigned *dst_count,
const struct pipe_vertex_buffer *src,
unsigned start_slot, unsigned count);
 
 void util_set_index_buffer(struct pipe_index_buffer *dst,
const struct pipe_index_buffer *src);
 
+bool util_save_and_upload_index_buffer(struct pipe_context *pipe,
+   const struct pipe_draw_info *info,
+   const struct pipe_index_buffer *ib,
+   struct pipe_index_buffer *out_saved);
+
 #ifdef __cplusplus
 }
 #endif
 
 #endif
diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c 
b/src/gallium/drivers/etnaviv/etnaviv_context.c
index 62297a0..d5bf106 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_context.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_context.c
@@ -40,20 +40,21 @@
 #include "etnaviv_state.h"
 #include "etnaviv_surface.h"
 #include "etnaviv_texture.h"
 #include "etnaviv_transfer.h"
 #include "etnaviv_translate.h"
 #include "etnaviv_zsa.h"
 
 #include "pipe/p_context.h"
 #include "pipe/p_state.h"
 #include "util/u_blitter.h"
+#include "util/u_helpers.h"
 #include "util/u_memory.h"
 #include "util/u_prim.h"
 #include "util/u_upload_mgr.h"
 
 #include "hw/common.xml.h"
 
 static void
 etna_context_destroy(struct pipe_context *pctx)
 {
struct etna_context *ctx = etna_context(pctx);
@@ -130,20 +131,29 @@ etna_draw_vbo(struct pipe_context *pctx, const struct 
pipe_draw_info *info)
   DBG("Invalid draw primitive mode=%i or no primitives to be drawn", 
info->mode);
   return;
}
 
draw_mode = translate_draw_mode(info->mode);
if (draw_mode == ETNA_NO_MATCH) {
   BUG("Unsupported draw mode");
   return;
   

[Mesa-dev] [Bug 99849] Dashed lines (drawn via GLAMOR) are not rendered correctly

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99849

--- Comment #2 from Max Staudt  ---
(In reply to Brian Paul from comment #1)
> Which software renderer?  swrast, softpipe, llvmpipe, swr?  I just did a
> quick test of softpipe and llvmpipe and stippled lines look OK here.
> 
> Which version of Mesa are you using?

I am running stock components included in openSUSE Leap 42.2:
  Xephyr 1.18.3
  Mesa 11.2.2

>From glxinfo when run in Xephyr:
  OpenGL vendor string: VMware, Inc.
  OpenGL renderer string: Gallium 0.4 on llvmpipe (LLVM 3.8, 256 bits)
  OpenGL core profile version string: 3.3 (Core Profile) Mesa 11.2.2
  OpenGL core profile shading language version string: 3.30


To reproduce this, start Xephyr like this:
  Xephyr -glamor :99

Then, run the program like this:
  DISPLAY=:99 ./x11dash

When you omit the -glamor parameter to Xephyr, or run on a system that does not
use GLAMOR (such as with stock xf86-video-intel DDX), X will use its internal
fallback software renderer for 2D drawing commands. It's important to involve
the GLAMOR subsystem to reproduce this bug.

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[Mesa-dev] [PATCH 4/4] gallium/hud: handle a thread switch for API-thread-busy monitoring

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/auxiliary/hud/hud_cpu.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/gallium/auxiliary/hud/hud_cpu.c 
b/src/gallium/auxiliary/hud/hud_cpu.c
index 1cba353..302445d 100644
--- a/src/gallium/auxiliary/hud/hud_cpu.c
+++ b/src/gallium/auxiliary/hud/hud_cpu.c
@@ -237,24 +237,30 @@ struct thread_info {
 
 static void
 query_api_thread_busy_status(struct hud_graph *gr)
 {
struct thread_info *info = gr->query_data;
int64_t now = os_time_get_nano();
 
if (info->last_time) {
   if (info->last_time + gr->pane->period*1000 <= now) {
  int64_t thread_now = pipe_current_thread_get_time_nano();
-
- hud_graph_add_value(gr,
- (thread_now - info->last_thread_time) * 100 /
- (now - info->last_time));
+ unsigned percent = (thread_now - info->last_thread_time) * 100 /
+(now - info->last_time);
+
+ /* Check if the context changed a thread, so that we don't show
+  * a random value. When a thread is changed, the new thread clock
+  * is different, which can result in "percent" being very high.
+  */
+ if (percent > 100)
+percent = 0;
+ hud_graph_add_value(gr, percent);
 
  info->last_thread_time = thread_now;
  info->last_time = now;
   }
} else {
   /* initialize */
   info->last_time = now;
   info->last_thread_time = pipe_current_thread_get_time_nano();
}
 }
-- 
2.7.4

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[Mesa-dev] [PATCH 3/4] gallium/hud: prevent an infinite loop

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/auxiliary/hud/hud_context.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/hud/hud_context.c 
b/src/gallium/auxiliary/hud/hud_context.c
index aaa52d5..488fe66 100644
--- a/src/gallium/auxiliary/hud/hud_context.c
+++ b/src/gallium/auxiliary/hud/hud_context.c
@@ -724,23 +724,23 @@ hud_pane_set_max_value(struct hud_pane *pane, uint64_t 
value)
uint64_t exp10;
int i;
 
/* The following code determines the max_value in the graph as well as
 * how many describing lines are drawn. The max_value is rounded up,
 * so that all drawn numbers are rounded for readability.
 * We want to print multiples of a simple number instead of multiples of
 * hard-to-read numbers like 1.753.
 */
 
-   /* Find the left-most digit. */
+   /* Find the left-most digit. Make sure exp10 * 9 doesn't overflow. */
exp10 = 1;
-   for (i = 0; value > 9 * exp10; i++) {
+   for (i = 0; exp10 <= UINT64_MAX / 9 && exp10 * 9 < value; i++) {
   exp10 *= 10;
   fixup_bytes(pane->type, i + 1, );
}
 
leftmost_digit = DIV_ROUND_UP(value, exp10);
 
/* Round 9 to 10. */
if (leftmost_digit == 9) {
   leftmost_digit = 1;
   exp10 *= 10;
-- 
2.7.4

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[Mesa-dev] [PATCH 2/4] gallium/u_queue: isolate util_queue_fence implementation

[Marek Olšák]

From: Marek Olšák 

it's cleaner this way.
---
 src/gallium/auxiliary/util/u_queue.c| 42 ++---
 src/gallium/auxiliary/util/u_queue.h|  2 +-
 src/gallium/drivers/freedreno/freedreno_batch.c |  2 +-
 src/gallium/drivers/radeonsi/si_state_shaders.c |  6 ++--
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c   |  2 +-
 src/gallium/winsys/radeon/drm/radeon_drm_cs.c   |  2 +-
 6 files changed, 30 insertions(+), 26 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_queue.c 
b/src/gallium/auxiliary/util/u_queue.c
index 89fb235..a223b7c 100644
--- a/src/gallium/auxiliary/util/u_queue.c
+++ b/src/gallium/auxiliary/util/u_queue.c
@@ -93,41 +93,62 @@ remove_from_atexit_list(struct util_queue *queue)
   iter = iter->next;
}
 
/* It must be the first one. */
assert(first_queue == queue);
first_queue = first_queue->next;
pipe_mutex_unlock(exit_mutex);
 }
 
 /
- * util_queue implementation
+ * util_queue_fence
  */
 
 static void
 util_queue_fence_signal(struct util_queue_fence *fence)
 {
pipe_mutex_lock(fence->mutex);
fence->signalled = true;
pipe_condvar_broadcast(fence->cond);
pipe_mutex_unlock(fence->mutex);
 }
 
 void
-util_queue_job_wait(struct util_queue_fence *fence)
+util_queue_fence_wait(struct util_queue_fence *fence)
 {
pipe_mutex_lock(fence->mutex);
while (!fence->signalled)
   pipe_condvar_wait(fence->cond, fence->mutex);
pipe_mutex_unlock(fence->mutex);
 }
 
+void
+util_queue_fence_init(struct util_queue_fence *fence)
+{
+   memset(fence, 0, sizeof(*fence));
+   pipe_mutex_init(fence->mutex);
+   pipe_condvar_init(fence->cond);
+   fence->signalled = true;
+}
+
+void
+util_queue_fence_destroy(struct util_queue_fence *fence)
+{
+   assert(fence->signalled);
+   pipe_condvar_destroy(fence->cond);
+   pipe_mutex_destroy(fence->mutex);
+}
+
+/
+ * util_queue implementation
+ */
+
 struct thread_input {
struct util_queue *queue;
int thread_index;
 };
 
 static PIPE_THREAD_ROUTINE(util_queue_thread_func, input)
 {
struct util_queue *queue = ((struct thread_input*)input)->queue;
int thread_index = ((struct thread_input*)input)->thread_index;
 
@@ -272,37 +293,20 @@ util_queue_destroy(struct util_queue *queue)
util_queue_killall_and_wait(queue);
 
pipe_condvar_destroy(queue->has_space_cond);
pipe_condvar_destroy(queue->has_queued_cond);
pipe_mutex_destroy(queue->lock);
FREE(queue->jobs);
FREE(queue->threads);
 }
 
 void
-util_queue_fence_init(struct util_queue_fence *fence)
-{
-   memset(fence, 0, sizeof(*fence));
-   pipe_mutex_init(fence->mutex);
-   pipe_condvar_init(fence->cond);
-   fence->signalled = true;
-}
-
-void
-util_queue_fence_destroy(struct util_queue_fence *fence)
-{
-   assert(fence->signalled);
-   pipe_condvar_destroy(fence->cond);
-   pipe_mutex_destroy(fence->mutex);
-}
-
-void
 util_queue_add_job(struct util_queue *queue,
void *job,
struct util_queue_fence *fence,
util_queue_execute_func execute,
util_queue_execute_func cleanup)
 {
struct util_queue_job *ptr;
 
assert(fence->signalled);
fence->signalled = false;
diff --git a/src/gallium/auxiliary/util/u_queue.h 
b/src/gallium/auxiliary/util/u_queue.h
index 4ddba33..21ceace 100644
--- a/src/gallium/auxiliary/util/u_queue.h
+++ b/src/gallium/auxiliary/util/u_queue.h
@@ -79,21 +79,21 @@ void util_queue_destroy(struct util_queue *queue);
 void util_queue_fence_init(struct util_queue_fence *fence);
 void util_queue_fence_destroy(struct util_queue_fence *fence);
 
 /* optional cleanup callback is called after fence is signaled: */
 void util_queue_add_job(struct util_queue *queue,
 void *job,
 struct util_queue_fence *fence,
 util_queue_execute_func execute,
 util_queue_execute_func cleanup);
 
-void util_queue_job_wait(struct util_queue_fence *fence);
+void util_queue_fence_wait(struct util_queue_fence *fence);
 int64_t util_queue_get_thread_time_nano(struct util_queue *queue,
 unsigned thread_index);
 
 /* util_queue needs to be cleared to zeroes for this to work */
 static inline bool
 util_queue_is_initialized(struct util_queue *queue)
 {
return queue->threads != NULL;
 }
 
diff --git a/src/gallium/drivers/freedreno/freedreno_batch.c 
b/src/gallium/drivers/freedreno/freedreno_batch.c
index f5a5c6a..c6dcf11 100644
--- a/src/gallium/drivers/freedreno/freedreno_batch.c
+++ b/src/gallium/drivers/freedreno/freedreno_batch.c
@@ -223,21 +223,21 @@ void
 __fd_batch_describe(char* buf, const struct fd_batch *batch)
 {
util_sprintf(buf, "fd_batch<%u>", batch->seqno);
 }
 
 void
 fd_batch_sync(struct fd_batch 

[Mesa-dev] [PATCH 1/4] gallium/u_queue: fix random crashes when the app calls exit()

[Marek Olšák]

From: Marek Olšák 

This fixes:
vdpauinfo: ../lib/CodeGen/TargetPassConfig.cpp:579: virtual void
llvm::TargetPassConfig::addMachinePasses(): Assertion `TPI && IPI &&
"Pass ID not registered!"' failed.

Cc: 13.0 17.0 
---
 src/gallium/auxiliary/util/u_queue.c | 88 +++-
 src/gallium/auxiliary/util/u_queue.h |  3 ++
 2 files changed, 89 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_queue.c 
b/src/gallium/auxiliary/util/u_queue.c
index 4da5d8e..89fb235 100644
--- a/src/gallium/auxiliary/util/u_queue.c
+++ b/src/gallium/auxiliary/util/u_queue.c
@@ -22,20 +22,94 @@
  * The above copyright notice and this permission notice (including the
  * next paragraph) shall be included in all copies or substantial portions
  * of the Software.
  */
 
 #include "u_queue.h"
 #include "u_memory.h"
 #include "u_string.h"
 #include "os/os_time.h"
 
+static void util_queue_killall_and_wait(struct util_queue *queue);
+
+/
+ * Wait for all queues to assert idle when exit() is called.
+ *
+ * Otherwise, C++ static variable destructors can be called while threads
+ * are using the static variables.
+ */
+
+static once_flag atexit_once_flag = ONCE_FLAG_INIT;
+static struct util_queue *first_queue;
+pipe_static_mutex(exit_mutex);
+
+static void
+atexit_handler(void)
+{
+   struct util_queue *queue;
+
+   pipe_mutex_lock(exit_mutex);
+   queue = first_queue;
+   /* Wait for all queues to assert idle. */
+   while (queue) {
+  util_queue_killall_and_wait(queue);
+  queue = queue->next;
+   }
+   pipe_mutex_unlock(exit_mutex);
+}
+
+static void
+call_atexit(void)
+{
+   atexit(atexit_handler);
+}
+
+static void
+add_to_atexit_list(struct util_queue *queue)
+{
+   call_once(_once_flag, call_atexit);
+
+   pipe_mutex_lock(exit_mutex);
+   queue->next = first_queue;
+   first_queue = queue;
+   pipe_mutex_unlock(exit_mutex);
+}
+
+static void
+remove_from_atexit_list(struct util_queue *queue)
+{
+   struct util_queue *iter;
+
+   pipe_mutex_lock(exit_mutex);
+   assert(first_queue);
+   iter = first_queue;
+
+   /* Search the list except the first one. */
+   while (iter->next) {
+  if (iter->next == queue) {
+ iter->next = queue->next;
+ pipe_mutex_unlock(exit_mutex);
+ return;
+  }
+  iter = iter->next;
+   }
+
+   /* It must be the first one. */
+   assert(first_queue == queue);
+   first_queue = first_queue->next;
+   pipe_mutex_unlock(exit_mutex);
+}
+
+/
+ * util_queue implementation
+ */
+
 static void
 util_queue_fence_signal(struct util_queue_fence *fence)
 {
pipe_mutex_lock(fence->mutex);
fence->signalled = true;
pipe_condvar_broadcast(fence->cond);
pipe_mutex_unlock(fence->mutex);
 }
 
 void
@@ -97,20 +171,21 @@ static PIPE_THREAD_ROUTINE(util_queue_thread_func, input)
}
 
/* signal remaining jobs before terminating */
pipe_mutex_lock(queue->lock);
while (queue->jobs[queue->read_idx].job) {
   util_queue_fence_signal(queue->jobs[queue->read_idx].fence);
 
   queue->jobs[queue->read_idx].job = NULL;
   queue->read_idx = (queue->read_idx + 1) % queue->max_jobs;
}
+   queue->num_queued = 0; /* reset this when exiting the thread */
pipe_mutex_unlock(queue->lock);
return 0;
 }
 
 bool
 util_queue_init(struct util_queue *queue,
 const char *name,
 unsigned max_jobs,
 unsigned num_threads)
 {
@@ -150,49 +225,58 @@ util_queue_init(struct util_queue *queue,
  if (i == 0) {
 /* no threads created, fail */
 goto fail;
  } else {
 /* at least one thread created, so use it */
 queue->num_threads = i+1;
 break;
  }
   }
}
+
+   add_to_atexit_list(queue);
return true;
 
 fail:
FREE(queue->threads);
 
if (queue->jobs) {
   pipe_condvar_destroy(queue->has_space_cond);
   pipe_condvar_destroy(queue->has_queued_cond);
   pipe_mutex_destroy(queue->lock);
   FREE(queue->jobs);
}
/* also util_queue_is_initialized can be used to check for success */
memset(queue, 0, sizeof(*queue));
return false;
 }
 
-void
-util_queue_destroy(struct util_queue *queue)
+static void
+util_queue_killall_and_wait(struct util_queue *queue)
 {
unsigned i;
 
/* Signal all threads to terminate. */
pipe_mutex_lock(queue->lock);
queue->kill_threads = 1;
pipe_condvar_broadcast(queue->has_queued_cond);
pipe_mutex_unlock(queue->lock);
 
for (i = 0; i < queue->num_threads; i++)
   pipe_thread_wait(queue->threads[i]);
+}
+
+void
+util_queue_destroy(struct util_queue *queue)
+{
+   remove_from_atexit_list(queue);
+   util_queue_killall_and_wait(queue);
 

Re: [Mesa-dev] [PATCH v2] isl: add MCS width constraint 16 samples

[Jason Ekstrand]

On Mon, Feb 20, 2017 at 8:10 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> Applies on top of Jason's patch :
>
>https://patchwork.freedesktop.org/patch/139603/
>
> Signed-off-by: Lionel Landwerlin 
> Cc: Jason Ekstrand 
> ---
>  src/intel/isl/isl.c | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> index 1a47da5257..b7f3aaee1c 100644
> --- a/src/intel/isl/isl.c
> +++ b/src/intel/isl/isl.c
> @@ -1417,6 +1417,15 @@ isl_surf_get_mcs_surf(const struct isl_device *dev,
> assert(surf->levels == 1);
> assert(surf->logical_level0_px.depth == 1);
>
> +   /* Internal documentation says (not found in PRMs) :
> +*
> +*"If Number of Multisamples is MULTISAMPLECOUNT_16, then Width
> must be
> +* 8K texels or less, or the surface must not use the a multisample
> +* control surface (MCS)."
>

I just remembered there's actually a very simple (and a bit silly) reason
for this restriction.  The "Auxiliary Surface Pitch" field is only 9 bits
which means 512 tiles.  A 16k wide MCS for 16x MSAA is 1024 tiles wide.  We
should probably document that rather than the opaque internal spec citation.


> +*/
> +   if (surf->samples == 16 && surf->width > 8192)
> +  return false;
> +
> enum isl_format mcs_format;
> switch (surf->samples) {
> case 2:  mcs_format = ISL_FORMAT_MCS_2X;  break;
> --
> 2.11.0
>
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Re: [Mesa-dev] [PATCH 00/13] Misc extern C fixes

[Emil Velikov]

On 20 February 2017 at 16:14, Brian Paul  wrote:
> On 02/16/2017 08:16 AM, Emil Velikov wrote:
>>
>> Just a bunch of extern C issues flagged by [1]. There's a few more
>> remaining such as the glsl_types C API living in nir_types.{cpp,h} but
>> that can be resolved at a later date.
>>
>> -Emil
>>
>> [1] git grep -B2 "#.*\" -- src/ | grep  "\"
>>
>
> Series, looks OK to me.  Though, one could imagine some .h files that aren't
> included by .cpp sources now being included by .cpp sources in the future.
> So, I'm not sure patches 1, 2, 13 are needed.
>
I thought about that but I doubt we'll need the extern C there anytime
soon. I'll give it a couple days more for people to shout.

> In any case,
> Reviewed-by: Brian Paul 
>
Thanks !
Emil
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Re: [Mesa-dev] [PATCH] android: glsl: build shader cache sources

[Emil Velikov]

On 20 February 2017 at 09:31, Tapani Pälli  wrote:
> On 02/19/2017 03:06 AM, Timothy Arceri wrote:
>>
>> I would have thought this commit [1] should have fixed it for android as
>> weel as scons.
>>
>> [1]
>>
>> https://cgit.freedesktop.org/mesa/mesa/commit/?id=172c48cc15e2a7b42a7de8ff9164ad8733155667
>
>
> Problem is that we have ENABLE_SHADER_CACHE on because it is linked to
> having SHA1 available, see following commit:
>
> 9f8dc3bf03ec825bae7041858dda6ca2e9a34363
>
> not sure how we should deal with shader cache on Android, it will probably
> require some custom location to write to, otherwise I guess it should work
> similar as on desktop.
>
Until 'the correct' place is established one can use
MESA_GLSL_CACHE_DIR envvar ;-)

-Emil
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Re: [Mesa-dev] [PATCH] android: glsl: build shader cache sources

[Emil Velikov]

On 19 February 2017 at 01:06, Timothy Arceri  wrote:
> I would have thought this commit [1] should have fixed it for android as
> weel as scons.
>
As Tapani mentioned - I've opted to disable the code for scons (since
it doesn't build) and enable it for everyone else... but I've missed
this hunk.
Plan is to a) ensure if builds for everyone and b) runs (I've poked
distros to run make check). Such that you get less bugs as we start
using it.

I might have been too selfish and asked first :-]

Mauro, I've pulled and updated your patches [1]. I believe all we need
for those:
10/12 - seems like a hack, but it's a small one so please add a
comment what/why we need libz (
11/12 - leaning towards dropping it - makes things more obvious for
non Android experts
12/12 - needs the piglit/deqp/other test results summary in the commit message

-Emil

[1] 
https://patchwork.freedesktop.org/project/mesa/patches/?submitter=mauro
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[Mesa-dev] [PATCH v2] softpipe: implement clear_texture

[Lars Hamre]

v2: rework util clear functions such that they operate on a resource
instead of a surface (Roland Scheidegger)

Implements the ARB_clear_texture extension for softpipe.
Passes all corresponding piglit tests.

Signed-off-by: Lars Hamre 

---

CC: Roland Scheidegger 

NOTE: someone with access will need to commit this post
  review process

 src/gallium/auxiliary/util/u_surface.c| 339 +-
 src/gallium/auxiliary/util/u_surface.h|  17 ++
 src/gallium/drivers/softpipe/sp_screen.c  |   3 +-
 src/gallium/drivers/softpipe/sp_texture.c |  51 +
 4 files changed, 262 insertions(+), 148 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_surface.c 
b/src/gallium/auxiliary/util/u_surface.c
index a9ed006..1ec168f 100644
--- a/src/gallium/auxiliary/util/u_surface.c
+++ b/src/gallium/auxiliary/util/u_surface.c
@@ -388,7 +388,66 @@ no_src_map:
;
 }
 
+static void
+util_clear_texture_helper(struct pipe_transfer *dst_trans,
+  ubyte *dst_map,
+  enum pipe_format format,
+  const union pipe_color_union *color,
+  unsigned width, unsigned height, unsigned depth)
+{
+   union util_color uc;
+
+   assert(dst_trans->stride > 0);
+
+   if (util_format_is_pure_integer(format)) {
+  /*
+   * We expect int/uint clear values here, though some APIs
+   * might disagree (but in any case util_pack_color()
+   * couldn't handle it)...
+   */
+  if (util_format_is_pure_sint(format)) {
+ util_format_write_4i(format, color->i, 0, , 0, 0, 0, 1, 1);
+  } else {
+ assert(util_format_is_pure_uint(format));
+ util_format_write_4ui(format, color->ui, 0, , 0, 0, 0, 1, 1);
+  }
+   } else {
+  util_pack_color(color->f, format, );
+   }
+
+   util_fill_box(dst_map, format,
+ dst_trans->stride, dst_trans->layer_stride,
+ 0, 0, 0, width, height, depth, );
+}
+
+void
+util_clear_texture(struct pipe_context *pipe,
+   struct pipe_resource *texture,
+   const union pipe_color_union *color,
+   unsigned level,
+   unsigned dstx, unsigned dsty, unsigned dstz,
+   unsigned width, unsigned height, unsigned depth)
+{
+   struct pipe_transfer *dst_trans;
+   ubyte *dst_map;
+   enum pipe_format format = texture->format;
 
+   dst_map = pipe_transfer_map_3d(pipe,
+  texture,
+  level,
+  PIPE_TRANSFER_WRITE,
+  dstx, dsty, dstz,
+  width, height, depth,
+  _trans);
+   if (!dst_map)
+  return;
+
+   if (dst_trans->stride > 0) {
+  util_clear_texture_helper(dst_trans, dst_map, format, color,
+width, height, depth);
+   }
+   pipe->transfer_unmap(pipe, dst_trans);
+}
 
 #define UBYTE_TO_USHORT(B) ((B) | ((B) << 8))
 
@@ -410,8 +469,6 @@ util_clear_render_target(struct pipe_context *pipe,
 {
struct pipe_transfer *dst_trans;
ubyte *dst_map;
-   union util_color uc;
-   unsigned max_layer;
 
assert(dst->texture);
if (!dst->texture)
@@ -426,54 +483,150 @@ util_clear_render_target(struct pipe_context *pipe,
   unsigned pixstride = util_format_get_blocksize(dst->format);
   dx = (dst->u.buf.first_element + dstx) * pixstride;
   w = width * pixstride;
-  max_layer = 0;
   dst_map = pipe_transfer_map(pipe,
   dst->texture,
   0, 0,
   PIPE_TRANSFER_WRITE,
   dx, 0, w, 1,
   _trans);
+  if (dst_map) {
+ util_clear_texture_helper(dst_trans, dst_map, dst->format, color,
+   width, height, 1);
+ pipe->transfer_unmap(pipe, dst_trans);
+  }
}
else {
-  max_layer = dst->u.tex.last_layer - dst->u.tex.first_layer;
-  dst_map = pipe_transfer_map_3d(pipe,
- dst->texture,
- dst->u.tex.level,
- PIPE_TRANSFER_WRITE,
- dstx, dsty, dst->u.tex.first_layer,
- width, height, max_layer + 1, _trans);
+  unsigned depth = dst->u.tex.last_layer - dst->u.tex.first_layer + 1;
+  util_clear_texture(pipe, dst->texture, color, dst->u.tex.level,
+ dstx, dsty, dst->u.tex.first_layer,
+ width, height, depth);
}
+}
 
+void
+util_clear_depth_stencil_texture(struct pipe_context *pipe,
+ struct pipe_resource *texture,
+ enum pipe_format format,
+ 

[Mesa-dev] [Bug 99875] [radv] gears demo triggers an assertion error on window resize

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99875

Bug ID: 99875
   Summary: [radv] gears demo triggers an assertion error on
window resize
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Vulkan/radeon
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: 0xe2.0x9a.0...@gmail.com
QA Contact: mesa-dev@lists.freedesktop.org

Created attachment 129759
  --> https://bugs.freedesktop.org/attachment.cgi?id=129759=edit
gdb backtrace

Steps to reproduce the issue:

1. Clone and compile https://github.com/SaschaWillems/Vulkan
2. cd bin
3. ./gears
4. Maximize the window

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[Mesa-dev] [Bug 99681] [vulkan/radeon] dota2 -vulkan assertion failure with LLVM 4.0.0-rc1

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99681

Jan Ziak <0xe2.0x9a.0...@gmail.com> changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

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[Mesa-dev] [Bug 98588] [vulkan/radeon] vulkancube & vulkansmoketest rendering issue on R9-390

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98588

Jan Ziak <0xe2.0x9a.0...@gmail.com> changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #4 from Jan Ziak <0xe2.0x9a.0...@gmail.com> ---
I don't have the two Vulkan demos installed to test it, but based on the fact
that other Vulkan demos are rendering correctly this issue is most likely fixed
now.

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Re: [Mesa-dev] [PATCH 4/4] r600/radeonsi: enable glsl/tgsi on-disk cache

[Marek Olšák]

You could do all of this in r600_pipe_common.c by using HAVE_LLVM and
rscreen->chip_class.

Marek

On Mon, Feb 20, 2017 at 1:15 AM, Timothy Arceri  wrote:
> ---
>  src/gallium/drivers/r600/r600_pipe.c  | 19 +++
>  src/gallium/drivers/radeon/r600_pipe_common.c |  8 +++-
>  src/gallium/drivers/radeon/r600_pipe_common.h |  5 +
>  src/gallium/drivers/radeonsi/si_pipe.c| 19 +++
>  src/mesa/state_tracker/st_context.c   |  2 ++
>  5 files changed, 52 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/r600/r600_pipe.c 
> b/src/gallium/drivers/r600/r600_pipe.c
> index 1803c26..162ebe8 100644
> --- a/src/gallium/drivers/r600/r600_pipe.c
> +++ b/src/gallium/drivers/r600/r600_pipe.c
> @@ -601,6 +601,7 @@ static void r600_destroy_screen(struct pipe_screen* 
> pscreen)
> compute_memory_pool_delete(rscreen->global_pool);
> }
>
> +   disk_cache_destroy(rscreen->b.disk_shader_cache);
> r600_destroy_common_screen(>b);
>  }
>
> @@ -614,6 +615,21 @@ static struct pipe_resource *r600_resource_create(struct 
> pipe_screen *screen,
> return r600_resource_create_common(screen, templ);
>  }
>
> +static void r600_disk_cache_create(struct r600_screen *rscreen)
> +{
> +   uint32_t mesa_timestamp;
> +   if (disk_cache_get_function_timestamp(r600_disk_cache_create,
> + _timestamp)) {
> +   char *timestamp_str;
> +   if (asprintf(_str, "%u", mesa_timestamp) != -1) {
> +   rscreen->b.disk_shader_cache =
> +   
> disk_cache_create(r600_get_chip_name(>b),
> + timestamp_str);
> +   free(timestamp_str);
> +   }
> +   }
> +}
> +
>  struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
>  {
> struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
> @@ -625,6 +641,7 @@ struct pipe_screen *r600_screen_create(struct 
> radeon_winsys *ws)
> /* Set functions first. */
> rscreen->b.b.context_create = r600_create_context;
> rscreen->b.b.destroy = r600_destroy_screen;
> +   rscreen->b.b.get_disk_shader_cache = r600_get_disk_shader_cache;
> rscreen->b.b.get_param = r600_get_param;
> rscreen->b.b.get_shader_param = r600_get_shader_param;
> rscreen->b.b.resource_create = r600_resource_create;
> @@ -634,6 +651,8 @@ struct pipe_screen *r600_screen_create(struct 
> radeon_winsys *ws)
> return NULL;
> }
>
> +   r600_disk_cache_create(rscreen);
> +
> if (rscreen->b.info.chip_class >= EVERGREEN) {
> rscreen->b.b.is_format_supported = 
> evergreen_is_format_supported;
> } else {
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
> b/src/gallium/drivers/radeon/r600_pipe_common.c
> index 1781584..a0ebcdd 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.c
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.c
> @@ -729,7 +729,7 @@ static const char* r600_get_device_vendor(struct 
> pipe_screen* pscreen)
> return "AMD";
>  }
>
> -static const char* r600_get_chip_name(struct r600_common_screen *rscreen)
> +const char* r600_get_chip_name(struct r600_common_screen *rscreen)
>  {
> switch (rscreen->info.family) {
> case CHIP_R600: return "AMD R600";
> @@ -779,6 +779,12 @@ static const char* r600_get_chip_name(struct 
> r600_common_screen *rscreen)
> }
>  }
>
> +struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
> +{
> +   struct r600_common_screen *rscreen = (struct 
> r600_common_screen*)pscreen;
> +   return rscreen->disk_shader_cache;
> +}
> +
>  static const char* r600_get_name(struct pipe_screen* pscreen)
>  {
> struct r600_common_screen *rscreen = (struct 
> r600_common_screen*)pscreen;
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
> b/src/gallium/drivers/radeon/r600_pipe_common.h
> index e8dbf5d..120bceb 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -36,6 +36,7 @@
>
>  #include "radeon/radeon_winsys.h"
>
> +#include "util/disk_cache.h"
>  #include "util/u_blitter.h"
>  #include "util/list.h"
>  #include "util/u_range.h"
> @@ -404,6 +405,8 @@ struct r600_common_screen {
> boolhas_cp_dma;
> boolhas_streamout;
>
> +   struct disk_cache   *disk_shader_cache;
> +
> struct slab_parent_pool pool_transfers;
>
> /* Texture filter settings. */
> @@ -768,6 +771,8 @@ void radeon_save_cs(struct radeon_winsys *ws, struct 
> radeon_winsys_cs *cs,
> struct radeon_saved_cs *saved);
>  void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
>  bool r600_check_device_reset(struct 

Re: [Mesa-dev] [PATCH] util/build-id: define ElfW and NT_GNU_BUILD_ID if needed

[Emil Velikov]

On 18 February 2017 at 07:56, Jonathan Gray  wrote:
> Define ElfW() and NT_GNU_BUILD_ID if needed as these defines are not
> present on at least OpenBSD and FreeBSD.  Fixes the build on OpenBSD.
>
> Signed-off-by: Jonathan Gray 
R-b and pushed to master. Thank you Jonathan !

-Emil
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Re: [Mesa-dev] [PATCH 1/7] gallium/util: remove unused helper util_draw_texquad

[Brian Paul]

I verified that the removed functions are not needed by our in-house code.

Other than comments on patch 5, the series is

Reviewed-by: Brian Paul 


On 02/16/2017 05:52 AM, Marek Olšák wrote:

From: Marek Olšák 

---
  src/gallium/auxiliary/util/u_draw_quad.c | 66 
  src/gallium/auxiliary/util/u_draw_quad.h |  6 ---
  2 files changed, 72 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_draw_quad.c 
b/src/gallium/auxiliary/util/u_draw_quad.c
index fa442af..ce3fa41 100644
--- a/src/gallium/auxiliary/util/u_draw_quad.c
+++ b/src/gallium/auxiliary/util/u_draw_quad.c
@@ -83,76 +83,10 @@ util_draw_user_vertex_buffer(struct cso_context *cso, void 
*buffer,
 assert(num_attribs <= PIPE_MAX_ATTRIBS);

 vbuffer.user_buffer = buffer;
 vbuffer.stride = num_attribs * 4 * sizeof(float);  /* vertex size */

 /* note: vertex elements already set by caller */

 cso_set_vertex_buffers(cso, 0, 1, );
 cso_draw_arrays(cso, prim_type, 0, num_verts);
  }
-
-
-/**
- * Draw screen-aligned textured quad.
- * Note: this isn't especially efficient.
- */
-void
-util_draw_texquad(struct pipe_context *pipe, struct cso_context *cso,
-  uint vbuf_slot,
-  float x0, float y0, float x1, float y1, float z)
-{
-   uint numAttribs = 2, i, j;
-   uint vertexBytes = 4 * (4 * numAttribs * sizeof(float));
-   struct pipe_resource *vbuf = NULL;
-   float *v = NULL;
-
-   v = MALLOC(vertexBytes);
-   if (!v)
-  goto out;
-
-   /*
-* Load vertex buffer
-*/
-   for (i = j = 0; i < 4; i++) {
-  v[j + 2] = z;   /* z */
-  v[j + 3] = 1.0; /* w */
-  v[j + 6] = 0.0; /* r */
-  v[j + 7] = 1.0; /* q */
-  j += 8;
-   }
-
-   v[0] = x0;
-   v[1] = y0;
-   v[4] = 0.0; /*s*/
-   v[5] = 0.0; /*t*/
-
-   v[8] = x1;
-   v[9] = y0;
-   v[12] = 1.0;
-   v[13] = 0.0;
-
-   v[16] = x1;
-   v[17] = y1;
-   v[20] = 1.0;
-   v[21] = 1.0;
-
-   v[24] = x0;
-   v[25] = y1;
-   v[28] = 0.0;
-   v[29] = 1.0;
-   
-   vbuf = pipe_buffer_create(pipe->screen, PIPE_BIND_VERTEX_BUFFER,
- PIPE_USAGE_STAGING, vertexBytes);
-   if (!vbuf)
-  goto out;
-   pipe_buffer_write(pipe, vbuf, 0, vertexBytes, v);
-
-   util_draw_vertex_buffer(pipe, cso, vbuf, vbuf_slot, 0,
-   PIPE_PRIM_TRIANGLE_FAN, 4, 2);
-
-out:
-   if (vbuf)
-  pipe_resource_reference(, NULL);
-
-   FREE(v);
-}
diff --git a/src/gallium/auxiliary/util/u_draw_quad.h 
b/src/gallium/auxiliary/util/u_draw_quad.h
index 6553d5d..e5b676a 100644
--- a/src/gallium/auxiliary/util/u_draw_quad.h
+++ b/src/gallium/auxiliary/util/u_draw_quad.h
@@ -44,22 +44,16 @@ struct cso_context;
  extern void
  util_draw_vertex_buffer(struct pipe_context *pipe, struct cso_context *cso,
  struct pipe_resource *vbuf, uint vbuf_slot,
  uint offset, uint prim_type, uint num_attribs,
  uint num_verts);

  void
  util_draw_user_vertex_buffer(struct cso_context *cso, void *buffer,
   uint prim_type, uint num_verts, uint 
num_attribs);

-extern void
-util_draw_texquad(struct pipe_context *pipe, struct cso_context *cso,
-  uint vbuf_slot,
-  float x0, float y0, float x1, float y1, float z);
-
-
  #ifdef __cplusplus
  }
  #endif


  #endif



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Re: [Mesa-dev] [PATCH 5/7] gallium/u_suballoc: allow setting pipe_resource::flags

[Brian Paul]

On 02/16/2017 05:52 AM, Marek Olšák wrote:

From: Marek Olšák 

---
  src/gallium/auxiliary/util/u_suballoc.c   | 22 ++
  src/gallium/auxiliary/util/u_suballoc.h   |  2 +-
  src/gallium/drivers/r600/r600_pipe.c  |  5 +++--
  src/gallium/drivers/radeon/r600_pipe_common.c |  2 +-
  src/gallium/drivers/radeonsi/si_pipe.c|  2 +-
  5 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_suballoc.c 
b/src/gallium/auxiliary/util/u_suballoc.c
index 8c463c9..392bba7 100644
--- a/src/gallium/auxiliary/util/u_suballoc.c
+++ b/src/gallium/auxiliary/util/u_suballoc.c
@@ -36,46 +36,48 @@

  #include "u_suballoc.h"


  struct u_suballocator {
 struct pipe_context *pipe;

 unsigned size;  /* Size of the whole buffer, in bytes. */
 unsigned bind;  /* Bitmask of PIPE_BIND_* flags. */
 enum pipe_resource_usage usage;
+   unsigned flags; /* pipe_resource::flags */


/* bitmask of PIPE_RESOURCE_FLAG_x */ would be more explicit.  And maybe 
even call the field 'resource_flags' instead.




 boolean zero_buffer_memory; /* If the buffer contents should be zeroed. */

 struct pipe_resource *buffer;   /* The buffer we suballocate from. */
 unsigned offset; /* Aligned offset pointing at the first unused byte. */
  };


  /**
   * Create a suballocator.
   *
   * \p zero_buffer_memory determines whether the buffer contents should be
   * cleared to 0 after the allocation.


Can you add a comment for the new param here?  As is, reading "unsigned 
flags" surely would require digging around to know what flags are expected.


\p flags  bitmask of PIPE_RESOURCE_FLAG_x bits.


I'd like to look at using true enums for some of our bitfield flags. 
Last time I looked, gdb was able to figure out when an enum represents a 
bitmask and helpfully printed the flag names.


-Brian



   */
  struct u_suballocator *
  u_suballocator_create(struct pipe_context *pipe, unsigned size, unsigned bind,
-  enum pipe_resource_usage usage,
+  enum pipe_resource_usage usage, unsigned flags,
  boolean zero_buffer_memory)
  {
 struct u_suballocator *allocator = CALLOC_STRUCT(u_suballocator);
 if (!allocator)
return NULL;

 allocator->pipe = pipe;
 allocator->size = size;
 allocator->bind = bind;
 allocator->usage = usage;
+   allocator->flags = flags;
 allocator->zero_buffer_memory = zero_buffer_memory;
 return allocator;
  }

  void
  u_suballocator_destroy(struct u_suballocator *allocator)
  {
 pipe_resource_reference(>buffer, NULL);
 FREE(allocator);
  }
@@ -90,23 +92,35 @@ u_suballocator_alloc(struct u_suballocator *allocator, 
unsigned size,
 /* Don't allow allocations larger than the buffer size. */
 if (size > allocator->size)
goto fail;

 /* Make sure we have enough space in the buffer. */
 if (!allocator->buffer ||
 allocator->offset + size > allocator->size) {
/* Allocate a new buffer. */
pipe_resource_reference(>buffer, NULL);
allocator->offset = 0;
-  allocator->buffer =
- pipe_buffer_create(allocator->pipe->screen, allocator->bind,
-allocator->usage, allocator->size);
+
+  struct pipe_resource templ;
+  memset(, 0, sizeof(templ));
+  templ.target = PIPE_BUFFER;
+  templ.format = PIPE_FORMAT_R8_UNORM;
+  templ.bind = allocator->bind;
+  templ.usage = allocator->usage;
+  templ.flags = allocator->flags;
+  templ.width0 = allocator->size;
+  templ.height0 = 1;
+  templ.depth0 = 1;
+  templ.array_size = 1;
+
+  struct pipe_screen *screen = allocator->pipe->screen;
+  allocator->buffer = screen->resource_create(screen, );
if (!allocator->buffer)
   goto fail;

/* Clear the memory if needed. */
if (allocator->zero_buffer_memory) {
   struct pipe_context *pipe = allocator->pipe;

   if (pipe->clear_buffer) {
  unsigned clear_value = 0;

diff --git a/src/gallium/auxiliary/util/u_suballoc.h 
b/src/gallium/auxiliary/util/u_suballoc.h
index fb08f16..e35382f 100644
--- a/src/gallium/auxiliary/util/u_suballoc.h
+++ b/src/gallium/auxiliary/util/u_suballoc.h
@@ -28,21 +28,21 @@

  /* A simple allocator that suballocates memory from a large buffer. */

  #ifndef U_SUBALLOC
  #define U_SUBALLOC

  struct u_suballocator;

  struct u_suballocator *
  u_suballocator_create(struct pipe_context *pipe, unsigned size, unsigned bind,
-  enum pipe_resource_usage usage,
+  enum pipe_resource_usage usage, unsigned flags,
  boolean zero_buffer_memory);

  void
  u_suballocator_destroy(struct u_suballocator *allocator);

  void
  u_suballocator_alloc(struct u_suballocator *allocator, unsigned size,
   unsigned alignment, unsigned 

Re: [Mesa-dev] [PATCH 6/6] radeonsi: fix issues with monolithic shaders

[Nicolai Hähnle]

For the series:

Reviewed-by: Nicolai Hähnle 


On 19.02.2017 17:27, Marek Olšák wrote:

From: Marek Olšák 

R600_DEBUG=mono has had no effect since:

commit 1fabb297177069e95ec1bb7053acb32f8ec3e092
Author: Marek Olšák 
Date:   Tue Feb 14 22:08:32 2017 +0100

radeonsi: have separate LS and ES main shader parts in the shader selector

Also, this assertion was failing:
si_state_shaders.c:1307: si_shader_select_with_key: Assertion
`!shader->is_optimized' failed.
---
 src/gallium/drivers/radeonsi/si_state_shaders.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 727ff33..12ea20b 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1235,20 +1235,21 @@ again:
return -ENOMEM;
}
shader->selector = sel;
shader->key = *key;
shader->compiler_ctx_state = *compiler_state;

/* Compile the main shader part if it doesn't exist. This can happen
 * if the initial guess was wrong. */
struct si_shader **mainp = si_get_main_shader_part(sel, key);
bool is_pure_monolithic =
+   sscreen->use_monolithic_shaders ||
memcmp(>mono, , sizeof(key->mono)) != 0;

if (!*mainp && !is_pure_monolithic) {
struct si_shader *main_part = CALLOC_STRUCT(si_shader);

if (!main_part) {
FREE(shader);
pipe_mutex_unlock(sel->mutex);
return -ENOMEM; /* skip the draw call */
}
@@ -1268,21 +1269,21 @@ again:
*mainp = main_part;
}

/* Monolithic-only shaders don't make a distinction between optimized
 * and unoptimized. */
shader->is_monolithic =
is_pure_monolithic ||
memcmp(>opt, , sizeof(key->opt)) != 0;

shader->is_optimized =
-   !sscreen->use_monolithic_shaders &&
+   !is_pure_monolithic &&
memcmp(>opt, , sizeof(key->opt)) != 0;
if (shader->is_optimized)
util_queue_fence_init(>optimized_ready);

if (!sel->last_variant) {
sel->first_variant = shader;
sel->last_variant = shader;
} else {
sel->last_variant->next_variant = shader;
sel->last_variant = shader;



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Re: [Mesa-dev] [PATCH 00/13] Misc extern C fixes

[Brian Paul]

On 02/16/2017 08:16 AM, Emil Velikov wrote:

Just a bunch of extern C issues flagged by [1]. There's a few more
remaining such as the glsl_types C API living in nir_types.{cpp,h} but
that can be resolved at a later date.

-Emil

[1] git grep -B2 "#.*\" -- src/ | grep  "\"



Series, looks OK to me.  Though, one could imagine some .h files that 
aren't included by .cpp sources now being included by .cpp sources in 
the future.  So, I'm not sure patches 1, 2, 13 are needed.


In any case,
Reviewed-by: Brian Paul 

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[Mesa-dev] [Bug 98279] [vulkan/radeon] dota2 -vulkan hangs the GPU on R9-390

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98279

Jan Ziak <0xe2.0x9a.0...@gmail.com> changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

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