Re: [Mesa-dev] [PATCH] i965/nir: do int64 lowering before optimization

[Iago Toral]

On Tue, 2017-12-12 at 08:20 +0100, Iago Toral wrote:
> On Mon, 2017-12-11 at 08:01 -0800, Jason Ekstrand wrote:
> > On Mon, Dec 11, 2017 at 12:55 AM, Iago Toral 
> > wrote:
> > > This didn't get any reviews yet. Any takers?
> > > 
> > > 
> > > 
> > > On Fri, 2017-12-01 at 13:46 +0100, Iago Toral Quiroga wrote:
> > > 
> > > > Otherwise loop unrolling will fail to see the actual cost of
> > > 
> > > > the unrolling operations when the loop body contains 64-bit
> > > integer
> > > 
> > > > instructions, and very specially when the divmod64 lowering
> > > applies,
> > > 
> > > > since its lowering is quite expensive.
> > > 
> > > >
> > > 
> > > > Without this change, some in-development CTS tests for int64
> > > 
> > > > get stuck forever trying to register allocate a shader with
> > > 
> > > > over 50K SSA values. The large number of SSA values is the
> > > result
> > > 
> > > > of NIR first unrolling multiple seemingly simple loops that
> > > involve
> > > 
> > > > int64 instructions, only to then lower these instructions to
> > > produce
> > > 
> > > > a massive pile of code (due to the divmod64 lowering in the
> > > unrolled
> > > 
> > > > instructions).
> > > 
> > > >
> > > 
> > > > With this change, loop unrolling will see the loops with the
> > > int64
> > > 
> > > > code already lowered and will realize that it is too expensive
> > > to
> > > 
> > > > unroll.
> > > 
> > 
> > Hrm... I'm not quite sure what I think of this.  I put it after
> > nir_optimize because I wanted opt_algebraic to be able to work it's
> > magic and hopefully remove a bunch of int64 ops before we lower
> > them.  In particular, we have optimizations to remove integer
> > division and replace it with shifts.  However, loop unrolling does
> > need to happen before lower_indirect_derefs so that
> > lower_indirect_derefs will do as little work as possible.
> > 
> > This is a bit of a pickle...  I don't really want to add a third
> > brw_nir_optimize call.  It probably wouldn't be the end of the
> > world but it does add compile time.
> > 
> > One crazy idea which I don't think I like would be to have a quick
> > pass that walks the IR and sees if there are any 64-bit SSA
> > values.  If it does, we run brw_nir_optimize without loop unrolling
> > then 64-bit lowering and then we go into the normal
> > brw_nir_optimize.
> 
> With the constraints you mention above, I am not sure that we have
> many more options... what if we always run opt_algebraic first
> followed by int64 lowering before the first nir_optimize? That would
> only add an extra opt_algebraic instead of a full nir_optimize. Would
> that be better than adding that 64-bit SSA scan pre-pass?

We still need to make a decision for this, does my proposal sound
better than than the other options on the table? If not I guess we
should go with the 64-bit SSA scan pre-pass.
Iago
> >  
> > > > ---
> > > 
> > > >  src/intel/compiler/brw_nir.c | 8 
> > > 
> > > >  1 file changed, 4 insertions(+), 4 deletions(-)
> > > 
> > > >
> > > 
> > > > diff --git a/src/intel/compiler/brw_nir.c
> > > 
> > > > b/src/intel/compiler/brw_nir.c
> > > 
> > > > index 8f3f77f89a..ef12cdfff8 100644
> > > 
> > > > --- a/src/intel/compiler/brw_nir.c
> > > 
> > > > +++ b/src/intel/compiler/brw_nir.c
> > > 
> > > > @@ -636,6 +636,10 @@ brw_preprocess_nir(const struct
> > > brw_compiler
> > > 
> > > > *compiler, nir_shader *nir)
> > > 
> > > >  
> > > 
> > > > OPT(nir_split_var_copies);
> > > 
> > > >  
> > > 
> > > > +   nir_lower_int64(nir, nir_lower_imul64 |
> > > 
> > > > +nir_lower_isign64 |
> > > 
> > > > +nir_lower_divmod64);
> > > 
> > > > +
> > > 
> > > > nir = brw_nir_optimize(nir, compiler, is_scalar);
> > > 
> > > >  
> > > 
> > > > if (is_scalar) {
> > > 
> > > > @@ -663,10 +667,6 @@ brw_preprocess_nir(const struct
> > > brw_compiler
> > > 
> > > > *compiler, nir_shader *nir)
> > > 
> > > >    brw_nir_no_indirect_mask(compiler, nir->info.stage);
> > > 
> > > > nir_lower_indirect_derefs(nir, indirect_mask);
> > > 
> > > >  
> > > 
> > > > -   nir_lower_int64(nir, nir_lower_imul64 |
> > > 
> > > > -nir_lower_isign64 |
> > > 
> > > > -nir_lower_divmod64);
> > > 
> > > > -
> > > 
> > > > /* Get rid of split copies */
> > > 
> > > > nir = brw_nir_optimize(nir, compiler, is_scalar);
> > > 
> > > >  
> > > 
> > > ___
> > > 
> > > mesa-dev mailing list
> > > 
> > > mesa-dev@lists.freedesktop.org
> > > 
> > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > > 
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Re: [Mesa-dev] [PATCH] i965: Don't allocate an MCS for 16x MSAA and width > 8192.

[Iago Toral]

Thanks Ken!

Reviewed-by: Iago Toral Quiroga 

On Wed, 2017-12-13 at 12:25 -0800, Kenneth Graunke wrote:
> The hardware doesn't support this, and isl_surf_get_mcs_surf will
> fail.
> 
> I feel a bit bad replicating this logic, but we want to decide up
> front.
> 
> This fixes the following test when run with --deqp-surface-
> width=16384:
> - GTF-
> GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframe
> buffer_multisampled_framebuffers_different_sample_count
> 
> Cc: ito...@igalia.com
> Cc: apuen...@igalia.com
> Cc: i...@freedesktop.org
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index c1a4ce184f5..ead0c359c0f 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -73,6 +73,10 @@ intel_miptree_supports_mcs(struct brw_context
> *brw,
> if (devinfo->gen < 7)
>    return false;
>  
> +   /* See isl_surf_get_mcs_surf for details. */
> +   if (mt->surf.samples == 16 && mt->surf.logical_level0_px.width >
> 8192)
> +  return false;
> +
> /* In Gen7, IMS layout is only used for depth and stencil
> buffers. */
> switch (_mesa_get_format_base_format(mt->format)) {
> case GL_DEPTH_COMPONENT:
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Re: [Mesa-dev] [PATCH 4/4] mesa: enable GL_EXT_disjoint_timer_query extension

[Tapani Pälli]

On 12/12/2017 07:00 PM, Ian Romanick wrote:

On 11/19/2017 11:18 PM, Tapani Pälli wrote:

Add GL_GPU_DISJOINT_EXT and enable extension when ARB_timer_query
is supported by the driver.

Following dEQP cases pass:
dEQP-EGL.functional.get_proc_address.extension.gl_ext_disjoint_timer_query
dEQP-EGL.functional.client_extensions.disjoint

Piglit test 'ext_disjoint_timer_query-simple' passes with these changes.

No changes/regression observed in Intel CI.

Signed-off-by: Tapani Pälli 
---
  src/mesa/main/extensions_table.h |  1 +
  src/mesa/main/get.c  | 17 +
  src/mesa/main/get_hash_params.py |  5 +
  src/mesa/main/glheader.h |  4 
  src/mesa/main/mtypes.h   |  1 +
  src/mesa/main/queryobj.c |  3 ++-
  6 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 5b66e7d30d..78f0d35feb 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -209,6 +209,7 @@ EXT(EXT_copy_image  , OES_copy_image
  EXT(EXT_copy_texture, dummy_true  
   , GLL,  x ,  x ,  x , 1995)
  EXT(EXT_depth_bounds_test   , EXT_depth_bounds_test   
   , GLL, GLC,  x ,  x , 2002)
  EXT(EXT_discard_framebuffer , dummy_true  
   ,  x ,  x , ES1, ES2, 2009)
+EXT(EXT_disjoint_timer_query, ARB_timer_query  
  ,  x ,  x ,  x , ES2, 2016)

  ^^^

This should be EXT_disjoint_timer_query, right?  All of the things below
seem to use that flag.


Right, seems like I did not think this through. Earlier I thought we 
could simply turn it on for all drivers that support ARB_timer_query 
(and robustness) but seems not all the drivers do so we need to toggle 
it on separately. I will need to update this one and add a separate 
patch to toggle it on in the i965 driver.




  EXT(EXT_draw_buffers, dummy_true  
   ,  x ,  x ,  x , ES2, 2012)
  EXT(EXT_draw_buffers2   , EXT_draw_buffers2   
   , GLL, GLC,  x ,  x , 2006)
  EXT(EXT_draw_buffers_indexed, ARB_draw_buffers_blend  
   ,  x ,  x ,  x ,  30, 2014)
diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index ea8d932b18..6c0d1f7e9a 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -578,6 +578,13 @@ static const int extra_EXT_provoking_vertex_32[] = {
 EXTRA_END
  };
  
+static const int extra_EXT_disjoint_timer_query[] = {

+   EXTRA_API_ES2,
+   EXTRA_API_ES3,
+   EXT(EXT_disjoint_timer_query),
+   EXTRA_END
+};
+
  
  /* This is the big table describing all the enums we accept in

   * glGet*v().  The table is partitioned into six parts: enums
@@ -1151,6 +1158,16 @@ find_custom_value(struct gl_context *ctx, const struct 
value_desc *d, union valu
   }
}
break;
+   /* GL_EXT_disjoint_timer_query */
+   case GL_GPU_DISJOINT_EXT:
+  {
+ simple_mtx_lock(>Shared->Mutex);
+ v->value_int = ctx->Shared->DisjointOperation;
+ /* Reset state as expected by the spec. */
+ ctx->Shared->DisjointOperation = false;
+ simple_mtx_unlock(>Shared->Mutex);
+  }
+  break;
 }
  }
  
diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py

index 20ef6e4977..55a956da84 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -254,6 +254,11 @@ descriptor=[
[ "POINT_SIZE_ARRAY_BUFFER_BINDING_OES", "LOC_CUSTOM, TYPE_INT, 0, 
NO_EXTRA" ],
  ]},
  
+# Enums in GLES2, GLES3

+{ "apis": ["GLES2", "GLES3"], "params": [
+  [ "GPU_DISJOINT_EXT", "LOC_CUSTOM, TYPE_INT, 0, 
extra_EXT_disjoint_timer_query" ],
+]},
+
  { "apis": ["GL", "GL_CORE", "GLES2"], "params": [
  # == GL_MAX_TEXTURE_COORDS_NV
[ "MAX_TEXTURE_COORDS_ARB", "CONTEXT_INT(Const.MaxTextureCoordUnits), 
extra_ARB_fragment_program" ],
diff --git a/src/mesa/main/glheader.h b/src/mesa/main/glheader.h
index 3f2a923782..35a442a77b 100644
--- a/src/mesa/main/glheader.h
+++ b/src/mesa/main/glheader.h
@@ -144,6 +144,10 @@ typedef void *GLeglImageOES;
  #define GL_FRAGMENT_SHADER_DISCARDS_SAMPLES_EXT 0x8A52
  #endif
  
+#ifndef GL_EXT_disjoint_timer_query

+#define GL_GPU_DISJOINT_EXT 0x8FBB
+#endif
+
  /* Inexplicably, GL_HALF_FLOAT_OES has a different value than GL_HALF_FLOAT.
   */
  #ifndef GL_HALF_FLOAT_OES
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 4cb6a74d69..9ed8d86688 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -4143,6 +4143,7 @@ struct gl_extensions
 GLboolean EXT_blend_func_separate;
 GLboolean EXT_blend_minmax;
 GLboolean EXT_depth_bounds_test;
+   GLboolean 

[Mesa-dev] [PATCH] st/st_glsl_to_nir: call nir_lower_64bit_pack

[Timothy Arceri]

Fixes 56 crashes in radeonsi.
---
 src/mesa/state_tracker/st_glsl_to_nir.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 7c9e76a2dce..5683dfe 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -267,20 +267,21 @@ st_nir_assign_uniform_locations(struct gl_program *prog,
*size = max;
 }
 
 static void
 st_nir_opts(nir_shader *nir)
 {
bool progress;
do {
   progress = false;
 
+  NIR_PASS_V(nir, nir_lower_64bit_pack);
   NIR_PASS(progress, nir, nir_copy_prop);
   NIR_PASS(progress, nir, nir_opt_remove_phis);
   NIR_PASS(progress, nir, nir_opt_dce);
   if (nir_opt_trivial_continues(nir)) {
  progress = true;
  NIR_PASS(progress, nir, nir_copy_prop);
  NIR_PASS(progress, nir, nir_opt_dce);
   }
   NIR_PASS(progress, nir, nir_opt_if);
   NIR_PASS(progress, nir, nir_opt_dead_cf);
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 22/22] st/dri: Add option to control exposure of 10 bpc color configs.

[Ilia Mirkin]

On Wed, Dec 13, 2017 at 10:45 PM, Mario Kleiner
 wrote:
> On 12/13/2017 05:27 PM, Marek Olšák wrote:
>>
>> Mario, can we push these patches?
>>
>> Marek
>>
>
> Sorry for the late response and thanks for the reviews! Was a bit sick the
> last days, so couldn't think or do anything about the recent comments so
> far.
>
> I think all patches have a r-b by you and/or Tapani, except the nouveau
> patch 20/22 on which Ilia commented. Not sure about that one. If we leave it
> out then stuff breaks on nouveau. If we leave it in, then as far as i
> understand Ilia's comments, we have a slight violation of spec atm. - If a
> app asks for a framebuffer without alpha channel (xrgb2101010), but then
> enables blending with DST_ALPHA it would potentially get random 2 x-bit
> trash instead of a well defined 1.0 DST_ALPHA. Otoh. it would be legal but a
> bit non-sensical for an app to ask for no alpha channel, but then choose
> blend functions that only make sense with an alpha channel?
>
> The third option would be to replace that patch with one that disables the
> rgb10 support for visuals on nouveau completely until we have a solution for
> properly emulating xrgb201010 on nouveau to cover such corner cases?

Hold on ... my understanding was that without that patch, nouveau just
wouldn't work with 30-bit. Which is the current status quo. I'd like
to investigate first-hand what the breakage is, perhaps it's actually
unrelated to the missing format, and can be made to work just fine
with the st using argb2101010.

Am I misunderstanding the state of things? I really don't want nouveau
to be holding anything up.

  -ilia
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[Mesa-dev] [PATCH] st/glsl_to_nir: call post opt functions after opts have finished

[Timothy Arceri]

We need to move this to a separate loop because
nir_compact_varyings() can alter the IR of a previous stage.

Fixes: 6648bd68fd27 "st/glsl_to_nir: enable NIR link time opts"
---
 src/mesa/state_tracker/st_glsl_to_nir.cpp | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index be34031bfb5..7c9e76a2dce 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -621,20 +621,26 @@ st_link_nir(struct gl_context *ctx,
   NIR_PASS_V(nir, nir_lower_system_values);
 
   nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
   shader->Program->info = nir->info;
 
   if (prev != -1) {
  
nir_compact_varyings(shader_program->_LinkedShaders[prev]->Program->nir,
   nir, ctx->API != API_OPENGL_COMPAT);
   }
   prev = i;
+   }
+
+   for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
+  struct gl_linked_shader *shader = shader_program->_LinkedShaders[i];
+  if (shader == NULL)
+ continue;
 
   st_glsl_to_nir_post_opts(st, shader->Program, shader_program);
 
   assert(shader->Program);
   if (!ctx->Driver.ProgramStringNotify(ctx,
_mesa_shader_stage_to_program(i),
shader->Program)) {
  _mesa_reference_program(ctx, >Program, NULL);
  return false;
   }
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 22/22] st/dri: Add option to control exposure of 10 bpc color configs.

[Mario Kleiner]

On 12/13/2017 05:27 PM, Marek Olšák wrote:

Mario, can we push these patches?

Marek



Sorry for the late response and thanks for the reviews! Was a bit sick 
the last days, so couldn't think or do anything about the recent 
comments so far.


I think all patches have a r-b by you and/or Tapani, except the nouveau 
patch 20/22 on which Ilia commented. Not sure about that one. If we 
leave it out then stuff breaks on nouveau. If we leave it in, then as 
far as i understand Ilia's comments, we have a slight violation of spec 
atm. - If a app asks for a framebuffer without alpha channel 
(xrgb2101010), but then enables blending with DST_ALPHA it would 
potentially get random 2 x-bit trash instead of a well defined 1.0 
DST_ALPHA. Otoh. it would be legal but a bit non-sensical for an app to 
ask for no alpha channel, but then choose blend functions that only make 
sense with an alpha channel?


The third option would be to replace that patch with one that disables 
the rgb10 support for visuals on nouveau completely until we have a 
solution for properly emulating xrgb201010 on nouveau to cover such 
corner cases?


-mario



On Wed, Nov 29, 2017 at 5:21 AM, Mario Kleiner
 wrote:

Some clients may not like rgb10 fbconfigs and visuals.
Support driconf option 'allow_rgb10_configs' on gallium
to allow per application enable/disable.

The option defaults to enabled.

Signed-off-by: Mario Kleiner 
---
  src/gallium/auxiliary/pipe-loader/driinfo_gallium.h | 1 +
  src/gallium/state_trackers/dri/dri_screen.c | 8 
  2 files changed, 9 insertions(+)

diff --git a/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h 
b/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
index d2d2c9d..db0d633 100644
--- a/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
+++ b/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
@@ -31,4 +31,5 @@ DRI_CONF_SECTION_END
  DRI_CONF_SECTION_MISCELLANEOUS
 DRI_CONF_ALWAYS_HAVE_DEPTH_BUFFER("false")
 DRI_CONF_GLSL_ZERO_INIT("false")
+   DRI_CONF_ALLOW_RGB10_CONFIGS("true")
  DRI_CONF_SECTION_END
diff --git a/src/gallium/state_trackers/dri/dri_screen.c 
b/src/gallium/state_trackers/dri/dri_screen.c
index 04afe71..d307b4f 100644
--- a/src/gallium/state_trackers/dri/dri_screen.c
+++ b/src/gallium/state_trackers/dri/dri_screen.c
@@ -156,6 +156,7 @@ dri_fill_in_modes(struct dri_screen *screen)
 struct pipe_screen *p_screen = screen->base.screen;
 boolean pf_z16, pf_x8z24, pf_z24x8, pf_s8z24, pf_z24s8, pf_z32;
 boolean mixed_color_depth;
+   boolean allow_rgb10;

 static const GLenum back_buffer_modes[] = {
__DRI_ATTRIB_SWAP_NONE, __DRI_ATTRIB_SWAP_UNDEFINED,
@@ -172,6 +173,8 @@ dri_fill_in_modes(struct dri_screen *screen)
depth_buffer_factor = 1;
 }

+   allow_rgb10 = driQueryOptionb(>dev->option_cache, 
"allow_rgb10_configs");
+
 msaa_samples_max = (screen->st_api->feature_mask & 
ST_API_FEATURE_MS_VISUALS_MASK)
? MSAA_VISUAL_MAX_SAMPLES : 1;

@@ -231,6 +234,11 @@ dri_fill_in_modes(struct dri_screen *screen)
unsigned num_msaa_modes = 0; /* includes a single-sample mode */
uint8_t msaa_modes[MSAA_VISUAL_MAX_SAMPLES];

+  if (!allow_rgb10 &&
+  (mesa_formats[format] == MESA_FORMAT_B10G10R10A2_UNORM ||
+   mesa_formats[format] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
if (!p_screen->is_format_supported(p_screen, pipe_formats[format],
   PIPE_TEXTURE_2D, 0,
   PIPE_BIND_RENDER_TARGET))
--
2.7.4

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Re: [Mesa-dev] [PATCH] gallium/docs: document behavior of set_sample_mask()

[Marek Olšák]

On Wed, Dec 13, 2017 at 4:43 AM, Roland Scheidegger  wrote:
> Am 13.12.2017 um 04:34 schrieb Brian Paul:
>> The sample mask is used even if msaa is not explicity enabled when we
>> have a framebuffer with multisampled surfaces.  That's DX behavior and
>> what the Radeon drivers do.  Not sure about other drivers at this point.
>> ---
>>  src/gallium/docs/source/context.rst | 5 -
>>  1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/docs/source/context.rst 
>> b/src/gallium/docs/source/context.rst
>> index 9d069b3..0ac7340 100644
>> --- a/src/gallium/docs/source/context.rst
>> +++ b/src/gallium/docs/source/context.rst
>> @@ -64,7 +64,10 @@ objects. They all follow simple, one-method binding 
>> calls, e.g.
>>  * ``set_stencil_ref`` sets the stencil front and back reference values
>>which are used as comparison values in stencil test.
>>  * ``set_blend_color``
>> -* ``set_sample_mask``
>> +* ``set_sample_mask``  sets the per-context multisample sample mask.  Note
>> +  that this takes effect even if multisampling is not explicitly enabled if
>> +  the frambuffer surface(s) are multisampled.  Also, this mask is AND-ed
>> +  with the optional fragment shader sample mask output (when emitted).
>>  * ``set_min_samples`` sets the minimum number of samples that must be run.
>>  * ``set_clip_state``
>>  * ``set_polygon_stipple``
>>
>
> Looks alright to me. Though note llvmpipe does this even for
> non-multisampled surfaces (as per dx behavior too). But as far as I
> know, radeons don't and it would have to be emulated (I suppose the dx10
> drivers do), so probably can't really make this gallium behavior (sample
> mask is pretty awkward with just one sample in the first place, and I
> doubt used in practice).

Old (and maybe even new) Radeons do obey the sample mask even with 1
sample. Sample mask == 0 kills all pixels.

Marek
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[Mesa-dev] [PATCH 1/2] i965/draw: Do resolves properly for textures used by TXF

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_draw.c | 41 
 1 file changed, 41 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 4945dec..9fd44e4 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -40,6 +40,7 @@
 #include "swrast_setup/swrast_setup.h"
 #include "drivers/common/meta.h"
 #include "util/bitscan.h"
+#include "util/bitset.h"
 
 #include "brw_blorp.h"
 #include "brw_draw.h"
@@ -371,6 +372,20 @@ intel_disable_rb_aux_buffer(struct brw_context *brw,
return found;
 }
 
+static void
+mark_textures_used_for_txf(BITSET_WORD *used_for_txf,
+   const struct gl_program *prog)
+{
+   if (!prog)
+  return;
+
+   unsigned mask = prog->SamplersUsed & prog->info.textures_used_by_txf;
+   while (mask) {
+  int s = u_bit_scan();
+  BITSET_SET(used_for_txf, prog->SamplerUnits[s]);
+   }
+}
+
 /**
  * \brief Resolve buffers before drawing.
  *
@@ -386,6 +401,18 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool 
rendering)
memset(brw->draw_aux_buffer_disabled, 0,
   sizeof(brw->draw_aux_buffer_disabled));
 
+   BITSET_DECLARE(used_for_txf, MAX_COMBINED_TEXTURE_IMAGE_UNITS);
+   memset(used_for_txf, 0, sizeof(used_for_txf));
+   if (rendering) {
+  mark_textures_used_for_txf(used_for_txf, ctx->VertexProgram._Current);
+  mark_textures_used_for_txf(used_for_txf, ctx->TessCtrlProgram._Current);
+  mark_textures_used_for_txf(used_for_txf, ctx->TessEvalProgram._Current);
+  mark_textures_used_for_txf(used_for_txf, ctx->GeometryProgram._Current);
+  mark_textures_used_for_txf(used_for_txf, ctx->FragmentProgram._Current);
+   } else {
+  mark_textures_used_for_txf(used_for_txf, ctx->ComputeProgram._Current);
+   }
+
/* Resolve depth buffer and render cache of each enabled texture. */
int maxEnabledUnit = ctx->Texture._MaxEnabledTexImageUnit;
for (int i = 0; i <= maxEnabledUnit; i++) {
@@ -422,6 +449,20 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool 
rendering)
 min_layer, num_layers,
 disable_aux);
 
+  /* If any programs are using it with texelFetch, we may need to also do
+   * a prepare with an sRGB format to ensure texelFetch works "properly".
+   */
+  if (BITSET_TEST(used_for_txf, i)) {
+ enum isl_format txf_format =
+translate_tex_format(brw, tex_obj->_Format, GL_DECODE_EXT);
+ if (txf_format != view_format) {
+intel_miptree_prepare_texture(brw, tex_obj->mt, txf_format,
+  min_level, num_levels,
+  min_layer, num_layers,
+  disable_aux);
+ }
+  }
+
   brw_cache_flush_for_read(brw, tex_obj->mt->bo);
 
   if (tex_obj->base.StencilSampling ||
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 2/2] i965: Enable CCS_E sampling of sRGB textures as UNORM

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index b87d356..e21e1da 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2566,9 +2566,8 @@ can_texture_with_ccs(struct brw_context *brw,
if (mt->aux_usage != ISL_AUX_USAGE_CCS_E)
   return false;
 
-   /* TODO: Replace with format_ccs_e_compat_with_miptree for better perf. */
-   if (!isl_formats_are_ccs_e_compatible(>screen->devinfo,
- mt->surf.format, view_format)) {
+   if (!format_ccs_e_compat_with_miptree(>screen->devinfo,
+ mt, view_format)) {
   perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
  isl_format_get_layout(view_format)->name,
  _mesa_get_format_name(mt->format));
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH 3/3] Revert "i965: Disable regular fast-clears (CCS_D) on gen9+"

[Jason Ekstrand]

Better commit message:

Re-enable regular fast-clears (CCS_D) on gen9+

This reverts commit ee57b15ec764736e2d5360beaef9fb2045ed0f68, "i965:
Disable regular fast-clears (CCS_D) on gen9+".  How taht we've fixed the
issue with too many different aux usages in the render cache, it should
be safe to re-enable CCS_D for sRGB.


On Wed, Dec 13, 2017 at 5:52 PM, Jason Ekstrand 
wrote:

> This reverts commit ee57b15ec764736e2d5360beaef9fb2045ed0f68.
>
> Cc: "17.3" 
> ---
>  src/mesa/drivers/dri/i965/brw_meta_util.c | 10 -
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 57
> ---
>  2 files changed, 25 insertions(+), 42 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c
> b/src/mesa/drivers/dri/i965/brw_meta_util.c
> index 54dc6a5..b311815 100644
> --- a/src/mesa/drivers/dri/i965/brw_meta_util.c
> +++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
> @@ -293,17 +293,7 @@ brw_is_color_fast_clear_compatible(struct
> brw_context *brw,
> brw->mesa_to_isl_render_format[mt->format])
>return false;
>
> -   /* Gen9 doesn't support fast clear on single-sampled SRGB buffers. When
> -* GL_FRAMEBUFFER_SRGB is enabled any color renderbuffers will be
> -* resolved in intel_update_state. In that case it's pointless to do a
> -* fast clear because it's very likely to be immediately resolved.
> -*/
> const bool srgb_rb = _mesa_get_srgb_format_linear(mt->format) !=
> mt->format;
> -   if (devinfo->gen >= 9 &&
> -   mt->surf.samples == 1 &&
> -   ctx->Color.sRGBEnabled && srgb_rb)
> -  return false;
> -
>/* Gen10 doesn't automatically decode the clear color of sRGB buffers.
> Since
> * we currently don't perform this decode in software, avoid a
> fast-clear
> * altogether. TODO: Do this in software.
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index c1a4ce1..b87d356 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -207,13 +207,7 @@ intel_miptree_supports_ccs(struct brw_context *brw,
> if (!brw->mesa_format_supports_render[mt->format])
>return false;
>
> -   if (devinfo->gen >= 9) {
> -  mesa_format linear_format = _mesa_get_srgb_format_linear(
> mt->format);
> -  const enum isl_format isl_format =
> - brw_isl_format_for_mesa_format(linear_format);
> -  return isl_format_supports_ccs_e(>screen->devinfo,
> isl_format);
> -   } else
> -  return true;
> +   return true;
>  }
>
>  static bool
> @@ -256,7 +250,7 @@ intel_miptree_supports_hiz(const struct brw_context
> *brw,
>   * our HW tends to support more linear formats than sRGB ones, we use this
>   * format variant for check for CCS_E compatibility.
>   */
> -MAYBE_UNUSED static bool
> +static bool
>  format_ccs_e_compat_with_miptree(const struct gen_device_info *devinfo,
>   const struct intel_mipmap_tree *mt,
>   enum isl_format access_format)
> @@ -290,12 +284,13 @@ intel_miptree_supports_ccs_e(struct brw_context
> *brw,
> if (!intel_miptree_supports_ccs(brw, mt))
>return false;
>
> -   /* Fast clear can be also used to clear srgb surfaces by using
> equivalent
> -* linear format. This trick, however, can't be extended to be used
> with
> -* lossless compression and therefore a check is needed to see if the
> format
> -* really is linear.
> +   /* Many window system buffers are sRGB even if they are never rendered
> as
> +* sRGB.  For those, we want CCS_E for when sRGBEncode is false.  When
> the
> +* surface is used as sRGB, we fall back to CCS_D.
>  */
> -   return _mesa_get_srgb_format_linear(mt->format) == mt->format;
> +   mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
> +   enum isl_format isl_format = brw_isl_format_for_mesa_
> format(linear_format);
> +   return isl_format_supports_ccs_e(>screen->devinfo, isl_format);
>  }
>
>  /**
> @@ -2686,29 +2681,27 @@ intel_miptree_render_aux_usage(struct brw_context
> *brw,
>return ISL_AUX_USAGE_MCS;
>
> case ISL_AUX_USAGE_CCS_D:
> -  /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any
> of
> -   * the single-sampled color renderbuffers because the CCS buffer
> isn't
> -   * supported for SRGB formats. This only matters if
> FRAMEBUFFER_SRGB is
> -   * enabled because otherwise the surface state will be programmed
> with
> -   * the linear equivalent format anyway.
> -   */
> -  if (isl_format_is_srgb(render_format) &&
> -  _mesa_get_srgb_format_linear(mt->format) != mt->format) {
> - return ISL_AUX_USAGE_NONE;
> -  } else if (!mt->mcs_buf) {
> - return ISL_AUX_USAGE_NONE;
> -  } else {
> - return ISL_AUX_USAGE_CCS_D;
> -  }
> +  return mt->mcs_buf ? 

[Mesa-dev] [PATCH 3/3] Revert "i965: Disable regular fast-clears (CCS_D) on gen9+"

[Jason Ekstrand]

This reverts commit ee57b15ec764736e2d5360beaef9fb2045ed0f68.

Cc: "17.3" 
---
 src/mesa/drivers/dri/i965/brw_meta_util.c | 10 -
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 57 ---
 2 files changed, 25 insertions(+), 42 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c 
b/src/mesa/drivers/dri/i965/brw_meta_util.c
index 54dc6a5..b311815 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -293,17 +293,7 @@ brw_is_color_fast_clear_compatible(struct brw_context *brw,
brw->mesa_to_isl_render_format[mt->format])
   return false;
 
-   /* Gen9 doesn't support fast clear on single-sampled SRGB buffers. When
-* GL_FRAMEBUFFER_SRGB is enabled any color renderbuffers will be
-* resolved in intel_update_state. In that case it's pointless to do a
-* fast clear because it's very likely to be immediately resolved.
-*/
const bool srgb_rb = _mesa_get_srgb_format_linear(mt->format) != mt->format;
-   if (devinfo->gen >= 9 &&
-   mt->surf.samples == 1 &&
-   ctx->Color.sRGBEnabled && srgb_rb)
-  return false;
-
   /* Gen10 doesn't automatically decode the clear color of sRGB buffers. Since
* we currently don't perform this decode in software, avoid a fast-clear
* altogether. TODO: Do this in software.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index c1a4ce1..b87d356 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -207,13 +207,7 @@ intel_miptree_supports_ccs(struct brw_context *brw,
if (!brw->mesa_format_supports_render[mt->format])
   return false;
 
-   if (devinfo->gen >= 9) {
-  mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
-  const enum isl_format isl_format =
- brw_isl_format_for_mesa_format(linear_format);
-  return isl_format_supports_ccs_e(>screen->devinfo, isl_format);
-   } else
-  return true;
+   return true;
 }
 
 static bool
@@ -256,7 +250,7 @@ intel_miptree_supports_hiz(const struct brw_context *brw,
  * our HW tends to support more linear formats than sRGB ones, we use this
  * format variant for check for CCS_E compatibility.
  */
-MAYBE_UNUSED static bool
+static bool
 format_ccs_e_compat_with_miptree(const struct gen_device_info *devinfo,
  const struct intel_mipmap_tree *mt,
  enum isl_format access_format)
@@ -290,12 +284,13 @@ intel_miptree_supports_ccs_e(struct brw_context *brw,
if (!intel_miptree_supports_ccs(brw, mt))
   return false;
 
-   /* Fast clear can be also used to clear srgb surfaces by using equivalent
-* linear format. This trick, however, can't be extended to be used with
-* lossless compression and therefore a check is needed to see if the format
-* really is linear.
+   /* Many window system buffers are sRGB even if they are never rendered as
+* sRGB.  For those, we want CCS_E for when sRGBEncode is false.  When the
+* surface is used as sRGB, we fall back to CCS_D.
 */
-   return _mesa_get_srgb_format_linear(mt->format) == mt->format;
+   mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
+   enum isl_format isl_format = brw_isl_format_for_mesa_format(linear_format);
+   return isl_format_supports_ccs_e(>screen->devinfo, isl_format);
 }
 
 /**
@@ -2686,29 +2681,27 @@ intel_miptree_render_aux_usage(struct brw_context *brw,
   return ISL_AUX_USAGE_MCS;
 
case ISL_AUX_USAGE_CCS_D:
-  /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
-   * the single-sampled color renderbuffers because the CCS buffer isn't
-   * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
-   * enabled because otherwise the surface state will be programmed with
-   * the linear equivalent format anyway.
-   */
-  if (isl_format_is_srgb(render_format) &&
-  _mesa_get_srgb_format_linear(mt->format) != mt->format) {
- return ISL_AUX_USAGE_NONE;
-  } else if (!mt->mcs_buf) {
- return ISL_AUX_USAGE_NONE;
-  } else {
- return ISL_AUX_USAGE_CCS_D;
-  }
+  return mt->mcs_buf ? ISL_AUX_USAGE_CCS_D : ISL_AUX_USAGE_NONE;
 
case ISL_AUX_USAGE_CCS_E: {
-  /* Lossless compression is not supported for SRGB formats, it
-   * should be impossible to get here with such surfaces.
+  /* If the format supports CCS_E and is compatible with the miptree,
+   * then we can use it.
*/
-  assert(!isl_format_is_srgb(render_format) ||
- _mesa_get_srgb_format_linear(mt->format) == mt->format);
+  if (format_ccs_e_compat_with_miptree(>screen->devinfo,
+   mt, render_format))
+ return ISL_AUX_USAGE_CCS_E;
+
+  /* Otherwise, we have to 

[Mesa-dev] [PATCH 2/3] i965: Track format and aux usage in the render cache

[Jason Ekstrand]

This lets us perform render cache flushes whenever a surface goes from
being used with one aux+format to a different aux+format.

This is the "proper" fix for https://bugs.freedesktop.org/102435.
ee57b15ec764736e2d5360beaef9fb2045ed0f68 which was really just a partial
revert of 3e57e9494c2279580ad6a83ab8c065d01e7e634e was just a hack to
get rid of a hang in a bunch of Valve games.  This solves the actual
problem responsible for the hang and lets us enable CCS_E once again.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102435
Cc: "17.3" 
---
 src/mesa/drivers/dri/i965/brw_context.h |  2 +-
 src/mesa/drivers/dri/i965/brw_draw.c| 12 +-
 src/mesa/drivers/dri/i965/genX_blorp_exec.c | 14 +--
 src/mesa/drivers/dri/i965/intel_fbo.c   | 65 ++---
 src/mesa/drivers/dri/i965/intel_fbo.h   |  8 +++-
 5 files changed, 78 insertions(+), 23 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 0f0aad8..d041032 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -730,7 +730,7 @@ struct brw_context
 * and would need flushing before being used from another cache domain that
 * isn't coherent with it (i.e. the sampler).
 */
-   struct set *render_cache;
+   struct hash_table *render_cache;
 
/**
 * Set of struct brw_bo * that have been used as a depth buffer within this
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 1f86378..4945dec 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -503,13 +503,17 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw)
   mesa_format mesa_format =
  _mesa_get_render_format(ctx, intel_rb_format(irb));
   enum isl_format isl_format = brw_isl_format_for_mesa_format(mesa_format);
+  enum isl_aux_usage aux_usage =
+ intel_miptree_render_aux_usage(brw, irb->mt, isl_format,
+ctx->Color.BlendEnabled & (1 << i));
 
   intel_miptree_prepare_render(brw, irb->mt, irb->mt_level,
irb->mt_layer, irb->layer_count,
isl_format,
ctx->Color.BlendEnabled & (1 << i));
 
-  brw_cache_flush_for_render(brw, irb->mt->bo);
+  brw_cache_flush_for_render(brw, irb->mt->bo,
+ isl_format, aux_usage);
}
 }
 
@@ -575,8 +579,12 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context 
*brw)
   mesa_format mesa_format =
  _mesa_get_render_format(ctx, intel_rb_format(irb));
   enum isl_format isl_format = brw_isl_format_for_mesa_format(mesa_format);
+  enum isl_aux_usage aux_usage =
+ intel_miptree_render_aux_usage(brw, irb->mt, isl_format,
+ctx->Color.BlendEnabled & (1 << i));
+
+  brw_render_cache_add_bo(brw, irb->mt->bo, isl_format, aux_usage);
 
-  brw_render_cache_add_bo(brw, irb->mt->bo);
   intel_miptree_finish_render(brw, irb->mt, irb->mt_level,
   irb->mt_layer, irb->layer_count,
   isl_format,
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c 
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index e8bc52e..062171a 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -239,8 +239,11 @@ genX(blorp_exec)(struct blorp_batch *batch,
 */
if (params->src.enabled)
   brw_cache_flush_for_read(brw, params->src.addr.buffer);
-   if (params->dst.enabled)
-  brw_cache_flush_for_render(brw, params->dst.addr.buffer);
+   if (params->dst.enabled) {
+  brw_cache_flush_for_render(brw, params->dst.addr.buffer,
+ params->dst.view.format,
+ params->dst.aux_usage);
+   }
if (params->depth.enabled)
   brw_cache_flush_for_depth(brw, params->depth.addr.buffer);
if (params->stencil.enabled)
@@ -310,8 +313,11 @@ retry:
   !params->stencil.enabled;
brw->ib.index_size = -1;
 
-   if (params->dst.enabled)
-  brw_render_cache_add_bo(brw, params->dst.addr.buffer);
+   if (params->dst.enabled) {
+  brw_render_cache_add_bo(brw, params->dst.addr.buffer,
+  params->dst.view.format,
+  params->dst.aux_usage);
+   }
if (params->depth.enabled)
   brw_depth_cache_add_bo(brw, params->depth.addr.buffer);
if (params->stencil.enabled)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
b/src/mesa/drivers/dri/i965/intel_fbo.c
index 75c85ec..ea17577 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -972,14 +972,13 @@ intel_renderbuffer_move_to_temp(struct brw_context 

[Mesa-dev] [PATCH 1/3] i965: Call brw_cache_flush_for_render in predraw_resolve_framebuffer

[Jason Ekstrand]

This makes sure we flush things out such as depth writes prior to using
a surface through the render cache.  Besides the overhead of a hash
table look-up, this function is harmless to call repeatedly with the
same arguments.

Cc: "17.3" 
---
 src/mesa/drivers/dri/i965/brw_draw.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 7e29dcf..1f86378 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -508,6 +508,8 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw)
irb->mt_layer, irb->layer_count,
isl_format,
ctx->Color.BlendEnabled & (1 << i));
+
+  brw_cache_flush_for_render(brw, irb->mt->bo);
}
 }
 
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH 11/29] anv/cmd_buffer: Add a mark_image_written helper

[Nanley Chery]

On Mon, Nov 27, 2017 at 07:06:01PM -0800, Jason Ekstrand wrote:
> Currently, this helper does nothing but we call it every place where an
> image is written through the render pipeline.  This will allow us to
> properly mark the aux state so that we can handle resolves correctly.
> ---
>  src/intel/vulkan/anv_blorp.c   | 36 
>  src/intel/vulkan/anv_cmd_buffer.c  | 12 
>  src/intel/vulkan/anv_genX.h|  6 ++
>  src/intel/vulkan/anv_private.h |  7 +++
>  src/intel/vulkan/genX_cmd_buffer.c | 17 +
>  5 files changed, 78 insertions(+)
> 
> diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> index da273d6..46e2eb0 100644
> --- a/src/intel/vulkan/anv_blorp.c
> +++ b/src/intel/vulkan/anv_blorp.c
> @@ -271,6 +271,7 @@ void anv_CmdCopyImage(
>  
>assert(anv_image_aspects_compatible(src_mask, dst_mask));
>  
> +  const uint32_t dst_level = pRegions[r].dstSubresource.mipLevel;
>if (_mesa_bitcount(src_mask) > 1) {
>   uint32_t aspect_bit;
>   anv_foreach_image_aspect_bit(aspect_bit, src_image, src_mask) {
> @@ -281,6 +282,10 @@ void anv_CmdCopyImage(
>  get_blorp_surf_for_anv_image(cmd_buffer->device,
>   dst_image, 1UL << aspect_bit,
>   ANV_AUX_USAGE_DEFAULT, _surf);
> +anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image,
> +  1UL << aspect_bit,
> +  dst_surf.aux_usage,
> +  dst_level);
>  
>  for (unsigned i = 0; i < layer_count; i++) {
> blorp_copy(, _surf, 
> pRegions[r].srcSubresource.mipLevel,
> @@ -298,6 +303,8 @@ void anv_CmdCopyImage(
>ANV_AUX_USAGE_DEFAULT, _surf);
>   get_blorp_surf_for_anv_image(cmd_buffer->device, dst_image, 
> dst_mask,
>ANV_AUX_USAGE_DEFAULT, _surf);
> + anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image, dst_mask,
> +   dst_surf.aux_usage, dst_level);
>  
>   for (unsigned i = 0; i < layer_count; i++) {
>  blorp_copy(, _surf, 
> pRegions[r].srcSubresource.mipLevel,
> @@ -387,6 +394,12 @@ copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
>  extent.width, extent.height,
>  buffer_row_pitch, buffer_format,
>  , _isl_surf);
> +  if (dst->surf.aux_usage != ISL_AUX_USAGE_NONE) {
> + assert(dst == );
> + anv_cmd_buffer_mark_image_written(cmd_buffer, anv_image,
> +   aspect, dst->surf.aux_usage,
> +   dst->level);
> +  }
>  
>for (unsigned z = 0; z < extent.depth; z++) {
>   blorp_copy(, >surf, src->level, src->offset.z,
> @@ -497,6 +510,10 @@ void anv_CmdBlitImage(
>get_blorp_surf_for_anv_image(cmd_buffer->device,
> dst_image, dst_res->aspectMask,
> ANV_AUX_USAGE_DEFAULT, );
> +  anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image,
> +dst_res->aspectMask,
> +dst.aux_usage,
> +dst_res->mipLevel);
>  
>struct anv_format_plane src_format =
>   anv_get_format_plane(_buffer->device->info, 
> src_image->vk_format,
> @@ -820,6 +837,10 @@ void anv_CmdClearColorImage(
>  layer_count = anv_minify(image->extent.depth, level);
>   }
>  
> + anv_cmd_buffer_mark_image_written(cmd_buffer, image,
> +   pRanges[r].aspectMask,
> +   surf.aux_usage, level);
> +
>   blorp_clear(, ,
>   src_format.isl_format, src_format.swizzle,
>   level, base_layer, layer_count,
> @@ -1215,6 +1236,11 @@ anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer 
> *cmd_buffer)
>  ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
>} else {
>   assert(image->n_planes == 1);
> + anv_cmd_buffer_mark_image_written(cmd_buffer, image,
> +   VK_IMAGE_ASPECT_COLOR_BIT,
> +   att_state->aux_usage,
> +   iview->planes[0].isl.base_level);
> +
>   blorp_clear(, , iview->planes[0].isl.format,
>   anv_swizzle_for_render(iview->planes[0].isl.swizzle),
>   iview->planes[0].isl.base_level,
> @@ -1355,6 +1381,8 @@ resolve_image(struct anv_device *device,
>

[Mesa-dev] [Bug 103852] Rendering errors when running dolphin-emu with Vulkan backend, radv (Super Smash Bros. Melee)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103852

Ben Clapp  changed:

   What|Removed |Added

Version|17.2|17.3

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[Mesa-dev] [Bug 103852] Rendering errors when running dolphin-emu with Vulkan backend, radv (Super Smash Bros. Melee)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103852

--- Comment #1 from Ben Clapp  ---
I've done some testing with mesa 17.3.0 on my computer with the RX 580 (using
the mesa 17.3.0-1 package available in debian unstable).
All of the previously mentioned bugs are still present on 17.3.0, so I'm
updating the version number for this ticket to 17.3 as well.

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[Mesa-dev] [PATCH] st/glsl_to_nir: add patch support to st_nir_assign_var_locations()

[Timothy Arceri]

---
 src/mesa/state_tracker/st_glsl_to_nir.cpp | 22 +-
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 70c5daaa225..be34031bfb5 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -119,46 +119,58 @@ st_nir_assign_vs_in_locations(struct gl_program *prog, 
nir_shader *nir)
  exec_list_push_tail(>globals, >node);
   }
}
 }
 
 static void
 st_nir_assign_var_locations(struct exec_list *var_list, unsigned *size,
 gl_shader_stage stage)
 {
unsigned location = 0;
-   unsigned assigned_locations[VARYING_SLOT_MAX];
+   unsigned assigned_locations[VARYING_SLOT_TESS_MAX];
uint64_t processed_locs = 0;
+   uint32_t processed_patch_locs = 0;
 
nir_foreach_variable(var, var_list) {
 
   const struct glsl_type *type = var->type;
   if (nir_is_per_vertex_io(var, stage)) {
  assert(glsl_type_is_array(type));
  type = glsl_get_array_element(type);
   }
 
+  bool processed = false;
+  if (var->data.patch) {
+ unsigned patch_loc = var->data.location - VARYING_SLOT_VAR0;
+ if (processed_patch_locs & (1 << patch_loc))
+processed = true;
+
+ processed_patch_locs |= (1 << patch_loc);
+  } else {
+ if (processed_locs & ((uint64_t)1 << var->data.location))
+processed = true;
+
+ processed_locs |= ((uint64_t)1 << var->data.location);
+  }
+
   /* Because component packing allows varyings to share the same location
* we may have already have processed this location.
*/
-  if (var->data.location >= VARYING_SLOT_VAR0 &&
-  processed_locs & ((uint64_t)1 << var->data.location)) {
+  if (processed && var->data.location >= VARYING_SLOT_VAR0) {
  var->data.driver_location = assigned_locations[var->data.location];
  *size += type_size(type);
  continue;
   }
 
   assigned_locations[var->data.location] = location;
   var->data.driver_location = location;
   location += type_size(type);
-
-  processed_locs |= ((uint64_t)1 << var->data.location);
}
 
*size += location;
 }
 
 static int
 st_nir_lookup_parameter_index(const struct gl_program_parameter_list *params,
   const char *name)
 {
int loc = _mesa_lookup_parameter_index(params, name);
-- 
2.14.3

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[Mesa-dev] [Bug 104251] st_update_single_texture: Assertion `texObj' failed.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104251

Bug ID: 104251
   Summary: st_update_single_texture: Assertion `texObj' failed.
   Product: Mesa
   Version: 17.3
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Mesa core
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: farmboy0+freedesk...@googlemail.com
QA Contact: mesa-dev@lists.freedesktop.org

KoTOR 1 on wine crashes with the following error when starting a new game:

/tmp/portage/media-libs/mesa-17.3.0/work/mesa-17.3.0/src/mesa/state_tracker/st_atom_texture.c:72:
st_update_single_texture: Assertion `texObj' failed.
wine: Assertion failed at address 0xf7f5fb19 (thread 0009), starting
debugger...

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Re: [Mesa-dev] [PATCH v2 3/4] meson: build clover

[Jan Vesely]

On Wed, 2017-12-13 at 17:23 -0500, Jan Vesely wrote:
> On Wed, 2017-12-13 at 13:54 -0800, Dylan Baker wrote:
> > Quoting Jan Vesely (2017-12-13 12:53:25)
> > > On Wed, 2017-12-13 at 09:47 -0800, Dylan Baker wrote:
> > > > +if (with_gallium_va or with_gallium_vdpau or with_gallium_omx or
> > > > +with_gallium_xvmc or with_dri)
> > > > +  pipe_loader_link_with += libgalliumvl
> > > > +else
> > > > +  pipe_loader_link_with += libgalliumvl_stubs
> > > > +endif
> > > > +if with_gallium_va or with_gallium_vdpau or with_gallium_omx or 
> > > > with_gallium_xvmc  
> > > 
> > > git am complains about whitespace errors at the end of the above line.
> > 
> > I can fix that.
> > 
> > > 
> > > I tested with:
> > > meson -Ddri-drivers= -Dgallium-drivers=r600 -Dopengl=true -Dplatforms=x11 
> > > -Dopencl=true
> > > 
> > > meson asked for libdrm_amdgpu dependency even though I'm only building 
> > > clover+r600g driver.
> > 
> > That's probably because you didn't add `-Dvulkan-drivers=`, since radv does 
> > depend
> > on libdrm_amdgpu. If you add that and still get a request for libdrm_amdgpu 
> > let
> > me know and I'll look into it further.
> 
> right, that fixes it. sorry for the noise.
> 
> > 
> > > after a bit of fiddling with PATH and PK_CONFIG_PATH to pick up the 
> > > latest llvm/liblclc
> > > linking failed with:
> > > src/gallium/auxiliary/libgallium.a(gallivm_lp_bld_misc.cpp.o):(.data.rel.ro._ZTI26DelegatingJITMemoryManager[_ZTI26DelegatingJITMemoryManager]+0x10):
> > >  undefined reference to `typeinfo for llvm::RTDyldMemoryManager'
> > > collect2: error: ld returned 1 exit status
> > > 
> > > this looks like it did not pick up the rtti setting from llvm-config:
> > > $ ~/.local/bin/llvm-config --has-rtti
> > > NO
> > > $ ~/.local/bin/llvm-config --cxxflags | grep -o fno-rtti
> > > fno-rtti
> > > 
> > > rtti setting is quite messy since clover uses dynamic_cast. I think it
> > > should be OK to only support rtti build of llvm if it's detected at
> > > configure time
> > > 
> > > it'd also be nice for meson to remember llvm-config location provided
> > > at configure time. otherwise I need to set PATH every time I run ninja
> > > in case it tries to reconfigure. I guess that's what "TODO llvm-prefix" 
> > > will achieve, right?
> > 
> > I'm not sure what the right way to solve this is, maybe to cache any 
> > relavent
> > environment variables between runs in meson itself, since pkg-config has the
> > same problem with PKG_CONFIG_PATH. ATM there is no way to implement the
> > llvm-prefix in meson the way it is in autotools.
> 
> would it be easier to explicitly set location of llvm-config and
> libclc.pc?
> currently it works OK with system packages,
> you can add Tested-by: Jan Vesely 
> 
> I'd need a way to permanently redirect the configuration to use local
> builds of both llvm and libclc to use meson as my daily driver.
> 
> >
> > 
> > > 
> > > in the end I got meson built clover to run (clinfo + simple demo) on my
> > > turks with these changes:
> > > * build and install libdrm_amdgpu -- should not be necessary for r600g
> > > only build
> > > * switch to distro (fedora) provided libclc and llvm -- avoids rtti
> > > build problem (note libclc is just tagging along llvm since my local
> > > builds install headers to the same location)
> > > * fiddle with pipe-loader dir, for some reason LIBGL_DRIVERS_PATH did
> > > not work when pointed to meson built pipe_r600.so. I'm not sure if this
> > > is meson specific, it might be just my ignorance.
> > 
> > I'm not certain, though Curro probably knows, but the dynamic pipeloader is
> > hard-coded to search $install/$libdir/gallium-pipe for pipe drivers, so you 
> > may
> > need to run ninja install to make it work. Alternatively LD_LIBRARY_PATH 
> > might
> > work as well.
> 
> I assumed that it was some loader configuration outside meson. the
> surprising part was that it tried to open cwd local paths:
> openat(AT_FDCWD, "lib64/gallium-pipe/pipe_r600.so", O_RDONLY|O_CLOEXEC) = -1 
> ENOENT (No such file or directory)
> 
> Is this expected without explicitly setting install prefix?
> 
> Jan

PS: I've also tested local builds of llvm and libclc (after rebuilding
with rtti) and -Dgallium-opencl=icd. it works as expected.

> 
> > 
> > Dylan


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Re: [Mesa-dev] [RFC libdrm 0/5] Move alloc_handle_t from gralloc impls.

[Gurchetan Singh]

Hi Robert,

Thanks for looking into this!  We need to decide if we want:

(1) A common struct that implementations can subclass, i.e:

struct blah_gralloc_handle {
alloc_handle_t alloc_handle;
int x, y, z;

}

(2) An accessor library that vendors can implement, i.e:

struct drmAndroidHandleInfo {
   uint32_t (*get_fourcc)(buffer_handle_t handle);
   uint32_t (*get_stride)(buffer_handle_t handle, uint32_t plane);
   uint32_t (*get_offsets)(buffer_handle_t handle, uint32_t plane);
   uint64_t (*get_modifier)(buffer_handle_t handle);
};

>From my perspective as someone who has to maintain the minigbm gralloc
implementation, (2) is preferable since:

a) We really don't have a need for fields like data_owner, void *data,
etc.  Also, minigbm puts per plane fds, strides, offsets into the handle.
Separating the information for the first plane (for the alloc_handle_t) and
then rest of the planes would be annoying.

b) we can avoid the struct within a struct that happens when we subclass,
since alignment/padding issues often pop up during
serialization/de-serialization.  Using __attribute__((aligned(xx))) is less
portable than maintaining a POD struct.

c) IMO creating the handle should be left to the gralloc implementation.
Having accessor functions clearly defines what we need from libdrm -- to
make up for shortcomings of the gralloc API for DRM/KMS use cases.


On Wed, Dec 13, 2017 at 9:30 AM, Robert Foss 
wrote:

> This series moves {gbm,drm,cros}_gralloc_handle_t struct to libdrm,
> since at least 4 implementations exist, and share a lot of contents.
> The idea is to keep the common stuff defined in one place, and libdrm
> is the common codebase to all of these platforms.
>
> Additionally, having this struct defined in libdrm will make it
> easier for mesa and grallocs to communicate.
>
> Curretly missing is:
>  - Planar formats
>  - Get/Set functions
>
>
> Planar formats
> --
> Support for planar formats is needed, but has not been added
> yet, mostly since this was not already implemented in {gbm,drm}_gralloc
> and the fact the having at least initial backwards compatability would
> be nice. Anonymous unions can of course be used later on to provide
> backwards compatability if so desired.
>
>
> Get/Set functions
> -
> During the previous discussion[1] one suggestion was to add accessor
> functions. In this RFC I've only provided a alloc_handle_create()
> function.
>
> The Get/Set functions have not been added yet, I was hoping for some
> conclusive arguments for them being adeded.
>
> Lastly it was suggested by Rob Herring that having a fourcc<->android
> pixel format conversion function would be useful.
>
>
> [1] https://lists.freedesktop.org/archives/mesa-dev/2017-
> November/178199.html
>
> Robert Foss (5):
>   android: Move gralloc handle struct to libdrm
>   android: Add version variable to alloc_handle_t
>   android: Mark alloc_handle_t magic variable as const
>   android: Remove member name from alloc_handle_t
>   android: Change alloc_handle_t format from Android format to fourcc
>
>  Android.mk   |  8 +++-
>  Makefile.sources |  3 ++
>  android/alloc_handle.h   | 87 ++
> ++
>  android/gralloc_drm_handle.h |  1 +
>  4 files changed, 97 insertions(+), 2 deletions(-)
>  create mode 100644 android/alloc_handle.h
>  create mode 12 android/gralloc_drm_handle.h
>
> --
> 2.14.1
>
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Re: [Mesa-dev] [PATCH v2 3/4] meson: build clover

[Dylan Baker]

Quoting Jan Vesely (2017-12-13 14:23:21)
> On Wed, 2017-12-13 at 13:54 -0800, Dylan Baker wrote:
> > Quoting Jan Vesely (2017-12-13 12:53:25)
> > > On Wed, 2017-12-13 at 09:47 -0800, Dylan Baker wrote:
> > > > +if (with_gallium_va or with_gallium_vdpau or with_gallium_omx or
> > > > +with_gallium_xvmc or with_dri)
> > > > +  pipe_loader_link_with += libgalliumvl
> > > > +else
> > > > +  pipe_loader_link_with += libgalliumvl_stubs
> > > > +endif
> > > > +if with_gallium_va or with_gallium_vdpau or with_gallium_omx or 
> > > > with_gallium_xvmc  
> > > 
> > > git am complains about whitespace errors at the end of the above line.
> > 
> > I can fix that.
> > 
> > > 
> > > I tested with:
> > > meson -Ddri-drivers= -Dgallium-drivers=r600 -Dopengl=true -Dplatforms=x11 
> > > -Dopencl=true
> > > 
> > > meson asked for libdrm_amdgpu dependency even though I'm only building 
> > > clover+r600g driver.
> > 
> > That's probably because you didn't add `-Dvulkan-drivers=`, since radv does 
> > depend
> > on libdrm_amdgpu. If you add that and still get a request for libdrm_amdgpu 
> > let
> > me know and I'll look into it further.
> 
> right, that fixes it. sorry for the noise.
> 
> > 
> > > after a bit of fiddling with PATH and PK_CONFIG_PATH to pick up the 
> > > latest llvm/liblclc
> > > linking failed with:
> > > src/gallium/auxiliary/libgallium.a(gallivm_lp_bld_misc.cpp.o):(.data.rel.ro._ZTI26DelegatingJITMemoryManager[_ZTI26DelegatingJITMemoryManager]+0x10):
> > >  undefined reference to `typeinfo for llvm::RTDyldMemoryManager'
> > > collect2: error: ld returned 1 exit status
> > > 
> > > this looks like it did not pick up the rtti setting from llvm-config:
> > > $ ~/.local/bin/llvm-config --has-rtti
> > > NO
> > > $ ~/.local/bin/llvm-config --cxxflags | grep -o fno-rtti
> > > fno-rtti
> > > 
> > > rtti setting is quite messy since clover uses dynamic_cast. I think it
> > > should be OK to only support rtti build of llvm if it's detected at
> > > configure time
> > > 
> > > it'd also be nice for meson to remember llvm-config location provided
> > > at configure time. otherwise I need to set PATH every time I run ninja
> > > in case it tries to reconfigure. I guess that's what "TODO llvm-prefix" 
> > > will achieve, right?
> > 
> > I'm not sure what the right way to solve this is, maybe to cache any 
> > relavent
> > environment variables between runs in meson itself, since pkg-config has the
> > same problem with PKG_CONFIG_PATH. ATM there is no way to implement the
> > llvm-prefix in meson the way it is in autotools.
> 
> would it be easier to explicitly set location of llvm-config and
> libclc.pc?
> currently it works OK with system packages,
> you can add Tested-by: Jan Vesely 
> 
> I'd need a way to permanently redirect the configuration to use local
> builds of both llvm and libclc to use meson as my daily driver.
> 
> >
> > 
> > > 
> > > in the end I got meson built clover to run (clinfo + simple demo) on my
> > > turks with these changes:
> > > * build and install libdrm_amdgpu -- should not be necessary for r600g
> > > only build
> > > * switch to distro (fedora) provided libclc and llvm -- avoids rtti
> > > build problem (note libclc is just tagging along llvm since my local
> > > builds install headers to the same location)
> > > * fiddle with pipe-loader dir, for some reason LIBGL_DRIVERS_PATH did
> > > not work when pointed to meson built pipe_r600.so. I'm not sure if this
> > > is meson specific, it might be just my ignorance.
> > 
> > I'm not certain, though Curro probably knows, but the dynamic pipeloader is
> > hard-coded to search $install/$libdir/gallium-pipe for pipe drivers, so you 
> > may
> > need to run ninja install to make it work. Alternatively LD_LIBRARY_PATH 
> > might
> > work as well.
> 
> I assumed that it was some loader configuration outside meson. the
> surprising part was that it tried to open cwd local paths:
> openat(AT_FDCWD, "lib64/gallium-pipe/pipe_r600.so", O_RDONLY|O_CLOEXEC) = -1 
> ENOENT (No such file or directory)
> 
> Is this expected without explicitly setting install prefix?
> 
> Jan

If you don't set a prefix you'll get the system default, for fedora (because of
the merged /usr) that's /. Does it work with autotools without install? I can't
image it would. But dynamic library loading in C is hardly my domain of
expertise so I could be totally wrong :)

Dylan


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Re: [Mesa-dev] [PATCH v2 3/4] meson: build clover

[Jan Vesely]

On Wed, 2017-12-13 at 13:54 -0800, Dylan Baker wrote:
> Quoting Jan Vesely (2017-12-13 12:53:25)
> > On Wed, 2017-12-13 at 09:47 -0800, Dylan Baker wrote:
> > > +if (with_gallium_va or with_gallium_vdpau or with_gallium_omx or
> > > +with_gallium_xvmc or with_dri)
> > > +  pipe_loader_link_with += libgalliumvl
> > > +else
> > > +  pipe_loader_link_with += libgalliumvl_stubs
> > > +endif
> > > +if with_gallium_va or with_gallium_vdpau or with_gallium_omx or 
> > > with_gallium_xvmc  
> > 
> > git am complains about whitespace errors at the end of the above line.
> 
> I can fix that.
> 
> > 
> > I tested with:
> > meson -Ddri-drivers= -Dgallium-drivers=r600 -Dopengl=true -Dplatforms=x11 
> > -Dopencl=true
> > 
> > meson asked for libdrm_amdgpu dependency even though I'm only building 
> > clover+r600g driver.
> 
> That's probably because you didn't add `-Dvulkan-drivers=`, since radv does 
> depend
> on libdrm_amdgpu. If you add that and still get a request for libdrm_amdgpu 
> let
> me know and I'll look into it further.

right, that fixes it. sorry for the noise.

> 
> > after a bit of fiddling with PATH and PK_CONFIG_PATH to pick up the latest 
> > llvm/liblclc
> > linking failed with:
> > src/gallium/auxiliary/libgallium.a(gallivm_lp_bld_misc.cpp.o):(.data.rel.ro._ZTI26DelegatingJITMemoryManager[_ZTI26DelegatingJITMemoryManager]+0x10):
> >  undefined reference to `typeinfo for llvm::RTDyldMemoryManager'
> > collect2: error: ld returned 1 exit status
> > 
> > this looks like it did not pick up the rtti setting from llvm-config:
> > $ ~/.local/bin/llvm-config --has-rtti
> > NO
> > $ ~/.local/bin/llvm-config --cxxflags | grep -o fno-rtti
> > fno-rtti
> > 
> > rtti setting is quite messy since clover uses dynamic_cast. I think it
> > should be OK to only support rtti build of llvm if it's detected at
> > configure time
> > 
> > it'd also be nice for meson to remember llvm-config location provided
> > at configure time. otherwise I need to set PATH every time I run ninja
> > in case it tries to reconfigure. I guess that's what "TODO llvm-prefix" 
> > will achieve, right?
> 
> I'm not sure what the right way to solve this is, maybe to cache any relavent
> environment variables between runs in meson itself, since pkg-config has the
> same problem with PKG_CONFIG_PATH. ATM there is no way to implement the
> llvm-prefix in meson the way it is in autotools.

would it be easier to explicitly set location of llvm-config and
libclc.pc?
currently it works OK with system packages,
you can add Tested-by: Jan Vesely 

I'd need a way to permanently redirect the configuration to use local
builds of both llvm and libclc to use meson as my daily driver.

>
> 
> > 
> > in the end I got meson built clover to run (clinfo + simple demo) on my
> > turks with these changes:
> > * build and install libdrm_amdgpu -- should not be necessary for r600g
> > only build
> > * switch to distro (fedora) provided libclc and llvm -- avoids rtti
> > build problem (note libclc is just tagging along llvm since my local
> > builds install headers to the same location)
> > * fiddle with pipe-loader dir, for some reason LIBGL_DRIVERS_PATH did
> > not work when pointed to meson built pipe_r600.so. I'm not sure if this
> > is meson specific, it might be just my ignorance.
> 
> I'm not certain, though Curro probably knows, but the dynamic pipeloader is
> hard-coded to search $install/$libdir/gallium-pipe for pipe drivers, so you 
> may
> need to run ninja install to make it work. Alternatively LD_LIBRARY_PATH might
> work as well.

I assumed that it was some loader configuration outside meson. the
surprising part was that it tried to open cwd local paths:
openat(AT_FDCWD, "lib64/gallium-pipe/pipe_r600.so", O_RDONLY|O_CLOEXEC) = -1 
ENOENT (No such file or directory)

Is this expected without explicitly setting install prefix?

Jan

> 
> Dylan


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Re: [Mesa-dev] [PATCH] meson: warn if building a non-debug build with asserts

[Dylan Baker]

Quoting Eric Engestrom (2017-12-13 13:43:24)
> On Wednesday, 2017-12-13 10:33:05 -0800, Dylan Baker wrote:
> > cc: Jason Ekstrand 
> > Signed-off-by: Dylan Baker 
> > ---
> >  meson.build | 9 +
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/meson.build b/meson.build
> > index 6e5ae4d24e9..b00c1ffc3dc 100644
> > --- a/meson.build
> > +++ b/meson.build
> > @@ -29,6 +29,15 @@ project(
> >default_options : ['buildtype=debugoptimized', 'c_std=c99', 
> > 'cpp_std=c++11']
> >  )
> >  
> > +if not get_option('b_ndebug') and not 
> > get_option('buildtype').startswith('debug')
> > +  _warn = 'Building a release or plain type build with asserts enabled. 
> > You probably also want to set -Dn_debug=true'
> > +  if meson.version().version_compare('< 0.44')
> > +message(_warn)
> > +  else
> > +warning(_warn)
> 
> A bit surprised this compiles on old meson versions (I guess you weren't
> lying when you said the parser was lazy ^^), but adding a warning for
> this is a good idea given the spread of the confusion that was revealed
> a little while ago.
> 
> Acked-by: Eric Engestrom 

Thanks! You basically need the parser to not evaluate paths it's not taking in
an interpreted language since you don't have a preprocessor to remove code that
an older interpreter doesn't understand. Python, for example, behaves the same
way.

Dylan


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Re: [Mesa-dev] [PATCH v2 3/4] meson: build clover

[Dylan Baker]

Quoting Jan Vesely (2017-12-13 13:36:25)
> On Wed, 2017-12-13 at 13:01 -0800, Francisco Jerez wrote:
> > Jan Vesely  writes:
> > 
> 
> autotools build works OK with no-rtti build of llvm, I've been running
> like that for some time. LLVM_CXXFLAGS which include fno-rtti are only
> used to build libclllvm.la, so it probably only works by accident.
> 
> fedora ships rtti enabled llvm, I'm not sure what other distros ship.
> 
> It opens up the question whether any flags from llvm-config --cxxflags
> should be used and whether meson needs an equivalent of
> "strip_unwanted_llvm_flags()"
> 
> Jan
> 

Meson only takes --cppflags from llvm-config (except -DNDEBUG), because frankly
LLVM puts garbage in llvm-config's --cflags and --cxxflags.

Dylan


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Re: [Mesa-dev] [PATCH v2 3/4] meson: build clover

[Francisco Jerez]

Dylan Baker  writes:

> Quoting Francisco Jerez (2017-12-13 13:01:29)
>> Jan Vesely  writes:
>> > meson asked for libdrm_amdgpu dependency even though I'm only building 
>> > clover+r600g driver.
>> > after a bit of fiddling with PATH and PK_CONFIG_PATH to pick up the latest 
>> > llvm/liblclc
>> > linking failed with:
>> > src/gallium/auxiliary/libgallium.a(gallivm_lp_bld_misc.cpp.o):(.data.rel.ro._ZTI26DelegatingJITMemoryManager[_ZTI26DelegatingJITMemoryManager]+0x10):
>> >  undefined reference to `typeinfo for llvm::RTDyldMemoryManager'
>> > collect2: error: ld returned 1 exit status
>> >
>> > this looks like it did not pick up the rtti setting from llvm-config:
>> > $ ~/.local/bin/llvm-config --has-rtti
>> > NO
>> > $ ~/.local/bin/llvm-config --cxxflags | grep -o fno-rtti
>> > fno-rtti
>> >
>> > rtti setting is quite messy since clover uses dynamic_cast. I think it
>> > should be OK to only support rtti build of llvm if it's detected at
>> > configure time
>> 
>> Is that any different with autotools?  Clover is not meant to link
>> against an -fno-rtti LLVM, because an LLVM library built in such a way
>> has a non-standard C++ ABI.  Picking up the -fno-rtti flag from
>> llvm-config is not guaranteed to fix anything.  Attempting to do so
>> should probably lead to a build error at configure time...
>
> I can add some logic to detect `-fno-rtti` and error out if you think that's 
> the
> right thing to do.

That would be great, but I wouldn't set it as a requirement for the
meson build, since the autotools build system is lacking the same
feature ;)


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Re: [Mesa-dev] [PATCH v2 3/4] meson: build clover

[Dylan Baker]

Quoting Francisco Jerez (2017-12-13 13:01:29)
> Jan Vesely  writes:
> > meson asked for libdrm_amdgpu dependency even though I'm only building 
> > clover+r600g driver.
> > after a bit of fiddling with PATH and PK_CONFIG_PATH to pick up the latest 
> > llvm/liblclc
> > linking failed with:
> > src/gallium/auxiliary/libgallium.a(gallivm_lp_bld_misc.cpp.o):(.data.rel.ro._ZTI26DelegatingJITMemoryManager[_ZTI26DelegatingJITMemoryManager]+0x10):
> >  undefined reference to `typeinfo for llvm::RTDyldMemoryManager'
> > collect2: error: ld returned 1 exit status
> >
> > this looks like it did not pick up the rtti setting from llvm-config:
> > $ ~/.local/bin/llvm-config --has-rtti
> > NO
> > $ ~/.local/bin/llvm-config --cxxflags | grep -o fno-rtti
> > fno-rtti
> >
> > rtti setting is quite messy since clover uses dynamic_cast. I think it
> > should be OK to only support rtti build of llvm if it's detected at
> > configure time
> 
> Is that any different with autotools?  Clover is not meant to link
> against an -fno-rtti LLVM, because an LLVM library built in such a way
> has a non-standard C++ ABI.  Picking up the -fno-rtti flag from
> llvm-config is not guaranteed to fix anything.  Attempting to do so
> should probably lead to a build error at configure time...

I can add some logic to detect `-fno-rtti` and error out if you think that's the
right thing to do.


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Re: [Mesa-dev] [PATCH v2 3/4] meson: build clover

[Dylan Baker]

Quoting Jan Vesely (2017-12-13 12:53:25)
> On Wed, 2017-12-13 at 09:47 -0800, Dylan Baker wrote:
> > +if (with_gallium_va or with_gallium_vdpau or with_gallium_omx or
> > +with_gallium_xvmc or with_dri)
> > +  pipe_loader_link_with += libgalliumvl
> > +else
> > +  pipe_loader_link_with += libgalliumvl_stubs
> > +endif
> > +if with_gallium_va or with_gallium_vdpau or with_gallium_omx or 
> > with_gallium_xvmc  
> 
> git am complains about whitespace errors at the end of the above line.

I can fix that.

> 
> I tested with:
> meson -Ddri-drivers= -Dgallium-drivers=r600 -Dopengl=true -Dplatforms=x11 
> -Dopencl=true
> 
> meson asked for libdrm_amdgpu dependency even though I'm only building 
> clover+r600g driver.

That's probably because you didn't add `-Dvulkan-drivers=`, since radv does 
depend
on libdrm_amdgpu. If you add that and still get a request for libdrm_amdgpu let
me know and I'll look into it further.

> after a bit of fiddling with PATH and PK_CONFIG_PATH to pick up the latest 
> llvm/liblclc
> linking failed with:
> src/gallium/auxiliary/libgallium.a(gallivm_lp_bld_misc.cpp.o):(.data.rel.ro._ZTI26DelegatingJITMemoryManager[_ZTI26DelegatingJITMemoryManager]+0x10):
>  undefined reference to `typeinfo for llvm::RTDyldMemoryManager'
> collect2: error: ld returned 1 exit status
> 
> this looks like it did not pick up the rtti setting from llvm-config:
> $ ~/.local/bin/llvm-config --has-rtti
> NO
> $ ~/.local/bin/llvm-config --cxxflags | grep -o fno-rtti
> fno-rtti
> 
> rtti setting is quite messy since clover uses dynamic_cast. I think it
> should be OK to only support rtti build of llvm if it's detected at
> configure time
> 
> it'd also be nice for meson to remember llvm-config location provided
> at configure time. otherwise I need to set PATH every time I run ninja
> in case it tries to reconfigure. I guess that's what "TODO llvm-prefix" 
> will achieve, right?

I'm not sure what the right way to solve this is, maybe to cache any relavent
environment variables between runs in meson itself, since pkg-config has the
same problem with PKG_CONFIG_PATH. ATM there is no way to implement the
llvm-prefix in meson the way it is in autotools.

> 
> in the end I got meson built clover to run (clinfo + simple demo) on my
> turks with these changes:
> * build and install libdrm_amdgpu -- should not be necessary for r600g
> only build
> * switch to distro (fedora) provided libclc and llvm -- avoids rtti
> build problem (note libclc is just tagging along llvm since my local
> builds install headers to the same location)
> * fiddle with pipe-loader dir, for some reason LIBGL_DRIVERS_PATH did
> not work when pointed to meson built pipe_r600.so. I'm not sure if this
> is meson specific, it might be just my ignorance.

I'm not certain, though Curro probably knows, but the dynamic pipeloader is
hard-coded to search $install/$libdir/gallium-pipe for pipe drivers, so you may
need to run ninja install to make it work. Alternatively LD_LIBRARY_PATH might
work as well.

Dylan


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Re: [Mesa-dev] [PATCH] i965: Don't allocate an MCS for 16x MSAA and width > 8192.

[Jason Ekstrand]

On Wed, Dec 13, 2017 at 12:25 PM, Kenneth Graunke 
wrote:

> The hardware doesn't support this, and isl_surf_get_mcs_surf will fail.
>
> I feel a bit bad replicating this logic, but we want to decide up front.
>

I do too.  One of these days, I'd like to move things around so that we
just call isl_surf_get_mcs_surf and disable MCS if it fails.  But that's a
lot of refactoring.

Reviewed-by: Jason Ekstrand 


> This fixes the following test when run with --deqp-surface-width=16384:
> - GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_
> blit_error_blitframebuffer_multisampled_framebuffers_
> different_sample_count
>
> Cc: ito...@igalia.com
> Cc: apuen...@igalia.com
> Cc: i...@freedesktop.org
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index c1a4ce184f5..ead0c359c0f 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -73,6 +73,10 @@ intel_miptree_supports_mcs(struct brw_context *brw,
> if (devinfo->gen < 7)
>return false;
>
> +   /* See isl_surf_get_mcs_surf for details. */
> +   if (mt->surf.samples == 16 && mt->surf.logical_level0_px.width > 8192)
> +  return false;
> +
> /* In Gen7, IMS layout is only used for depth and stencil buffers. */
> switch (_mesa_get_format_base_format(mt->format)) {
> case GL_DEPTH_COMPONENT:
> --
> 2.15.1
>
>
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Re: [Mesa-dev] [PATCH] Android: fix missing generation of vtn_gather_types.c

[Jason Ekstrand]

Rb


On Wed, Dec 13, 2017 at 1:08 PM, Rob Herring  wrote:

> Commit bb1e6ff161c9 ("spirv: Add a prepass to set types on vtn_values")
> added generation of vtn_gather_types.c, but forgot to add it to the
> Android build files.
>
> Fixes: bb1e6ff161c9 ("spirv: Add a prepass to set types on vtn_values")
> Cc: Jason Ekstrand 
> Signed-off-by: Rob Herring 
> ---
>  src/compiler/Android.nir.gen.mk | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/src/compiler/Android.nir.gen.mk b/src/compiler/Android.nir.
> gen.mk
> index e2187d081df8..aaa27128b41a 100644
> --- a/src/compiler/Android.nir.gen.mk
> +++ b/src/compiler/Android.nir.gen.mk
> @@ -98,3 +98,8 @@ $(intermediates)/nir/nir_opt_algebraic.c:
> $(nir_opt_algebraic_deps)
>  $(intermediates)/spirv/spirv_info.c: $(LOCAL_PATH)/spirv/spirv_info_c.py
> $(LOCAL_PATH)/spirv/spirv.core.grammar.json
> @mkdir -p $(dir $@)
> $(hide) $(MESA_PYTHON2) $^ $@ || ($(RM) $@; false)
> +
> +$(intermediates)/spirv/vtn_gather_types.c:: 
> $(LOCAL_PATH)/spirv/vtn_gather_types_c.py
> $(LOCAL_PATH)/spirv/spirv.core.grammar.json
> +   @mkdir -p $(dir $@)
> +   $(hide) $(MESA_PYTHON2) $^ $@ || ($(RM) $@; false)
> +
> --
> 2.14.1
>
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Re: [Mesa-dev] [PATCH] meson: warn if building a non-debug build with asserts

[Eric Engestrom]

On Wednesday, 2017-12-13 10:33:05 -0800, Dylan Baker wrote:
> cc: Jason Ekstrand 
> Signed-off-by: Dylan Baker 
> ---
>  meson.build | 9 +
>  1 file changed, 9 insertions(+)
> 
> diff --git a/meson.build b/meson.build
> index 6e5ae4d24e9..b00c1ffc3dc 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -29,6 +29,15 @@ project(
>default_options : ['buildtype=debugoptimized', 'c_std=c99', 
> 'cpp_std=c++11']
>  )
>  
> +if not get_option('b_ndebug') and not 
> get_option('buildtype').startswith('debug')
> +  _warn = 'Building a release or plain type build with asserts enabled. You 
> probably also want to set -Dn_debug=true'
> +  if meson.version().version_compare('< 0.44')
> +message(_warn)
> +  else
> +warning(_warn)

A bit surprised this compiles on old meson versions (I guess you weren't
lying when you said the parser was lazy ^^), but adding a warning for
this is a good idea given the spread of the confusion that was revealed
a little while ago.

Acked-by: Eric Engestrom 

> +  endif
> +endif
> +
>  # Arguments for the preprocessor, put these in a separate array from the C 
> and
>  # C++ (cpp in meson terminology) arguments since they need to be added to the
>  # default arguments for both C and C++.
> -- 
> 2.15.1
> 
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Re: [Mesa-dev] [PATCH v2 3/4] meson: build clover

[Francisco Jerez]

Jan Vesely  writes:

> On Wed, 2017-12-13 at 13:01 -0800, Francisco Jerez wrote:
>> Jan Vesely  writes:
>> 
>> > On Wed, 2017-12-13 at 09:47 -0800, Dylan Baker wrote:
>> > > This has only been compile tested.
>> > > 
>> > > v2: - Have a single option for opencl (Eric E)
>> > > - fix typo "tgis" -> "tgsi" (Curro)
>> > > - Don't add "lib" prefix to pipe loader libraries, which matches the
>> > >   autotools behavior
>> > > 
>> > > cc: Curro Jerez 
>> > > cc: Jan Vesely 
>> > > cc: Aaron Watry 
>> > > Signed-off-by: Dylan Baker 
>> > > ---
>> > > 
>> > > Jan and Aaron (or whoever decides to test this):
>> > > 
>> > > I think this should address the issues raised so far, so maybe this is
>> > > better for testing?
>> > > 
>> > >  include/meson.build   |  19 
>> > >  meson.build   |  29 +-
>> > >  meson_options.txt |   7 ++
>> > >  src/gallium/meson.build   |  12 ++-
>> > >  src/gallium/state_trackers/clover/meson.build | 122 
>> > > ++
>> > >  src/gallium/targets/opencl/meson.build|  73 +++
>> > >  src/gallium/targets/pipe-loader/meson.build   |  77 
>> > >  7 files changed, 334 insertions(+), 5 deletions(-)
>> > >  create mode 100644 src/gallium/state_trackers/clover/meson.build
>> > >  create mode 100644 src/gallium/targets/opencl/meson.build
>> > >  create mode 100644 src/gallium/targets/pipe-loader/meson.build
>> > > 
>> > > diff --git a/include/meson.build b/include/meson.build
>> > > index e4dae91cede..a2e7ce6580e 100644
>> > > --- a/include/meson.build
>> > > +++ b/include/meson.build
>> > > @@ -78,3 +78,22 @@ if with_gallium_st_nine
>> > >  subdir : 'd3dadapter',
>> > >)
>> > >  endif
>> > > +
>> > > +# Only install the headers if we are building a stand alone 
>> > > implementation and
>> > > +# not an ICD enabled implementation
>> > > +if with_gallium_opencl and not with_opencl_icd
>> > > +  install_headers(
>> > > +'CL/cl.h',
>> > > +'CL/cl.hpp',
>> > > +'CL/cl_d3d10.h',
>> > > +'CL/cl_d3d11.h',
>> > > +'CL/cl_dx9_media_sharing.h',
>> > > +'CL/cl_egl.h',
>> > > +'CL/cl_ext.h',
>> > > +'CL/cl_gl.h',
>> > > +'CL/cl_gl_ext.h',
>> > > +'CL/cl_platform.h',
>> > > +'CL/opencl.h',
>> > > +subdir: 'CL'
>> > > +  )
>> > > +endif
>> > > diff --git a/meson.build b/meson.build
>> > > index 842d441199e..74b2d5c49dc 100644
>> > > --- a/meson.build
>> > > +++ b/meson.build
>> > > @@ -583,6 +583,22 @@ if with_gallium_st_nine
>> > >endif
>> > >  endif
>> > >  
>> > > +_opencl = get_option('gallium-opencl')
>> > > +if _opencl !=' disabled'
>> > > +  if not with_gallium
>> > > +error('OpenCL Clover implementation requires at least one gallium 
>> > > driver.')
>> > > +  endif
>> > > +
>> > > +  # TODO: alitvec?
>> > > +  dep_clc = dependency('libclc')
>> > > +  with_gallium_opencl = true
>> > > +  with_opencl_icd = _opencl == 'icd'
>> > > +else
>> > > +  dep_clc = []
>> > > +  with_gallium_opencl = false
>> > > +  with_gallium_icd = false
>> > > +endif
>> > > +
>> > >  gl_pkgconfig_c_flags = []
>> > >  if with_platform_x11
>> > >if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
>> > > @@ -930,7 +946,7 @@ dep_thread = dependency('threads')
>> > >  if dep_thread.found() and host_machine.system() != 'windows'
>> > >pre_args += '-DHAVE_PTHREAD'
>> > >  endif
>> > > -if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 # TODO: 
>> > > clover
>> > > +if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 or 
>> > > with_gallium_opencl
>> > >dep_elf = dependency('libelf', required : false)
>> > >if not dep_elf.found()
>> > >  dep_elf = cc.find_library('elf')
>> > > @@ -972,12 +988,19 @@ if with_amd_vk or with_gallium_radeonsi or 
>> > > with_gallium_r600
>> > >  llvm_modules += 'asmparser'
>> > >endif
>> > >  endif
>> > > +if with_gallium_opencl
>> > > +  llvm_modules += [
>> > > +'all-targets', 'linker', 'coverage', 'instrumentation', 'ipo', 
>> > > 'irreader',
>> > > +'lto', 'option', 'objcarcopts', 'profiledata',
>> > > +  ]
>> > > +  # TODO: optional modules
>> > > +endif
>> > >  
>> > >  _llvm = get_option('llvm')
>> > >  if _llvm == 'auto'
>> > >dep_llvm = dependency(
>> > >  'llvm', version : '>= 3.9.0', modules : llvm_modules,
>> > > -required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr,
>> > > +required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr 
>> > > or with_gallium_opencl,
>> > >)
>> > >with_llvm = dep_llvm.found()
>> > >  elif _llvm == 'true'
>> > > @@ -1154,8 +1177,6 @@ else
>> > >dep_lmsensors = []
>> > >  endif
>> > >  
>> > > -# TODO: clover
>> > > -
>> > >  # TODO: gallium tests
>> > >  
>> > >  # 

Re: [Mesa-dev] [PATCH v2 3/4] meson: build clover

[Jan Vesely]

On Wed, 2017-12-13 at 13:01 -0800, Francisco Jerez wrote:
> Jan Vesely  writes:
> 
> > On Wed, 2017-12-13 at 09:47 -0800, Dylan Baker wrote:
> > > This has only been compile tested.
> > > 
> > > v2: - Have a single option for opencl (Eric E)
> > > - fix typo "tgis" -> "tgsi" (Curro)
> > > - Don't add "lib" prefix to pipe loader libraries, which matches the
> > >   autotools behavior
> > > 
> > > cc: Curro Jerez 
> > > cc: Jan Vesely 
> > > cc: Aaron Watry 
> > > Signed-off-by: Dylan Baker 
> > > ---
> > > 
> > > Jan and Aaron (or whoever decides to test this):
> > > 
> > > I think this should address the issues raised so far, so maybe this is
> > > better for testing?
> > > 
> > >  include/meson.build   |  19 
> > >  meson.build   |  29 +-
> > >  meson_options.txt |   7 ++
> > >  src/gallium/meson.build   |  12 ++-
> > >  src/gallium/state_trackers/clover/meson.build | 122 
> > > ++
> > >  src/gallium/targets/opencl/meson.build|  73 +++
> > >  src/gallium/targets/pipe-loader/meson.build   |  77 
> > >  7 files changed, 334 insertions(+), 5 deletions(-)
> > >  create mode 100644 src/gallium/state_trackers/clover/meson.build
> > >  create mode 100644 src/gallium/targets/opencl/meson.build
> > >  create mode 100644 src/gallium/targets/pipe-loader/meson.build
> > > 
> > > diff --git a/include/meson.build b/include/meson.build
> > > index e4dae91cede..a2e7ce6580e 100644
> > > --- a/include/meson.build
> > > +++ b/include/meson.build
> > > @@ -78,3 +78,22 @@ if with_gallium_st_nine
> > >  subdir : 'd3dadapter',
> > >)
> > >  endif
> > > +
> > > +# Only install the headers if we are building a stand alone 
> > > implementation and
> > > +# not an ICD enabled implementation
> > > +if with_gallium_opencl and not with_opencl_icd
> > > +  install_headers(
> > > +'CL/cl.h',
> > > +'CL/cl.hpp',
> > > +'CL/cl_d3d10.h',
> > > +'CL/cl_d3d11.h',
> > > +'CL/cl_dx9_media_sharing.h',
> > > +'CL/cl_egl.h',
> > > +'CL/cl_ext.h',
> > > +'CL/cl_gl.h',
> > > +'CL/cl_gl_ext.h',
> > > +'CL/cl_platform.h',
> > > +'CL/opencl.h',
> > > +subdir: 'CL'
> > > +  )
> > > +endif
> > > diff --git a/meson.build b/meson.build
> > > index 842d441199e..74b2d5c49dc 100644
> > > --- a/meson.build
> > > +++ b/meson.build
> > > @@ -583,6 +583,22 @@ if with_gallium_st_nine
> > >endif
> > >  endif
> > >  
> > > +_opencl = get_option('gallium-opencl')
> > > +if _opencl !=' disabled'
> > > +  if not with_gallium
> > > +error('OpenCL Clover implementation requires at least one gallium 
> > > driver.')
> > > +  endif
> > > +
> > > +  # TODO: alitvec?
> > > +  dep_clc = dependency('libclc')
> > > +  with_gallium_opencl = true
> > > +  with_opencl_icd = _opencl == 'icd'
> > > +else
> > > +  dep_clc = []
> > > +  with_gallium_opencl = false
> > > +  with_gallium_icd = false
> > > +endif
> > > +
> > >  gl_pkgconfig_c_flags = []
> > >  if with_platform_x11
> > >if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
> > > @@ -930,7 +946,7 @@ dep_thread = dependency('threads')
> > >  if dep_thread.found() and host_machine.system() != 'windows'
> > >pre_args += '-DHAVE_PTHREAD'
> > >  endif
> > > -if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 # TODO: 
> > > clover
> > > +if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 or 
> > > with_gallium_opencl
> > >dep_elf = dependency('libelf', required : false)
> > >if not dep_elf.found()
> > >  dep_elf = cc.find_library('elf')
> > > @@ -972,12 +988,19 @@ if with_amd_vk or with_gallium_radeonsi or 
> > > with_gallium_r600
> > >  llvm_modules += 'asmparser'
> > >endif
> > >  endif
> > > +if with_gallium_opencl
> > > +  llvm_modules += [
> > > +'all-targets', 'linker', 'coverage', 'instrumentation', 'ipo', 
> > > 'irreader',
> > > +'lto', 'option', 'objcarcopts', 'profiledata',
> > > +  ]
> > > +  # TODO: optional modules
> > > +endif
> > >  
> > >  _llvm = get_option('llvm')
> > >  if _llvm == 'auto'
> > >dep_llvm = dependency(
> > >  'llvm', version : '>= 3.9.0', modules : llvm_modules,
> > > -required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr,
> > > +required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr 
> > > or with_gallium_opencl,
> > >)
> > >with_llvm = dep_llvm.found()
> > >  elif _llvm == 'true'
> > > @@ -1154,8 +1177,6 @@ else
> > >dep_lmsensors = []
> > >  endif
> > >  
> > > -# TODO: clover
> > > -
> > >  # TODO: gallium tests
> > >  
> > >  # TODO: various libdirs
> > > diff --git a/meson_options.txt b/meson_options.txt
> > > index 4f4db5b7d26..894378985fd 100644
> > > --- a/meson_options.txt
> > > +++ b/meson_options.txt

[Mesa-dev] [Bug 104231] DispatchSanity_test.GL30 regression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104231

Dylan Baker  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #2 from Dylan Baker  ---
5364e73624a..e5d8ffdda6b  master -> master

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Re: [Mesa-dev] [PATCH v2 3/4] meson: build clover

[Francisco Jerez]

Jan Vesely  writes:

> On Wed, 2017-12-13 at 09:47 -0800, Dylan Baker wrote:
>> This has only been compile tested.
>> 
>> v2: - Have a single option for opencl (Eric E)
>> - fix typo "tgis" -> "tgsi" (Curro)
>> - Don't add "lib" prefix to pipe loader libraries, which matches the
>>   autotools behavior
>> 
>> cc: Curro Jerez 
>> cc: Jan Vesely 
>> cc: Aaron Watry 
>> Signed-off-by: Dylan Baker 
>> ---
>> 
>> Jan and Aaron (or whoever decides to test this):
>> 
>> I think this should address the issues raised so far, so maybe this is
>> better for testing?
>> 
>>  include/meson.build   |  19 
>>  meson.build   |  29 +-
>>  meson_options.txt |   7 ++
>>  src/gallium/meson.build   |  12 ++-
>>  src/gallium/state_trackers/clover/meson.build | 122 
>> ++
>>  src/gallium/targets/opencl/meson.build|  73 +++
>>  src/gallium/targets/pipe-loader/meson.build   |  77 
>>  7 files changed, 334 insertions(+), 5 deletions(-)
>>  create mode 100644 src/gallium/state_trackers/clover/meson.build
>>  create mode 100644 src/gallium/targets/opencl/meson.build
>>  create mode 100644 src/gallium/targets/pipe-loader/meson.build
>> 
>> diff --git a/include/meson.build b/include/meson.build
>> index e4dae91cede..a2e7ce6580e 100644
>> --- a/include/meson.build
>> +++ b/include/meson.build
>> @@ -78,3 +78,22 @@ if with_gallium_st_nine
>>  subdir : 'd3dadapter',
>>)
>>  endif
>> +
>> +# Only install the headers if we are building a stand alone implementation 
>> and
>> +# not an ICD enabled implementation
>> +if with_gallium_opencl and not with_opencl_icd
>> +  install_headers(
>> +'CL/cl.h',
>> +'CL/cl.hpp',
>> +'CL/cl_d3d10.h',
>> +'CL/cl_d3d11.h',
>> +'CL/cl_dx9_media_sharing.h',
>> +'CL/cl_egl.h',
>> +'CL/cl_ext.h',
>> +'CL/cl_gl.h',
>> +'CL/cl_gl_ext.h',
>> +'CL/cl_platform.h',
>> +'CL/opencl.h',
>> +subdir: 'CL'
>> +  )
>> +endif
>> diff --git a/meson.build b/meson.build
>> index 842d441199e..74b2d5c49dc 100644
>> --- a/meson.build
>> +++ b/meson.build
>> @@ -583,6 +583,22 @@ if with_gallium_st_nine
>>endif
>>  endif
>>  
>> +_opencl = get_option('gallium-opencl')
>> +if _opencl !=' disabled'
>> +  if not with_gallium
>> +error('OpenCL Clover implementation requires at least one gallium 
>> driver.')
>> +  endif
>> +
>> +  # TODO: alitvec?
>> +  dep_clc = dependency('libclc')
>> +  with_gallium_opencl = true
>> +  with_opencl_icd = _opencl == 'icd'
>> +else
>> +  dep_clc = []
>> +  with_gallium_opencl = false
>> +  with_gallium_icd = false
>> +endif
>> +
>>  gl_pkgconfig_c_flags = []
>>  if with_platform_x11
>>if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
>> @@ -930,7 +946,7 @@ dep_thread = dependency('threads')
>>  if dep_thread.found() and host_machine.system() != 'windows'
>>pre_args += '-DHAVE_PTHREAD'
>>  endif
>> -if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 # TODO: clover
>> +if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 or 
>> with_gallium_opencl
>>dep_elf = dependency('libelf', required : false)
>>if not dep_elf.found()
>>  dep_elf = cc.find_library('elf')
>> @@ -972,12 +988,19 @@ if with_amd_vk or with_gallium_radeonsi or 
>> with_gallium_r600
>>  llvm_modules += 'asmparser'
>>endif
>>  endif
>> +if with_gallium_opencl
>> +  llvm_modules += [
>> +'all-targets', 'linker', 'coverage', 'instrumentation', 'ipo', 
>> 'irreader',
>> +'lto', 'option', 'objcarcopts', 'profiledata',
>> +  ]
>> +  # TODO: optional modules
>> +endif
>>  
>>  _llvm = get_option('llvm')
>>  if _llvm == 'auto'
>>dep_llvm = dependency(
>>  'llvm', version : '>= 3.9.0', modules : llvm_modules,
>> -required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr,
>> +required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr or 
>> with_gallium_opencl,
>>)
>>with_llvm = dep_llvm.found()
>>  elif _llvm == 'true'
>> @@ -1154,8 +1177,6 @@ else
>>dep_lmsensors = []
>>  endif
>>  
>> -# TODO: clover
>> -
>>  # TODO: gallium tests
>>  
>>  # TODO: various libdirs
>> diff --git a/meson_options.txt b/meson_options.txt
>> index 4f4db5b7d26..894378985fd 100644
>> --- a/meson_options.txt
>> +++ b/meson_options.txt
>> @@ -120,6 +120,13 @@ option(
>>value : false,
>>description : 'build gallium "nine" Direct3D 9.x state tracker.',
>>  )
>> +option(
>> +  'gallium-opencl',
>> +  type : 'combo',
>> +  choices : ['icd', 'standalone', 'disabled'],
>> +  value : 'disabled',
>> +  description : 'build gallium "clover" OpenCL state tracker.',
>> +)
>>  option(
>>'d3d-drivers-path',
>>type : 'string',
>> diff --git a/src/gallium/meson.build b/src/gallium/meson.build
>> 

Re: [Mesa-dev] [PATCH v2] egl/android: Partially handle HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED

[Rob Herring]

On Wed, Dec 13, 2017 at 11:58 AM, Robert Foss  wrote:
> Hey Rob,
>
> I've chatted to both of you about this patch, and it seemed acceptable
> to both of you.
>
> Can I have a s-o-b for either of you?

I've applied it and pushed to master.

Rob
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[Mesa-dev] [PATCH] Android: fix missing generation of vtn_gather_types.c

[Rob Herring]

Commit bb1e6ff161c9 ("spirv: Add a prepass to set types on vtn_values")
added generation of vtn_gather_types.c, but forgot to add it to the
Android build files.

Fixes: bb1e6ff161c9 ("spirv: Add a prepass to set types on vtn_values")
Cc: Jason Ekstrand 
Signed-off-by: Rob Herring 
---
 src/compiler/Android.nir.gen.mk | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/compiler/Android.nir.gen.mk b/src/compiler/Android.nir.gen.mk
index e2187d081df8..aaa27128b41a 100644
--- a/src/compiler/Android.nir.gen.mk
+++ b/src/compiler/Android.nir.gen.mk
@@ -98,3 +98,8 @@ $(intermediates)/nir/nir_opt_algebraic.c: 
$(nir_opt_algebraic_deps)
 $(intermediates)/spirv/spirv_info.c: $(LOCAL_PATH)/spirv/spirv_info_c.py 
$(LOCAL_PATH)/spirv/spirv.core.grammar.json
@mkdir -p $(dir $@)
$(hide) $(MESA_PYTHON2) $^ $@ || ($(RM) $@; false)
+
+$(intermediates)/spirv/vtn_gather_types.c:: 
$(LOCAL_PATH)/spirv/vtn_gather_types_c.py 
$(LOCAL_PATH)/spirv/spirv.core.grammar.json
+   @mkdir -p $(dir $@)
+   $(hide) $(MESA_PYTHON2) $^ $@ || ($(RM) $@; false)
+
-- 
2.14.1

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Re: [Mesa-dev] [PATCH] mesa: Add glSpecializeShaderARB to common_desktop_functions

[Ian Romanick]

Thank you for the perfectly timed fix. :)

Reviewed-by: Ian Romanick 

On 12/12/2017 11:50 AM, Dylan Baker wrote:
> CC: Nicolai Hähnle 
> CC: Reviewed-by: Ian Romanick 
> CC: Mark Janes 
> Fixes: 46b21b8f906 ("mesa: add GL_ARB_gl_spirv boilerplate")
> Signed-off-by: Dylan Baker 
> ---
>  src/mesa/main/tests/dispatch_sanity.cpp | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/src/mesa/main/tests/dispatch_sanity.cpp 
> b/src/mesa/main/tests/dispatch_sanity.cpp
> index b2ff35717b7..00754deb461 100644
> --- a/src/mesa/main/tests/dispatch_sanity.cpp
> +++ b/src/mesa/main/tests/dispatch_sanity.cpp
> @@ -1020,6 +1020,9 @@ const struct function 
> common_desktop_functions_possible[] = {
> { "glImportMemoryFdEXT", 45, -1 },
> { "glImportSemaphoreFdEXT", 45, -1 },
>  
> +   /* GL_ARB_gl_spirv */
> +   { "glSpecializeShaderARB", 45, -1 },
> +
> { NULL, 0, -1 }
>  };
>  
> 

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Re: [Mesa-dev] [PATCH 3/4] meson: set opencl flags for r600

[Eric Engestrom]

On Tuesday, 2017-12-12 11:58:14 -0800, Dylan Baker wrote:
> Quoting Eric Engestrom (2017-12-12 06:15:58)
> > On Monday, 2017-12-11 11:50:01 -0800, Dylan Baker wrote:
> > > Quoting Eric Engestrom (2017-12-11 07:55:30)
> > > > On Friday, 2017-12-08 16:27:21 -0800, Dylan Baker wrote:
> > > > > Signed-off-by: Dylan Baker 
> > > > 
> > > > Should come after the current 4/4, but
> > > > Reviewed-by: Eric Engestrom 
> > > > 
> > > > > ---
> > > > >  src/gallium/drivers/r600/meson.build | 7 +--
> > > > >  1 file changed, 5 insertions(+), 2 deletions(-)
> > > > > 
> > > > > diff --git a/src/gallium/drivers/r600/meson.build 
> > > > > b/src/gallium/drivers/r600/meson.build
> > > > > index 2132dbb33ad..5899518a2e8 100644
> > > > > --- a/src/gallium/drivers/r600/meson.build
> > > > > +++ b/src/gallium/drivers/r600/meson.build
> > > > > @@ -113,12 +113,15 @@ egd_tables_h = custom_target(
> > > > >capture : true,
> > > > >  )
> > > > >  
> > > > > -# TODO: compute defines
> > > > > +r600_c_args = []
> > > > > +if with_gallium_opencl
> > > > > +  r600_c_args += '-DHAVE_OPENCL'
> > > > > +endif
> > > > >  
> > > > >  libr600 = static_library(
> > > > >'r600',
> > > > >[files_r600, egd_tables_h],
> > > > > -  c_args : [c_vis_args],
> > > > > +  c_args : [c_vis_args, r600_c_args],
> > > > >cpp_args : [cpp_vis_args],
> > > > >include_directories : [
> > > > >  inc_src, inc_include, inc_gallium, inc_gallium_aux, 
> > > > > inc_amd_common,
> > > > > -- 
> > > > > 2.15.1
> > > > > 
> > > 
> > > r600 needs this to work with clover at all. Since it's so minimal, how 
> > > would you
> > > feel about just squashing this into 4/4?
> > 
> > You mean r600 would be broken after 4/4 if 3/4 wasn't applied?
> > I'm OK with squashing them if so.
> > 
> > My issue was just that with this order, the build would be broken
> > between 3/4 and 4/4 because `with_gallium_opencl` doesn't exist yet.
> 
> Right, the current order is broken. Unless I've misunderstood the code without
> this patch the code will compile, but trying to run OpenCL workloads with r600
> will fail. Maybe it's fine to put that in a follow up patch?

Sure, squash with 4/4 or swap them, both work for me, with a small
preference on the latter ;)
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Re: [Mesa-dev] [PATCH v2 3/4] meson: build clover

[Jan Vesely]

On Wed, 2017-12-13 at 09:47 -0800, Dylan Baker wrote:
> This has only been compile tested.
> 
> v2: - Have a single option for opencl (Eric E)
> - fix typo "tgis" -> "tgsi" (Curro)
> - Don't add "lib" prefix to pipe loader libraries, which matches the
>   autotools behavior
> 
> cc: Curro Jerez 
> cc: Jan Vesely 
> cc: Aaron Watry 
> Signed-off-by: Dylan Baker 
> ---
> 
> Jan and Aaron (or whoever decides to test this):
> 
> I think this should address the issues raised so far, so maybe this is
> better for testing?
> 
>  include/meson.build   |  19 
>  meson.build   |  29 +-
>  meson_options.txt |   7 ++
>  src/gallium/meson.build   |  12 ++-
>  src/gallium/state_trackers/clover/meson.build | 122 
> ++
>  src/gallium/targets/opencl/meson.build|  73 +++
>  src/gallium/targets/pipe-loader/meson.build   |  77 
>  7 files changed, 334 insertions(+), 5 deletions(-)
>  create mode 100644 src/gallium/state_trackers/clover/meson.build
>  create mode 100644 src/gallium/targets/opencl/meson.build
>  create mode 100644 src/gallium/targets/pipe-loader/meson.build
> 
> diff --git a/include/meson.build b/include/meson.build
> index e4dae91cede..a2e7ce6580e 100644
> --- a/include/meson.build
> +++ b/include/meson.build
> @@ -78,3 +78,22 @@ if with_gallium_st_nine
>  subdir : 'd3dadapter',
>)
>  endif
> +
> +# Only install the headers if we are building a stand alone implementation 
> and
> +# not an ICD enabled implementation
> +if with_gallium_opencl and not with_opencl_icd
> +  install_headers(
> +'CL/cl.h',
> +'CL/cl.hpp',
> +'CL/cl_d3d10.h',
> +'CL/cl_d3d11.h',
> +'CL/cl_dx9_media_sharing.h',
> +'CL/cl_egl.h',
> +'CL/cl_ext.h',
> +'CL/cl_gl.h',
> +'CL/cl_gl_ext.h',
> +'CL/cl_platform.h',
> +'CL/opencl.h',
> +subdir: 'CL'
> +  )
> +endif
> diff --git a/meson.build b/meson.build
> index 842d441199e..74b2d5c49dc 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -583,6 +583,22 @@ if with_gallium_st_nine
>endif
>  endif
>  
> +_opencl = get_option('gallium-opencl')
> +if _opencl !=' disabled'
> +  if not with_gallium
> +error('OpenCL Clover implementation requires at least one gallium 
> driver.')
> +  endif
> +
> +  # TODO: alitvec?
> +  dep_clc = dependency('libclc')
> +  with_gallium_opencl = true
> +  with_opencl_icd = _opencl == 'icd'
> +else
> +  dep_clc = []
> +  with_gallium_opencl = false
> +  with_gallium_icd = false
> +endif
> +
>  gl_pkgconfig_c_flags = []
>  if with_platform_x11
>if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
> @@ -930,7 +946,7 @@ dep_thread = dependency('threads')
>  if dep_thread.found() and host_machine.system() != 'windows'
>pre_args += '-DHAVE_PTHREAD'
>  endif
> -if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 # TODO: clover
> +if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 or 
> with_gallium_opencl
>dep_elf = dependency('libelf', required : false)
>if not dep_elf.found()
>  dep_elf = cc.find_library('elf')
> @@ -972,12 +988,19 @@ if with_amd_vk or with_gallium_radeonsi or 
> with_gallium_r600
>  llvm_modules += 'asmparser'
>endif
>  endif
> +if with_gallium_opencl
> +  llvm_modules += [
> +'all-targets', 'linker', 'coverage', 'instrumentation', 'ipo', 
> 'irreader',
> +'lto', 'option', 'objcarcopts', 'profiledata',
> +  ]
> +  # TODO: optional modules
> +endif
>  
>  _llvm = get_option('llvm')
>  if _llvm == 'auto'
>dep_llvm = dependency(
>  'llvm', version : '>= 3.9.0', modules : llvm_modules,
> -required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr,
> +required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr or 
> with_gallium_opencl,
>)
>with_llvm = dep_llvm.found()
>  elif _llvm == 'true'
> @@ -1154,8 +1177,6 @@ else
>dep_lmsensors = []
>  endif
>  
> -# TODO: clover
> -
>  # TODO: gallium tests
>  
>  # TODO: various libdirs
> diff --git a/meson_options.txt b/meson_options.txt
> index 4f4db5b7d26..894378985fd 100644
> --- a/meson_options.txt
> +++ b/meson_options.txt
> @@ -120,6 +120,13 @@ option(
>value : false,
>description : 'build gallium "nine" Direct3D 9.x state tracker.',
>  )
> +option(
> +  'gallium-opencl',
> +  type : 'combo',
> +  choices : ['icd', 'standalone', 'disabled'],
> +  value : 'disabled',
> +  description : 'build gallium "clover" OpenCL state tracker.',
> +)
>  option(
>'d3d-drivers-path',
>type : 'string',
> diff --git a/src/gallium/meson.build b/src/gallium/meson.build
> index fc21dcf03e1..6330c7514af 100644
> --- a/src/gallium/meson.build
> +++ b/src/gallium/meson.build
> @@ -145,7 +145,17 @@ endif
>  if with_gallium_st_nine
>subdir('state_trackers/nine')
>  

Re: [Mesa-dev] [RFC libdrm 3/5] android: Mark alloc_handle_t magic variable as const

[Rob Herring]

On Wed, Dec 13, 2017 at 11:30 AM, Robert Foss  wrote:
> Mark magic member of alloc_handle_t as const.
> Also bump the version of alloc_handle_t.
>
> Sign-off-by: Robert Foss 
> ---
>  android/alloc_handle.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/android/alloc_handle.h b/android/alloc_handle.h
> index b722615638e7..fe93ad7e6567 100644
> --- a/android/alloc_handle.h
> +++ b/android/alloc_handle.h
> @@ -32,7 +32,7 @@ struct alloc_handle_t {
> native_handle_t base;
>
> /* api variables */
> -   int magic; /* differentiate between allocator impls */
> +   const int magic; /* differentiate between allocator impls */
> const int version; /* api version */
>
> int prime_fd; /* dma-buf file descriptor */
> @@ -52,7 +52,7 @@ struct alloc_handle_t {
> } __attribute__((aligned(8)));
>  };
>
> -#define ALLOC_HANDLE_VERSION 1
> +#define ALLOC_HANDLE_VERSION 2

I don't think bumping the version here is necessary. Users can only be
directly accessing the member and no run-time version checking would
fix the compile time breakage. IOW, this isn't a backwards compatible
change, so a version check is not going to help. Plus, it's highly
unlikely any user modifies magic.

Rob
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Re: [Mesa-dev] [RFC libdrm 1/5] android: Move gralloc handle struct to libdrm

[Rob Herring]

On Wed, Dec 13, 2017 at 11:30 AM, Robert Foss  wrote:
> This struct is used in mesa and drm_hwcomposer.
> Versions of if have been implemented in several grallocs:
> drm_gralloc, gbm_gralloc, minigbm and intel-minigbm.
>
> Other than the 1:1 move of the struct a new generic name
> has been chosen and variables have had comments added to them.
>
> Sign-off-by: Robert Foss 
> ---
>  Android.mk   |  8 +++--
>  Makefile.sources |  3 ++
>  android/alloc_handle.h   | 84 
> 
>  android/gralloc_drm_handle.h |  1 +
>  4 files changed, 94 insertions(+), 2 deletions(-)
>  create mode 100644 android/alloc_handle.h
>  create mode 12 android/gralloc_drm_handle.h
>
> diff --git a/Android.mk b/Android.mk
> index 292be2360263..209123a56940 100644
> --- a/Android.mk
> +++ b/Android.mk
> @@ -28,7 +28,7 @@ LIBDRM_TOP := $(LOCAL_PATH)
>
>  include $(CLEAR_VARS)
>
> -# Import variables LIBDRM_{,H_,INCLUDE_H_,INCLUDE_VMWGFX_H_}FILES
> +# Import variables 
> LIBDRM_{,H,INCLUDE_H,INCLUDE_ANDROID_H,INCLUDE_VMWGFX_H}_FILES
>  include $(LOCAL_PATH)/Makefile.sources
>
>  #static library for the device (recovery)
> @@ -38,7 +38,8 @@ LOCAL_MODULE := libdrm
>  LOCAL_SRC_FILES := $(LIBDRM_FILES)
>  LOCAL_EXPORT_C_INCLUDE_DIRS := \
> $(LOCAL_PATH) \
> -   $(LOCAL_PATH)/include/drm
> +   $(LOCAL_PATH)/include/drm \
> +   $(LOCAL_PATH)/include/android

The path doesn't match.

>
>  LOCAL_C_INCLUDES := \
> $(LOCAL_PATH)/include/drm
> @@ -54,6 +55,9 @@ LOCAL_SRC_FILES := $(LIBDRM_FILES)
>  LOCAL_EXPORT_C_INCLUDE_DIRS := \
>  $(LOCAL_PATH)/include/drm
>
> +LOCAL_SHARED_LIBRARIES := \
> +   libcutils
> +
>  LOCAL_C_INCLUDES := \
>  $(LOCAL_PATH)/include/drm
>
> diff --git a/Makefile.sources b/Makefile.sources
> index 10aa1d0f4b6e..545b5bbb35e5 100644
> --- a/Makefile.sources
> +++ b/Makefile.sources
> @@ -37,5 +37,8 @@ LIBDRM_INCLUDE_H_FILES := \
> include/drm/via_drm.h \
> include/drm/virtgpu_drm.h
>
> +LIBDRM_INCLUDE_ANDROID_H_FILES := \
> +   android/alloc_handle.h
> +
>  LIBDRM_INCLUDE_VMWGFX_H_FILES := \
> include/drm/vmwgfx_drm.h
> diff --git a/android/alloc_handle.h b/android/alloc_handle.h
> new file mode 100644
> index ..75cb895a962a
> --- /dev/null
> +++ b/android/alloc_handle.h
> @@ -0,0 +1,84 @@
> +/*
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#ifndef __ANDROID_ALLOC_HANDLE_H__
> +#define __ANDROID_ALLOC_HANDLE_H__
> +
> +#include 
> +
> +/* support users of drm_gralloc/gbm_gralloc */
> +#define gralloc_gbm_handle_t alloc_handle_t
> +#define gralloc_drm_handle_t alloc_handle_t
> +
> +struct alloc_handle_t {
> +   native_handle_t base;
> +
> +   /* integers */
> +   int magic; /* differentiate between allocator impls */
> +
> +   int prime_fd; /* dma-buf file descriptor */

You changed the order here and it is important that fd's come first.

> +   int width; /* width of buffer in pixels */
> +   int height; /* height of buffer in pixels */
> +   int format; /* pixel format (Android) */
> +   int usage; /* android libhardware usage flags */
> +
> +   int name;   /* the name of the bo */
> +   int stride; /* the stride in bytes */
> +   uint64_t modifier; /* buffer modifiers */
> +
> +   int data_owner; /* owner of data (for validation) */
> +   union {
> +   void *data; /* pointer to struct gralloc_gbm_bo_t */
> +   uint64_t reserved;
> +   } __attribute__((aligned(8)));
> +};
> +
> +#define ALLOC_HANDLE_MAGIC 0x60585350
> +#define ALLOC_HANDLE_NUM_FDS 1
> +#define ALLOC_HANDLE_NUM_INTS (\
> +   ((sizeof(struct alloc_handle_t) - 
> sizeof(native_handle_t))/sizeof(int)) \
> +- ALLOC_HANDLE_NUM_FDS)
> +
> 

[Mesa-dev] [PATCH] i965: Don't allocate an MCS for 16x MSAA and width > 8192.

[Kenneth Graunke]

The hardware doesn't support this, and isl_surf_get_mcs_surf will fail.

I feel a bit bad replicating this logic, but we want to decide up front.

This fixes the following test when run with --deqp-surface-width=16384:
- 
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_framebuffers_different_sample_count

Cc: ito...@igalia.com
Cc: apuen...@igalia.com
Cc: i...@freedesktop.org
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index c1a4ce184f5..ead0c359c0f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -73,6 +73,10 @@ intel_miptree_supports_mcs(struct brw_context *brw,
if (devinfo->gen < 7)
   return false;
 
+   /* See isl_surf_get_mcs_surf for details. */
+   if (mt->surf.samples == 16 && mt->surf.logical_level0_px.width > 8192)
+  return false;
+
/* In Gen7, IMS layout is only used for depth and stencil buffers. */
switch (_mesa_get_format_base_format(mt->format)) {
case GL_DEPTH_COMPONENT:
-- 
2.15.1

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Re: [Mesa-dev] [PATCH] radv: export SampleMask from pixel shaders at full rate

[Bas Nieuwenhuizen]

On Tue, Dec 12, 2017 at 6:08 PM, Samuel Pitoiset
 wrote:
> Use 16_ABGR instead of 32_ABGR if Z isn't written.
>
> Ported from RadeonSI.
>
> No CTS regressions on Polaris.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/common/ac_nir_to_llvm.c | 65 
> ++---
>  src/amd/vulkan/radv_pipeline.c  | 29 ++
>  2 files changed, 78 insertions(+), 16 deletions(-)
>
> diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
> index 663b27d265..5916619e97 100644
> --- a/src/amd/common/ac_nir_to_llvm.c
> +++ b/src/amd/common/ac_nir_to_llvm.c
> @@ -6166,6 +6166,26 @@ si_export_mrt_color(struct nir_to_llvm_context *ctx,
> return true;
>  }
>
> +static unsigned
> +si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
> +  bool writes_samplemask)
> +{
> +   if (writes_z) {
> +   /* Z needs 32 bits. */
> +   if (writes_samplemask)
> +   return V_028710_SPI_SHADER_32_ABGR;
> +   else if (writes_stencil)
> +   return V_028710_SPI_SHADER_32_GR;
> +   else
> +   return V_028710_SPI_SHADER_32_R;
> +   } else if (writes_stencil || writes_samplemask) {
> +   /* Both stencil and sample mask need only 16 bits. */
> +   return V_028710_SPI_SHADER_UINT16_ABGR;
> +   } else {
> +   return V_028710_SPI_SHADER_ZERO;
> +   }
> +}

I'm not a fan of having this function in two places. Can we export the
format from the compiler to radv, or the other way around?

Otherwise,

Reviewed-by: Bas Nieuwenhuizen 

> +
>  static void
>  si_export_mrt_z(struct nir_to_llvm_context *ctx,
> LLVMValueRef depth, LLVMValueRef stencil,
> @@ -6184,19 +6204,42 @@ si_export_mrt_z(struct nir_to_llvm_context *ctx,
> args.out[2] = LLVMGetUndef(ctx->ac.f32); /* B, sample mask */
> args.out[3] = LLVMGetUndef(ctx->ac.f32); /* A, alpha to mask */
>
> -   if (depth) {
> -   args.out[0] = depth;
> -   args.enabled_channels |= 0x1;
> -   }
> +   unsigned format = si_get_spi_shader_z_format(depth != NULL,
> +stencil != NULL,
> +samplemask != NULL);
> +
> +   if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
> +   assert(!depth);
> +   args.compr = 1; /* COMPR flag */
> +
> +   if (stencil) {
> +   /* Stencil should be in X[23:16]. */
> +   stencil = ac_to_integer(>ac, stencil);
> +   stencil = LLVMBuildShl(ctx->builder, stencil,
> +  LLVMConstInt(ctx->ac.i32, 16, 
> 0), "");
> +   args.out[0] = ac_to_float(>ac, stencil);
> +   args.enabled_channels |= 0x3;
> +   }
> +   if (samplemask) {
> +   /* SampleMask should be in Y[15:0]. */
> +   args.out[1] = samplemask;
> +   args.enabled_channels |= 0xc;
> +   }
> +   } else {
> +   if (depth) {
> +   args.out[0] = depth;
> +   args.enabled_channels |= 0x1;
> +   }
>
> -   if (stencil) {
> -   args.out[1] = stencil;
> -   args.enabled_channels |= 0x2;
> -   }
> +   if (stencil) {
> +   args.out[1] = stencil;
> +   args.enabled_channels |= 0x2;
> +   }
>
> -   if (samplemask) {
> -   args.out[2] = samplemask;
> -   args.enabled_channels |= 0x4;
> +   if (samplemask) {
> +   args.out[2] = samplemask;
> +   args.enabled_channels |= 0x4;
> +   }
> }
>
> /* SI (except OLAND and HAINAN) has a bug that it only looks
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index 0146d6935e..baaf5c4c77 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -2013,6 +2013,25 @@ radv_pipeline_stage_to_user_data_0(struct 
> radv_pipeline *pipeline,
> }
>  }
>
> +static unsigned
> +si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
> +  bool writes_samplemask)
> +{
> +   if (writes_z) {
> +   /* Z needs 32 bits. */
> +   if (writes_samplemask)
> +   return V_028710_SPI_SHADER_32_ABGR;
> +   else if (writes_stencil)
> +   return V_028710_SPI_SHADER_32_GR;
> +   else
> +   return V_028710_SPI_SHADER_32_R;
> +   } else if (writes_stencil || writes_samplemask) {
> + 

Re: [Mesa-dev] [PATCH v2 05/25] mesa: implement SPIR-V loading in glShaderBinary

[Jon Turney]

On 30/11/2017 23:57, Ian Romanick wrote:

On 11/30/2017 09:28 AM, Eduardo Lima Mitev wrote:

From: Nicolai Hähnle 

v2: * Add a gl_shader_spirv_data member to gl_shader, which already
encapsulates a gl_spirv_module where the binary will be saved.
(Eduardo Lima)

 * Just use the 'spirv_data' member to know whether a gl_shader has
the SPIR_V_BINARY_ARB state. (Timothy Arceri)

 * Remove redundant argument checks. Move extension presence check
to API entry point where the rest of checks are. Retype 'n' and
'length'arguments to use the correct and more standard types.
(Ian Romanick)
---
  src/mesa/main/glspirv.c   | 43 +++
  src/mesa/main/glspirv.h   |  5 +
  src/mesa/main/mtypes.h|  4 
  src/mesa/main/shaderapi.c | 45 ++---
  src/mesa/main/shaderobj.c |  2 ++
  5 files changed, 96 insertions(+), 3 deletions(-)

diff --git a/src/mesa/main/glspirv.c b/src/mesa/main/glspirv.c
index 8d1e652e088..d2e76bb1927 100644
--- a/src/mesa/main/glspirv.c
+++ b/src/mesa/main/glspirv.c

[...]

+
+   sh = alloca(sizeof(*sh) * (size_t)n);
+   if (!sh) {
+  _mesa_error(ctx, GL_OUT_OF_MEMORY, "glShaderBinary");
+  return;
+   }
+


This adds a use of alloca() without a corresponding #include.

Patch attached.

From 3b00c72a92ca1091d11ecffd8db404dcd598e63d Mon Sep 17 00:00:00 2001
From: Jon Turney 
Date: Wed, 13 Dec 2017 19:49:07 +
Subject: [PATCH] Fix use of alloca() without #include 
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

../../../src/mesa/main/shaderapi.c: In function ‘_mesa_ShaderBinary’:
../../../src/mesa/main/shaderapi.c:2188:9: error: implicit declaration of 
function ‘alloca’ [-Werror=implicit-function-declaration]

Signed-off-by: Jon Turney 
---
 src/mesa/main/shaderapi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index d824a88ca2f..2c11e4d5bb6 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -38,6 +38,7 @@
 
 
 #include 
+#include 
 #include "main/glheader.h"
 #include "main/context.h"
 #include "main/dispatch.h"
-- 
2.15.1

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[Mesa-dev] [PATCH v3 6/6] i965: enable ARB_spirv_extensions for gen8+

[Eduardo Lima Mitev]

From: Alejandro Piñeiro 

---
 src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 4d17393948a..39680ed194a 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -280,6 +280,7 @@ intelInitExtensions(struct gl_context *ctx)
   ctx->Extensions.ARB_gpu_shader_int64 = true;
   ctx->Extensions.ARB_shader_ballot = true; /* requires 
ARB_gpu_shader_int64 */
   ctx->Extensions.ARB_ES3_2_compatibility = true;
+  ctx->Extensions.ARB_spirv_extensions = true;
}
 
if (devinfo->gen >= 9) {
-- 
2.15.1

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[Mesa-dev] [PATCH v3 5/6] spirv_extensions: i965: initialize SPIR-V extensions

[Eduardo Lima Mitev]

From: Alejandro Piñeiro 

v2: Rebase update after changes on previous patches.
---
 src/mesa/drivers/dri/i965/brw_context.c | 9 -
 src/mesa/main/context.c | 2 ++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index a37bbb753d8..ea5892a8abf 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -76,6 +76,7 @@
 #include "isl/isl.h"
 
 #include "compiler/spirv/nir_spirv.h"
+#include "compiler/spirv/spirv_extensions.h"
 /***
  * Mesa's Driver Functions
  ***/
@@ -1084,9 +1085,15 @@ brwCreateContext(gl_api api,
_mesa_compute_version(ctx);
 
/* GL_ARB_gl_spirv */
-   if (ctx->Version >= 33)
+   if (ctx->Version >= 33) {
   brw_initialize_spirv_supported_capabilities(brw);
 
+  /* GL_ARB_spirv_extensions */
+  ctx->Const.SpirVExtensions = MALLOC_STRUCT(spirv_supported_extensions);
+  spirv_fill_supported_spirv_extensions(ctx->Const.SpirVExtensions,
+ >Const.SpirVCapabilities);
+   }
+
_mesa_initialize_dispatch_tables(ctx);
_mesa_initialize_vbo_vtxfmt(ctx);
 
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 3fa9f69f883..b48481d4372 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -1377,6 +1377,8 @@ _mesa_free_context_data( struct gl_context *ctx )
if (ctx == _mesa_get_current_context()) {
   _mesa_make_current(NULL, NULL, NULL);
}
+
+   free(ctx->Const.SpirVExtensions);
 }
 
 
-- 
2.15.1

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[Mesa-dev] [PATCH v3 4/6] spirv_extensions: add spirv_supported_extensions on gl_constants

[Eduardo Lima Mitev]

From: Alejandro Piñeiro 

We can use it to get real values for ARB_spirv_extensions methods.

v2: Rebase update after changes on previous patches.
---
 src/mesa/main/mtypes.h   |  3 +++
 src/mesa/main/spirv_extensions.c | 20 +++-
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 36534c3de81..cba12008599 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -4040,6 +4040,9 @@ struct gl_constants
 
/** GL_ARB_gl_spirv */
struct spirv_supported_capabilities SpirVCapabilities;
+
+   /** GL_ARB_spirv_extensions */
+   struct spirv_supported_extensions *SpirVExtensions;
 };
 
 
diff --git a/src/mesa/main/spirv_extensions.c b/src/mesa/main/spirv_extensions.c
index 40a89c133aa..2bb29461fd4 100644
--- a/src/mesa/main/spirv_extensions.c
+++ b/src/mesa/main/spirv_extensions.c
@@ -27,16 +27,34 @@
  */
 
 #include "spirv_extensions.h"
+#include "compiler/spirv/spirv_extensions.h"
 
 GLuint
 _mesa_get_spirv_extension_count(struct gl_context *ctx)
 {
-   return 0;
+   if (ctx->Const.SpirVExtensions == NULL)
+  return 0;
+
+   return ctx->Const.SpirVExtensions->count;
 }
 
 const GLubyte *
 _mesa_get_enabled_spirv_extension(struct gl_context *ctx,
   GLuint index)
 {
+   unsigned int n = 0;
+
+   if (ctx->Const.SpirVExtensions == NULL)
+  return (const GLubyte *) 0;
+
+   for (unsigned int i = 0; i < SPV_EXTENSIONS_COUNT; i++) {
+  if (ctx->Const.SpirVExtensions->supported[i]) {
+ if (n == index)
+return (const GLubyte *) spirv_extensions_to_string(i);
+ else
+n++;
+  }
+   }
+
return (const GLubyte *) 0;
 }
-- 
2.15.1

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[Mesa-dev] [PATCH v3 3/6] spirv_extensions: define spirv_extensions_supported

[Eduardo Lima Mitev]

From: Alejandro Piñeiro 

Add a struct to maintain which SPIR-V extensions are supported, and an
utility method to initialize it based on
nir_spirv_supported_capabilities.

v2:
  * Fixing code style (Ian Romanick)
  * Adding a prefix (spirv) to fill_supported_spirv_extensions (Ian Romanick)

v3: rebase update (nir_spirv_supported_extensions renamed)
---
 src/compiler/spirv/spirv_extensions.c | 32 
 src/compiler/spirv/spirv_extensions.h | 13 +
 2 files changed, 45 insertions(+)

diff --git a/src/compiler/spirv/spirv_extensions.c 
b/src/compiler/spirv/spirv_extensions.c
index 3acbe28408a..dd8df817c8c 100644
--- a/src/compiler/spirv/spirv_extensions.c
+++ b/src/compiler/spirv/spirv_extensions.c
@@ -21,6 +21,7 @@
  * IN THE SOFTWARE.
  */
 
+#include 
 #include "spirv_extensions.h"
 #include "util/macros.h"
 
@@ -44,3 +45,34 @@ spirv_extensions_to_string(enum SpvExtension ext)
 
return "unknown";
 }
+
+/**
+ * Sets the supported flags for known SPIR-V extensions based on the
+ * capabilites supported (spirv capabilities based on the spirv to nir
+ * support).
+ *
+ * One could argue that makes more sense in the other way around, as from the
+ * spec pov capabilities are enable for a given extension. But from our pov,
+ * we support or not (depending on the driver) some given capability, and
+ * spirv_to_nir check for capabilities not extensions. Also we usually fill
+ * first the supported capabilities, that are not always related to an
+ * extension.
+ */
+void
+spirv_fill_supported_spirv_extensions(struct spirv_supported_extensions *ext,
+  const struct 
spirv_supported_capabilities *cap)
+{
+   for (unsigned i = 0; i < SPV_EXTENSIONS_COUNT; i++)
+  ext->supported[i] = false;
+
+   ext->count = 0;
+
+   ext->supported[SPV_KHR_shader_draw_parameters] = cap->draw_parameters;
+   ext->supported[SPV_KHR_multiview] = cap->multiview;
+   ext->supported[SPV_KHR_variable_pointers] = cap->variable_pointers;
+
+   for (unsigned i = 0; i < SPV_EXTENSIONS_COUNT; i++) {
+  if (ext->supported[i])
+ ext->count++;
+   }
+}
diff --git a/src/compiler/spirv/spirv_extensions.h 
b/src/compiler/spirv/spirv_extensions.h
index 478b128e1da..d26882a8d4c 100644
--- a/src/compiler/spirv/spirv_extensions.h
+++ b/src/compiler/spirv/spirv_extensions.h
@@ -24,6 +24,8 @@
 #ifndef _SPIRV_EXTENSIONS_H_
 #define _SPIRV_EXTENSIONS_H_
 
+#include "compiler/shader_info.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -40,8 +42,19 @@ enum SpvExtension {
SPV_EXTENSIONS_COUNT
 };
 
+struct spirv_supported_extensions {
+   /** Flags the supported extensions. Array to make it easier to iterate. */
+   bool supported[SPV_EXTENSIONS_COUNT];
+
+   /** Number of supported extensions */
+   unsigned int count;
+};
+
 const char *spirv_extensions_to_string(enum SpvExtension ext);
 
+void spirv_fill_supported_spirv_extensions(struct spirv_supported_extensions 
*ext,
+   const struct 
spirv_supported_capabilities *cap);
+
 #ifdef __cplusplus
 }
 #endif
-- 
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[Mesa-dev] [PATCH v3 2/6] spirv_extensions: add list of extensions and to_string method

[Eduardo Lima Mitev]

From: Alejandro Piñeiro 

Ideally this should be generated somehow. One option would be gather
all the extension dependencies listed on the core grammar, but there
would be the possibility of not including some of the extensions.

Note that spirv-tools is doing it just slightly better, as it has a
hardcoded list of extensions manually took from the registry, that
they parse to get the enum and the to_string method (see
generate_grammar_tables.py).

v2:
  * Use a macro to improve readability. (Tapani Pälli)
  * Add unreachable on the switch, no default (Eric Engestrom)
  * No typedef enum (Ian Romanick)
  * Sort extensions names (Ian Romanick)
  * Don't add extensions unlikely to be supported by Mesa at any point
(Ian Romanick)

v3: rebase update
---
 src/compiler/Makefile.sources |  2 ++
 src/compiler/nir/meson.build  |  2 ++
 src/compiler/spirv/spirv_extensions.c | 46 
 src/compiler/spirv/spirv_extensions.h | 49 +++
 4 files changed, 99 insertions(+)
 create mode 100644 src/compiler/spirv/spirv_extensions.c
 create mode 100644 src/compiler/spirv/spirv_extensions.h

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index d3f746f5f94..7961841bc79 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -297,6 +297,8 @@ SPIRV_FILES = \
spirv/GLSL.std.450.h \
spirv/nir_spirv.h \
spirv/spirv.h \
+   spirv/spirv_extensions.c \
+   spirv/spirv_extensions.h \
spirv/spirv_info.h \
spirv/spirv_to_nir.c \
spirv/vtn_alu.c \
diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index 5dd21e6652f..e3e4398e28b 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -185,6 +185,8 @@ files_libnir = files(
   '../spirv/GLSL.std.450.h',
   '../spirv/nir_spirv.h',
   '../spirv/spirv.h',
+  '../spirv/spirv_extensions.c',
+  '../spirv/spirv_extensions.h',
   '../spirv/spirv_info.h',
   '../spirv/spirv_to_nir.c',
   '../spirv/vtn_alu.c',
diff --git a/src/compiler/spirv/spirv_extensions.c 
b/src/compiler/spirv/spirv_extensions.c
new file mode 100644
index 000..3acbe28408a
--- /dev/null
+++ b/src/compiler/spirv/spirv_extensions.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "spirv_extensions.h"
+#include "util/macros.h"
+
+const char *
+spirv_extensions_to_string(enum SpvExtension ext)
+{
+#define STR(x) case x: return #x;
+   switch (ext) {
+   STR(SPV_KHR_16bit_storage);
+   STR(SPV_KHR_device_group);
+   STR(SPV_KHR_multiview);
+   STR(SPV_KHR_shader_ballot);
+   STR(SPV_KHR_shader_draw_parameters);
+   STR(SPV_KHR_storage_buffer_storage_class);
+   STR(SPV_KHR_subgroup_vote);
+   STR(SPV_KHR_variable_pointers);
+   case SPV_EXTENSIONS_COUNT:
+  unreachable("Unknown SPIR-V extension");
+   }
+#undef STR
+
+   return "unknown";
+}
diff --git a/src/compiler/spirv/spirv_extensions.h 
b/src/compiler/spirv/spirv_extensions.h
new file mode 100644
index 000..478b128e1da
--- /dev/null
+++ b/src/compiler/spirv/spirv_extensions.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE 

[Mesa-dev] [PATCH v3 1/6] spirv_extensions: add GL_ARB_spirv_extensions boilerplate

[Eduardo Lima Mitev]

From: Alejandro Piñeiro 

v2:
  * Mention extension gap at gl_API.xml (Emil Velikov)
  * Bail with INVALID_ENUM if extension not available on getStringi (Emil 
Velikov)
  * Use EXTRA_EXT macro when defining the extension at
get.c/get_hash_params.py (Emil Velikov)
  * Rename source files (spirvextensions.[ch] -> spirv_extensions.[ch]) (Ian)

Reviewed-by: Ian Romanick 
---
 src/mapi/glapi/gen/ARB_spirv_extensions.xml | 13 
 src/mapi/glapi/gen/Makefile.am  |  1 +
 src/mapi/glapi/gen/gl_API.xml   |  4 +++
 src/mapi/glapi/gen/meson.build  |  1 +
 src/mesa/Makefile.sources   |  2 ++
 src/mesa/main/extensions_table.h|  1 +
 src/mesa/main/get.c |  6 
 src/mesa/main/get_hash_params.py|  3 ++
 src/mesa/main/getstring.c   | 12 +++
 src/mesa/main/mtypes.h  |  1 +
 src/mesa/main/spirv_extensions.c| 42 +
 src/mesa/main/spirv_extensions.h| 49 +
 src/mesa/meson.build|  2 ++
 13 files changed, 137 insertions(+)
 create mode 100644 src/mapi/glapi/gen/ARB_spirv_extensions.xml
 create mode 100644 src/mesa/main/spirv_extensions.c
 create mode 100644 src/mesa/main/spirv_extensions.h

diff --git a/src/mapi/glapi/gen/ARB_spirv_extensions.xml 
b/src/mapi/glapi/gen/ARB_spirv_extensions.xml
new file mode 100644
index 000..103393104c2
--- /dev/null
+++ b/src/mapi/glapi/gen/ARB_spirv_extensions.xml
@@ -0,0 +1,13 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am
index 35e37e95a9f..9a7a268adbf 100644
--- a/src/mapi/glapi/gen/Makefile.am
+++ b/src/mapi/glapi/gen/Makefile.am
@@ -167,6 +167,7 @@ API_XML = \
ARB_shader_subroutine.xml \
ARB_shader_storage_buffer_object.xml \
ARB_sparse_buffer.xml \
+   ARB_spirv_extensions.xml \
ARB_sync.xml \
ARB_tessellation_shader.xml \
ARB_texture_barrier.xml \
diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index d3594cfe195..00cf83eca03 100644
--- a/src/mapi/glapi/gen/gl_API.xml
+++ b/src/mapi/glapi/gen/gl_API.xml
@@ -8404,6 +8404,10 @@
 
 http://www.w3.org/2001/XInclude"/>
 
+
+
+http://www.w3.org/2001/XInclude"/>
+
 
 
 
diff --git a/src/mapi/glapi/gen/meson.build b/src/mapi/glapi/gen/meson.build
index a6a93cc83be..bfc766f7944 100644
--- a/src/mapi/glapi/gen/meson.build
+++ b/src/mapi/glapi/gen/meson.build
@@ -75,6 +75,7 @@ api_xml_files = files(
   'ARB_shader_subroutine.xml',
   'ARB_shader_storage_buffer_object.xml',
   'ARB_sparse_buffer.xml',
+  'ARB_spirv_extensions.xml',
   'ARB_sync.xml',
   'ARB_tessellation_shader.xml',
   'ARB_texture_barrier.xml',
diff --git a/src/mesa/Makefile.sources b/src/mesa/Makefile.sources
index 53fa486364d..8a41ed1eeef 100644
--- a/src/mesa/Makefile.sources
+++ b/src/mesa/Makefile.sources
@@ -205,6 +205,8 @@ MAIN_FILES = \
main/shader_query.cpp \
main/shared.c \
main/shared.h \
+   main/spirv_extensions.c \
+   main/spirv_extensions.h \
main/state.c \
main/state.h \
main/stencil.c \
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index ab15ceb9414..06deabd0640 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -129,6 +129,7 @@ EXT(ARB_shading_language_420pack, 
ARB_shading_language_420pack
 EXT(ARB_shading_language_packing, ARB_shading_language_packing 
  , GLL, GLC,  x ,  x , 2011)
 EXT(ARB_shadow  , ARB_shadow   
  , GLL,  x ,  x ,  x , 2001)
 EXT(ARB_sparse_buffer   , ARB_sparse_buffer
  , GLL, GLC,  x ,  x , 2014)
+EXT(ARB_spirv_extensions, ARB_spirv_extensions 
  ,  x,  GLC,  x ,  x , 2016)
 EXT(ARB_stencil_texturing   , ARB_stencil_texturing
  , GLL, GLC,  x ,  x , 2012)
 EXT(ARB_sync, ARB_sync 
  , GLL, GLC,  x ,  x , 2003)
 EXT(ARB_tessellation_shader , ARB_tessellation_shader  
  ,  x , GLC,  x ,  x , 2009)
diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index c1b1a89ee05..0d3302dd962 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -34,6 +34,7 @@
 #include "get.h"
 #include "macros.h"
 #include "mtypes.h"
+#include "spirv_extensions.h"
 #include "state.h"
 #include "texcompress.h"
 #include "texstate.h"
@@ -501,6 +502,7 @@ EXTRA_EXT(OES_primitive_bounding_box);
 EXTRA_EXT(ARB_compute_variable_group_size);
 EXTRA_EXT(KHR_robustness);
 EXTRA_EXT(ARB_sparse_buffer);
+EXTRA_EXT(ARB_spirv_extensions);
 
 static const int
 extra_ARB_color_buffer_float_or_glcore[] = {
@@ -1159,6 +1161,10 @@ 

[Mesa-dev] [PATCH v3 0/6] ARB_spirv_extensions support in Mesa and i965

[Eduardo Lima Mitev]

Hi,

This series is the latest version of the support for ARB_spirv_extensions on 
i965.

It was split from a previous series that included also support for gl_spirv, 
but since this is an independent extension, we have chosen to send it 
separately to streamline review of the two series.

This extension however depends on gl_spirv, so it should be applied on top of 
the v3 series I just sent for gl_spirv 
 if 
someone wants to try it.

A tree of this series can be found at 
.

Thanks for reviewing!

cheers,
Eduardo

Alejandro Piñeiro (6):
  spirv_extensions: add GL_ARB_spirv_extensions boilerplate
  spirv_extensions: add list of extensions and to_string method
  spirv_extensions: define spirv_extensions_supported
  spirv_extensions: add spirv_supported_extensions on gl_constants
  spirv_extensions: i965: initialize SPIR-V extensions
  i965: enable ARB_spirv_extensions for gen8+

 src/compiler/Makefile.sources|  2 +
 src/compiler/nir/meson.build |  2 +
 src/compiler/spirv/spirv_extensions.c| 78 
 src/compiler/spirv/spirv_extensions.h| 62 ++
 src/mapi/glapi/gen/ARB_spirv_extensions.xml  | 13 +
 src/mapi/glapi/gen/Makefile.am   |  1 +
 src/mapi/glapi/gen/gl_API.xml|  4 ++
 src/mapi/glapi/gen/meson.build   |  1 +
 src/mesa/Makefile.sources|  2 +
 src/mesa/drivers/dri/i965/brw_context.c  |  9 +++-
 src/mesa/drivers/dri/i965/intel_extensions.c |  1 +
 src/mesa/main/context.c  |  2 +
 src/mesa/main/extensions_table.h |  1 +
 src/mesa/main/get.c  |  6 +++
 src/mesa/main/get_hash_params.py |  3 ++
 src/mesa/main/getstring.c| 12 +
 src/mesa/main/mtypes.h   |  4 ++
 src/mesa/main/spirv_extensions.c | 60 +
 src/mesa/main/spirv_extensions.h | 49 +
 src/mesa/meson.build |  2 +
 20 files changed, 313 insertions(+), 1 deletion(-)
 create mode 100644 src/compiler/spirv/spirv_extensions.c
 create mode 100644 src/compiler/spirv/spirv_extensions.h
 create mode 100644 src/mapi/glapi/gen/ARB_spirv_extensions.xml
 create mode 100644 src/mesa/main/spirv_extensions.c
 create mode 100644 src/mesa/main/spirv_extensions.h

-- 
2.15.1

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[Mesa-dev] [PATCH 10/11] intel/batch-decoder: Decode registers

[Jason Ekstrand]

---
 src/intel/tools/gen_batch_decoder.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/intel/tools/gen_batch_decoder.c 
b/src/intel/tools/gen_batch_decoder.c
index ab566aa..782e9fd 100644
--- a/src/intel/tools/gen_batch_decoder.c
+++ b/src/intel/tools/gen_batch_decoder.c
@@ -652,6 +652,18 @@ decode_3dstate_scissor_state_pointers(struct 
gen_batch_decode_ctx *ctx,
decode_dynamic_state_pointers(ctx, "SCISSOR_RECT", p, 1);
 }
 
+static void
+decode_load_register_imm(struct gen_batch_decode_ctx *ctx, const uint32_t *p)
+{
+   struct gen_group *reg = gen_spec_find_register(ctx->spec, p[1]);
+
+   if (reg != NULL) {
+  fprintf(ctx->fp, "register %s (0x%x): 0x%x\n",
+  reg->name, reg->register_offset, p[2]);
+  ctx_print_group(ctx, reg, reg->register_offset, [2]);
+   }
+}
+
 struct custom_decoder {
const char *cmd_name;
void (*decode)(struct gen_batch_decode_ctx *ctx, const uint32_t *p);
@@ -689,6 +701,7 @@ struct custom_decoder {
{ "3DSTATE_BLEND_STATE_POINTERS", decode_3dstate_blend_state_pointers },
{ "3DSTATE_CC_STATE_POINTERS", decode_3dstate_cc_state_pointers },
{ "3DSTATE_SCISSOR_STATE_POINTERS", decode_3dstate_scissor_state_pointers },
+   { "MI_LOAD_REGISTER_IMM", decode_load_register_imm }
 };
 
 static inline uint64_t
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 09/11] intel/batch-decoder: Decode dynamic state

[Jason Ekstrand]

Unfortunately, in aubinator and aubinator_error_decode we don't always
know how many of a given state we have, so we must guess.  One day,
we'll come up with a way to annotate the batch to solve this problem.
---
 src/intel/tools/gen_batch_decoder.c | 91 +
 1 file changed, 91 insertions(+)

diff --git a/src/intel/tools/gen_batch_decoder.c 
b/src/intel/tools/gen_batch_decoder.c
index 5b01879..ab566aa 100644
--- a/src/intel/tools/gen_batch_decoder.c
+++ b/src/intel/tools/gen_batch_decoder.c
@@ -567,6 +567,91 @@ decode_3dstate_sampler_state_pointers_gen6(struct 
gen_batch_decode_ctx *ctx,
dump_samplers(ctx, p[3], -1);
 }
 
+static void
+decode_dynamic_state_pointers(struct gen_batch_decode_ctx *ctx,
+  const char *struct_type, const uint32_t *p,
+  int count)
+{
+   struct gen_group *inst = gen_spec_find_instruction(ctx->spec, p);
+   struct gen_group *state = gen_spec_find_struct(ctx->spec, struct_type);
+
+   uint32_t state_offset;
+
+   struct gen_field_iterator iter;
+   gen_field_iterator_init(, inst, p, 0, false);
+   do {
+  if (strstr(iter.name, "Pointer")) {
+ state_offset = iter.raw_value;
+ break;
+  }
+   } while (gen_field_iterator_next());
+
+   uint32_t state_addr = ctx->dynamic_base.addr + state_offset;
+   const uint32_t *state_map = ctx->dynamic_base.map + state_offset;
+   for (int i = 0; i < count; i++) {
+  fprintf(ctx->fp, "%s %d\n", struct_type, i);
+  ctx_print_group(ctx, state, state_offset, state_map);
+
+  state_addr += state->dw_length * 4;
+  state_map += state->dw_length;
+   }
+}
+
+static void
+decode_3dstate_viewport_state_pointers_cc(struct gen_batch_decode_ctx *ctx,
+  const uint32_t *p)
+{
+   decode_dynamic_state_pointers(ctx, "CC_VIEWPORT", p, 4);
+}
+
+static void
+decode_3dstate_viewport_state_pointers_sf_clip(struct gen_batch_decode_ctx 
*ctx,
+   const uint32_t *p)
+{
+   decode_dynamic_state_pointers(ctx, "SF_CLIP_VIEWPORT", p, 4);
+}
+
+static void
+decode_3dstate_blend_state_pointers(struct gen_batch_decode_ctx *ctx,
+const uint32_t *p)
+{
+   struct gen_group *inst = gen_spec_find_instruction(ctx->spec, p);
+   struct gen_group *state = gen_spec_find_struct(ctx->spec, "BLEND_STATE");
+
+   uint32_t state_offset;
+
+   struct gen_field_iterator iter;
+   gen_field_iterator_init(, inst, p, 0, false);
+   do {
+  if (strstr(iter.name, "Pointer")) {
+ state_offset = iter.raw_value;
+ break;
+  }
+   } while (gen_field_iterator_next());
+
+   /* Decode 8 blend states */
+   int dw_length = state->dw_length + (8 * 2);
+
+   uint32_t state_addr = ctx->dynamic_base.addr + state_offset;
+   const void *state_map = ctx->dynamic_base.map + state_offset;
+   gen_print_group_length(ctx->fp, state, state_addr, state_map, dw_length,
+  (ctx->flags & GEN_BATCH_DECODE_IN_COLOR) != 0);
+}
+
+static void
+decode_3dstate_cc_state_pointers(struct gen_batch_decode_ctx *ctx,
+ const uint32_t *p)
+{
+   decode_dynamic_state_pointers(ctx, "COLOR_CALC_STATE", p, 1);
+}
+
+static void
+decode_3dstate_scissor_state_pointers(struct gen_batch_decode_ctx *ctx,
+  const uint32_t *p)
+{
+   decode_dynamic_state_pointers(ctx, "SCISSOR_RECT", p, 1);
+}
+
 struct custom_decoder {
const char *cmd_name;
void (*decode)(struct gen_batch_decode_ctx *ctx, const uint32_t *p);
@@ -598,6 +683,12 @@ struct custom_decoder {
{ "3DSTATE_SAMPLER_STATE_POINTERS_GS", 
decode_3dstate_sampler_state_pointers },
{ "3DSTATE_SAMPLER_STATE_POINTERS_PS", 
decode_3dstate_sampler_state_pointers },
{ "3DSTATE_SAMPLER_STATE_POINTERS", 
decode_3dstate_sampler_state_pointers_gen6 },
+
+   { "3DSTATE_VIEWPORT_STATE_POINTERS_CC", 
decode_3dstate_viewport_state_pointers_cc },
+   { "3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP", 
decode_3dstate_viewport_state_pointers_sf_clip },
+   { "3DSTATE_BLEND_STATE_POINTERS", decode_3dstate_blend_state_pointers },
+   { "3DSTATE_CC_STATE_POINTERS", decode_3dstate_cc_state_pointers },
+   { "3DSTATE_SCISSOR_STATE_POINTERS", decode_3dstate_scissor_state_pointers },
 };
 
 static inline uint64_t
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 11/11] intel/tools: Convert aubinator over to the common framework

[Jason Ekstrand]

---
 src/intel/Makefile.tools.am |   1 +
 src/intel/tools/aubinator.c | 719 ++--
 src/intel/tools/meson.build |   3 +-
 3 files changed, 33 insertions(+), 690 deletions(-)

diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am
index 9332ae3..944ee19 100644
--- a/src/intel/Makefile.tools.am
+++ b/src/intel/Makefile.tools.am
@@ -26,6 +26,7 @@ noinst_PROGRAMS += \
 tools_aubinator_SOURCES = \
tools/aubinator.c \
tools/disasm.c \
+   tools/gen_batch_decoder.c \
tools/gen_disasm.h \
tools/intel_aub.h
 
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index c093c1a..ed7446c 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -64,8 +64,8 @@ static enum { COLOR_AUTO, COLOR_ALWAYS, COLOR_NEVER } 
option_color;
 
 uint16_t pci_id = 0;
 char *input_file = NULL, *xml_path = NULL;
-struct gen_spec *spec;
-struct gen_disasm *disasm;
+struct gen_device_info devinfo;
+struct gen_batch_decode_ctx batch_ctx;
 
 uint64_t gtt_size, gtt_end;
 void *gtt;
@@ -95,683 +95,6 @@ valid_offset(uint32_t offset)
return offset < gtt_end;
 }
 
-static void
-decode_group(struct gen_group *strct, const uint32_t *p, int starting_dword)
-{
-   uint64_t offset = option_print_offsets ? (void *) p - gtt : 0;
-
-   gen_print_group(outfile, strct, offset, p, option_color == COLOR_ALWAYS);
-}
-
-static void
-dump_binding_table(struct gen_spec *spec, uint32_t offset)
-{
-   uint32_t *pointers, i;
-   uint64_t start;
-   struct gen_group *surface_state;
-
-   surface_state = gen_spec_find_struct(spec, "RENDER_SURFACE_STATE");
-   if (surface_state == NULL) {
-  fprintf(outfile, "did not find RENDER_SURFACE_STATE info\n");
-  return;
-   }
-
-   start = surface_state_base + offset;
-   pointers = gtt + start;
-   for (i = 0; i < 16; i++) {
-  if (pointers[i] == 0)
- continue;
-  start = pointers[i] + surface_state_base;
-  if (!valid_offset(start)) {
- fprintf(outfile, "pointer %u: %08x \n",
- i, pointers[i]);
- continue;
-  } else {
- fprintf(outfile, "pointer %u: %08x\n", i, pointers[i]);
-  }
-
-  decode_group(surface_state, gtt + start, 0);
-   }
-}
-
-static void
-handle_3dstate_index_buffer(struct gen_spec *spec, uint32_t *p)
-{
-   void *start;
-   uint32_t length, i, type, size;
-
-   start = gtt + p[2];
-   type = (p[1] >> 8) & 3;
-   size = 1 << type;
-   length = p[4] / size;
-   if (length > 10)
-  length = 10;
-
-   fprintf(outfile, "\t");
-
-   for (i = 0; i < length; i++) {
-  switch (type) {
-  case 0:
- fprintf(outfile, "%3d ", ((uint8_t *)start)[i]);
- break;
-  case 1:
- fprintf(outfile, "%3d ", ((uint16_t *)start)[i]);
- break;
-  case 2:
- fprintf(outfile, "%3d ", ((uint32_t *)start)[i]);
- break;
-  }
-   }
-   if (length < p[4] / size)
-  fprintf(outfile, "...\n");
-   else
-  fprintf(outfile, "\n");
-}
-
-static inline uint64_t
-get_address(struct gen_spec *spec, uint32_t *p)
-{
-   /* Addresses are always guaranteed to be page-aligned and sometimes
-* hardware packets have extra stuff stuffed in the bottom 12 bits.
-*/
-   uint64_t addr = p[0] & ~0xfffu;
-
-   if (gen_spec_get_gen(spec) >= gen_make_gen(8,0)) {
-  /* On Broadwell and above, we have 48-bit addresses which consume two
-   * dwords.  Some packets require that these get stored in a "canonical
-   * form" which means that bit 47 is sign-extended through the upper
-   * bits. In order to correctly handle those aub dumps, we need to mask
-   * off the top 16 bits.
-   */
-  addr |= ((uint64_t)p[1] & 0x) << 32;
-   }
-
-   return addr;
-}
-
-static inline uint64_t
-get_offset(uint32_t *p, uint32_t start, uint32_t end)
-{
-   assert(start <= end);
-   assert(end < 64);
-
-   uint64_t mask = (~0ull >> (64 - (end - start + 1))) << start;
-
-   uint64_t offset = p[0];
-   if (end >= 32)
-  offset |= (uint64_t) p[1] << 32;
-
-   return offset & mask;
-}
-
-static void
-handle_state_base_address(struct gen_spec *spec, uint32_t *p)
-{
-   if (gen_spec_get_gen(spec) >= gen_make_gen(8,0)) {
-  if (p[1] & 1)
- general_state_base = get_address(spec, [1]);
-  if (p[4] & 1)
- surface_state_base = get_address(spec, [4]);
-  if (p[6] & 1)
- dynamic_state_base = get_address(spec, [6]);
-  if (p[10] & 1)
- instruction_base = get_address(spec, [10]);
-  if (p[15] & 1)
- instruction_bound = p[15] & 0xfff;
-   } else {
-  if (p[2] & 1)
- surface_state_base = get_address(spec, [2]);
-  if (p[3] & 1)
- dynamic_state_base = get_address(spec, [3]);
-  if (p[5] & 1)
- instruction_base = get_address(spec, [5]);
-  if (p[9] & 1)
- instruction_bound = get_address(spec, [9]);
-   }
-}
-
-static void
-dump_samplers(struct gen_spec *spec, uint32_t 

[Mesa-dev] [PATCH 04/11] intel/batch-decoder: Decode vertex and index buffers

[Jason Ekstrand]

---
 src/intel/common/gen_decoder.h  |   2 +
 src/intel/tools/gen_batch_decoder.c | 159 
 2 files changed, 161 insertions(+)

diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index d401929..2532a36 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -191,6 +191,8 @@ enum gen_batch_decode_flags {
GEN_BATCH_DECODE_FULL  = (1 << 1),
/** Print offsets along with the batch */
GEN_BATCH_DECODE_OFFSETS   = (1 << 2),
+   /** Guess when a value is a float and print it as such */
+   GEN_BATCH_DECODE_FLOATS= (1 << 3),
 };
 
 struct gen_batch_decode_bo {
diff --git a/src/intel/tools/gen_batch_decoder.c 
b/src/intel/tools/gen_batch_decoder.c
index b8c1350..5f46714 100644
--- a/src/intel/tools/gen_batch_decoder.c
+++ b/src/intel/tools/gen_batch_decoder.c
@@ -115,6 +115,57 @@ ctx_disassemble_program(struct gen_batch_decode_ctx *ctx,
   ctx->fp);
 }
 
+/* Heuristic to determine whether a uint32_t is probably actually a float
+ * (http://stackoverflow.com/a/2953466)
+ */
+
+static bool
+probably_float(uint32_t bits)
+{
+   int exp = ((bits & 0x7f80U) >> 23) - 127;
+   uint32_t mant = bits & 0x007f;
+
+   /* +- 0.0 */
+   if (exp == -127 && mant == 0)
+  return true;
+
+   /* +- 1 billionth to 1 billion */
+   if (-30 <= exp && exp <= 30)
+  return true;
+
+   /* some value with only a few binary digits */
+   if ((mant & 0x) == 0)
+  return true;
+
+   return false;
+}
+
+static void
+ctx_print_buffer(struct gen_batch_decode_ctx *ctx,
+ struct gen_batch_decode_bo bo,
+ uint32_t read_length,
+ uint32_t pitch)
+{
+   const uint32_t *dw_end = bo.map + MIN2(bo.size, read_length);
+
+   unsigned line_count = 0;
+   for (const uint32_t *dw = bo.map; dw < dw_end; dw++) {
+  if (line_count * 4 == pitch || line_count == 8) {
+ fprintf(ctx->fp, "\n");
+ line_count = 0;
+  }
+  fprintf(ctx->fp, line_count == 0 ? "  " : " ");
+
+  if ((ctx->flags & GEN_BATCH_DECODE_FLOATS) && probably_float(*dw))
+ fprintf(ctx->fp, "  %8.2f", *(float *) dw);
+  else
+ fprintf(ctx->fp, "  0x%08x", *dw);
+
+  line_count++;
+   }
+   fprintf(ctx->fp, "\n");
+}
+
 static void
 handle_state_base_address(struct gen_batch_decode_ctx *ctx, const uint32_t *p)
 {
@@ -265,12 +316,120 @@ handle_media_interface_descriptor_load(struct 
gen_batch_decode_ctx *ctx,
}
 }
 
+static void
+handle_3dstate_vertex_buffers(struct gen_batch_decode_ctx *ctx,
+  const uint32_t *p)
+{
+   struct gen_group *inst = gen_spec_find_instruction(ctx->spec, p);
+
+   struct gen_batch_decode_bo vb = {};
+   uint32_t vb_size = 0;
+   int index = -1;
+   int pitch = -1;
+   bool ready = false;
+
+   struct gen_field_iterator iter;
+   gen_field_iterator_init(, inst, p, 0, false);
+   do {
+  if (strcmp(iter.name, "Vertex Buffer Index") == 0) {
+ index = iter.raw_value;
+  } else if (strcmp(iter.name, "Buffer Pitch") == 0) {
+ pitch = iter.raw_value;
+  } else if (strcmp(iter.name, "Buffer Starting Address") == 0) {
+ vb = ctx_get_bo(ctx, iter.raw_value);
+  } else if (strcmp(iter.name, "Buffer Size") == 0) {
+ vb_size = iter.raw_value;
+ ready = true;
+  } else if (strcmp(iter.name, "End Address") == 0) {
+ if (vb.map && iter.raw_value >= vb.addr)
+vb_size = iter.raw_value - vb.addr;
+ else
+vb_size = 0;
+ ready = true;
+  }
+
+  if (!ready)
+ continue;
+
+  fprintf(ctx->fp, "vertex buffer %d, size %d\n", index, vb_size);
+
+  if (vb.map == NULL) {
+ fprintf(ctx->fp, "  buffer contents unavailable\n");
+ continue;
+  }
+
+  if (vb.map == 0 || vb_size == 0)
+ continue;
+
+  ctx_print_buffer(ctx, vb, vb_size, pitch);
+
+  vb.map = NULL;
+  vb_size = 0;
+  index = -1;
+  pitch = -1;
+  ready = false;
+   } while (gen_field_iterator_next());
+}
+
+static void
+handle_3dstate_index_buffer(struct gen_batch_decode_ctx *ctx,
+const uint32_t *p)
+{
+   struct gen_group *inst = gen_spec_find_instruction(ctx->spec, p);
+
+   struct gen_batch_decode_bo ib = {};
+   uint32_t ib_size = 0;
+   uint32_t format = 0;
+
+   struct gen_field_iterator iter;
+   gen_field_iterator_init(, inst, p, 0, false);
+   do {
+  if (strcmp(iter.name, "Index Format") == 0) {
+ format = iter.raw_value;
+  } else if (strcmp(iter.name, "Buffer Starting Address") == 0) {
+ ib = ctx_get_bo(ctx, iter.raw_value);
+  } else if (strcmp(iter.name, "Buffer Size") == 0) {
+ ib_size = iter.raw_value;
+  }
+   } while (gen_field_iterator_next());
+
+   if (ib.map == NULL) {
+  fprintf(ctx->fp, "  buffer contents unavailable\n");
+  return;
+   }
+
+   const void *m = 

[Mesa-dev] [PATCH 08/11] intel/decoder: Add a gen_print_group_length helper

[Jason Ekstrand]

---
 src/intel/common/gen_decoder.c | 17 ++---
 src/intel/common/gen_decoder.h |  5 +
 2 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 1f6b984..c6ddae0 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -1014,7 +1014,7 @@ gen_field_is_header(struct gen_field *field)
 
 static void
 _gen_print_group(FILE *outfile, struct gen_group *group, uint64_t offset,
- const uint32_t *p, int p_bit, bool color)
+ const uint32_t *p, int p_bit, int dw_length, bool color)
 {
struct gen_field_iterator iter;
int last_dword = -1;
@@ -1022,6 +1022,9 @@ _gen_print_group(FILE *outfile, struct gen_group *group, 
uint64_t offset,
gen_field_iterator_init(, group, p, p_bit, color);
do {
   int iter_dword = iter.bit / 32;
+  if (dw_length >= 0 && iter_dword >= dw_length)
+ break;
+
   if (last_dword != iter_dword) {
  for (int i = last_dword + 1; i <= iter_dword; i++)
 print_dword_header(outfile, , offset, i);
@@ -1032,7 +1035,8 @@ _gen_print_group(FILE *outfile, struct gen_group *group, 
uint64_t offset,
  if (iter.struct_desc) {
 uint64_t struct_offset = offset + 4 * iter_dword;
 _gen_print_group(outfile, iter.struct_desc, struct_offset,
- [iter_dword], iter.bit % 32, color);
+ [iter_dword], iter.bit % 32,
+ dw_length - iter_dword, color);
  }
   }
} while (gen_field_iterator_next());
@@ -1042,5 +1046,12 @@ void
 gen_print_group(FILE *outfile, struct gen_group *group, uint64_t offset,
 const uint32_t *p, bool color)
 {
-   _gen_print_group(outfile, group, offset, p, 0, color);
+   _gen_print_group(outfile, group, offset, p, 0, -1, color);
+}
+
+void
+gen_print_group_length(FILE *outfile, struct gen_group *group, uint64_t offset,
+   const uint32_t *p, int dw_length, bool color)
+{
+   _gen_print_group(outfile, group, offset, p, 0, dw_length, color);
 }
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index 2532a36..300dd8f 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -184,6 +184,11 @@ void gen_print_group(FILE *out,
  uint64_t offset, const uint32_t *p,
  bool color);
 
+void gen_print_group_length(FILE *out,
+struct gen_group *group,
+uint64_t offset, const uint32_t *p,
+int dw_length, bool color);
+
 enum gen_batch_decode_flags {
/** Print in color! */
GEN_BATCH_DECODE_IN_COLOR  = (1 << 0),
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 03/11] intel/batch-decoder: Decode MEDIA_INTERFACE_DESCRIPTOR_LOAD

[Jason Ekstrand]

---
 src/intel/tools/gen_batch_decoder.c | 145 
 1 file changed, 145 insertions(+)

diff --git a/src/intel/tools/gen_batch_decoder.c 
b/src/intel/tools/gen_batch_decoder.c
index 8d9f15e..b8c1350 100644
--- a/src/intel/tools/gen_batch_decoder.c
+++ b/src/intel/tools/gen_batch_decoder.c
@@ -103,6 +103,19 @@ ctx_get_bo(struct gen_batch_decode_ctx *ctx, uint64_t addr)
 }
 
 static void
+ctx_disassemble_program(struct gen_batch_decode_ctx *ctx,
+uint32_t ksp, const char *type)
+{
+   if (!ctx->instruction_base.map)
+  return;
+
+   printf("\nReferenced %s:\n", type);
+   gen_disasm_disassemble(ctx->disasm,
+  (void *)ctx->instruction_base.map, ksp,
+  ctx->fp);
+}
+
+static void
 handle_state_base_address(struct gen_batch_decode_ctx *ctx, const uint32_t *p)
 {
struct gen_group *inst = gen_spec_find_instruction(ctx->spec, p);
@@ -121,11 +134,143 @@ handle_state_base_address(struct gen_batch_decode_ctx 
*ctx, const uint32_t *p)
} while (gen_field_iterator_next());
 }
 
+static void
+dump_binding_table(struct gen_batch_decode_ctx *ctx, uint32_t offset, int 
count)
+{
+   struct gen_group *strct =
+  gen_spec_find_struct(ctx->spec, "RENDER_SURFACE_STATE");
+   if (strct == NULL) {
+  fprintf(ctx->fp, "did not find RENDER_SURFACE_STATE info\n");
+  return;
+   }
+
+   /* If we don't know the actual count, guess. */
+   if (count < 0)
+  count = 8;
+
+   if (ctx->surface_base.map == NULL) {
+  fprintf(ctx->fp, "  binding table unavailable\n");
+  return;
+   }
+
+   if (offset % 32 != 0 || offset >= UINT16_MAX ||
+   offset >= ctx->surface_base.size) {
+  fprintf(ctx->fp, "  invalid binding table pointer\n");
+  return;
+   }
+
+   const uint32_t *pointers = ctx->surface_base.map + offset;
+   for (int i = 0; i < count; i++) {
+  if (pointers[i] == 0)
+ continue;
+
+  if (pointers[i] % 32 != 0 ||
+  (pointers[i] + strct->dw_length * 4) >= ctx->surface_base.size) {
+ fprintf(ctx->fp, "pointer %u: %08x \n", i, pointers[i]);
+ continue;
+  }
+
+  fprintf(ctx->fp, "pointer %u: %08x\n", i, pointers[i]);
+  ctx_print_group(ctx, strct, ctx->surface_base.addr + pointers[i],
+  ctx->surface_base.map + pointers[i]);
+   }
+}
+
+static void
+dump_samplers(struct gen_batch_decode_ctx *ctx, uint32_t offset, int count)
+{
+   struct gen_group *strct = gen_spec_find_struct(ctx->spec, "SAMPLER_STATE");
+
+   /* If we don't know the actual count, guess. */
+   if (count < 0)
+  count = 4;
+
+   if (ctx->dynamic_base.map == NULL) {
+  fprintf(ctx->fp, "  samplers unavailable\n");
+  return;
+   }
+
+   if (offset % 32 != 0 || offset >= ctx->dynamic_base.size) {
+  fprintf(ctx->fp, "  invalid sampler state pointer\n");
+  return;
+   }
+
+   uint64_t state_addr = ctx->dynamic_base.addr + offset;
+   const void *state_map = ctx->dynamic_base.map + offset;
+   for (int i = 0; i < count; i++) {
+  fprintf(ctx->fp, "sampler state %d\n", i);
+  ctx_print_group(ctx, strct, state_addr, state_map);
+  state_addr += 16;
+  state_map += 16;
+   }
+}
+
+static void
+handle_media_interface_descriptor_load(struct gen_batch_decode_ctx *ctx,
+   const uint32_t *p)
+{
+   if (ctx->dynamic_base.map == NULL)
+  return;
+
+   struct gen_group *inst = gen_spec_find_instruction(ctx->spec, p);
+   struct gen_group *desc =
+  gen_spec_find_struct(ctx->spec, "INTERFACE_DESCRIPTOR_DATA");
+
+   struct gen_field_iterator iter;
+   gen_field_iterator_init(, inst, p, 0, false);
+   uint32_t descriptor_offset = 0;
+   int descriptor_count = 0;
+   do {
+  if (strcmp(iter.name, "Interface Descriptor Data Start Address") == 0) {
+ descriptor_offset = strtol(iter.value, NULL, 16);
+  } else if (strcmp(iter.name, "Interface Descriptor Total Length") == 0) {
+ descriptor_count =
+strtol(iter.value, NULL, 16) / (desc->dw_length * 4);
+  }
+   } while (gen_field_iterator_next());
+
+   uint64_t desc_addr = ctx->dynamic_base.addr + descriptor_offset;
+   const uint32_t *desc_map = ctx->dynamic_base.map + descriptor_offset;
+   for (int i = 0; i < descriptor_count; i++) {
+  fprintf(ctx->fp, "descriptor %d: %08x\n", i, descriptor_offset);
+
+  ctx_print_group(ctx, inst, desc_addr, desc_map);
+
+  gen_field_iterator_init(, desc, desc_map, 0, false);
+  uint64_t ksp;
+  uint32_t sampler_offset, sampler_count;
+  uint32_t binding_table_offset, binding_entry_count;
+  do {
+ if (strcmp(iter.name, "Kernel Start Pointer") == 0) {
+ksp = strtoll(iter.value, NULL, 16);
+ } else if (strcmp(iter.name, "Sampler State Pointer") == 0) {
+sampler_offset = strtol(iter.value, NULL, 16);
+ } else if (strcmp(iter.name, "Sampler Count") == 0) {
+sampler_count = 

[Mesa-dev] [PATCH 07/11] intel/batch-decoder: Decode constants, binding tables, and samplers

[Jason Ekstrand]

---
 src/intel/tools/gen_batch_decoder.c | 73 +
 1 file changed, 73 insertions(+)

diff --git a/src/intel/tools/gen_batch_decoder.c 
b/src/intel/tools/gen_batch_decoder.c
index f7064b1..5b01879 100644
--- a/src/intel/tools/gen_batch_decoder.c
+++ b/src/intel/tools/gen_batch_decoder.c
@@ -512,6 +512,61 @@ decode_ps_kernels(struct gen_batch_decode_ctx *ctx, const 
uint32_t *p)
fprintf(ctx->fp, "\n");
 }
 
+static void
+decode_3dstate_constant(struct gen_batch_decode_ctx *ctx, const uint32_t *p)
+{
+   struct gen_group *inst = gen_spec_find_instruction(ctx->spec, p);
+
+   uint32_t read_length[4];
+   struct gen_batch_decode_bo buffer[4];
+   memset(buffer, 0, sizeof(buffer));
+
+   int rlidx = 0, bidx = 0;
+
+   struct gen_field_iterator iter;
+   gen_field_iterator_init(, inst, p, 0, false);
+   do {
+  if (strcmp(iter.name, "Read Length") == 0) {
+ read_length[rlidx++] = iter.raw_value;
+  } else if (strcmp(iter.name, "Buffer") == 0) {
+ buffer[bidx++] = ctx_get_bo(ctx, iter.raw_value);
+  }
+   } while (gen_field_iterator_next());
+
+   for (int i = 0; i < 4; i++) {
+  if (read_length[i] == 0 || buffer[i].map == NULL)
+ continue;
+
+  unsigned size = read_length[i] * 32;
+  fprintf(ctx->fp, "constant buffer %d, size %u\n", i, size);
+
+  ctx_print_buffer(ctx, buffer[i], size, 0);
+   }
+}
+
+static void
+decode_3dstate_binding_table_pointers(struct gen_batch_decode_ctx *ctx,
+  const uint32_t *p)
+{
+   dump_binding_table(ctx, p[1], -1);
+}
+
+static void
+decode_3dstate_sampler_state_pointers(struct gen_batch_decode_ctx *ctx,
+  const uint32_t *p)
+{
+   dump_samplers(ctx, p[1], -1);
+}
+
+static void
+decode_3dstate_sampler_state_pointers_gen6(struct gen_batch_decode_ctx *ctx,
+   const uint32_t *p)
+{
+   dump_samplers(ctx, p[1], -1);
+   dump_samplers(ctx, p[2], -1);
+   dump_samplers(ctx, p[3], -1);
+}
+
 struct custom_decoder {
const char *cmd_name;
void (*decode)(struct gen_batch_decode_ctx *ctx, const uint32_t *p);
@@ -525,6 +580,24 @@ struct custom_decoder {
{ "3DSTATE_DS", decode_single_ksp },
{ "3DSTATE_HS", decode_single_ksp },
{ "3DSTATE_PS", decode_ps_kernels },
+   { "3DSTATE_CONSTANT_VS", decode_3dstate_constant },
+   { "3DSTATE_CONSTANT_GS", decode_3dstate_constant },
+   { "3DSTATE_CONSTANT_PS", decode_3dstate_constant },
+   { "3DSTATE_CONSTANT_HS", decode_3dstate_constant },
+   { "3DSTATE_CONSTANT_DS", decode_3dstate_constant },
+
+   { "3DSTATE_BINDING_TABLE_POINTERS_VS", 
decode_3dstate_binding_table_pointers },
+   { "3DSTATE_BINDING_TABLE_POINTERS_HS", 
decode_3dstate_binding_table_pointers },
+   { "3DSTATE_BINDING_TABLE_POINTERS_DS", 
decode_3dstate_binding_table_pointers },
+   { "3DSTATE_BINDING_TABLE_POINTERS_GS", 
decode_3dstate_binding_table_pointers },
+   { "3DSTATE_BINDING_TABLE_POINTERS_PS", 
decode_3dstate_binding_table_pointers },
+
+   { "3DSTATE_SAMPLER_STATE_POINTERS_VS", 
decode_3dstate_sampler_state_pointers },
+   { "3DSTATE_SAMPLER_STATE_POINTERS_HS", 
decode_3dstate_sampler_state_pointers },
+   { "3DSTATE_SAMPLER_STATE_POINTERS_DS", 
decode_3dstate_sampler_state_pointers },
+   { "3DSTATE_SAMPLER_STATE_POINTERS_GS", 
decode_3dstate_sampler_state_pointers },
+   { "3DSTATE_SAMPLER_STATE_POINTERS_PS", 
decode_3dstate_sampler_state_pointers },
+   { "3DSTATE_SAMPLER_STATE_POINTERS", 
decode_3dstate_sampler_state_pointers_gen6 },
 };
 
 static inline uint64_t
-- 
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[Mesa-dev] [PATCH 05/11] intel/batch-decoder: Decode graphics shaders

[Jason Ekstrand]

---
 src/intel/tools/gen_batch_decoder.c | 95 +
 1 file changed, 95 insertions(+)

diff --git a/src/intel/tools/gen_batch_decoder.c 
b/src/intel/tools/gen_batch_decoder.c
index 5f46714..f7064b1 100644
--- a/src/intel/tools/gen_batch_decoder.c
+++ b/src/intel/tools/gen_batch_decoder.c
@@ -422,6 +422,96 @@ handle_3dstate_index_buffer(struct gen_batch_decode_ctx 
*ctx,
fprintf(ctx->fp, "\n");
 }
 
+static void
+decode_single_ksp(struct gen_batch_decode_ctx *ctx, const uint32_t *p)
+{
+   struct gen_group *inst = gen_spec_find_instruction(ctx->spec, p);
+
+   uint64_t ksp = 0;
+   bool is_simd8 = false; /* vertex shaders on Gen8+ only */
+   bool is_enabled = true;
+
+   struct gen_field_iterator iter;
+   gen_field_iterator_init(, inst, p, 0, false);
+   do {
+  if (strcmp(iter.name, "Kernel Start Pointer") == 0) {
+ ksp = iter.raw_value;
+  } else if (strcmp(iter.name, "SIMD8 Dispatch Enable") == 0) {
+ is_simd8 = iter.raw_value;
+  } else if (strcmp(iter.name, "Dispatch Mode") == 0) {
+ is_simd8 = strcmp(iter.value, "SIMD8") == 0;
+  } else if (strcmp(iter.name, "Dispatch Enable") == 0) {
+ is_simd8 = strcmp(iter.value, "SIMD8") == 0;
+  } else if (strcmp(iter.name, "Enable") == 0) {
+ is_enabled = iter.raw_value;
+  }
+   } while (gen_field_iterator_next());
+
+   const char *type =
+  strcmp(inst->name,   "VS_STATE") == 0 ? "vertex shader" :
+  strcmp(inst->name,   "GS_STATE") == 0 ? "geometry shader" :
+  strcmp(inst->name,   "SF_STATE") == 0 ? "strips and fans shader" :
+  strcmp(inst->name, "CLIP_STATE") == 0 ? "clip shader" :
+  strcmp(inst->name, "3DSTATE_DS") == 0 ? "tessellation control shader" :
+  strcmp(inst->name, "3DSTATE_HS") == 0 ? "tessellation evaluation shader" 
:
+  strcmp(inst->name, "3DSTATE_VS") == 0 ? (is_simd8 ? "SIMD8 vertex 
shader" : "vec4 vertex shader") :
+  strcmp(inst->name, "3DSTATE_GS") == 0 ? (is_simd8 ? "SIMD8 geometry 
shader" : "vec4 geometry shader") :
+  NULL;
+
+   if (is_enabled) {
+  ctx_disassemble_program(ctx, ksp, type);
+  printf("\n");
+   }
+}
+
+static void
+decode_ps_kernels(struct gen_batch_decode_ctx *ctx, const uint32_t *p)
+{
+   struct gen_group *inst = gen_spec_find_instruction(ctx->spec, p);
+
+   uint64_t ksp[3] = {0, 0, 0};
+   bool enabled[3] = {false, false, false};
+
+   struct gen_field_iterator iter;
+   gen_field_iterator_init(, inst, p, 0, false);
+   do {
+  if (strncmp(iter.name, "Kernel Start Pointer ",
+  strlen("Kernel Start Pointer ")) == 0) {
+ int idx = iter.name[strlen("Kernel Start Pointer ")] - '0';
+ ksp[idx] = strtol(iter.value, NULL, 16);
+  } else if (strcmp(iter.name, "8 Pixel Dispatch Enable") == 0) {
+ enabled[0] = strcmp(iter.value, "true") == 0;
+  } else if (strcmp(iter.name, "16 Pixel Dispatch Enable") == 0) {
+ enabled[1] = strcmp(iter.value, "true") == 0;
+  } else if (strcmp(iter.name, "32 Pixel Dispatch Enable") == 0) {
+ enabled[2] = strcmp(iter.value, "true") == 0;
+  }
+   } while (gen_field_iterator_next());
+
+   /* Reorder KSPs to be [8, 16, 32] instead of the hardware order. */
+   if (enabled[0] + enabled[1] + enabled[2] == 1) {
+  if (enabled[1]) {
+ ksp[1] = ksp[0];
+ ksp[0] = 0;
+  } else if (enabled[2]) {
+ ksp[2] = ksp[0];
+ ksp[0] = 0;
+  }
+   } else {
+  uint64_t tmp = ksp[1];
+  ksp[1] = ksp[2];
+  ksp[2] = tmp;
+   }
+
+   if (enabled[0])
+  ctx_disassemble_program(ctx, ksp[0], "SIMD8 fragment shader");
+   if (enabled[1])
+  ctx_disassemble_program(ctx, ksp[1], "SIMD16 fragment shader");
+   if (enabled[2])
+  ctx_disassemble_program(ctx, ksp[2], "SIMD32 fragment shader");
+   fprintf(ctx->fp, "\n");
+}
+
 struct custom_decoder {
const char *cmd_name;
void (*decode)(struct gen_batch_decode_ctx *ctx, const uint32_t *p);
@@ -430,6 +520,11 @@ struct custom_decoder {
{ "MEDIA_INTERFACE_DESCRIPTOR_LOAD", handle_media_interface_descriptor_load 
},
{ "3DSTATE_VERTEX_BUFFERS", handle_3dstate_vertex_buffers },
{ "3DSTATE_INDEX_BUFFER", handle_3dstate_index_buffer },
+   { "3DSTATE_VS", decode_single_ksp },
+   { "3DSTATE_GS", decode_single_ksp },
+   { "3DSTATE_DS", decode_single_ksp },
+   { "3DSTATE_HS", decode_single_ksp },
+   { "3DSTATE_PS", decode_ps_kernels },
 };
 
 static inline uint64_t
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 06/11] intel/tools: Switch aubinator_error_decode over to the gen_print_batch

[Jason Ekstrand]

The shared framework can now do everything that aubinator_error_decode
ever did and more.  It's time to make the switch.
---
 src/intel/Makefile.tools.am  |   1 +
 src/intel/tools/aubinator_error_decode.c | 238 +--
 src/intel/tools/meson.build  |   3 +-
 3 files changed, 37 insertions(+), 205 deletions(-)

diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am
index af8cd5b..9332ae3 100644
--- a/src/intel/Makefile.tools.am
+++ b/src/intel/Makefile.tools.am
@@ -47,6 +47,7 @@ tools_aubinator_LDADD = \
 tools_aubinator_error_decode_SOURCES = \
tools/aubinator_error_decode.c \
tools/disasm.c \
+   tools/gen_batch_decoder.c \
tools/gen_disasm.h
 
 tools_aubinator_error_decode_LDADD = \
diff --git a/src/intel/tools/aubinator_error_decode.c 
b/src/intel/tools/aubinator_error_decode.c
index 21569d7..397ae94 100644
--- a/src/intel/tools/aubinator_error_decode.c
+++ b/src/intel/tools/aubinator_error_decode.c
@@ -40,7 +40,6 @@
 
 #include "common/gen_decoder.h"
 #include "util/macros.h"
-#include "gen_disasm.h"
 
 #define CSI "\e["
 #define BLUE_HEADER  CSI "0;44m"
@@ -223,204 +222,6 @@ struct section {
 #define MAX_SECTIONS 30
 static struct section sections[MAX_SECTIONS];
 
-static void
-disassemble_program(struct gen_disasm *disasm, const char *type,
-const struct section *instruction_section,
-uint64_t ksp)
-{
-   if (!instruction_section)
-  return;
-
-   printf("\nReferenced %s:\n", type);
-   gen_disasm_disassemble(disasm, instruction_section->data, ksp, stdout);
-}
-
-static const struct section *
-find_section(const char *str_base_address)
-{
-   uint64_t base_address = strtol(str_base_address, NULL, 16);
-   for (int s = 0; s < MAX_SECTIONS; s++) {
-  if (sections[s].gtt_offset == base_address)
- return [s];
-   }
-   return NULL;
-}
-
-static void
-decode(struct gen_spec *spec, struct gen_disasm *disasm,
-   const struct section *section)
-{
-   uint64_t gtt_offset = section->gtt_offset;
-   uint32_t *data = section->data;
-   uint32_t *p, *end = (data + section->count);
-   int length;
-   struct gen_group *inst;
-   const struct section *current_instruction_buffer = NULL;
-   const struct section *current_dynamic_state_buffer = NULL;
-
-   for (p = data; p < end; p += length) {
-  const char *color = option_full_decode ? BLUE_HEADER : NORMAL,
- *reset_color = NORMAL;
-  uint64_t offset = gtt_offset + 4 * (p - data);
-
-  inst = gen_spec_find_instruction(spec, p);
-  length = gen_group_get_length(inst, p);
-  assert(inst == NULL || length > 0);
-  length = MAX2(1, length);
-  if (inst == NULL) {
- printf("unknown instruction %08x\n", p[0]);
- continue;
-  }
-  if (option_color == COLOR_NEVER) {
- color = "";
- reset_color = "";
-  }
-
-  printf("%s0x%08"PRIx64":  0x%08x:  %-80s%s\n",
- color, offset, p[0], gen_group_get_name(inst), reset_color);
-
-  gen_print_group(stdout, inst, offset, p, 0,
-  option_color == COLOR_ALWAYS);
-
-  if (strcmp(inst->name, "MI_BATCH_BUFFER_END") == 0)
- break;
-
-  if (strcmp(inst->name, "STATE_BASE_ADDRESS") == 0) {
- struct gen_field_iterator iter;
- gen_field_iterator_init(, inst, p, 0, false);
-
- do {
-if (strcmp(iter.name, "Instruction Base Address") == 0) {
-   current_instruction_buffer = find_section(iter.value);
-} else if (strcmp(iter.name, "Dynamic State Base Address") == 0) {
-   current_dynamic_state_buffer = find_section(iter.value);
-}
- } while (gen_field_iterator_next());
-  } else if (strcmp(inst->name,   "WM_STATE") == 0 ||
- strcmp(inst->name, "3DSTATE_PS") == 0 ||
- strcmp(inst->name, "3DSTATE_WM") == 0) {
- struct gen_field_iterator iter;
- gen_field_iterator_init(, inst, p, 0, false);
- uint64_t ksp[3] = {0, 0, 0};
- bool enabled[3] = {false, false, false};
-
- do {
-if (strncmp(iter.name, "Kernel Start Pointer ",
-strlen("Kernel Start Pointer ")) == 0) {
-   int idx = iter.name[strlen("Kernel Start Pointer ")] - '0';
-   ksp[idx] = strtol(iter.value, NULL, 16);
-} else if (strcmp(iter.name, "8 Pixel Dispatch Enable") == 0) {
-   enabled[0] = strcmp(iter.value, "true") == 0;
-} else if (strcmp(iter.name, "16 Pixel Dispatch Enable") == 0) {
-   enabled[1] = strcmp(iter.value, "true") == 0;
-} else if (strcmp(iter.name, "32 Pixel Dispatch Enable") == 0) {
-   enabled[2] = strcmp(iter.value, "true") == 0;
-}
- } while (gen_field_iterator_next());
-
- /* Reorder KSPs to be [8, 16, 32] instead of the hardware order. */
- if (enabled[0] + 

[Mesa-dev] [PATCH 02/11] intel/tools: Add the start of a generic batch decoder

[Jason Ekstrand]

---
 src/intel/common/gen_decoder.h  |  48 +++
 src/intel/tools/gen_batch_decoder.c | 258 
 2 files changed, 306 insertions(+)
 create mode 100644 src/intel/tools/gen_batch_decoder.c

diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index 7b141ec..d401929 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -26,6 +26,7 @@
 
 #include 
 #include 
+#include 
 
 #include "common/gen_device_info.h"
 #include "util/hash_table.h"
@@ -183,6 +184,53 @@ void gen_print_group(FILE *out,
  uint64_t offset, const uint32_t *p,
  bool color);
 
+enum gen_batch_decode_flags {
+   /** Print in color! */
+   GEN_BATCH_DECODE_IN_COLOR  = (1 << 0),
+   /** Print everything, not just headers */
+   GEN_BATCH_DECODE_FULL  = (1 << 1),
+   /** Print offsets along with the batch */
+   GEN_BATCH_DECODE_OFFSETS   = (1 << 2),
+};
+
+struct gen_batch_decode_bo {
+   uint64_t addr;
+   uint32_t size;
+   const void *map;
+};
+
+struct gen_disasm *disasm;
+
+struct gen_batch_decode_ctx {
+   struct gen_batch_decode_bo (*get_bo)(void *user_data,
+uint64_t base_address);
+   void *user_data;
+
+   FILE *fp;
+   struct gen_spec *spec;
+   enum gen_batch_decode_flags flags;
+
+   struct gen_disasm *disasm;
+
+   struct gen_batch_decode_bo surface_base;
+   struct gen_batch_decode_bo dynamic_base;
+   struct gen_batch_decode_bo instruction_base;
+};
+
+void gen_batch_decode_ctx_init(struct gen_batch_decode_ctx *ctx,
+   const struct gen_device_info *devinfo,
+   FILE *fp, enum gen_batch_decode_flags flags,
+   const char *xml_path,
+   struct gen_batch_decode_bo (*get_bo)(void *,
+uint64_t),
+   void *user_data);
+void gen_batch_decode_ctx_finish(struct gen_batch_decode_ctx *ctx);
+
+
+void gen_print_batch(struct gen_batch_decode_ctx *ctx,
+ const uint32_t *batch, uint32_t batch_size,
+ uint64_t batch_addr);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/intel/tools/gen_batch_decoder.c 
b/src/intel/tools/gen_batch_decoder.c
new file mode 100644
index 000..8d9f15e
--- /dev/null
+++ b/src/intel/tools/gen_batch_decoder.c
@@ -0,0 +1,258 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "common/gen_decoder.h"
+#include "gen_disasm.h"
+
+#include 
+
+void
+gen_batch_decode_ctx_init(struct gen_batch_decode_ctx *ctx,
+  const struct gen_device_info *devinfo,
+  FILE *fp, enum gen_batch_decode_flags flags,
+  const char *xml_path,
+  struct gen_batch_decode_bo (*get_bo)(void *,
+   uint64_t),
+  void *user_data)
+{
+   memset(ctx, 0, sizeof(*ctx));
+
+   ctx->get_bo = get_bo;
+   ctx->user_data = user_data;
+   ctx->fp = fp;
+   ctx->flags = flags;
+
+   if (xml_path == NULL)
+  ctx->spec = gen_spec_load(devinfo);
+   else
+  ctx->spec = gen_spec_load_from_path(devinfo, xml_path);
+   ctx->disasm = gen_disasm_create(devinfo);
+}
+
+void
+gen_batch_decode_ctx_finish(struct gen_batch_decode_ctx *ctx)
+{
+   gen_spec_destroy(ctx->spec);
+   gen_disasm_destroy(ctx->disasm);
+}
+
+#define CSI "\e["
+#define BLUE_HEADER  CSI "0;44m"
+#define GREEN_HEADER CSI "1;42m"
+#define NORMAL   CSI "0m"
+
+#define ARRAY_LENGTH(a) (sizeof (a) / sizeof (a)[0])
+
+static void
+ctx_print_group(struct gen_batch_decode_ctx *ctx,
+struct gen_group *group,
+uint64_t address, const void *map)
+{
+   

[Mesa-dev] [PATCH 01/11] intel/decoder: Expose the raw field value in the iterator

[Jason Ekstrand]

---
 src/intel/common/gen_decoder.c | 3 ++-
 src/intel/common/gen_decoder.h | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 333b5ab..1f6b984 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -889,10 +889,11 @@ iter_decode_field(struct gen_field_iterator *iter)
 
memset(, 0, sizeof(v));
 
-   v.qw = iter_decode_field_raw(iter);
+   iter->raw_value = iter_decode_field_raw(iter);
 
const char *enum_name = NULL;
 
+   v.qw = iter->raw_value;
switch (iter->field->type.kind) {
case GEN_TYPE_UNKNOWN:
case GEN_TYPE_INT: {
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index 7516042..7b141ec 100644
--- a/src/intel/common/gen_decoder.h
+++ b/src/intel/common/gen_decoder.h
@@ -67,6 +67,7 @@ struct gen_field_iterator {
struct gen_group *group;
char name[128];
char value[128];
+   uint64_t raw_value;
struct gen_group *struct_desc;
const uint32_t *p;
int p_bit; /**< bit offset into p */
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 00/11] intel/tools: Unify batch decoding between aubinators

[Jason Ekstrand]

Both aubinator and aubinator_error_decode try and do the same task of
decoding batches.  They both have code to try and decode various things
such as shaders from the batch.  All of that code is completely different
between the two.

This little series reworks the two to use a common gen_print_batch
function.  In order to handle dynamic states, a callback is provided that
lets the decoder ask for a mapped buffer given a memory address.  The basic
structure of the new code is taken from aubinator but many of the state
decoding details are taken from aubinator_error_decode.  This new version
should have all the goodness of both.  In particular, aubinator_error_decode
should now properly handle 48-bit addresses (not well tested) and it should
also be able to handle batch chaining.  Meanwhile, aubinator gains the
field-based decoding scheme so there are a lot fewer gen-specific manual
decoding paths.  Everyone wins!

The reason I haven't converted INTEL_DEBUG=bat yet is treefold:

 1) We really should come up with some mechanism to say how many dynamic
states you have for a given pointers packet.  We could do some sort of
callback but, if we want it to work for aubinator or error_decode, we
will need some form of batch annotations.

 2) I'm not convinced I didn't break gen4-5.  (I don't think it worked in
either of those tools in the first place).

 3) I put it in src/intel/tools because I really don't want to rewrite the
build system right now to put it somewhere more common.  We can't put
it in src/intel/common along with the other decoder stuff because it
depends on the compiler and we don't want i965 to depend on
src/intel/tools.

Jason Ekstrand (11):
  intel/decoder: Expose the raw field value in the iterator
  intel/tools: Add the start of a generic batch decoder
  intel/batch-decoder: Decode MEDIA_INTERFACE_DESCRIPTOR_LOAD
  intel/batch-decoder: Decode vertex and index buffers
  intel/batch-decoder: Decode graphics shaders
  intel/tools: Switch aubinator_error_decode over to the gen_print_batch
  intel/batch-decoder: Decode constants, binding tables, and samplers
  intel/decoder: Add a gen_print_group_length helper
  intel/batch-decoder: Decode dynamic state
  intel/batch-decoder: Decode registers
  intel/tools: Convert aubinator over to the common framework

 src/intel/Makefile.tools.am  |   2 +
 src/intel/common/gen_decoder.c   |  20 +-
 src/intel/common/gen_decoder.h   |  56 +++
 src/intel/tools/aubinator.c  | 719 ++
 src/intel/tools/aubinator_error_decode.c | 238 ++---
 src/intel/tools/gen_batch_decoder.c  | 834 +++
 src/intel/tools/meson.build  |   6 +-
 7 files changed, 976 insertions(+), 899 deletions(-)
 create mode 100644 src/intel/tools/gen_batch_decoder.c

-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH 2/2] gallium/u_blitter: enable MSAA when blitting to MSAA surfaces

[Brian Paul]

I'm actually going to drop these patches for now.  It seems that 
implicitly enabling MSAA when the sample mask != ~0 is expected behavior 
with D3D and some (most?) hardware, including our virtual GPU (I'm 
fixing a bug there).


-Brian

On 12/13/2017 12:35 PM, Marek Olšák wrote:

Reviewed-by: Marek Olšák 

Marek

On Mon, Dec 11, 2017 at 9:09 PM, Brian Paul  wrote:

If we're doing a Z -> Z MSAA blit (for example) we need to enable
msaa rasterization when drawing the quads so that we can properly
write the per-sample values.

This fixes a number of Piglit ext_framebuffer_multisample blit tests
such as ext_framebuffer_multisample/no-color 2 depth combined with
the VMware driver.

v2: This depends on the previous patch to save/set/restore the
min_samples state.
---
  src/gallium/auxiliary/util/u_blitter.c | 54 +-
  1 file changed, 33 insertions(+), 21 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_blitter.c 
b/src/gallium/auxiliary/util/u_blitter.c
index 371daf1..acb9fcf 100644
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -123,7 +123,8 @@ struct blitter_context_priv
 void *sampler_state_rect_linear;

 /* Rasterizer state. */
-   void *rs_state, *rs_state_scissor, *rs_discard_state;
+   void *rs_state[2][2];  /**< [scissor][msaa] */
+   void *rs_discard_state;

 /* Destination surface dimensions. */
 unsigned dst_width;
@@ -275,13 +276,19 @@ struct blitter_context *util_blitter_create(struct 
pipe_context *pipe)
 rs_state.bottom_edge_rule = 1;
 rs_state.flatshade = 1;
 rs_state.depth_clip = 1;
-   ctx->rs_state = pipe->create_rasterizer_state(pipe, _state);

-   rs_state.scissor = 1;
-   ctx->rs_state_scissor = pipe->create_rasterizer_state(pipe, _state);
+   unsigned scissor, msaa;
+   for (scissor = 0; scissor < 2; scissor++) {
+  for (msaa = 0; msaa < 2; msaa++) {
+ rs_state.scissor = scissor;
+ rs_state.multisample = msaa;
+ ctx->rs_state[scissor][msaa] =
+pipe->create_rasterizer_state(pipe, _state);
+  }
+   }

 if (ctx->has_stream_out) {
-  rs_state.scissor = 0;
+  rs_state.scissor = rs_state.multisample = 0;
rs_state.rasterizer_discard = 1;
ctx->rs_discard_state = pipe->create_rasterizer_state(pipe, _state);
 }
@@ -454,8 +461,13 @@ void util_blitter_destroy(struct blitter_context *blitter)
 pipe->delete_depth_stencil_alpha_state(pipe, ctx->dsa_write_depth_stencil);
 pipe->delete_depth_stencil_alpha_state(pipe, 
ctx->dsa_keep_depth_write_stencil);

-   pipe->delete_rasterizer_state(pipe, ctx->rs_state);
-   pipe->delete_rasterizer_state(pipe, ctx->rs_state_scissor);
+   unsigned scissor, msaa;
+   for (scissor = 0; scissor < 2; scissor++) {
+  for (msaa = 0; msaa < 2; msaa++) {
+ pipe->delete_rasterizer_state(pipe, ctx->rs_state[scissor][msaa]);
+  }
+   }
+
 if (ctx->rs_discard_state)
pipe->delete_rasterizer_state(pipe, ctx->rs_discard_state);
 if (ctx->vs)
@@ -1222,12 +1234,12 @@ void util_blitter_cache_all_shaders(struct 
blitter_context *blitter)
  }

  static void blitter_set_common_draw_rect_state(struct blitter_context_priv 
*ctx,
-   bool scissor)
+   bool scissor, bool msaa)
  {
 struct pipe_context *pipe = ctx->base.pipe;

-   pipe->bind_rasterizer_state(pipe, scissor ? ctx->rs_state_scissor
- : ctx->rs_state);
+   pipe->bind_rasterizer_state(pipe, ctx->rs_state[scissor][msaa]);
+
 if (ctx->has_geometry_shader)
pipe->bind_gs_state(pipe, NULL);
 if (ctx->has_tessellation) {
@@ -1401,7 +1413,7 @@ static void util_blitter_clear_custom(struct 
blitter_context *blitter,
 if (num_layers > 1 && ctx->has_layered) {
blitter_get_vs_func get_vs = get_vs_layered;

-  blitter_set_common_draw_rect_state(ctx, false);
+  blitter_set_common_draw_rect_state(ctx, false, false);
blitter->draw_rectangle(blitter, ctx->velem_state, get_vs,
0, 0, width, height,
(float) depth, num_layers, type, );
@@ -1413,7 +1425,7 @@ static void util_blitter_clear_custom(struct 
blitter_context *blitter,
else
   get_vs = get_vs_passthrough_pos;

-  blitter_set_common_draw_rect_state(ctx, false);
+  blitter_set_common_draw_rect_state(ctx, false, false);
blitter->draw_rectangle(blitter, ctx->velem_state, get_vs,
0, 0, width, height,
(float) depth, 1, type, );
@@ -1966,7 +1978,7 @@ void util_blitter_blit_generic(struct blitter_context 
*blitter,
pipe->set_scissor_states(pipe, 0, 1, scissor);
 }

-   blitter_set_common_draw_rect_state(ctx, scissor != NULL);
+   blitter_set_common_draw_rect_state(ctx, scissor != NULL, 

Re: [Mesa-dev] [PATCH 10/29] anv/cmd_buffer: Add an anv_genX_call macro

[Nanley Chery]

On Mon, Nov 27, 2017 at 07:06:00PM -0800, Jason Ekstrand wrote:
> This is copied and pasted from the similar macro we added to ISL.
> ---
>  src/intel/vulkan/anv_cmd_buffer.c | 40 
> ---
>  1 file changed, 25 insertions(+), 15 deletions(-)
> 

This patch is
Reviewed-by: Nanley Chery 

> diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
> b/src/intel/vulkan/anv_cmd_buffer.c
> index 69acafa..7e7580c 100644
> --- a/src/intel/vulkan/anv_cmd_buffer.c
> +++ b/src/intel/vulkan/anv_cmd_buffer.c
> @@ -323,24 +323,34 @@ VkResult anv_ResetCommandBuffer(
> return anv_cmd_buffer_reset(cmd_buffer);
>  }
>  
> +#define anv_genX_call(devinfo, func, ...)  \
> +   switch ((devinfo)->gen) {   \
> +   case 7: \
> +  if ((devinfo)->is_haswell) { \
> + gen75_##func(__VA_ARGS__);\
> +  } else { \
> + gen7_##func(__VA_ARGS__); \
> +  }\
> +  break;   \
> +   case 8: \
> +  gen8_##func(__VA_ARGS__);\
> +  break;   \
> +   case 9: \
> +  gen9_##func(__VA_ARGS__);\
> +  break;   \
> +   case 10:\
> +  gen10_##func(__VA_ARGS__);   \
> +  break;   \
> +   default:\
> +  assert(!"Unknown hardware generation");  \
> +   }
> +
>  void
>  anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
>  {
> -   switch (cmd_buffer->device->info.gen) {
> -   case 7:
> -  if (cmd_buffer->device->info.is_haswell)
> - return gen75_cmd_buffer_emit_state_base_address(cmd_buffer);
> -  else
> - return gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
> -   case 8:
> -  return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
> -   case 9:
> -  return gen9_cmd_buffer_emit_state_base_address(cmd_buffer);
> -   case 10:
> -  return gen10_cmd_buffer_emit_state_base_address(cmd_buffer);
> -   default:
> -  unreachable("unsupported gen\n");
> -   }
> +   anv_genX_call(_buffer->device->info,
> + cmd_buffer_emit_state_base_address,
> + cmd_buffer);
>  }
>  
>  void anv_CmdBindPipeline(
> -- 
> 2.5.0.400.gff86faf
> 
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Re: [Mesa-dev] [PATCH 2/2] gallium/u_blitter: enable MSAA when blitting to MSAA surfaces

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Mon, Dec 11, 2017 at 9:09 PM, Brian Paul  wrote:
> If we're doing a Z -> Z MSAA blit (for example) we need to enable
> msaa rasterization when drawing the quads so that we can properly
> write the per-sample values.
>
> This fixes a number of Piglit ext_framebuffer_multisample blit tests
> such as ext_framebuffer_multisample/no-color 2 depth combined with
> the VMware driver.
>
> v2: This depends on the previous patch to save/set/restore the
> min_samples state.
> ---
>  src/gallium/auxiliary/util/u_blitter.c | 54 
> +-
>  1 file changed, 33 insertions(+), 21 deletions(-)
>
> diff --git a/src/gallium/auxiliary/util/u_blitter.c 
> b/src/gallium/auxiliary/util/u_blitter.c
> index 371daf1..acb9fcf 100644
> --- a/src/gallium/auxiliary/util/u_blitter.c
> +++ b/src/gallium/auxiliary/util/u_blitter.c
> @@ -123,7 +123,8 @@ struct blitter_context_priv
> void *sampler_state_rect_linear;
>
> /* Rasterizer state. */
> -   void *rs_state, *rs_state_scissor, *rs_discard_state;
> +   void *rs_state[2][2];  /**< [scissor][msaa] */
> +   void *rs_discard_state;
>
> /* Destination surface dimensions. */
> unsigned dst_width;
> @@ -275,13 +276,19 @@ struct blitter_context *util_blitter_create(struct 
> pipe_context *pipe)
> rs_state.bottom_edge_rule = 1;
> rs_state.flatshade = 1;
> rs_state.depth_clip = 1;
> -   ctx->rs_state = pipe->create_rasterizer_state(pipe, _state);
>
> -   rs_state.scissor = 1;
> -   ctx->rs_state_scissor = pipe->create_rasterizer_state(pipe, _state);
> +   unsigned scissor, msaa;
> +   for (scissor = 0; scissor < 2; scissor++) {
> +  for (msaa = 0; msaa < 2; msaa++) {
> + rs_state.scissor = scissor;
> + rs_state.multisample = msaa;
> + ctx->rs_state[scissor][msaa] =
> +pipe->create_rasterizer_state(pipe, _state);
> +  }
> +   }
>
> if (ctx->has_stream_out) {
> -  rs_state.scissor = 0;
> +  rs_state.scissor = rs_state.multisample = 0;
>rs_state.rasterizer_discard = 1;
>ctx->rs_discard_state = pipe->create_rasterizer_state(pipe, _state);
> }
> @@ -454,8 +461,13 @@ void util_blitter_destroy(struct blitter_context 
> *blitter)
> pipe->delete_depth_stencil_alpha_state(pipe, 
> ctx->dsa_write_depth_stencil);
> pipe->delete_depth_stencil_alpha_state(pipe, 
> ctx->dsa_keep_depth_write_stencil);
>
> -   pipe->delete_rasterizer_state(pipe, ctx->rs_state);
> -   pipe->delete_rasterizer_state(pipe, ctx->rs_state_scissor);
> +   unsigned scissor, msaa;
> +   for (scissor = 0; scissor < 2; scissor++) {
> +  for (msaa = 0; msaa < 2; msaa++) {
> + pipe->delete_rasterizer_state(pipe, ctx->rs_state[scissor][msaa]);
> +  }
> +   }
> +
> if (ctx->rs_discard_state)
>pipe->delete_rasterizer_state(pipe, ctx->rs_discard_state);
> if (ctx->vs)
> @@ -1222,12 +1234,12 @@ void util_blitter_cache_all_shaders(struct 
> blitter_context *blitter)
>  }
>
>  static void blitter_set_common_draw_rect_state(struct blitter_context_priv 
> *ctx,
> -   bool scissor)
> +   bool scissor, bool msaa)
>  {
> struct pipe_context *pipe = ctx->base.pipe;
>
> -   pipe->bind_rasterizer_state(pipe, scissor ? ctx->rs_state_scissor
> - : ctx->rs_state);
> +   pipe->bind_rasterizer_state(pipe, ctx->rs_state[scissor][msaa]);
> +
> if (ctx->has_geometry_shader)
>pipe->bind_gs_state(pipe, NULL);
> if (ctx->has_tessellation) {
> @@ -1401,7 +1413,7 @@ static void util_blitter_clear_custom(struct 
> blitter_context *blitter,
> if (num_layers > 1 && ctx->has_layered) {
>blitter_get_vs_func get_vs = get_vs_layered;
>
> -  blitter_set_common_draw_rect_state(ctx, false);
> +  blitter_set_common_draw_rect_state(ctx, false, false);
>blitter->draw_rectangle(blitter, ctx->velem_state, get_vs,
>0, 0, width, height,
>(float) depth, num_layers, type, );
> @@ -1413,7 +1425,7 @@ static void util_blitter_clear_custom(struct 
> blitter_context *blitter,
>else
>   get_vs = get_vs_passthrough_pos;
>
> -  blitter_set_common_draw_rect_state(ctx, false);
> +  blitter_set_common_draw_rect_state(ctx, false, false);
>blitter->draw_rectangle(blitter, ctx->velem_state, get_vs,
>0, 0, width, height,
>(float) depth, 1, type, );
> @@ -1966,7 +1978,7 @@ void util_blitter_blit_generic(struct blitter_context 
> *blitter,
>pipe->set_scissor_states(pipe, 0, 1, scissor);
> }
>
> -   blitter_set_common_draw_rect_state(ctx, scissor != NULL);
> +   blitter_set_common_draw_rect_state(ctx, scissor != NULL, dst_samples > 1);
>
> do_blits(ctx, dst, dstbox, src, src_width0, src_height0,
>  

Re: [Mesa-dev] [PATCH 1/2] gallium/u_blitter: add code to save/set/restore min_samples for msaa

[Marek Olšák]

On Mon, Dec 11, 2017 at 9:09 PM, Brian Paul  wrote:
> Will be used by the next patch.
> ---
>  src/gallium/auxiliary/util/u_blitter.c |  8 
>  src/gallium/auxiliary/util/u_blitter.h | 11 +++
>  2 files changed, 19 insertions(+)
>
> diff --git a/src/gallium/auxiliary/util/u_blitter.c 
> b/src/gallium/auxiliary/util/u_blitter.c
> index 476ef08..371daf1 100644
> --- a/src/gallium/auxiliary/util/u_blitter.c
> +++ b/src/gallium/auxiliary/util/u_blitter.c
> @@ -646,6 +646,12 @@ void util_blitter_restore_fragment_states(struct 
> blitter_context *blitter)
>ctx->base.is_sample_mask_saved = false;
> }
>
> +   /* Min samples. */
> +   if (ctx->base.is_min_samples_saved) {
> +  pipe->set_min_samples(pipe, ctx->base.saved_min_samples);
> +  ctx->base.is_min_samples_saved = false;
> +   }
> +
> /* Miscellaneous states. */
> /* XXX check whether these are saved and whether they need to be restored
>  * (depending on the operation) */
> @@ -1675,6 +1681,8 @@ static void do_blits(struct blitter_context_priv *ctx,
>
> blitter_set_dst_dimensions(ctx, fb_state.width, fb_state.height);
>
> +   pipe->set_min_samples(pipe, 1);

Some drivers like r300 and svga don't implement set_min_samples.

With that fixed:

Reviewed-by: Marek Olšák 

Marek

> +
> if ((src_target == PIPE_TEXTURE_1D ||
>  src_target == PIPE_TEXTURE_2D ||
>  src_target == PIPE_TEXTURE_RECT) &&
> diff --git a/src/gallium/auxiliary/util/u_blitter.h 
> b/src/gallium/auxiliary/util/u_blitter.h
> index dba7739..251cd9b 100644
> --- a/src/gallium/auxiliary/util/u_blitter.h
> +++ b/src/gallium/auxiliary/util/u_blitter.h
> @@ -117,6 +117,9 @@ struct blitter_context
> bool is_sample_mask_saved;
> unsigned saved_sample_mask;
>
> +   bool is_min_samples_saved;
> +   unsigned saved_min_samples;
> +
> unsigned saved_num_sampler_states;
> void *saved_sampler_states[PIPE_MAX_SAMPLERS];
>
> @@ -546,6 +549,14 @@ util_blitter_save_sample_mask(struct blitter_context 
> *blitter,
>  }
>
>  static inline void
> +util_blitter_save_min_samples(struct blitter_context *blitter,
> +  unsigned min_samples)
> +{
> +   blitter->is_min_samples_saved = true;
> +   blitter->saved_min_samples = min_samples;
> +}
> +
> +static inline void
>  util_blitter_save_render_condition(struct blitter_context *blitter,
> struct pipe_query *query,
> bool condition,
> --
> 1.9.1
>
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[Mesa-dev] [PATCH v3 07/10] mesa/program: Link SPIR-V shaders using the SPIR-V code-path

[Eduardo Lima Mitev]

---
 src/mesa/program/ir_to_mesa.cpp | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index 29198509a6c..5d56c2ef44a 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -36,6 +36,7 @@
 #include "main/shaderapi.h"
 #include "main/shaderobj.h"
 #include "main/uniforms.h"
+#include "main/glspirv.h"
 #include "compiler/glsl/ast.h"
 #include "compiler/glsl/ir.h"
 #include "compiler/glsl/ir_expression_flattening.h"
@@ -3112,7 +3113,10 @@ _mesa_glsl_link_shader(struct gl_context *ctx, struct 
gl_shader_program *prog)
}
 
if (prog->data->LinkStatus) {
-  link_shaders(ctx, prog);
+  if (!spirv)
+ link_shaders(ctx, prog);
+  else
+ _mesa_spirv_link_shaders(ctx, prog);
}
 
/* If LinkStatus is linking_success, then reset sampler validated to true.
-- 
2.15.1

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[Mesa-dev] [PATCH v3 09/10] i965: Call spirv_to_nir() instead of glsl_to_nir() for SPIR-V shaders

[Eduardo Lima Mitev]

This is the main fork of the shader compilation code-path, where a NIR
shader is obtained by calling spirv_to_nir() or glsl_to_nir(),
depending on its nature..

v2: Use 'spirv_data' member from gl_linked_shader to know which method
   to call. (Timothy Arceri)

Reviewed-by: Timothy Arceri 
---
 src/mesa/drivers/dri/i965/brw_program.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index 5b168c25e3d..5f564541cb2 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -31,6 +31,7 @@
 
 #include 
 #include "main/imports.h"
+#include "main/glspirv.h"
 #include "program/prog_parameter.h"
 #include "program/prog_print.h"
 #include "program/prog_to_nir.h"
@@ -74,9 +75,14 @@ brw_create_nir(struct brw_context *brw,
   ctx->Const.ShaderCompilerOptions[stage].NirOptions;
nir_shader *nir;
 
-   /* First, lower the GLSL IR or Mesa IR to NIR */
+   /* First, lower the GLSL/Mesa IR or SPIR-V to NIR */
if (shader_prog) {
-  nir = glsl_to_nir(shader_prog, stage, options);
+  if (shader_prog->_LinkedShaders[stage]->spirv_data)
+ nir = _mesa_spirv_to_nir(ctx, shader_prog, stage, options);
+  else
+ nir = glsl_to_nir(shader_prog, stage, options);
+  assert (nir);
+
   nir_remove_dead_variables(nir, nir_var_shader_in | nir_var_shader_out);
   nir_lower_returns(nir);
   nir_validate_shader(nir);
-- 
2.15.1

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[Mesa-dev] [PATCH v3 06/10] mesa/glspirv: Add _mesa_spirv_link_shaders() function

[Eduardo Lima Mitev]

This is the equivalent to link_shaders() from
src/compiler/glsl/linker.cpp, but for SPIR-V programs. It just
creates the program and its gl_linked_shader objects, giving drivers
the opportunity to implement any linking of SPIR-V shaders they choose,
at a later stage.

v2: Bail out if we see more that one shader for the same stage, and add
   a corresponding comment. (Timothy Arceri)

v3: * Adds also a linker error log to the condition above, with a reference
   to the specification issue. (Timothy Arceri)
* Squash with the patch adding the function boilerplate (Timothy Arceri)

Reviewed-by: Timothy Arceri 
---
 src/mesa/main/glspirv.c | 71 +
 src/mesa/main/glspirv.h |  4 +++
 2 files changed, 75 insertions(+)

diff --git a/src/mesa/main/glspirv.c b/src/mesa/main/glspirv.c
index e8370e4c6f2..baed58380a8 100644
--- a/src/mesa/main/glspirv.c
+++ b/src/mesa/main/glspirv.c
@@ -28,6 +28,8 @@
 #include "compiler/nir/nir.h"
 #include "compiler/spirv/nir_spirv.h"
 
+#include "program/program.h"
+
 #include "util/u_atomic.h"
 
 void
@@ -103,6 +105,75 @@ _mesa_spirv_shader_binary(struct gl_context *ctx,
}
 }
 
+/**
+ * This is the equivalent to compiler/glsl/linker.cpp::link_shaders()
+ * but for SPIR-V programs.
+ *
+ * This method just creates the gl_linked_shader structs with a reference to
+ * the SPIR-V data collected during previous steps.
+ *
+ * The real linking happens later in the driver-specifc call LinkShader().
+ * This is so backends can implement different linking strategies for
+ * SPIR-V programs.
+ */
+void
+_mesa_spirv_link_shaders(struct gl_context *ctx, struct gl_shader_program 
*prog)
+{
+   prog->data->LinkStatus = linking_success;
+   prog->data->Validated = false;
+
+   for (unsigned i = 0; i < prog->NumShaders; i++) {
+  struct gl_shader *shader = prog->Shaders[i];
+  gl_shader_stage shader_type = shader->Stage;
+
+  /* We only support one shader per stage. The gl_spirv spec doesn't seem
+   * to prevent this, but the way the API is designed, requiring all 
shaders
+   * to be specialized with an entry point, makes supporting this quite
+   * undefined.
+   *
+   * TODO: Turn this into a proper error once the spec bug
+   *  is resolved.
+   */
+  if (prog->_LinkedShaders[shader_type]) {
+ ralloc_strcat(>data->InfoLog,
+   "\nError trying to link more than one SPIR-V shader "
+   "per stage.\n");
+ prog->data->LinkStatus = linking_failure;
+ return;
+  }
+
+  assert(shader->spirv_data);
+
+  struct gl_linked_shader *linked = rzalloc(NULL, struct gl_linked_shader);
+  linked->Stage = shader_type;
+
+  /* Create program and attach it to the linked shader */
+  struct gl_program *gl_prog =
+ ctx->Driver.NewProgram(ctx,
+_mesa_shader_stage_to_program(shader_type),
+prog->Name, false);
+  if (!gl_prog) {
+ prog->data->LinkStatus = linking_failure;
+ _mesa_delete_linked_shader(ctx, linked);
+ return;
+  }
+
+  _mesa_reference_shader_program_data(ctx,
+  _prog->sh.data,
+  prog->data);
+
+  /* Don't use _mesa_reference_program() just take ownership */
+  linked->Program = gl_prog;
+
+  /* Reference the SPIR-V data from shader to the linked shader */
+  _mesa_shader_spirv_data_reference(>spirv_data,
+shader->spirv_data);
+
+  prog->_LinkedShaders[shader_type] = linked;
+  prog->data->linked_stages |= 1 << shader_type;
+   }
+}
+
 void GLAPIENTRY
 _mesa_SpecializeShaderARB(GLuint shader,
   const GLchar *pEntryPoint,
diff --git a/src/mesa/main/glspirv.h b/src/mesa/main/glspirv.h
index ba281f68bef..0f03b75c111 100644
--- a/src/mesa/main/glspirv.h
+++ b/src/mesa/main/glspirv.h
@@ -76,6 +76,10 @@ _mesa_spirv_shader_binary(struct gl_context *ctx,
   unsigned n, struct gl_shader **shaders,
   const void* binary, size_t length);
 
+void
+_mesa_spirv_link_shaders(struct gl_context *ctx,
+ struct gl_shader_program *prog);
+
 /**
  * \name API functions
  */
-- 
2.15.1

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[Mesa-dev] [PATCH v3 05/10] mesa: Add a reference to gl_shader_spirv_data to gl_linked_shader

[Eduardo Lima Mitev]

This is a reference to the spirv_data object stored in gl_shader, which
stores shader SPIR-V data that is needed during linking too.

Reviewed-by: Timothy Arceri 
---
 src/mesa/main/mtypes.h| 8 
 src/mesa/main/shaderobj.c | 1 +
 2 files changed, 9 insertions(+)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 2cc844da1d0..4ec60e25204 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2541,6 +2541,14 @@ struct gl_linked_shader
struct exec_list *packed_varyings;
struct exec_list *fragdata_arrays;
struct glsl_symbol_table *symbols;
+
+   /**
+* ARB_gl_spirv related data.
+*
+* This is actually a reference to the gl_shader::spirv_data, which
+* stores information that is also needed during linking.
+*/
+   struct gl_shader_spirv_data *spirv_data;
 };
 
 
diff --git a/src/mesa/main/shaderobj.c b/src/mesa/main/shaderobj.c
index 5c1cdd6b27a..834e2a92ec4 100644
--- a/src/mesa/main/shaderobj.c
+++ b/src/mesa/main/shaderobj.c
@@ -137,6 +137,7 @@ void
 _mesa_delete_linked_shader(struct gl_context *ctx,
struct gl_linked_shader *sh)
 {
+   _mesa_shader_spirv_data_reference(>spirv_data, NULL);
_mesa_reference_program(ctx, >Program, NULL);
ralloc_free(sh);
 }
-- 
2.15.1

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[Mesa-dev] [PATCH v3 10/10] i965: Don't call process_glsl_ir() for SPIR-V shaders

[Eduardo Lima Mitev]

v2: Use 'spirv_data' from gl_linked_shader instead, to check if shader
   is SPIR-V. (Timothy Arceri)

Reviewed-by: Timothy Arceri 
---
 src/mesa/drivers/dri/i965/brw_link.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 64267671c05..a010aadf2a5 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -236,7 +236,8 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
   struct gl_program *prog = shader->Program;
   prog->Parameters = _mesa_new_parameter_list();
 
-  process_glsl_ir(brw, shProg, shader);
+  if (!shader->spirv_data)
+ process_glsl_ir(brw, shProg, shader);
 
   _mesa_copy_linked_program_data(shProg, shader);
 
-- 
2.15.1

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[Mesa-dev] [PATCH v3 03/10] nir/spirv: add gl_spirv_validation method

[Eduardo Lima Mitev]

From: Alejandro Piñeiro 

ARB_gl_spirv adds the ability to use SPIR-V binaries, and a new
method, glSpecializeShader. From OpenGL 4.6 spec, section 7.2.1
"Shader Specialization", error table:

   INVALID_VALUE is generated if  does not name a valid
   entry point for .

   INVALID_VALUE is generated if any element of 
   refers to a specialization constant that does not exist in the
   shader module contained in .""

But we are not really interested on creating the nir shader at that
point, and adding nir structures on the gl_program, so at that point
we are just interested on the error checking.

So we add a new method focused on just checking those errors. It still
needs to parse the binary, but skips what it is not needed, and
doesn't create the nir shader.

v2: rebase update (spirv_to_nir options added, changes on the warning
logging, and others)
v3: include passing options on common initialization, doesn't call
setjmp on common_initialization
---
 src/compiler/spirv/nir_spirv.h|   5 +
 src/compiler/spirv/spirv_to_nir.c | 191 ++
 2 files changed, 180 insertions(+), 16 deletions(-)

diff --git a/src/compiler/spirv/nir_spirv.h b/src/compiler/spirv/nir_spirv.h
index a2c40e57d18..d2766abb7f9 100644
--- a/src/compiler/spirv/nir_spirv.h
+++ b/src/compiler/spirv/nir_spirv.h
@@ -41,6 +41,7 @@ struct nir_spirv_specialization {
   uint32_t data32;
   uint64_t data64;
};
+   bool defined_on_module;
 };
 
 enum nir_spirv_debug_level {
@@ -69,6 +70,10 @@ struct spirv_to_nir_options {
} debug;
 };
 
+bool gl_spirv_validation(const uint32_t *words, size_t word_count,
+ struct nir_spirv_specialization *spec, unsigned 
num_spec,
+ gl_shader_stage stage, const char *entry_point_name);
+
 nir_function *spirv_to_nir(const uint32_t *words, size_t word_count,
struct nir_spirv_specialization *specializations,
unsigned num_specializations,
diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 0493dd3a8b1..7f959711be6 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1227,6 +1227,7 @@ spec_constant_decoration_cb(struct vtn_builder *b, struct 
vtn_value *v,
 const_value->data64 = b->specializations[i].data64;
  else
 const_value->data32 = b->specializations[i].data32;
+ b->specializations[i].defined_on_module = true;
  return;
   }
}
@@ -1261,7 +1262,13 @@ handle_workgroup_size_decoration_cb(struct vtn_builder 
*b,
 const struct vtn_decoration *dec,
 void *data)
 {
+   /* This can happens if we are gl_spirv_validation. We can return safely, as
+* we don't need the workgroup info for such validation. */
+   if (b->shader == NULL)
+  return;
+
vtn_assert(member == -1);
+
if (dec->decoration != SpvDecorationBuiltIn ||
dec->literals[0] != SpvBuiltInWorkgroupSize)
   return;
@@ -3162,6 +3169,49 @@ vtn_handle_preamble_instruction(struct vtn_builder *b, 
SpvOp opcode,
return true;
 }
 
+/*
+ * gl_spirv validation. Just need to check for the entry point.
+ */
+static bool
+vtn_validate_preamble_instruction(struct vtn_builder *b, SpvOp opcode,
+  const uint32_t *w, unsigned count)
+{
+   switch (opcode) {
+   /* The following opcodes are not needed for gl_spirv, so we can skip
+* them.
+*/
+   case SpvOpSource:
+   case SpvOpSourceExtension:
+   case SpvOpSourceContinued:
+   case SpvOpExtension:
+   case SpvOpCapability:
+   case SpvOpExtInstImport:
+   case SpvOpMemoryModel:
+   case SpvOpString:
+   case SpvOpName:
+   case SpvOpMemberName:
+   case SpvOpExecutionMode:
+   case SpvOpDecorationGroup:
+   case SpvOpMemberDecorate:
+   case SpvOpGroupDecorate:
+   case SpvOpGroupMemberDecorate:
+  break;
+
+   case SpvOpEntryPoint:
+  vtn_handle_preamble_instruction(b, opcode, w, count);
+  break;
+
+   case SpvOpDecorate:
+  vtn_handle_decoration(b, opcode, w, count);
+  break;
+
+   default:
+  return false; /* End of preamble */
+   }
+
+   return true;
+}
+
 static void
 vtn_handle_execution_mode(struct vtn_builder *b, struct vtn_value *entry_point,
   const struct vtn_decoration *mode, void *data)
@@ -3371,6 +3421,22 @@ vtn_handle_variable_or_type_instruction(struct 
vtn_builder *b, SpvOp opcode,
return true;
 }
 
+static bool
+vtn_handle_constant_or_type_instruction(struct vtn_builder *b, SpvOp opcode,
+const uint32_t *w, unsigned count)
+{
+   switch (opcode) {
+   case SpvOpUndef:
+   case SpvOpVariable:
+  break;
+
+   default:
+  return vtn_handle_variable_or_type_instruction(b, opcode, w, count);
+   }
+
+   return true;
+}
+
 static bool
 

[Mesa-dev] [PATCH v3 04/10] mesa: Implement glSpecializeShaderARB

[Eduardo Lima Mitev]

From: Nicolai Hähnle 

v2: * Use gl_spirv_validation instead of spirv_to_nir.
   This method just validates the shader. The conversion to NIR will
   happen later, during linking. (Alejandro Piñeiro)

* Use gl_shader_spirv_data struct to store the SPIR-V data.
   (Eduardo Lima)

* Use the 'spirv_data' member to tell if the gl_shader is
   a SPIR-V shader, instead of a dedicated flag. (Timothy Arceri)
---
 src/mesa/main/glspirv.c | 107 +++-
 1 file changed, 105 insertions(+), 2 deletions(-)

diff --git a/src/mesa/main/glspirv.c b/src/mesa/main/glspirv.c
index 81303057d05..e8370e4c6f2 100644
--- a/src/mesa/main/glspirv.c
+++ b/src/mesa/main/glspirv.c
@@ -23,6 +23,11 @@
 
 #include "glspirv.h"
 #include "errors.h"
+#include "shaderobj.h"
+
+#include "compiler/nir/nir.h"
+#include "compiler/spirv/nir_spirv.h"
+
 #include "util/u_atomic.h"
 
 void
@@ -106,7 +111,105 @@ _mesa_SpecializeShaderARB(GLuint shader,
   const GLuint *pConstantValue)
 {
GET_CURRENT_CONTEXT(ctx);
+   struct gl_shader *sh;
+   bool has_entry_point;
+   struct nir_spirv_specialization *spec_entries = NULL;
+
+   if (!ctx->Extensions.ARB_gl_spirv) {
+  _mesa_error(ctx, GL_INVALID_OPERATION, "glSpecializeShaderARB");
+  return;
+   }
+
+   sh = _mesa_lookup_shader_err(ctx, shader, "glSpecializeShaderARB");
+   if (!sh)
+  return;
+
+   if (!sh->spirv_data) {
+  _mesa_error(ctx, GL_INVALID_OPERATION,
+  "glSpecializeShaderARB(not SPIR-V)");
+  return;
+   }
+
+   if (sh->CompileStatus) {
+  _mesa_error(ctx, GL_INVALID_OPERATION,
+  "glSpecializeShaderARB(already specialized)");
+  return;
+   }
+
+   struct gl_shader_spirv_data *spirv_data = sh->spirv_data;
+
+   /* From the GL_ARB_gl_spirv spec:
+*
+*"The OpenGL API expects the SPIR-V module to have already been
+* validated, and can return an error if it discovers anything invalid
+* in the module. An invalid SPIR-V module is allowed to result in
+* undefined behavior."
+*
+* However, the following errors still need to be detected (from the same
+* spec):
+*
+*"INVALID_VALUE is generated if  does not name a valid
+* entry point for .
+*
+* INVALID_VALUE is generated if any element of 
+* refers to a specialization constant that does not exist in the
+* shader module contained in ."
+*
+* We cannot flag those errors a-priori because detecting them requires
+* parsing the module. However, flagging them during specialization is okay,
+* since it makes no difference in terms of application-visible state.
+*/
+   spec_entries = calloc(sizeof(*spec_entries), numSpecializationConstants);
+
+   for (unsigned i = 0; i < numSpecializationConstants; ++i) {
+  spec_entries[i].id = pConstantIndex[i];
+  spec_entries[i].data32 = pConstantValue[i];
+  spec_entries[i].defined_on_module = false;
+   }
+
+   has_entry_point =
+  gl_spirv_validation((uint32_t *)_data->SpirVModule->Binary[0],
+  spirv_data->SpirVModule->Length / 4,
+  spec_entries, numSpecializationConstants,
+  sh->Stage, pEntryPoint);
+
+   /* See previous spec comment */
+   if (!has_entry_point) {
+  _mesa_error(ctx, GL_INVALID_VALUE,
+  "glSpecializeShaderARB(\"%s\" is not a valid entry point"
+  " for shader)", pEntryPoint);
+  goto end;
+   }
+
+   for (unsigned i = 0; i < numSpecializationConstants; ++i) {
+  if (spec_entries[i].defined_on_module == false) {
+ _mesa_error(ctx, GL_INVALID_VALUE,
+ "glSpecializeShaderARB(constant \"%i\" does not exist "
+ "in shader)", spec_entries[i].id);
+ goto end;
+  }
+   }
+
+   spirv_data->SpirVEntryPoint = ralloc_strdup(spirv_data, pEntryPoint);
+
+   /* Note that we didn't make a real compilation of the module (spirv_to_nir),
+* but just checked some error conditions. Real "compilation" will be done
+* later, upon linking.
+*/
+   sh->CompileStatus = compile_success;
+
+   spirv_data->NumSpecializationConstants = numSpecializationConstants;
+   spirv_data->SpecializationConstantsIndex =
+  rzalloc_array_size(spirv_data, sizeof(GLuint),
+ numSpecializationConstants);
+   spirv_data->SpecializationConstantsValue =
+  rzalloc_array_size(spirv_data, sizeof(GLuint),
+ numSpecializationConstants);
+   for (unsigned i = 0; i < numSpecializationConstants; ++i) {
+  spirv_data->SpecializationConstantsIndex[i] = pConstantIndex[i];
+  spirv_data->SpecializationConstantsValue[i] = pConstantValue[i];
+   }
 
-   /* Just return GL_INVALID_OPERATION error while this is boilerplate */
-   _mesa_error(ctx, GL_INVALID_OPERATION, "SpecializeShaderARB");
+ end:
+   

[Mesa-dev] [PATCH v3 01/10] mesa: add gl_constants::SpirVCapabilities

[Eduardo Lima Mitev]

From: Nicolai Hähnle 

For drivers to declare which SPIR-V features they support.

v2: Don't use a pointer (Ian Romanick)
---
 src/mesa/main/mtypes.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index b372921e9f0..2cc844da1d0 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -4029,6 +4029,9 @@ struct gl_constants
 
/** GL_ARB_get_program_binary */
GLuint NumProgramBinaryFormats;
+
+   /** GL_ARB_gl_spirv */
+   struct spirv_supported_capabilities SpirVCapabilities;
 };
 
 
-- 
2.15.1

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[Mesa-dev] [PATCH v3 02/10] i965: initialize SPIR-V capabilities

[Eduardo Lima Mitev]

From: Alejandro Piñeiro 

Needed for ARB_gl_spirv. Right now those are the same that the intel
vulkan driver, but those are not shared. From the ARB_spirv_extensions
spec:

   "3. If a new GL extension is added that includes SPIR-V support via
   a new SPIR-V extension does it's SPIR-V extension also get
   enumerated by the SPIR_V_EXTENSIONS_ARB query?.

   RESOLVED. Yes. It's good to include it for consistency. Any SPIR-V
   functionality supported beyond the SPIR-V version that is required
   for the GL API version should be enumerated."

Reading between lines, there is the possibility of specific GL
extensions enabling specific SPIR-V extensions (so capabilities). That
would mean that it is possible that OpenGL and Vulkan not having the
same capabilities supported, even for the same driver. So for now we
keep them separate. Perhaps in the future it is better to keep them
the same and synced.

Note: we initialize SPIR-V capabilities at brwCreateContext instead of
the usual brw_initialize_context_constants because we want to do that
only for version >= 3.3. At brw_initialize_context_constans GL version
is still not computed.

v2:
   * Rebase update (SpirVCapabilities not a pointer anymore)
   * Fill spirv capabilities for OpenGL >= 3.3 (Ian Romanick)
---
 src/mesa/drivers/dri/i965/brw_context.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 126c187f629..a37bbb753d8 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -75,6 +75,7 @@
 #include "util/debug.h"
 #include "isl/isl.h"
 
+#include "compiler/spirv/nir_spirv.h"
 /***
  * Mesa's Driver Functions
  ***/
@@ -338,6 +339,21 @@ brw_init_driver_functions(struct brw_context *brw,
   brw_deserialize_program_binary;
 }
 
+static void
+brw_initialize_spirv_supported_capabilities(struct brw_context *brw)
+{
+   const struct gen_device_info *devinfo = >screen->devinfo;
+   struct gl_context *ctx = >ctx;
+
+   ctx->Const.SpirVCapabilities.float64 = devinfo->gen >= 8;
+   ctx->Const.SpirVCapabilities.int64 = devinfo->gen >= 8;
+   ctx->Const.SpirVCapabilities.tessellation = true;
+   ctx->Const.SpirVCapabilities.draw_parameters = true;
+   ctx->Const.SpirVCapabilities.image_write_without_format = true;
+   ctx->Const.SpirVCapabilities.multiview = true;
+   ctx->Const.SpirVCapabilities.variable_pointers = true;
+}
+
 static void
 brw_initialize_context_constants(struct brw_context *brw)
 {
@@ -1067,6 +1083,10 @@ brwCreateContext(gl_api api,
_mesa_override_extensions(ctx);
_mesa_compute_version(ctx);
 
+   /* GL_ARB_gl_spirv */
+   if (ctx->Version >= 33)
+  brw_initialize_spirv_supported_capabilities(brw);
+
_mesa_initialize_dispatch_tables(ctx);
_mesa_initialize_vbo_vtxfmt(ctx);
 
-- 
2.15.1

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[Mesa-dev] [PATCH v3 08/10] mesa/glspirv: Add a _mesa_spirv_to_nir() function

[Eduardo Lima Mitev]

This is basically a wrapper around spirv_to_nir() that includes
arguments setup and post-conversion validation.

v2: * Rebase update (SpirVCapabilities not a pointer anymore,
spirv_to_nir_options added, and others).
* Code-style improvements and remove debug hunk. (Timothy Arceri)

Reviewed-by: Timothy Arceri 
---
 src/mesa/main/glspirv.c | 58 +
 src/mesa/main/glspirv.h |  7 ++
 2 files changed, 65 insertions(+)

diff --git a/src/mesa/main/glspirv.c b/src/mesa/main/glspirv.c
index baed58380a8..a5a2254bf9c 100644
--- a/src/mesa/main/glspirv.c
+++ b/src/mesa/main/glspirv.c
@@ -174,6 +174,64 @@ _mesa_spirv_link_shaders(struct gl_context *ctx, struct 
gl_shader_program *prog)
}
 }
 
+nir_shader *
+_mesa_spirv_to_nir(struct gl_context *ctx,
+   const struct gl_shader_program *prog,
+   gl_shader_stage stage,
+   const nir_shader_compiler_options *options)
+{
+   nir_shader *nir = NULL;
+
+   struct gl_linked_shader *linked_shader = prog->_LinkedShaders[stage];
+   assert (linked_shader);
+
+   struct gl_shader_spirv_data *spirv_data = linked_shader->spirv_data;
+   assert(spirv_data);
+
+   struct gl_spirv_module *spirv_module = spirv_data->SpirVModule;
+   assert (spirv_module != NULL);
+
+   const char *entry_point_name = spirv_data->SpirVEntryPoint;
+   assert(entry_point_name);
+
+   struct nir_spirv_specialization *spec_entries =
+  calloc(sizeof(*spec_entries),
+ spirv_data->NumSpecializationConstants);
+
+   for (unsigned i = 0; i < spirv_data->NumSpecializationConstants; ++i) {
+  spec_entries[i].id = spirv_data->SpecializationConstantsIndex[i];
+  spec_entries[i].data32 = spirv_data->SpecializationConstantsValue[i];
+  spec_entries[i].defined_on_module = false;
+   }
+
+   const struct spirv_to_nir_options spirv_options = {
+  .caps = ctx->Const.SpirVCapabilities
+   };
+
+   nir_function *entry_point =
+  spirv_to_nir((const uint32_t *) _module->Binary[0],
+   spirv_module->Length / 4,
+   spec_entries, spirv_data->NumSpecializationConstants,
+   stage, entry_point_name,
+   _options,
+   options);
+   free(spec_entries);
+
+   assert (entry_point);
+   nir = entry_point->shader;
+   assert(nir->info.stage == stage);
+
+   nir->options = options;
+
+   nir->info.name =
+  ralloc_asprintf(nir, "SPIRV:%s:%d",
+  _mesa_shader_stage_to_abbrev(nir->info.stage),
+  prog->Name);
+   nir_validate_shader(nir);
+
+   return nir;
+}
+
 void GLAPIENTRY
 _mesa_SpecializeShaderARB(GLuint shader,
   const GLchar *pEntryPoint,
diff --git a/src/mesa/main/glspirv.h b/src/mesa/main/glspirv.h
index 0f03b75c111..81626ce75b5 100644
--- a/src/mesa/main/glspirv.h
+++ b/src/mesa/main/glspirv.h
@@ -24,6 +24,7 @@
 #ifndef GLSPIRV_H
 #define GLSPIRV_H
 
+#include "compiler/nir/nir.h"
 #include "mtypes.h"
 
 #ifdef __cplusplus
@@ -80,6 +81,12 @@ void
 _mesa_spirv_link_shaders(struct gl_context *ctx,
  struct gl_shader_program *prog);
 
+nir_shader *
+_mesa_spirv_to_nir(struct gl_context *ctx,
+   const struct gl_shader_program *prog,
+   gl_shader_stage stage,
+   const nir_shader_compiler_options *options);
+
 /**
  * \name API functions
  */
-- 
2.15.1

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[Mesa-dev] [PATCH v3 00/10] Initial gl_spirv support in Mesa and i965

[Eduardo Lima Mitev]

Hi,

This is the 3rd version of the series adding initial support for ARB_gl_spirv.

Previous versions of this series included also support for 
ARB_spirv_extensions, but we have decided to split the two to ease review. So I 
will be sending a second series with only the patches for spirv_extensions.

Notice also that some patches from version 2 were merged in master. These were 
already reviewed favorably and were fairly independent from the rest of the 
series.

There are still some patches in this new series with a Reviewed-by tag that we 
didn't merge yet because we consider they should go in with the rest of the 
series. The patches missing review are 01, 02, 03, 04 and 07.

As usual, a git tree containing this series can be found at 
 and the larger, 
work-in-progress series at 
.

Thanks for reviewing!

cheers,
Eduardo

Alejandro Piñeiro (2):
  i965: initialize SPIR-V capabilities
  nir/spirv: add gl_spirv_validation method

Eduardo Lima Mitev (6):
  mesa: Add a reference to gl_shader_spirv_data to gl_linked_shader
  mesa/glspirv: Add _mesa_spirv_link_shaders() function
  mesa/program: Link SPIR-V shaders using the SPIR-V code-path
  mesa/glspirv: Add a _mesa_spirv_to_nir() function
  i965: Call spirv_to_nir() instead of glsl_to_nir() for SPIR-V shaders
  i965: Don't call process_glsl_ir() for SPIR-V shaders

Nicolai Hähnle (2):
  mesa: add gl_constants::SpirVCapabilities
  mesa: Implement glSpecializeShaderARB

 src/compiler/spirv/nir_spirv.h  |   5 +
 src/compiler/spirv/spirv_to_nir.c   | 191 +++---
 src/mesa/drivers/dri/i965/brw_context.c |  20 +++
 src/mesa/drivers/dri/i965/brw_link.cpp  |   3 +-
 src/mesa/drivers/dri/i965/brw_program.c |  10 +-
 src/mesa/main/glspirv.c | 236 +++-
 src/mesa/main/glspirv.h |  11 ++
 src/mesa/main/mtypes.h  |  11 ++
 src/mesa/main/shaderobj.c   |   1 +
 src/mesa/program/ir_to_mesa.cpp |   6 +-
 10 files changed, 472 insertions(+), 22 deletions(-)

-- 
2.15.1

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Re: [Mesa-dev] [PATCH v2 1/4] meson: Build SWR driver

[Jan Vesely]

On Wed, 2017-12-13 at 09:47 -0800, Dylan Baker wrote:
> This enables the SWR driver, but doesn't actually hook it up to any of
> the targets yet. I felt like this patch was big and complicated enough
> without adding that.
> 
> v2: - Fix typo 'delemeited' -> 'delimited' (Eric E)
> - Fix type 'errror' -> 'error' (Eric E)
> - Use variables to hold files instead of looking above the current
>   meson build (Eric E)
> - Use foreach loops to reduce the number of unique generators
> - Add comment about why some generators have names and some are just
>   added to a list
> 
> CC: George Kyriazis 
> Signed-off-by: Dylan Baker 
> ---
>  meson.build|  12 +-
>  meson_options.txt  |   6 +
>  src/gallium/drivers/swr/meson.build| 289 
> +
>  .../drivers/swr/rasterizer/codegen/meson.build | 158 +++
>  src/gallium/meson.build|   8 +
>  5 files changed, 467 insertions(+), 6 deletions(-)
>  create mode 100644 src/gallium/drivers/swr/meson.build
>  create mode 100644 src/gallium/drivers/swr/rasterizer/codegen/meson.build
> 
> diff --git a/meson.build b/meson.build
> index 6e5ae4d24e9..842d441199e 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -47,6 +47,7 @@ with_valgrind = get_option('valgrind')
>  with_libunwind = get_option('libunwind')
>  with_asm = get_option('asm')
>  with_osmesa = get_option('osmesa')
> +with_swr_arches = get_option('swr-arches').split(',')
>  if get_option('texture-float')
>pre_args += '-DTEXTURE_FLOAT_ENABLED'
>message('WARNING: Floating-point texture enabled. Please consult 
> docs/patents.txt and your lawyer before building mesa.')
> @@ -155,6 +156,7 @@ if _drivers != ''
>with_gallium_i915 = _split.contains('i915')
>with_gallium_svga = _split.contains('svga')
>with_gallium_virgl = _split.contains('virgl')
> +  with_gallium_swr = _split.contains('swr')
>with_gallium = true
>  endif
>  
> @@ -181,7 +183,7 @@ if _vulkan_drivers != ''
>with_any_vk = with_amd_vk or with_intel_vk
>  endif
>  
> -if with_dri_swrast and with_gallium_softpipe
> +if with_dri_swrast and (with_gallium_softpipe or with_gallium_swr)
>error('Only one swrast provider can be built')
>  endif
>  if with_dri_i915 and with_gallium_i915
> @@ -975,7 +977,7 @@ _llvm = get_option('llvm')
>  if _llvm == 'auto'
>dep_llvm = dependency(
>  'llvm', version : '>= 3.9.0', modules : llvm_modules,
> -required : with_amd_vk or with_gallium_radeonsi,
> +required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr,
>)
>with_llvm = dep_llvm.found()
>  elif _llvm == 'true'
> @@ -997,8 +999,8 @@ if with_llvm
>  '-DHAVE_LLVM=0x0@0@@1@@2@'.format(_llvm_version[0], _llvm_version[1], 
> _llvm_patch),
>  '-DMESA_LLVM_VERSION_PATCH=@0@'.format(_llvm_patch),
>]
> -elif with_amd_vk or with_gallium_radeonsi
> -  error('The following drivers requires LLVM: Radv, RadeonSI. One of these 
> is enabled, but LLVM is disabled.')
> +elif with_amd_vk or with_gallium_radeonsi or with_gallium_swr
> +  error('The following drivers requires LLVM: Radv, RadeonSI, SWR. One of 
> these is enabled, but LLVM is disabled.')
>  endif
>  
>  dep_glvnd = []
> @@ -1158,8 +1160,6 @@ endif
>  
>  # TODO: various libdirs
>  
> -# TODO: swr
> -
>  # TODO: gallium driver dirs
>  
>  # FIXME: this is a workaround for #2326
> diff --git a/meson_options.txt b/meson_options.txt
> index 39b137cbeaf..4f4db5b7d26 100644
> --- a/meson_options.txt
> +++ b/meson_options.txt
> @@ -261,3 +261,9 @@ option(
>choices : ['8', '16', '32'],
>description : 'Number of channel bits for OSMesa.'
>  )
> +option(
> +  'swr-arches',
> +  type : 'string',
> +  value : 'avx,avx2',
> +  description : 'Comma delemited swr architectures. choices : 
> avx,avx2,knl,skx'
> +)
> diff --git a/src/gallium/drivers/swr/meson.build 
> b/src/gallium/drivers/swr/meson.build
> new file mode 100644
> index 000..c8c69b096a6
> --- /dev/null
> +++ b/src/gallium/drivers/swr/meson.build
> @@ -0,0 +1,289 @@
> +# Copyright © 2017 Intel Corporation
> +
> +# Permission is hereby granted, free of charge, to any person obtaining a 
> copy
> +# of this software and associated documentation files (the "Software"), to 
> deal
> +# in the Software without restriction, including without limitation the 
> rights
> +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> +# copies of the Software, and to permit persons to whom the Software is
> +# furnished to do so, subject to the following conditions:
> +
> +# The above copyright notice and this permission notice shall be included in
> +# all copies or substantial portions of the Software.
> +
> +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> +# 

[Mesa-dev] [Bug 104229] radeon_icd.i686.json api_version is 1.0.3

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104229

mercuriete  changed:

   What|Removed |Added

Version|unspecified |17.3
 OS|All |Linux (All)
   Hardware|Other   |x86-64 (AMD64)

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Re: [Mesa-dev] [PATCH 06/29] anv/image: Add a helper for determining when fast clears are supported

[Nanley Chery]

On Mon, Nov 27, 2017 at 07:05:56PM -0800, Jason Ekstrand wrote:
> ---
>  src/intel/vulkan/anv_image.c   | 58 
> ++
>  src/intel/vulkan/anv_private.h |  5 
>  2 files changed, 63 insertions(+)
> 
> diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
> index a872149..561da28 100644
> --- a/src/intel/vulkan/anv_image.c
> +++ b/src/intel/vulkan/anv_image.c
> @@ -837,6 +837,64 @@ anv_layout_to_aux_usage(const struct gen_device_info * 
> const devinfo,
> unreachable("layout is not a VkImageLayout enumeration member.");
>  }
>  
> +/**
> + * This function returns true if the given image in the given VkImageLayout
> + * supports unresolved fast-clears.
> + *
> + * @param devinfo The device information of the Intel GPU.
> + * @param image The image that may contain a collection of buffers.
> + * @param aspect The aspect of the image to be accessed.
> + * @param layout The current layout of the image aspect(s).
> + */
> +bool
> +anv_layout_supports_fast_clear(const struct gen_device_info * const devinfo,
> +   const struct anv_image * const image,
> +   const VkImageAspectFlagBits aspect,
> +   const VkImageLayout layout)
> +{
> +   /* The aspect must be exactly one of the image aspects. */
> +   assert(_mesa_bitcount(aspect) == 1 && (aspect & image->aspects));
> +
> +   uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
> +
> +   /* If there is no auxiliary surface allocated, there are no fast-clears */
> +   if (image->planes[plane].aux_surface.isl.size == 0)
> +  return false;
> +
> +   /* All images that use an auxiliary surface are required to be tiled. */
> +   assert(image->tiling == VK_IMAGE_TILING_OPTIMAL);
> +
> +   /* Stencil has no aux */
> +   assert(aspect != VK_IMAGE_ASPECT_STENCIL_BIT);
> +
> +   if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
> +  /* For depth images (with HiZ), the layout supports fast-clears if and
> +   * only if it supports HiZ.
> +   */
> +  enum isl_aux_usage aux_usage =
> + anv_layout_to_aux_usage(devinfo, image, aspect, layout);
> +  return aux_usage == ISL_AUX_USAGE_HIZ;
> +   }
> +
> +   assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
> +
> +   /* Multisample fast-clear is not yet supported. */
> +   if (image->samples > 1)
> +  return false;
> +
> +   /* The only layout which actually supports fast-clears today is
> +* VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL.  Some day in the future
> +* this may change if our ability to track clear colors improves.
> +*/
> +   switch (layout) {
> +   case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
> +  return true;
> +

This is kind of tricky. We actually allow fast-clears for CCS_E textures
in the GENERAL layout if the clear color is all zeros. When this
happens, we set the needs_resolve predicate to false. This means that
unresolved fast-clears is potentially in use for CCS_E images in any
layout.

-Nanley

> +   default:
> +  return false;
> +   }
> +}
> +
>  
>  static struct anv_state
>  alloc_surface_state(struct anv_device *device)
> diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
> index 5dd95a3..461bfed 100644
> --- a/src/intel/vulkan/anv_private.h
> +++ b/src/intel/vulkan/anv_private.h
> @@ -2559,6 +2559,11 @@ anv_layout_to_aux_usage(const struct gen_device_info * 
> const devinfo,
>  const struct anv_image *image,
>  const VkImageAspectFlagBits aspect,
>  const VkImageLayout layout);
> +bool
> +anv_layout_supports_fast_clear(const struct gen_device_info * const devinfo,
> +   const struct anv_image * const image,
> +   const VkImageAspectFlagBits aspect,
> +   const VkImageLayout layout);
>  
>  /* This is defined as a macro so that it works for both
>   * VkImageSubresourceRange and VkImageSubresourceLayers
> -- 
> 2.5.0.400.gff86faf
> 
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Re: [Mesa-dev] [PATCH 09/29] anv/cmd_buffer: Generalize transition_color_buffer

[Nanley Chery]

On Mon, Nov 27, 2017 at 07:05:59PM -0800, Jason Ekstrand wrote:
> This moves it to being based on layout_to_aux_usage instead of being
> hard-coded based on bits of a priori knowledge of how transitions
> interact with layouts.  This conceptually simplifies things because
> we're now using layout_to_aux_usage and layout_supports_fast_clear to
> make resolve decisions so changes to those functions will do what one
> expects.
> 
> This fixes a potential bug with window system integration on gen9+ where
> we wouldn't do a resolve when transitioning to the PRESENT_SRC layout
> because we just assume that everything that handles CCS_E can handle it
> all the time.  When handing a CCS_E image off to the window system, we
> may need to do a full resolve if the window system does not support the
> CCS_E modifier.  The only reason why this hasn't been a problem yet is
> because we don't support modifiers in Vulkan WSI and so we always get X
> tiling which implies no CCS on gen9+.
> ---
>  src/intel/vulkan/genX_cmd_buffer.c | 53 
> +-
>  1 file changed, 41 insertions(+), 12 deletions(-)
> 
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
> b/src/intel/vulkan/genX_cmd_buffer.c
> index be717eb..65cc85d 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -593,6 +593,7 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
>  VkImageLayout initial_layout,
>  VkImageLayout final_layout)
>  {
> +   const struct gen_device_info *devinfo = _buffer->device->info;
> /* Validate the inputs. */
> assert(cmd_buffer);
> assert(image && image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
> @@ -733,17 +734,48 @@ transition_color_buffer(struct anv_cmd_buffer 
> *cmd_buffer,
>   VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL,
>   final_layout);
>}
> -   } else if (initial_layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL) {
> -  /* Resolves are only necessary if the subresource may contain blocks
> -   * fast-cleared to values unsupported in other layouts. This only 
> occurs
> -   * if the initial layout is COLOR_ATTACHMENT_OPTIMAL.
> -   */
> -  return;
> -   } else if (image->samples > 1) {
> -  /* MCS buffers don't need resolving. */
>return;
> }
>  
> +   /* If initial aux usage is NONE, there is nothing to resolve */
> +   enum isl_aux_usage initial_aux_usage =
> +  anv_layout_to_aux_usage(devinfo, image, aspect, initial_layout);
> +   if (initial_aux_usage == ISL_AUX_USAGE_NONE)
> +  return;
> +
> +   enum isl_aux_op resolve_op = ISL_AUX_OP_NONE;
> +
> +   /* If the initial layout supports fast clear but the final one does not,
> +* then we need at least a partial resolve.
> +*/
> +   if (anv_layout_supports_fast_clear(devinfo, image, aspect, 
> initial_layout) &&
> +   !anv_layout_supports_fast_clear(devinfo, image, aspect, final_layout))
> +  resolve_op = ISL_AUX_OP_PARTIAL_RESOLVE;

I find this hunk more readable, when resolve_op is modified less. How
about the following?
  if (anv_layout_supports_fast_clear(devinfo, image, aspect, 
initial_layout) &&
  !anv_layout_supports_fast_clear(devinfo, image, aspect, 
final_layout)) {
 /* CCS_D only supports full resolves and BLORP will assert on
  * us if we try to do a partial resolve on a CCS_D surface.
  */
 if (initial_aux_usage == ISL_AUX_USAGE_CCS_D) {
resolve_op = ISL_AUX_OP_FULL_RESOLVE;
 } else {
resolve_op = ISL_AUX_OP_PARTIAL_RESOLVE;
 }
  }

It may even be more readable to have most of these changes in a function
called something like color_transition_to_aux_op(). We shouldn't even
need a resolve_op variable in that case. Just a thought.

> +
> +   enum isl_aux_usage final_aux_usage =

With all the equality comparisons going on with initial_aux_usage and
final_aux_usage it would be helpful to have them const.

> +  anv_layout_to_aux_usage(devinfo, image, aspect, final_layout);
> +   if (initial_aux_usage == ISL_AUX_USAGE_CCS_E &&
> +   final_aux_usage != ISL_AUX_USAGE_CCS_E)
> +  resolve_op = ISL_AUX_OP_FULL_RESOLVE;
> +
> +   /* CCS_D only supports full resolves and BLORP will assert on us if we try
> +* to do a partial resolve on a CCS_D surface.
> +*/
> +   if (resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE &&
> +   initial_aux_usage == ISL_AUX_USAGE_CCS_D)
> +  resolve_op = ISL_AUX_OP_FULL_RESOLVE;
> +
> +   if (resolve_op == ISL_AUX_OP_NONE)
> +  return;
> +
> +   /* Even though the above code can theoretically handle multiple resolve
> +* types such as CCS_D -> CCS_E, the predication code below can't.  We 
> only

I may be missing something obvious, but what kind of resolve is needed
for CCS_D -> CCS_E? Also, why can't the predication code handle multiple
resolve types?

> 

[Mesa-dev] [PATCH 3/4] st/va: directly use idr pic flag

[boyuan.zhang]

From: Boyuan Zhang 

Remove is_idr flag, and use idr_pic_flag provided by vaapi directly

Signed-off-by: Boyuan Zhang 
Reviewed-by: Christian König 
---
 src/gallium/state_trackers/va/picture.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index 55ca16e..8951573 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -432,7 +432,6 @@ handleVAEncPictureParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vlV
h264 = buf->data;
context->desc.h264enc.frame_num = h264->frame_num;
context->desc.h264enc.not_referenced = false;
-   context->desc.h264enc.is_idr = (h264->pic_fields.bits.idr_pic_flag == 1);
context->desc.h264enc.pic_order_cnt = h264->CurrPic.TopFieldOrderCnt;
if (context->desc.h264enc.gop_cnt == 0)
   context->desc.h264enc.i_remain = context->gop_coeff;
@@ -451,7 +450,7 @@ handleVAEncPictureParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vlV
   UINT_TO_PTR(h264->CurrPic.picture_id),
   UINT_TO_PTR(h264->frame_num));
 
-   if (context->desc.h264enc.is_idr)
+   if (h264->pic_fields.bits.idr_pic_flag == 1)
   context->desc.h264enc.picture_type = PIPE_H264_ENC_PICTURE_TYPE_IDR;
else
   context->desc.h264enc.picture_type = PIPE_H264_ENC_PICTURE_TYPE_P;
@@ -493,10 +492,9 @@ handleVAEncSliceParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vlVaB
else if (h264->slice_type == 0)
   context->desc.h264enc.picture_type = PIPE_H264_ENC_PICTURE_TYPE_P;
else if (h264->slice_type == 2) {
-  if (context->desc.h264enc.is_idr){
- context->desc.h264enc.picture_type = PIPE_H264_ENC_PICTURE_TYPE_IDR;
+  if (context->desc.h264enc.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
  context->desc.h264enc.idr_pic_id++;
-  } else
+  else
  context->desc.h264enc.picture_type = PIPE_H264_ENC_PICTURE_TYPE_I;
} else
   context->desc.h264enc.picture_type = PIPE_H264_ENC_PICTURE_TYPE_SKIP;
-- 
2.7.4

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[Mesa-dev] [PATCH 4/4] vl: remove is idr flag

[boyuan.zhang]

From: Boyuan Zhang 

Remove is_idr flag since not being used anymore.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Christian König 
---
 src/gallium/include/pipe/p_video_state.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/gallium/include/pipe/p_video_state.h 
b/src/gallium/include/pipe/p_video_state.h
index 1d57165..5a88e6c 100644
--- a/src/gallium/include/pipe/p_video_state.h
+++ b/src/gallium/include/pipe/p_video_state.h
@@ -407,7 +407,6 @@ struct pipe_h264_enc_picture_desc
unsigned ref_pic_mode;
 
bool not_referenced;
-   bool is_idr;
bool enable_vui;
struct util_hash_table *frame_idx;
 
-- 
2.7.4

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[Mesa-dev] [PATCH 1/4] radeon/vcn: determine idr by pic type

[boyuan.zhang]

From: Boyuan Zhang 

Vaapi encode interface provides idr frame flags, where omx interface doesn't.
Therefore, change to use picture type to determine idr frame, which will
work for both interfaces.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Leo Liu 
Reviewed-by: Christian König 
---
 src/gallium/drivers/radeon/radeon_vcn_enc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index abc89a7..06579c8 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -47,7 +47,7 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder 
*enc, struct pipe_h26
enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
enc->enc_pic.not_referenced = pic->not_referenced;
-   enc->enc_pic.is_idr = pic->is_idr;
+   enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H264_ENC_PICTURE_TYPE_IDR);
enc->enc_pic.crop_left = 0;
enc->enc_pic.crop_right = (align(enc->base.width, 16) - 
enc->base.width) / 2;
enc->enc_pic.crop_top = 0;
-- 
2.7.4

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[Mesa-dev] [PATCH 2/4] radeon/vce: determine idr by pic type

[boyuan.zhang]

From: Boyuan Zhang 

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vce_52.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vce_52.c 
b/src/gallium/drivers/radeon/radeon_vce_52.c
index 10bf718..a941c47 100644
--- a/src/gallium/drivers/radeon/radeon_vce_52.c
+++ b/src/gallium/drivers/radeon/radeon_vce_52.c
@@ -162,7 +162,7 @@ void si_vce_52_get_param(struct rvce_encoder *enc, struct 
pipe_h264_enc_picture_
enc->enc_pic.addrmode_arraymode_disrdo_distwoinstants = 
0x0201;
else
enc->enc_pic.addrmode_arraymode_disrdo_distwoinstants = 
0x01000201;
-   enc->enc_pic.is_idr = pic->is_idr;
+   enc->enc_pic.is_idr = (pic->picture_type == 
PIPE_H264_ENC_PICTURE_TYPE_IDR);
 }
 
 static void create(struct rvce_encoder *enc)
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 2/2] gallivm: fix an issue with NaNs with seamless cube filtering

[Jose Fonseca]

On 13/12/17 02:34, srol...@vmware.com wrote:

From: Roland Scheidegger 

Cube texture wrapping is a bit special since the values (post face
projection) always are within [0,1], so we took advantage of that and
omitted some clamps.
However, we can still get NaNs (either because the coords already had NaNs,
or the face projection generated them), and in fact we didn't handle them
quite safely. I've seen -INT_MAX + 1 been propagated through as the final int
coord value, albeit I didn't observe a crash. (Not quite a coincidence, since
any stride mul with -INT_MAX or -INT_MAX+1 will turn up as a small positive
number - nevertheless, I'd rather not try my luck, I'm not entirely sure it
can't really turn up negative neither due to seamless coord swapping, plus
ifloor of a NaN is not guaranteed to return -INT_MAX by any standard. And
we kill off NaNs similarly with ordinary texture wrapping too.)
So kill off the NaNs by using the common max against zero method.
---
  src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c | 11 +++
  1 file changed, 11 insertions(+)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c 
b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
index 571a968..ff8cbf6 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
@@ -1123,6 +1123,17 @@ lp_build_sample_image_linear(struct 
lp_build_sample_context *bld,
 */
/* should always have normalized coords, and offsets are undefined */
assert(bld->static_sampler_state->normalized_coords);
+  /*
+   * The coords should all be between [0,1] however we can have NaNs,
+   * which will wreak havoc. In particular the y1_clamped value below
+   * can be -INT_MAX (on x86) and be propagated right through (probably
+   * other values might be bogus in the end too).
+   * So kill off the NaNs here.
+   */
+  coords[0] = lp_build_max_ext(coord_bld, coords[0], coord_bld->zero,
+   GALLIVM_NAN_RETURN_OTHER_SECOND_NONNAN);
+  coords[1] = lp_build_max_ext(coord_bld, coords[1], coord_bld->zero,
+   GALLIVM_NAN_RETURN_OTHER_SECOND_NONNAN);
coord = lp_build_mul(coord_bld, coords[0], flt_width_vec);
/* instead of clamp, build mask if overflowed */
coord = lp_build_sub(coord_bld, coord, half);



Series LGTM.

Reviewed-by: Jose Fonseca 
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[Mesa-dev] [PATCH] meson: warn if building a non-debug build with asserts

[Dylan Baker]

cc: Jason Ekstrand 
Signed-off-by: Dylan Baker 
---
 meson.build | 9 +
 1 file changed, 9 insertions(+)

diff --git a/meson.build b/meson.build
index 6e5ae4d24e9..b00c1ffc3dc 100644
--- a/meson.build
+++ b/meson.build
@@ -29,6 +29,15 @@ project(
   default_options : ['buildtype=debugoptimized', 'c_std=c99', 'cpp_std=c++11']
 )
 
+if not get_option('b_ndebug') and not 
get_option('buildtype').startswith('debug')
+  _warn = 'Building a release or plain type build with asserts enabled. You 
probably also want to set -Dn_debug=true'
+  if meson.version().version_compare('< 0.44')
+message(_warn)
+  else
+warning(_warn)
+  endif
+endif
+
 # Arguments for the preprocessor, put these in a separate array from the C and
 # C++ (cpp in meson terminology) arguments since they need to be added to the
 # default arguments for both C and C++.
-- 
2.15.1

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Re: [Mesa-dev] [PATCH v2] egl/android: Partially handle HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED

[Robert Foss]

Hey Rob,

I've chatted to both of you about this patch, and it seemed acceptable
to both of you.

Can I have a s-o-b for either of you?


Rob.

On Mon, 2017-12-04 at 19:22 +0100, Robert Foss wrote:
> From: Tomasz Figa 
> 
> There is no API available to properly query the
> IMPLEMENTATION_DEFINED
> format. As a workaround we rely here on gralloc allocating either
> an arbitrary YCbCr 4:2:0 or RGBX_, with the latter being
> recognized
> by lock_ycbcr failing.
> 
> Reviewed-on: https://chromium-review.googlesource.com/566793
> 
> Signed-off-by: Tomasz Figa 
> Reviewed-by: Chad Versace 
> Signed-off-by: Robert Foss 
> ---
> Changes since v1:
>  - Replaced bug id with full link
> 
>  src/egl/drivers/dri2/platform_android.c | 41
> +++--
>  1 file changed, 39 insertions(+), 2 deletions(-)
> 
> diff --git a/src/egl/drivers/dri2/platform_android.c
> b/src/egl/drivers/dri2/platform_android.c
> index 63223e9a69..2320fb6f21 100644
> --- a/src/egl/drivers/dri2/platform_android.c
> +++ b/src/egl/drivers/dri2/platform_android.c
> @@ -59,6 +59,11 @@ static const struct droid_yuv_format
> droid_yuv_formats[] = {
> { HAL_PIXEL_FORMAT_YCbCr_420_888,   0, 1,
> __DRI_IMAGE_FOURCC_YUV420 },
> { HAL_PIXEL_FORMAT_YCbCr_420_888,   1, 1,
> __DRI_IMAGE_FOURCC_YVU420 },
> { HAL_PIXEL_FORMAT_YV12,1, 1,
> __DRI_IMAGE_FOURCC_YVU420 },
> +   /* HACK: See droid_create_image_from_prime_fd() and
> +* https://issuetracker.google.com/32077885. */
> +   { HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED,   0, 2,
> __DRI_IMAGE_FOURCC_NV12 },
> +   { HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED,   0, 1,
> __DRI_IMAGE_FOURCC_YUV420 },
> +   { HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED,   1, 1,
> __DRI_IMAGE_FOURCC_YVU420 },
>  };
>  
>  static int
> @@ -90,6 +95,11 @@ get_format_bpp(int native)
>  
> switch (native) {
> case HAL_PIXEL_FORMAT_RGBA_:
> +   case HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED:
> +  /*
> +   * HACK: Hardcode this to RGBX_ as per cros_gralloc hack.
> +   * TODO: Remove this once https://issuetracker.google.com/3207
> 7885 is fixed.
> +   */
> case HAL_PIXEL_FORMAT_RGBX_:
> case HAL_PIXEL_FORMAT_BGRA_:
>bpp = 4;
> @@ -112,6 +122,11 @@ static int get_fourcc(int native)
> case HAL_PIXEL_FORMAT_RGB_565:   return
> __DRI_IMAGE_FOURCC_RGB565;
> case HAL_PIXEL_FORMAT_BGRA_: return
> __DRI_IMAGE_FOURCC_ARGB;
> case HAL_PIXEL_FORMAT_RGBA_: return
> __DRI_IMAGE_FOURCC_ABGR;
> +   case HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED:
> +  /*
> +   * HACK: Hardcode this to RGBX_ as per cros_gralloc hack.
> +   * TODO: Remove this once https://issuetracker.google.com/3207
> 7885 is fixed.
> +   */
> case HAL_PIXEL_FORMAT_RGBX_: return
> __DRI_IMAGE_FOURCC_XBGR;
> default:
>_eglLog(_EGL_WARNING, "unsupported native buffer format 0x%x",
> native);
> @@ -125,6 +140,11 @@ static int get_format(int format)
> case HAL_PIXEL_FORMAT_BGRA_: return
> __DRI_IMAGE_FORMAT_ARGB;
> case HAL_PIXEL_FORMAT_RGB_565:   return
> __DRI_IMAGE_FORMAT_RGB565;
> case HAL_PIXEL_FORMAT_RGBA_: return
> __DRI_IMAGE_FORMAT_ABGR;
> +   case HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED:
> +  /*
> +   * HACK: Hardcode this to RGBX_ as per cros_gralloc hack.
> +   * TODO: Revert this once https://issuetracker.google.com/3207
> 7885 is fixed.
> +   */
> case HAL_PIXEL_FORMAT_RGBX_: return
> __DRI_IMAGE_FORMAT_XBGR;
> default:
>_eglLog(_EGL_WARNING, "unsupported native buffer format 0x%x",
> format);
> @@ -678,6 +698,11 @@ droid_create_image_from_prime_fd_yuv(_EGLDisplay
> *disp, _EGLContext *ctx,
> ret = dri2_dpy->gralloc->lock_ycbcr(dri2_dpy->gralloc, buf-
> >handle,
> 0, 0, 0, 0, 0, );
> if (ret) {
> +  /* HACK: See droid_create_image_from_prime_fd() and
> +   * https://issuetracker.google.com/32077885.*/
> +  if (buf->format == HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED)
> + return NULL;
> +
>_eglLog(_EGL_WARNING, "gralloc->lock_ycbcr failed: %d", ret);
>return NULL;
> }
> @@ -757,8 +782,20 @@ droid_create_image_from_prime_fd(_EGLDisplay
> *disp, _EGLContext *ctx,
>  {
> unsigned int pitch;
>  
> -   if (is_yuv(buf->format))
> -  return droid_create_image_from_prime_fd_yuv(disp, ctx, buf,
> fd);
> +   if (is_yuv(buf->format)) {
> +  _EGLImage *image;
> +
> +  image = droid_create_image_from_prime_fd_yuv(disp, ctx, buf,
> fd);
> +  /*
> +   * HACK: https://issuetracker.google.com/32077885
> +   * There is no API available to properly query the
> IMPLEMENTATION_DEFINED
> +   * format. As a workaround we rely here on gralloc allocating
> either
> +   * an arbitrary YCbCr 4:2:0 or RGBX_, with the latter
> being recognized
> +   * 

[Mesa-dev] [PATCH v2 4/4] meson: set opencl flags for r600

[Dylan Baker]

Signed-off-by: Dylan Baker 
---
 src/gallium/drivers/r600/meson.build | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/meson.build 
b/src/gallium/drivers/r600/meson.build
index 2132dbb33ad..5899518a2e8 100644
--- a/src/gallium/drivers/r600/meson.build
+++ b/src/gallium/drivers/r600/meson.build
@@ -113,12 +113,15 @@ egd_tables_h = custom_target(
   capture : true,
 )
 
-# TODO: compute defines
+r600_c_args = []
+if with_gallium_opencl
+  r600_c_args += '-DHAVE_OPENCL'
+endif
 
 libr600 = static_library(
   'r600',
   [files_r600, egd_tables_h],
-  c_args : [c_vis_args],
+  c_args : [c_vis_args, r600_c_args],
   cpp_args : [cpp_vis_args],
   include_directories : [
 inc_src, inc_include, inc_gallium, inc_gallium_aux, inc_amd_common,
-- 
2.15.1

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[Mesa-dev] [PATCH v2 3/4] meson: build clover

[Dylan Baker]

This has only been compile tested.

v2: - Have a single option for opencl (Eric E)
- fix typo "tgis" -> "tgsi" (Curro)
- Don't add "lib" prefix to pipe loader libraries, which matches the
  autotools behavior

cc: Curro Jerez 
cc: Jan Vesely 
cc: Aaron Watry 
Signed-off-by: Dylan Baker 
---

Jan and Aaron (or whoever decides to test this):

I think this should address the issues raised so far, so maybe this is
better for testing?

 include/meson.build   |  19 
 meson.build   |  29 +-
 meson_options.txt |   7 ++
 src/gallium/meson.build   |  12 ++-
 src/gallium/state_trackers/clover/meson.build | 122 ++
 src/gallium/targets/opencl/meson.build|  73 +++
 src/gallium/targets/pipe-loader/meson.build   |  77 
 7 files changed, 334 insertions(+), 5 deletions(-)
 create mode 100644 src/gallium/state_trackers/clover/meson.build
 create mode 100644 src/gallium/targets/opencl/meson.build
 create mode 100644 src/gallium/targets/pipe-loader/meson.build

diff --git a/include/meson.build b/include/meson.build
index e4dae91cede..a2e7ce6580e 100644
--- a/include/meson.build
+++ b/include/meson.build
@@ -78,3 +78,22 @@ if with_gallium_st_nine
 subdir : 'd3dadapter',
   )
 endif
+
+# Only install the headers if we are building a stand alone implementation and
+# not an ICD enabled implementation
+if with_gallium_opencl and not with_opencl_icd
+  install_headers(
+'CL/cl.h',
+'CL/cl.hpp',
+'CL/cl_d3d10.h',
+'CL/cl_d3d11.h',
+'CL/cl_dx9_media_sharing.h',
+'CL/cl_egl.h',
+'CL/cl_ext.h',
+'CL/cl_gl.h',
+'CL/cl_gl_ext.h',
+'CL/cl_platform.h',
+'CL/opencl.h',
+subdir: 'CL'
+  )
+endif
diff --git a/meson.build b/meson.build
index 842d441199e..74b2d5c49dc 100644
--- a/meson.build
+++ b/meson.build
@@ -583,6 +583,22 @@ if with_gallium_st_nine
   endif
 endif
 
+_opencl = get_option('gallium-opencl')
+if _opencl !=' disabled'
+  if not with_gallium
+error('OpenCL Clover implementation requires at least one gallium driver.')
+  endif
+
+  # TODO: alitvec?
+  dep_clc = dependency('libclc')
+  with_gallium_opencl = true
+  with_opencl_icd = _opencl == 'icd'
+else
+  dep_clc = []
+  with_gallium_opencl = false
+  with_gallium_icd = false
+endif
+
 gl_pkgconfig_c_flags = []
 if with_platform_x11
   if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
@@ -930,7 +946,7 @@ dep_thread = dependency('threads')
 if dep_thread.found() and host_machine.system() != 'windows'
   pre_args += '-DHAVE_PTHREAD'
 endif
-if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 # TODO: clover
+if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 or 
with_gallium_opencl
   dep_elf = dependency('libelf', required : false)
   if not dep_elf.found()
 dep_elf = cc.find_library('elf')
@@ -972,12 +988,19 @@ if with_amd_vk or with_gallium_radeonsi or 
with_gallium_r600
 llvm_modules += 'asmparser'
   endif
 endif
+if with_gallium_opencl
+  llvm_modules += [
+'all-targets', 'linker', 'coverage', 'instrumentation', 'ipo', 'irreader',
+'lto', 'option', 'objcarcopts', 'profiledata',
+  ]
+  # TODO: optional modules
+endif
 
 _llvm = get_option('llvm')
 if _llvm == 'auto'
   dep_llvm = dependency(
 'llvm', version : '>= 3.9.0', modules : llvm_modules,
-required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr,
+required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr or 
with_gallium_opencl,
   )
   with_llvm = dep_llvm.found()
 elif _llvm == 'true'
@@ -1154,8 +1177,6 @@ else
   dep_lmsensors = []
 endif
 
-# TODO: clover
-
 # TODO: gallium tests
 
 # TODO: various libdirs
diff --git a/meson_options.txt b/meson_options.txt
index 4f4db5b7d26..894378985fd 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -120,6 +120,13 @@ option(
   value : false,
   description : 'build gallium "nine" Direct3D 9.x state tracker.',
 )
+option(
+  'gallium-opencl',
+  type : 'combo',
+  choices : ['icd', 'standalone', 'disabled'],
+  value : 'disabled',
+  description : 'build gallium "clover" OpenCL state tracker.',
+)
 option(
   'd3d-drivers-path',
   type : 'string',
diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index fc21dcf03e1..6330c7514af 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -145,7 +145,17 @@ endif
 if with_gallium_st_nine
   subdir('state_trackers/nine')
 endif
-# TODO: clover
+if with_gallium_opencl
+  # TODO: this isn't really clover specific, but ATM clover is the only
+  # consumer
+  subdir('targets/pipe-loader')
+
+  if meson.version().version_compare('< 0.44.0')
+error('OpenCL requires meson 0.44.0 or greater.')
+  endif
+  subdir('state_trackers/clover')
+  subdir('targets/opencl')
+endif
 if with_dri
   

[Mesa-dev] [PATCH v2 2/4] meson: Turn on swr for relevant targets

[Dylan Baker]

Currently that's dri, libgl-xlib, and osmesa.

v2: - put drivers on a separate line from normal dependencies (Eric E)

Signed-off-by: Dylan Baker 
Reviewed-by: Eric Engestrom 
---
 src/gallium/meson.build| 1 -
 src/gallium/targets/dri/meson.build| 4 ++--
 src/gallium/targets/libgl-xlib/meson.build | 4 ++--
 src/gallium/targets/osmesa/meson.build | 5 ++---
 4 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index 3e2fd095710..fc21dcf03e1 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -145,7 +145,6 @@ endif
 if with_gallium_st_nine
   subdir('state_trackers/nine')
 endif
-# TODO: SWR
 # TODO: clover
 if with_dri
   subdir('state_trackers/dri')
diff --git a/src/gallium/targets/dri/meson.build 
b/src/gallium/targets/dri/meson.build
index 5ca7b015d91..edf8d67fe39 100644
--- a/src/gallium/targets/dri/meson.build
+++ b/src/gallium/targets/dri/meson.build
@@ -69,7 +69,7 @@ libgallium_dri = shared_library(
 dep_selinux, dep_expat, dep_libdrm, dep_llvm, dep_lmsensors, dep_thread,
 driver_swrast, driver_r300, driver_r600, driver_radeonsi, driver_nouveau,
 driver_pl111, driver_vc4, driver_vc5, driver_freedreno, driver_etnaviv,
-driver_imx, driver_i915, driver_svga, driver_virgl,
+driver_imx, driver_i915, driver_svga, driver_virgl, driver_swr,
   ],
 )
 
@@ -77,7 +77,7 @@ foreach d : [[with_gallium_pl111, 'pl111_dri.so'],
  [with_gallium_radeonsi, 'radeonsi_dri.so'],
  [with_gallium_nouveau, 'nouveau_dri.so'],
  [with_gallium_freedreno, ['msm_dri.so', 'kgsl_dri.so']],
- [with_gallium_softpipe, 'swrast_dri.so'],
+ [with_gallium_softpipe or with_gallium_swr, 'swrast_dri.so'],
  [with_gallium_softpipe and with_gallium_drisw_kms, 
'kms_swrast_dri.so'],
  [with_gallium_vc4, 'vc4_dri.so'],
  [with_gallium_vc5, 'vc5_dri.so'],
diff --git a/src/gallium/targets/libgl-xlib/meson.build 
b/src/gallium/targets/libgl-xlib/meson.build
index c413a25bd66..6c8d2b4bc0e 100644
--- a/src/gallium/targets/libgl-xlib/meson.build
+++ b/src/gallium/targets/libgl-xlib/meson.build
@@ -38,7 +38,6 @@ endif
 if with_shared_glapi
   gallium_xlib_link_with += libglapi
 endif
-# TODO: SWR
 
 libgl = shared_library(
   'GL',
@@ -55,7 +54,8 @@ libgl = shared_library(
 libgallium, libmesa_util, libmesa_gallium, gallium_xlib_link_with,
   ],
   dependencies : [
-dep_thread, dep_clock, dep_unwind, dep_lmsensors, driver_swrast,
+dep_thread, dep_clock, dep_unwind, dep_lmsensors,
+driver_swrast, driver_swr,
   ],
   install : true,
   version : '1.5.0',
diff --git a/src/gallium/targets/osmesa/meson.build 
b/src/gallium/targets/osmesa/meson.build
index cbf0e3d096a..e51c54f8bc4 100644
--- a/src/gallium/targets/osmesa/meson.build
+++ b/src/gallium/targets/osmesa/meson.build
@@ -32,8 +32,6 @@ if with_ld_version_script
   osmesa_link_deps += files('osmesa.sym')
 endif
 
-# TODO: swr
-
 libosmesa = shared_library(
   osmesa_lib_name,
   'target.c',
@@ -51,7 +49,8 @@ libosmesa = shared_library(
 osmesa_link_with,
   ],
   dependencies : [
-dep_selinux, dep_thread, dep_clock, dep_unwind, driver_swrast,
+dep_selinux, dep_thread, dep_clock, dep_unwind,
+driver_swrast, driver_swr,
   ],
   version : '8.0.0',
   install : true,
-- 
2.15.1

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[Mesa-dev] [PATCH v2 1/4] meson: Build SWR driver

[Dylan Baker]

This enables the SWR driver, but doesn't actually hook it up to any of
the targets yet. I felt like this patch was big and complicated enough
without adding that.

v2: - Fix typo 'delemeited' -> 'delimited' (Eric E)
- Fix type 'errror' -> 'error' (Eric E)
- Use variables to hold files instead of looking above the current
  meson build (Eric E)
- Use foreach loops to reduce the number of unique generators
- Add comment about why some generators have names and some are just
  added to a list

CC: George Kyriazis 
Signed-off-by: Dylan Baker 
---
 meson.build|  12 +-
 meson_options.txt  |   6 +
 src/gallium/drivers/swr/meson.build| 289 +
 .../drivers/swr/rasterizer/codegen/meson.build | 158 +++
 src/gallium/meson.build|   8 +
 5 files changed, 467 insertions(+), 6 deletions(-)
 create mode 100644 src/gallium/drivers/swr/meson.build
 create mode 100644 src/gallium/drivers/swr/rasterizer/codegen/meson.build

diff --git a/meson.build b/meson.build
index 6e5ae4d24e9..842d441199e 100644
--- a/meson.build
+++ b/meson.build
@@ -47,6 +47,7 @@ with_valgrind = get_option('valgrind')
 with_libunwind = get_option('libunwind')
 with_asm = get_option('asm')
 with_osmesa = get_option('osmesa')
+with_swr_arches = get_option('swr-arches').split(',')
 if get_option('texture-float')
   pre_args += '-DTEXTURE_FLOAT_ENABLED'
   message('WARNING: Floating-point texture enabled. Please consult 
docs/patents.txt and your lawyer before building mesa.')
@@ -155,6 +156,7 @@ if _drivers != ''
   with_gallium_i915 = _split.contains('i915')
   with_gallium_svga = _split.contains('svga')
   with_gallium_virgl = _split.contains('virgl')
+  with_gallium_swr = _split.contains('swr')
   with_gallium = true
 endif
 
@@ -181,7 +183,7 @@ if _vulkan_drivers != ''
   with_any_vk = with_amd_vk or with_intel_vk
 endif
 
-if with_dri_swrast and with_gallium_softpipe
+if with_dri_swrast and (with_gallium_softpipe or with_gallium_swr)
   error('Only one swrast provider can be built')
 endif
 if with_dri_i915 and with_gallium_i915
@@ -975,7 +977,7 @@ _llvm = get_option('llvm')
 if _llvm == 'auto'
   dep_llvm = dependency(
 'llvm', version : '>= 3.9.0', modules : llvm_modules,
-required : with_amd_vk or with_gallium_radeonsi,
+required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr,
   )
   with_llvm = dep_llvm.found()
 elif _llvm == 'true'
@@ -997,8 +999,8 @@ if with_llvm
 '-DHAVE_LLVM=0x0@0@@1@@2@'.format(_llvm_version[0], _llvm_version[1], 
_llvm_patch),
 '-DMESA_LLVM_VERSION_PATCH=@0@'.format(_llvm_patch),
   ]
-elif with_amd_vk or with_gallium_radeonsi
-  error('The following drivers requires LLVM: Radv, RadeonSI. One of these is 
enabled, but LLVM is disabled.')
+elif with_amd_vk or with_gallium_radeonsi or with_gallium_swr
+  error('The following drivers requires LLVM: Radv, RadeonSI, SWR. One of 
these is enabled, but LLVM is disabled.')
 endif
 
 dep_glvnd = []
@@ -1158,8 +1160,6 @@ endif
 
 # TODO: various libdirs
 
-# TODO: swr
-
 # TODO: gallium driver dirs
 
 # FIXME: this is a workaround for #2326
diff --git a/meson_options.txt b/meson_options.txt
index 39b137cbeaf..4f4db5b7d26 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -261,3 +261,9 @@ option(
   choices : ['8', '16', '32'],
   description : 'Number of channel bits for OSMesa.'
 )
+option(
+  'swr-arches',
+  type : 'string',
+  value : 'avx,avx2',
+  description : 'Comma delemited swr architectures. choices : avx,avx2,knl,skx'
+)
diff --git a/src/gallium/drivers/swr/meson.build 
b/src/gallium/drivers/swr/meson.build
new file mode 100644
index 000..c8c69b096a6
--- /dev/null
+++ b/src/gallium/drivers/swr/meson.build
@@ -0,0 +1,289 @@
+# Copyright © 2017 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# 

[Mesa-dev] [RFC libdrm 5/5] android: Change alloc_handle_t format from Android format to fourcc

[Robert Foss]

Change the alloc_handle_t format to signify the fourcc pixel format
code instead of the Android pixel format definition.

This is desirable since the fourcc code is what is used within the DRM
subsystem. Naturally translation will still have to happen somewhere.

Also bump the alloc_handle_t version.

Sign-off-by: Robert Foss 
---
 android/alloc_handle.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/android/alloc_handle.h b/android/alloc_handle.h
index ed9a720a8990..70a311a8cfa9 100644
--- a/android/alloc_handle.h
+++ b/android/alloc_handle.h
@@ -38,7 +38,7 @@ struct alloc_handle_t {
int prime_fd; /* dma-buf file descriptor */
int width; /* width of buffer in pixels */
int height; /* height of buffer in pixels */
-   int format; /* pixel format (Android) */
+   int format; /* pixel format (fourcc) */
int usage; /* android libhardware usage flags */
 
int stride; /* the stride in bytes */
@@ -51,7 +51,7 @@ struct alloc_handle_t {
} __attribute__((aligned(8)));
 };
 
-#define ALLOC_HANDLE_VERSION 3
+#define ALLOC_HANDLE_VERSION 4
 #define ALLOC_HANDLE_MAGIC 0x60585350
 #define ALLOC_HANDLE_NUM_FDS 1
 #define ALLOC_HANDLE_NUM_INTS (\
-- 
2.14.1

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[Mesa-dev] [RFC libdrm 0/5] Move alloc_handle_t from gralloc impls.

[Robert Foss]

This series moves {gbm,drm,cros}_gralloc_handle_t struct to libdrm,
since at least 4 implementations exist, and share a lot of contents.
The idea is to keep the common stuff defined in one place, and libdrm
is the common codebase to all of these platforms.

Additionally, having this struct defined in libdrm will make it
easier for mesa and grallocs to communicate.

Curretly missing is:
 - Planar formats
 - Get/Set functions


Planar formats
--
Support for planar formats is needed, but has not been added
yet, mostly since this was not already implemented in {gbm,drm}_gralloc
and the fact the having at least initial backwards compatability would
be nice. Anonymous unions can of course be used later on to provide
backwards compatability if so desired.


Get/Set functions
-
During the previous discussion[1] one suggestion was to add accessor
functions. In this RFC I've only provided a alloc_handle_create()
function.

The Get/Set functions have not been added yet, I was hoping for some
conclusive arguments for them being adeded.

Lastly it was suggested by Rob Herring that having a fourcc<->android
pixel format conversion function would be useful.


[1] https://lists.freedesktop.org/archives/mesa-dev/2017-November/178199.html

Robert Foss (5):
  android: Move gralloc handle struct to libdrm
  android: Add version variable to alloc_handle_t
  android: Mark alloc_handle_t magic variable as const
  android: Remove member name from alloc_handle_t
  android: Change alloc_handle_t format from Android format to fourcc

 Android.mk   |  8 +++-
 Makefile.sources |  3 ++
 android/alloc_handle.h   | 87 
 android/gralloc_drm_handle.h |  1 +
 4 files changed, 97 insertions(+), 2 deletions(-)
 create mode 100644 android/alloc_handle.h
 create mode 12 android/gralloc_drm_handle.h

-- 
2.14.1

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[Mesa-dev] [RFC libdrm 1/5] android: Move gralloc handle struct to libdrm

[Robert Foss]

This struct is used in mesa and drm_hwcomposer.
Versions of if have been implemented in several grallocs:
drm_gralloc, gbm_gralloc, minigbm and intel-minigbm.

Other than the 1:1 move of the struct a new generic name
has been chosen and variables have had comments added to them.

Sign-off-by: Robert Foss 
---
 Android.mk   |  8 +++--
 Makefile.sources |  3 ++
 android/alloc_handle.h   | 84 
 android/gralloc_drm_handle.h |  1 +
 4 files changed, 94 insertions(+), 2 deletions(-)
 create mode 100644 android/alloc_handle.h
 create mode 12 android/gralloc_drm_handle.h

diff --git a/Android.mk b/Android.mk
index 292be2360263..209123a56940 100644
--- a/Android.mk
+++ b/Android.mk
@@ -28,7 +28,7 @@ LIBDRM_TOP := $(LOCAL_PATH)
 
 include $(CLEAR_VARS)
 
-# Import variables LIBDRM_{,H_,INCLUDE_H_,INCLUDE_VMWGFX_H_}FILES
+# Import variables 
LIBDRM_{,H,INCLUDE_H,INCLUDE_ANDROID_H,INCLUDE_VMWGFX_H}_FILES
 include $(LOCAL_PATH)/Makefile.sources
 
 #static library for the device (recovery)
@@ -38,7 +38,8 @@ LOCAL_MODULE := libdrm
 LOCAL_SRC_FILES := $(LIBDRM_FILES)
 LOCAL_EXPORT_C_INCLUDE_DIRS := \
$(LOCAL_PATH) \
-   $(LOCAL_PATH)/include/drm
+   $(LOCAL_PATH)/include/drm \
+   $(LOCAL_PATH)/include/android
 
 LOCAL_C_INCLUDES := \
$(LOCAL_PATH)/include/drm
@@ -54,6 +55,9 @@ LOCAL_SRC_FILES := $(LIBDRM_FILES)
 LOCAL_EXPORT_C_INCLUDE_DIRS := \
 $(LOCAL_PATH)/include/drm
 
+LOCAL_SHARED_LIBRARIES := \
+   libcutils
+
 LOCAL_C_INCLUDES := \
 $(LOCAL_PATH)/include/drm
 
diff --git a/Makefile.sources b/Makefile.sources
index 10aa1d0f4b6e..545b5bbb35e5 100644
--- a/Makefile.sources
+++ b/Makefile.sources
@@ -37,5 +37,8 @@ LIBDRM_INCLUDE_H_FILES := \
include/drm/via_drm.h \
include/drm/virtgpu_drm.h
 
+LIBDRM_INCLUDE_ANDROID_H_FILES := \
+   android/alloc_handle.h
+
 LIBDRM_INCLUDE_VMWGFX_H_FILES := \
include/drm/vmwgfx_drm.h
diff --git a/android/alloc_handle.h b/android/alloc_handle.h
new file mode 100644
index ..75cb895a962a
--- /dev/null
+++ b/android/alloc_handle.h
@@ -0,0 +1,84 @@
+/*
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __ANDROID_ALLOC_HANDLE_H__
+#define __ANDROID_ALLOC_HANDLE_H__
+
+#include 
+
+/* support users of drm_gralloc/gbm_gralloc */
+#define gralloc_gbm_handle_t alloc_handle_t
+#define gralloc_drm_handle_t alloc_handle_t
+
+struct alloc_handle_t {
+   native_handle_t base;
+   
+   /* integers */
+   int magic; /* differentiate between allocator impls */
+
+   int prime_fd; /* dma-buf file descriptor */
+   int width; /* width of buffer in pixels */
+   int height; /* height of buffer in pixels */
+   int format; /* pixel format (Android) */
+   int usage; /* android libhardware usage flags */
+
+   int name;   /* the name of the bo */
+   int stride; /* the stride in bytes */
+   uint64_t modifier; /* buffer modifiers */
+
+   int data_owner; /* owner of data (for validation) */
+   union {
+   void *data; /* pointer to struct gralloc_gbm_bo_t */
+   uint64_t reserved;
+   } __attribute__((aligned(8)));
+};
+
+#define ALLOC_HANDLE_MAGIC 0x60585350
+#define ALLOC_HANDLE_NUM_FDS 1
+#define ALLOC_HANDLE_NUM_INTS (\
+   ((sizeof(struct alloc_handle_t) - sizeof(native_handle_t))/sizeof(int)) 
\
+- ALLOC_HANDLE_NUM_FDS)
+
+/**
+ * Create a buffer handle.
+ */
+struct alloc_handle_t *alloc_handle_create(int width, int height, int format,
+  int usage)
+{
+   struct alloc_handle_t handle = { .magic = ALLOC_HANDLE_MAGIC };
+
+   handle->base.version = sizeof(handle->base);
+   handle->base.numInts = ALLOC_HANDLE_NUM_INTS;
+   handle->base.numFds = ALLOC_HANDLE_NUM_FDS;
+
+ 

[Mesa-dev] [RFC libdrm 3/5] android: Mark alloc_handle_t magic variable as const

[Robert Foss]

Mark magic member of alloc_handle_t as const.
Also bump the version of alloc_handle_t.

Sign-off-by: Robert Foss 
---
 android/alloc_handle.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/android/alloc_handle.h b/android/alloc_handle.h
index b722615638e7..fe93ad7e6567 100644
--- a/android/alloc_handle.h
+++ b/android/alloc_handle.h
@@ -32,7 +32,7 @@ struct alloc_handle_t {
native_handle_t base;
 
/* api variables */
-   int magic; /* differentiate between allocator impls */
+   const int magic; /* differentiate between allocator impls */
const int version; /* api version */
 
int prime_fd; /* dma-buf file descriptor */
@@ -52,7 +52,7 @@ struct alloc_handle_t {
} __attribute__((aligned(8)));
 };
 
-#define ALLOC_HANDLE_VERSION 1
+#define ALLOC_HANDLE_VERSION 2
 #define ALLOC_HANDLE_MAGIC 0x60585350
 #define ALLOC_HANDLE_NUM_FDS 1
 #define ALLOC_HANDLE_NUM_INTS (\
-- 
2.14.1

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[Mesa-dev] [RFC libdrm 2/5] android: Add version variable to alloc_handle_t

[Robert Foss]

The version variable will be used for versioning of this
struct and the corresponding accessor functions.

Signed-off-by: Robert Foss 
---
 android/alloc_handle.h | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/android/alloc_handle.h b/android/alloc_handle.h
index 75cb895a962a..b722615638e7 100644
--- a/android/alloc_handle.h
+++ b/android/alloc_handle.h
@@ -30,9 +30,10 @@
 
 struct alloc_handle_t {
native_handle_t base;
-   
-   /* integers */
+
+   /* api variables */
int magic; /* differentiate between allocator impls */
+   const int version; /* api version */
 
int prime_fd; /* dma-buf file descriptor */
int width; /* width of buffer in pixels */
@@ -51,6 +52,7 @@ struct alloc_handle_t {
} __attribute__((aligned(8)));
 };
 
+#define ALLOC_HANDLE_VERSION 1
 #define ALLOC_HANDLE_MAGIC 0x60585350
 #define ALLOC_HANDLE_NUM_FDS 1
 #define ALLOC_HANDLE_NUM_INTS (\
@@ -63,7 +65,9 @@ struct alloc_handle_t {
 struct alloc_handle_t *alloc_handle_create(int width, int height, int format,
   int usage)
 {
-   struct alloc_handle_t handle = { .magic = ALLOC_HANDLE_MAGIC };
+   struct alloc_handle_t handle = {
+   .magic = ALLOC_HANDLE_MAGIC,
+   .version = ALLOC_HANDLE_VERSION };
 
handle->base.version = sizeof(handle->base);
handle->base.numInts = ALLOC_HANDLE_NUM_INTS;
-- 
2.14.1

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[Mesa-dev] [RFC libdrm 4/5] android: Remove member name from alloc_handle_t

[Robert Foss]

The name member of alloc_handle_t is no longer needed and has been removed.
The version field has also been bumped.

Signed-off-by: Robert Foss 
---
 android/alloc_handle.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/android/alloc_handle.h b/android/alloc_handle.h
index fe93ad7e6567..ed9a720a8990 100644
--- a/android/alloc_handle.h
+++ b/android/alloc_handle.h
@@ -41,7 +41,6 @@ struct alloc_handle_t {
int format; /* pixel format (Android) */
int usage; /* android libhardware usage flags */
 
-   int name;   /* the name of the bo */
int stride; /* the stride in bytes */
uint64_t modifier; /* buffer modifiers */
 
@@ -52,7 +51,7 @@ struct alloc_handle_t {
} __attribute__((aligned(8)));
 };
 
-#define ALLOC_HANDLE_VERSION 2
+#define ALLOC_HANDLE_VERSION 3
 #define ALLOC_HANDLE_MAGIC 0x60585350
 #define ALLOC_HANDLE_NUM_FDS 1
 #define ALLOC_HANDLE_NUM_INTS (\
-- 
2.14.1

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