Re: [Mesa-dev] [PATCH] gbm: Fix the alpha masks in the GBM format table.

Reviewed-by: Daniel Stone You can probably tell I only tested XRGB. Sorry!___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v2 4/9] anv/blorp: Allow indirect clear colors on blorp sources on gen7

--- src/intel/vulkan/genX_blorp_exec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c index f956715..ac6e736 100644 --- a/src/intel/vulkan/genX_blorp_exec.c +++ b/src/intel/vulkan/genX_blorp_exec.c

[Mesa-dev] [PATCH v2 5/9] anv/blorp: Pass the clear address to blorp for subpass MSAA resolves

--- src/intel/vulkan/anv_blorp.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index e71d90a..8f29bc8 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -1325,6 +1325,12 @@

[Mesa-dev] [PATCH v2 7/9] anv/cmd_buffer: Add helpers for computing resolve predicates

We'll want to re-use the complex resolve predicate computations for MCS resolves so it's nice to have them as helper functions. --- src/intel/vulkan/genX_cmd_buffer.c | 74 -- 1 file changed, 64 insertions(+), 10 deletions(-) diff --git

[Mesa-dev] [PATCH v2 6/9] anv/cmd_buffer: Handle MCS identical to CCS_E in compute_aux_usage

This doesn't actually do anything because att_state->fast_clear is determined based on the return value of anv_layout_to_fast_clear_type which currently returns NONE for multisampled images. --- src/intel/vulkan/genX_cmd_buffer.c | 14 +- 1 file changed, 5 insertions(+), 9

[Mesa-dev] [PATCH v2 9/9] anv: Enable MSAA fast-clears

This speeds up the Sascha Willems multisampling demo by around 25% when using 8x or 16x MSAA. --- src/intel/vulkan/anv_image.c | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index a2bae7b..922c469 100644

[Mesa-dev] [PATCH v2 2/9] intel/blorp: Add indirect clear color support to mcs_partial_resolve

This is a bit complicated because we have to get the indirect clear color in there somehow. In order to not do any more work in the shader than needed, we set it up as it's own vertex binding which points directly at the clear color address specified by the client. ---

[Mesa-dev] [PATCH v2 8/9] anv/cmd_buffer: Add support for MCS fast-clears and resolves

--- src/intel/vulkan/genX_cmd_buffer.c | 44 +- 1 file changed, 39 insertions(+), 5 deletions(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 47542ea..98e58ca 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++

[Mesa-dev] [PATCH v2 0/9] anv: Enable fast-clears for multisampled images

We've had multisample compression support for some time and we've had single-sampled fast-clears but multisampled fast clears haven't been all that high on anyone's priority list. I did send out a patch series for it back in November: https://patchwork.freedesktop.org/series/33727/ Unfortunately,

[Mesa-dev] [PATCH v2 3/9] anv/blorp: Add partial clear support to anv_image_mcs_op

--- src/intel/vulkan/anv_blorp.c | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index efa2ced..e71d90a 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -1606,6 +1606,16

[Mesa-dev] [PATCH v2 1/9] intel/blorp: Add a helper for filling out VERTEX_BUFFER_STATE

There are enough #ifs in there that it's kind-of pointless to duplicate it for each buffer. --- src/intel/blorp/blorp_genX_exec.h | 69 +++ 1 file changed, 33 insertions(+), 36 deletions(-) diff --git a/src/intel/blorp/blorp_genX_exec.h

Re: [Mesa-dev] [PATCH 12/14] intel/blorp: Add indirect clear color support to mcs_partial_resolve

On Tue, Nov 14, 2017 at 9:25 PM, Jason Ekstrand wrote: > On Tue, Nov 14, 2017 at 3:28 PM, Lionel Landwerlin < > lionel.g.landwer...@intel.com> wrote: > >> On 13/11/17 16:12, Jason Ekstrand wrote: >> >>> This is a bit complicated because we have to get the indirect clear >>>

Re: [Mesa-dev] [PATCH 1/1] ac/nir: use ordered float comparisons except for not equal

Using this on its own I believe will cause CTS regressions, which is what the other patches were about. Feel free to take on the feedback and come up with a proper solution. I'm not really sure how to progress this. On 24/02/18 00:21, Samuel Pitoiset wrote: Original patch from Timothy

Re: [Mesa-dev] [PATCH crucible 3/3] Increase descriptor pool maxSets for miptree tests.

All three are Reviewed-by: Jason Ekstrand On Fri, Feb 23, 2018 at 5:29 PM, Bas Nieuwenhuizen wrote: > From: Bas Nieuwenhuizen > > Some tests, e.g. func.miptree.r8g8b8a8-unorm. >

[Mesa-dev] [PATCH crucible 1/3] Allow multiple devices.

From: Bas Nieuwenhuizen Ideally we would be able to choose the device of course, but at least allowing tests to run is a good start. --- src/qonos/qonos.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/qonos/qonos.c b/src/qonos/qonos.c index

[Mesa-dev] [PATCH crucible 3/3] Increase descriptor pool maxSets for miptree tests.

From: Bas Nieuwenhuizen Some tests, e.g. func.miptree.r8g8b8a8-unorm.aspect-color.view-2d.levels01.array02.extent-512x512.upload-copy-with-draw.download-copy-with-draw use 2 sets on each phase for 2 phases without deallocating in between, so we need 4 sets. ---

[Mesa-dev] [PATCH crucible 2/3] Fix timestamp frequency.

From: Bas Nieuwenhuizen Per spec: "timestampPeriod is the number of nanoseconds required for a timestamp query to be incremented by 1." So: period = nanoseconds/cycle and difference = cycles difference * period = nanoseconds difference * period / 100 = milliseconds

Re: [Mesa-dev] [PATCH] radv: Really use correct HTILE expanded words.

On Fri, Feb 23, 2018 at 11:52 AM, James Legg wrote: > On Thu, 2018-02-22 at 22:48 +0100, Bas Nieuwenhuizen wrote: >> since IIRC the last change was also done due to Feral noticing and we >> are clearly lacking testcases in this area, can you check that that >> case

Re: [Mesa-dev] [PATCH 11/22] nir: Recognize some more open-coded fmin / fmax

On Fri, Feb 23, 2018 at 3:55 PM, Ian Romanick wrote: > From: Ian Romanick > > shader-db results: > > Haswell, Broadwell, and Skylake had similar results. (Skylake shown) > total instructions in shared programs: 14514817 -> 14514808 (<.01%) >

[Mesa-dev] [Bug 104654] r600/sb: Alien Isolation GPU lock

https://bugs.freedesktop.org/show_bug.cgi?id=104654 Gert Wollny changed: What|Removed |Added Attachment #136842|0 |1 is

Re: [Mesa-dev] [PATCH 04/22] i965: Silence unused parameter warnings in generated OA code

Rb! On 23/02/18 23:55, Ian Romanick wrote: From: Ian Romanick Reduces my build from 6301 warnings to 2075 warnings by silencing 4226 instances of things like src/mesa/drivers/dri/i965/i965@sta/brw_oa_hsw.c: In function ‘hsw__render_basic__gpu_core_clocks__read’:

Re: [Mesa-dev] [PATCH 1/7] vulkan: Add KHR_display extension to anv and radv using DRM

On Fri, Feb 23, 2018 at 3:43 PM, Keith Packard wrote: > Jason Ekstrand writes: > > > I think I like option 1 (KEITHP_kms_display). If the client knows the > > difference between render and primary for 2, then they are most likely > > already opening the

Re: [Mesa-dev] [RFC PATCH mesa 5/5] WIP - meson: add a message block at the end of the configuration stage

Quoting Eric Engestrom (2018-02-23 10:08:48) > The messages are basically the same as the ones in configure.ac > > Signed-off-by: Eric Engestrom > --- > Sent out because it's as much as I could do before the weekend, and > before I try to figure out the last bits I'd

Re: [Mesa-dev] [RFC PATCH mesa 4/5] meson: store the result of whether we have gallium-extra-hud and lmsensors

Quoting Eric Engestrom (2018-02-23 10:08:47) > Signed-off-by: Eric Engestrom > --- > meson.build | 4 > 1 file changed, 4 insertions(+) > > diff --git a/meson.build b/meson.build > index 6c22601f9e8864f08e08..770fdc7e50653bcfa7c2 100644 > --- a/meson.build > +++

Re: [Mesa-dev] [PATCH 2/2] glxinfo/wglinfo: print list of 4.3 shading language versions

The OCD side of me says it doesn't look right :P The lazy side of me says it's fine Either way it doesn't make much difference, it's only exposed with the extended output anyway On Fri, 23 Feb 2018 at 16:32 Brian Paul wrote: > On 02/23/2018 03:06 AM, Mike Lothian wrote: > >

Re: [Mesa-dev] [PATCH 01/21] vulkan: Add KHR_display extension using DRM

Continuing on the new version of the patch... On Tue, Feb 13, 2018 at 4:31 PM, Keith Packard wrote: > +enum wsi_image_state { > + wsi_image_idle, > + wsi_image_drawing, > + wsi_image_queued, > + wsi_image_flipping, > + wsi_image_displaying > +}; > With the

Re: [Mesa-dev] [RFC PATCH mesa 2/5] meson: simplify the gbm option code, and avoid changing types

Quoting Eric Engestrom (2018-02-23 10:08:45) > Signed-off-by: Eric Engestrom > --- > meson.build | 16 +++- > 1 file changed, 7 insertions(+), 9 deletions(-) > > diff --git a/meson.build b/meson.build > index 2d474b140373292e49e7..28d068742ff914a623f6

Re: [Mesa-dev] [RFC PATCH mesa 3/5] meson: avoid changing types for the dri3 option

Reviewed-by: Dylan Baker Quoting Eric Engestrom (2018-02-23 10:08:46) > Signed-off-by: Eric Engestrom > --- > meson.build | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/meson.build b/meson.build > index

Re: [Mesa-dev] [RFC PATCH mesa 1/5] meson: give different names to the vars containing dri drivers vs gallium drivers

Quoting Eric Engestrom (2018-02-23 10:08:44) > Signed-off-by: Eric Engestrom > --- > meson.build | 26 +- > 1 file changed, 13 insertions(+), 13 deletions(-) > > diff --git a/meson.build b/meson.build > index

Re: [Mesa-dev] [PATCH 12/17] intel/compiler/fs: Implement ddy without using align16 for Gen11+

On Tuesday, February 20, 2018 9:15:19 PM PST Matt Turner wrote: > Align16 is no more. We previously generated an align16 ADD instruction > to calculate DDY: > >add(8) g11<1>F -g10<4>.xyxyF g10<4>.zwzwF { align16 1Q }; > > Without align16, we now implement it as two align1 instructions: >

Re: [Mesa-dev] [PATCH 2/9] meson: recommend building the surfaceless platform

Quoting Emil Velikov (2018-02-23 11:32:01) > From: Emil Velikov > > It has no special requirements, size and build-time is effectively zero. > > Signed-off-by: Emil Velikov > --- > meson.build | 2 +- > 1 file changed, 1 insertion(+), 1

Re: [Mesa-dev] [PATCH 6/9] autotools: error out when building with mangling and glvnd

Quoting Emil Velikov (2018-02-23 11:32:05) > From: Emil Velikov > > It's not a thing that can work, nor is a wise idea to attempt. > > Signed-off-by: Emil Velikov > --- > configure.ac | 3 +++ > 1 file changed, 3 insertions(+) > > diff

Re: [Mesa-dev] [PATCH 4/9] meson: require shared glapi when using DRI based libGL

Quoting Emil Velikov (2018-02-23 11:32:03) > From: Emil Velikov > > Just like we do in the autotools build. > > Signed-off-by: Emil Velikov > --- > meson.build | 8 ++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff

Re: [Mesa-dev] [PATCH 11/17] intel/compiler/fs: Simplify ddx/ddy code generation

On Tuesday, February 20, 2018 9:15:18 PM PST Matt Turner wrote: > The brw_reg() constructor just obfuscates things here, in my opinion. > --- > src/intel/compiler/brw_fs_generator.cpp | 77 > +++-- > 1 file changed, 35 insertions(+), 42 deletions(-) > > diff --git

Re: [Mesa-dev] [PATCH 3/9] meson: remove unreachable with_glx == 'auto' check

Quoting Emil Velikov (2018-02-23 11:32:02) > From: Emil Velikov > > Cannot happen since, props to the autodetection further up. > > Signed-off-by: Emil Velikov > --- > meson.build | 6 +- > 1 file changed, 1 insertion(+), 5

Re: [Mesa-dev] [PATCH 15/17] intel/compiler: Add instruction compaction support on Gen11

On Tuesday, February 20, 2018 9:15:22 PM PST Matt Turner wrote: > Gen11 only differs from SKL+ in that it uses a new datatype index table. > --- > src/intel/compiler/brw_eu_compact.c | 42 > + > 1 file changed, 42 insertions(+) > > diff --git

Re: [Mesa-dev] [PATCH 16/17] intel/compiler: Disable Align16 tests on Gen11+

On Tuesday, February 20, 2018 9:15:23 PM PST Matt Turner wrote: > Align16 is no more. Patches 16-17 are: Reviewed-by: Kenneth Graunke signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list

Re: [Mesa-dev] [PATCH 14/17] intel/compiler: Mark line, pln, and lrp as removed on Gen11+

On Tuesday, February 20, 2018 9:15:21 PM PST Matt Turner wrote: > --- > src/intel/compiler/brw_eu.c | 10 ++ > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c > index bc297a21b32..3646076a8e8 100644 > ---

Re: [Mesa-dev] [PATCH 09/17] intel/compiler/fs: Don't generate integer DWord multiply on Gen11

On Tuesday, February 20, 2018 9:15:16 PM PST Matt Turner wrote: > Like CHV et al., Gen11 does not support 32x32 -> 32/64-bit integer > multiplies. > --- > src/intel/common/gen_device_info.c | 4 > src/intel/common/gen_device_info.h | 1 + > src/intel/compiler/brw_fs.cpp | 6 +- > 3

Re: [Mesa-dev] [PATCH 08/17] intel/compiler/fs: Fix application of cmod and saturate to LINE/MAC pair

On Tuesday, February 20, 2018 9:15:15 PM PST Matt Turner wrote: > --- > src/intel/compiler/brw_fs_generator.cpp | 17 + > 1 file changed, 13 insertions(+), 4 deletions(-) > > diff --git a/src/intel/compiler/brw_fs_generator.cpp > b/src/intel/compiler/brw_fs_generator.cpp > index

Re: [Mesa-dev] [PATCH 13/17] intel/compiler: Lower flrp32 on Gen11+

On Tuesday, February 20, 2018 9:15:20 PM PST Matt Turner wrote: > The LRP instruction is no more. > --- > src/intel/compiler/brw_compiler.c | 35 > + > src/intel/compiler/brw_fs_builder.h | 2 +- > src/intel/compiler/brw_fs_generator.cpp | 2 +- >

Re: [Mesa-dev] [PATCH 06/17] intel/compiler/fs: Implement FS_OPCODE_LINTERP with MADs on Gen11+

On Tuesday, February 20, 2018 9:15:13 PM PST Matt Turner wrote: > The PLN instruction is no more. Its functionality is now implemented > using two MAD instructions with the new native-float type. Instead of > >pln(16) r20.0<1>:F r10.4<0;1,0>:F r4.0<8;8,1>:F > > we now have > >mad(8)

Re: [Mesa-dev] [PATCH 07/17] intel/compiler/fs: Return multiple_instructions_emitted from generate_linterp

On Friday, February 23, 2018 3:51:37 PM PST Kenneth Graunke wrote: > On Tuesday, February 20, 2018 9:15:14 PM PST Matt Turner wrote: > > If multiple instructions are emitted, special handling of things like > > conditional mod, saturate, and NoDDClr/NoDDChk need to be performed. > > > > I noticed

[Mesa-dev] [PATCH 14/22] nir: Replace fmin(b2f(a), b) with a bcsel

From: Ian Romanick All of the affected shaders are HDR mappers from Serious Sam 3. All Gen7+ platforms had similar results. (Skylake shown) total instructions in shared programs: 14516285 -> 14516273 (<.01%) instructions in affected programs: 348 -> 336 (-3.45%)

[Mesa-dev] [PATCH 20/22] i965/vec4: Relax writemask condition in CSE

From: Ian Romanick If the previously seen instruction generates more fields than the new instruction, still allow CSE to happen. This doesn't do much, but it also enables a couple more shaders in the next patch. It helped quite a bit in another change series that I

[Mesa-dev] [PATCH 19/22] i965/fs: Merge CMP and SEL into CSEL on Gen8+

From: Ian Romanick Skylake total instructions in shared programs: 14514547 -> 14503025 (-0.08%) instructions in affected programs: 2008312 -> 1996790 (-0.57%) helped: 5816 HURT: 0 helped stats (abs) min: 1 max: 27 x̄: 1.98 x̃: 1 helped stats (rel) min: 0.03% max: 6.34%

[Mesa-dev] [PATCH 08/22] isl: Silence unused parameter warnings in __gen_combine_address implementations

From: Ian Romanick Reduces my build from 1808 warnings to 1772 warnings by silencing 36 instances of things like ../../SOURCE/master/src/intel/isl/isl_emit_depth_stencil.c: In function ‘__gen_combine_address’:

[Mesa-dev] [PATCH 12/22] nir: Replace an odd comparison involving fmin of -b2f

From: Ian Romanick I noticed the fge version while looking at a shader for an unrelated reason. The feq version prevents a regression in a later change that performs strength reduction of some compares. Broadwell and Skylake had similar results. (Skylake shown) total

[Mesa-dev] [PATCH 21/22] i965/vec4: Allow CSE on subset VF constant loads

From: Ian Romanick No changes on other platforms. Haswell, Ivy Bridge, and Sandy Bridge had similar results. (Haswell shown) total instructions in shared programs: 13059891 -> 13059884 (<.01%) instructions in affected programs: 431 -> 424 (-1.62%) helped: 7 HURT: 0

[Mesa-dev] [PATCH 13/22] nir: Pull b2f out of bcsel

From: Ian Romanick All platforms had similar results. (Skylake shown) total instructions in shared programs: 14516592 -> 14516586 (<.01%) instructions in affected programs: 500 -> 494 (-1.20%) helped: 2 HURT: 0 total cycles in shared programs: 533167044 -> 533166998

[Mesa-dev] [PATCH 18/22] i965/fs: Add infrastructure for generating CSEL instructions.

From: Kenneth Graunke v2 (idr): Don't allow CSEL with a non-float src2. v3 (idr): Add CSEL to fs_inst::flags_written. Suggested by Matt. Signed-off-by: Kenneth Graunke Signed-off-by: Ian Romanick ---

[Mesa-dev] [PATCH 07/22] genxml: Silence unused parameter warnings in generated pack code

From: Ian Romanick Reduces my build from 1960 warnings to 1808 warnings by silencing 152 instances of things like In file included from ../../SOURCE/master/src/intel/genxml/genX_pack.h:32:0, from

[Mesa-dev] [PATCH 05/22] nir: Silence unused parameter warnings in generated nir_constant_expressions code

From: Ian Romanick Reduces my build from 2075 warnings to 2023 warnings by silencing 52 instances of things like src/compiler/nir/nir_constant_expressions.c: In function ‘evaluate_bfi’: src/compiler/nir/nir_constant_expressions.c:1812:61: warning: unused parameter

[Mesa-dev] [PATCH 17/22] nir: Narrow some dot product operations

From: Ian Romanick On vector platforms, this helps elide some constant loads. No changes on Broadwell or Skylake. Haswell total instructions in shared programs: 13093793 -> 13060163 (-0.26%) instructions in affected programs: 1277532 -> 1243902 (-2.63%) helped: 13216

[Mesa-dev] [PATCH 09/22] i965: Silence unused parameter warnings in genX_state_upload

From: Ian Romanick Reduces my build from 1772 warnings to 1717 warnings by silencing 55 instances of things like ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function ‘gen4_emit_vertex_buffer_state’:

[Mesa-dev] [PATCH 16/22] nir: Simplify some comparisons like a+b < a

From: Ian Romanick All Gen7+ platforms had similar results. (Skylake shown) total instructions in shared programs: 14514555 -> 14514547 (<.01%) instructions in affected programs: 1972 -> 1964 (-0.41%) helped: 8 HURT: 0 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1

[Mesa-dev] [PATCH 10/22] mesa: Silence unused parameter warnings from TEXSTORE_PARAMS

From: Ian Romanick Reduces my build from 1717 warnings to 1547 warnings by silencing 170 instances of things like In file included from ../../SOURCE/master/src/mesa/main/texcompress_bptc.h:30:0, from

[Mesa-dev] [PATCH 22/22] nir: Don't i2b a value that is already Boolean

From: Ian Romanick A bunch of shaders have sequences like: i2b(u2i(floatBitsToUint(intBitsToFloat(x == y ? -1 : 0 Other optimizations (and NIR's typeless nature) reduce this to i2b(x == y) which is silly. Skylake total instructions in shared programs:

[Mesa-dev] [PATCH 03/22] i965: Silence warnings about mixing enum and non-enum in conditional

From: Ian Romanick Reduces my build from 6451 warnings to 6301 warnings by silencing 150 instances of ../../SOURCE/master/src/intel/compiler/brw_inst.h: In function ‘brw_reg_type brw_inst_src1_type(const gen_device_info*, const brw_inst*)’:

[Mesa-dev] [PATCH 06/22] i965: Silence unused parameter warnings in blorp

From: Ian Romanick Reduces my build from 2023 warnings to 1960 warnings by silencing 63 instances of things like In file included from ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:33:0: ../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h: In

[Mesa-dev] [PATCH 15/22] nir: Use De Morgan's Law on logic compounded comparisons

From: Ian Romanick The replacement of the comparison operators must happen during this step. If it does not, the next pass of nir_opt_algebraic will reapply De Morgan's Law in the "opposite direction" before performing dead code elimination. The resulting infinite

[Mesa-dev] [PATCH 11/22] nir: Recognize some more open-coded fmin / fmax

From: Ian Romanick shader-db results: Haswell, Broadwell, and Skylake had similar results. (Skylake shown) total instructions in shared programs: 14514817 -> 14514808 (<.01%) instructions in affected programs: 229 -> 220 (-3.93%) helped: 3 HURT: 0 helped stats (abs)

[Mesa-dev] [PATCH 04/22] i965: Silence unused parameter warnings in generated OA code

From: Ian Romanick Reduces my build from 6301 warnings to 2075 warnings by silencing 4226 instances of things like src/mesa/drivers/dri/i965/i965@sta/brw_oa_hsw.c: In function ‘hsw__render_basic__gpu_core_clocks__read’:

[Mesa-dev] [PATCH 02/22] intel/compiler: Silence unused parameter warnings in release builds

From: Ian Romanick Reduces my build from 7005 warnings to 6451 warnings by silencing 554 instances of In file included from ../../SOURCE/master/src/intel/compiler/brw_disasm.c:28:0: ../../SOURCE/master/src/intel/compiler/brw_inst.h: In function

[Mesa-dev] [PATCH 01/22] i965: Silence unused parameter warnings

From: Ian Romanick Reduces my build from 7119 warnings to 7005 warnings by silencing 114 instances of In file included from ../../SOURCE/master/src/mesa/drivers/dri/i965/brw_context.h:46:0, from

Re: [Mesa-dev] [PATCH 07/17] intel/compiler/fs: Return multiple_instructions_emitted from generate_linterp

On Tuesday, February 20, 2018 9:15:14 PM PST Matt Turner wrote: > If multiple instructions are emitted, special handling of things like > conditional mod, saturate, and NoDDClr/NoDDChk need to be performed. > > I noticed that conditional mods were misapplied when adding support for > Gen11 (in

Re: [Mesa-dev] Patch submit question

On 2018-02-23 13:20:21, Kyriazis, George wrote: > Hello mesa-dev, > > I have a quick patch submission question: > > I have a patch that I’d like to also nominate to mesa-stable > (specifically 18.0.1 or 18.0.2), however the same patch is different > between master and stable branches, due to

Re: [Mesa-dev] [PATCH 1/7] vulkan: Add KHR_display extension to anv and radv using DRM

Jason Ekstrand writes: > I think I like option 1 (KEITHP_kms_display). If the client knows the > difference between render and primary for 2, then they are most likely > already opening the master node themselves or at least have access to > the FD. Ok, I'll work on

[Mesa-dev] [PATCH crucible 0/3] amd: gcn_shader and shader_trinary_minmax tests

These Patches contain crucible tests for the two extensions: VK_AMD_gcn_shader VK_AMD_shader_trinary_minmax The tests cover basic functionality, including some boundaries and constant folding. amd_common contains functions to run the tests. Bas Nieuwenhuizen (2): amd: common functions for amd

[Mesa-dev] [PATCH crucible 1/3] amd: common functions for amd extension tests

From: Bas Nieuwenhuizen Co-authored-by: Daniel Schürmann Signed-off-by: Daniel Schürmann --- Makefile.am | 3 ++ src/tests/func/amd/amd_common.c | 115

[Mesa-dev] [PATCH crucible 2/3] amd: gcn_shader extension tests

Signed-off-by: Daniel Schürmann --- Makefile.am | 1 + src/tests/func/amd/gcn_shader.c | 252 2 files changed, 253 insertions(+) create mode 100644 src/tests/func/amd/gcn_shader.c diff --git

[Mesa-dev] [PATCH crucible 3/3] amd: shader_trinary_minmax extension tests

From: Bas Nieuwenhuizen Co-authored-by: Daniel Schürmann Signed-off-by: Daniel Schürmann --- Makefile.am| 1 + src/tests/func/amd/shader_trinary_minmax.c | 576

Re: [Mesa-dev] [PATCH] gbm: Fix the alpha masks in the GBM format table.

Reviewed-by: Ilia Mirkin On Fri, Feb 23, 2018 at 5:57 PM, Eric Anholt wrote: > Once GBM started looking at the values of the alpha masks, ARGB/ABGR > wouldn't match any more because we had both A and R in the low bits. > > Fixes: 2ed344645d65 ("gbm/dri:

Re: [Mesa-dev] [PATCH 1/7] vulkan: Add KHR_display extension to anv and radv using DRM

On Thu, Feb 15, 2018 at 9:46 AM, Keith Packard wrote: > Jason Ekstrand writes: > > > It seems a little odd to me to default to opening the master node and > then > > fall back to the render node if it doesn't work. I suppose that's > probably > > ok so

[Mesa-dev] [PATCH] gbm: Fix the alpha masks in the GBM format table.

Once GBM started looking at the values of the alpha masks, ARGB/ABGR wouldn't match any more because we had both A and R in the low bits. Fixes: 2ed344645d65 ("gbm/dri: Add RGBA masks to GBM format table") --- src/gbm/backends/dri/gbm_dri.c | 4 ++-- 1 file changed, 2 insertions(+), 2

Re: [Mesa-dev] [PATCH] radv/extensions: fix c_vk_version for patch == None

Huh, can confirm that it generates None for me too, no clue what defines that symbol. Reviewed-by: Bas Nieuwenhuizen Did you have push access? Otherwise I can push it. On Fri, Feb 23, 2018 at 11:33 PM, Mauro Rossi wrote: > Similar to cb0d1ba156

[Mesa-dev] [PATCH] radv/extensions: fix c_vk_version for patch == None

Similar to cb0d1ba156 ("anv/extensions: Fix VkVersion::c_vk_version for patch == None") fixes the following building errors: out/target/product/x86_64/obj_x86/STATIC_LIBRARIES/libmesa_radv_common_intermediates/radv_entrypoints.c:1161:48: error: use of undeclared identifier 'None'; did you mean

[Mesa-dev] [Bug 104681] Einstein@Home BOINC FGRPB1G GPU app crash

https://bugs.freedesktop.org/show_bug.cgi?id=104681 Germano Massullo changed: What|Removed |Added CC|

[Mesa-dev] [Bug 104182] Seti@Home OpenCL program starts then returns: "CL file build failure"

https://bugs.freedesktop.org/show_bug.cgi?id=104182 Germano Massullo changed: What|Removed |Added CC|

[Mesa-dev] [RFC 2/2] anv: enable VK_EXT_shader_viewport_index_layer

--- src/intel/vulkan/anv_extensions.py | 1 + src/intel/vulkan/anv_pipeline.c| 1 + 2 files changed, 2 insertions(+) diff --git a/src/intel/vulkan/anv_extensions.py b/src/intel/vulkan/anv_extensions.py index 581921e62a..00760fdd4e 100644 --- a/src/intel/vulkan/anv_extensions.py +++

[Mesa-dev] [PATCH v3 1/2] spirv: Add SpvCapabilityShaderViewportIndexLayerEXT

This capability allows gl_ViewportIndex and gl_Layer to also be used as outputs in Vertex and Tesselation shaders. v2: Make conditional to the capability, add gl_Layer, add tesselation shaders. (Iago) v3: Don't export to tesselation control shader. --- src/compiler/shader_info.h | 1

Re: [Mesa-dev] [PATCH v2 1/2] spirv: Add SpvCapabilityShaderViewportIndexLayerEXT

On Fri, Feb 23, 2018 at 11:34:31AM -0800, Caio Marcelo de Oliveira Filho wrote: > Hi, > > > diff --git a/src/compiler/spirv/vtn_variables.c > > b/src/compiler/spirv/vtn_variables.c > > index 9eb85c24e9..ba2b74c2c2 100644 > > --- a/src/compiler/spirv/vtn_variables.c > > +++

Re: [Mesa-dev] [PATCH] mesa: Update vertex processing mode on _mesa_UseProgram.

On Fri, Feb 23, 2018 at 09:01:17PM +0100, mathias.froehl...@gmx.net wrote: From: Mathias Fröhlich Hi Clayton, The following change fixes the reported problem on my site. Please test/review!! Just ran this through the CI and the previously failing test is now

Re: [Mesa-dev] [PATCH 6/7] spirv/i965/anv: Relax push constant offset assertions being 32-bit aligned

Assuming the CTS is still happy with it after those changes, Reviewed-by: Jason Ekstrand On Fri, Feb 23, 2018 at 1:16 PM, Chema Casanova wrote: > On 23/02/18 20:09, Jason Ekstrand wrote: > > On Fri, Feb 23, 2018 at 1:26 AM, Jose Maria Casanova

Re: [Mesa-dev] [PATCH 5/7] spirv: Calculate properly 16-bit vector sizes (v2)

Reviewed-by: Jason Ekstrand On Fri, Feb 23, 2018 at 1:30 PM, Jose Maria Casanova Crespo < jmcasan...@igalia.com> wrote: > Range in 16-bit push constants load was being calculated > wrongly using 4-bytes per element instead of 2-bytes as it > should be. > > v2: Use

Re: [Mesa-dev] [PATCH 1/7] anv/spirv: SSBO/UBO buffers needs padding size is not multiple of 32-bits

On Fri, Feb 23, 2018 at 12:28 PM, Chema Casanova wrote: > > > El 23/02/18 a las 17:26, Jason Ekstrand escribió: > > On Fri, Feb 23, 2018 at 1:26 AM, Jose Maria Casanova Crespo > > > wrote: > > > > The surfaces that

[Mesa-dev] [PATCH 5/7] spirv: Calculate properly 16-bit vector sizes (v2)

Range in 16-bit push constants load was being calculated wrongly using 4-bytes per element instead of 2-bytes as it should be. v2: Use glsl_get_bit_size instead of if statement (Jason Ekstrand) --- src/compiler/spirv/vtn_variables.c | 7 ++- 1 file changed, 2 insertions(+), 5

Re: [Mesa-dev] [PATCH] mesa: Update vertex processing mode on _mesa_UseProgram.

On Fri, Feb 23, 2018 at 4:24 PM, Mark Janes wrote: > writes: > >> From: Mathias Fröhlich >> >> Hi Clayton, >> >> The following change fixes the reported problem on my site. >> Please test/review!! >> >> best >> >>

Re: [Mesa-dev] [PATCH] mesa: Update vertex processing mode on _mesa_UseProgram.

writes: > From: Mathias Fröhlich > > Hi Clayton, > > The following change fixes the reported problem on my site. > Please test/review!! > > best > > Mathias > > > The change is a bug fix for 92d76a169: > mesa: Provide an alternative to

[Mesa-dev] Patch submit question

Hello mesa-dev, I have a quick patch submission question: I have a patch that I’d like to also nominate to mesa-stable (specifically 18.0.1 or 18.0.2), however the same patch is different between master and stable branches, due to neighboring code having changed in the meantime. What’s the

Re: [Mesa-dev] [PATCH 6/7] spirv/i965/anv: Relax push constant offset assertions being 32-bit aligned

On 23/02/18 20:09, Jason Ekstrand wrote: > On Fri, Feb 23, 2018 at 1:26 AM, Jose Maria Casanova Crespo > > wrote: > > The introduction of 16-bit types with VK_KHR_16bit_storages implies that > push constant offsets could be multiple of

Re: [Mesa-dev] [PATCH] mesa: Update vertex processing mode on _mesa_UseProgram.

Hi Brian, On Friday, 23 February 2018 21:04:54 CET Brian Paul wrote: > LGTM. > > Reviewed-by: Brian Paul Thanks!! And pushed. Mathias ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org

Re: [Mesa-dev] [PATCH 2/7] i965/fs: Support 16-bit do_read_vector with VK_KHR_relaxed_block_layout

On Fri, Feb 23, 2018 at 1:26 AM, Jose Maria Casanova Crespo < jmcasan...@igalia.com> wrote: > 16-bit load_ubo/ssbo operations that call do_untyped_read_vector doesn't > guarantee that offsets are multiple of 4-bytes as required by untyped_read > message. This happens for example on 16-bit scalar

Re: [Mesa-dev] [PATCH 1/7] anv/spirv: SSBO/UBO buffers needs padding size is not multiple of 32-bits

El 23/02/18 a las 17:26, Jason Ekstrand escribió: > On Fri, Feb 23, 2018 at 1:26 AM, Jose Maria Casanova Crespo > > wrote: > > The surfaces that backup the GPU buffers have a boundary check that > considers that access to partial

Re: [Mesa-dev] [PATCH 3/7] i965/fs: Support 16-bit store_ssbo with VK_KHR_relaxed_block_layout

On Fri, Feb 23, 2018 at 1:26 AM, Jose Maria Casanova Crespo < jmcasan...@igalia.com> wrote: > Restrict the use of untyped_surface_write with 16-bit pairs in > ssbo to the cases where we can guarantee that offset is multiple > of 4. > > Taking into account that VK_KHR_relaxed_block_layout is

Re: [Mesa-dev] [PATCH] mesa: Update vertex processing mode on _mesa_UseProgram.

On 02/23/2018 01:01 PM, mathias.froehl...@gmx.net wrote: From: Mathias Fröhlich Hi Clayton, The following change fixes the reported problem on my site. Please test/review!! best Mathias The change is a bug fix for 92d76a169: mesa: Provide an alternative to

[Mesa-dev] [PATCH] mesa: Update vertex processing mode on _mesa_UseProgram.

From: Mathias Fröhlich Hi Clayton, The following change fixes the reported problem on my site. Please test/review!! best Mathias The change is a bug fix for 92d76a169: mesa: Provide an alternative to get_vp_mode() that actually got exposed through 4562a7b0:

Re: [Mesa-dev] [PATCH 5/5] ac: use correct LLVM opcodes for ordered comparisons

On Fri, Feb 23, 2018 at 8:18 PM, Bas Nieuwenhuizen wrote: > On Fri, Feb 23, 2018 at 6:39 PM, Connor Abbott wrote: >> On Fri, Feb 23, 2018 at 8:30 AM, Bas Nieuwenhuizen >> wrote: >>> >>> >>> On Thu, Feb 15, 2018 at 8:54 AM,

[Mesa-dev] [PATCH] st/mesa: expose 0 shader binary formats for compat profiles for Qt

From: Marek Olšák Bugzilla: https://bugreports.qt.io/browse/QTBUG-66420 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105065 Cc: "18.0" --- src/mesa/state_tracker/st_context.c| 2 +- src/mesa/state_tracker/st_extensions.c |

Re: [Mesa-dev] Killing broken configure toggles and fixing autotools gl.pc

On 02/23/2018 12:31 PM, Emil Velikov wrote: Hi all, While fixing a gl.pc + glvnd bug (well sort of), I noticed the following: With GLVND, we started abusing GL_LIB a lot more. Currently autotools can do a) custom libGL name, b) mangled GL and c) GLVND. Turns out that a + b was broken, since b

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