[Mesa-dev] [PATCH v2] i965/sbe: fix number of inputs for active components

In 16631ca30ea6 we fixed gen9 active components to account for padded inputs in the URB, which we can have with SSO programs. To do that, instead of going through the bitfield of inputs (which doesn't include padding information), we compute the number of inputs from the size of the URB entry.

Re: [Mesa-dev] [PATCH] Vulkan: Android.mk: Fix source files path for gen11

Reviewed-by: Tapani Pälli On 02/27/2018 08:44 AM, Harish Krupo wrote: Signed-off-by: Harish Krupo --- src/intel/Android.vulkan.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/Android.vulkan.mk

[Mesa-dev] [PATCH] Vulkan: Android.mk: Fix source files path for gen11

Signed-off-by: Harish Krupo --- src/intel/Android.vulkan.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk index 07e69d890a..419d560b0c 100644 --- a/src/intel/Android.vulkan.mk +++

Re: [Mesa-dev] [PATCH] ac: fix nir_op_fdd{x,y} handling

Reviewed-by: Dave Airlie Though I suspect the test should handle getting either. Dave. On 27 February 2018 at 15:49, Timothy Arceri wrote: > radeonsi, i965 and anv all treat fdd{x,y} opcodes the same as > fdd{x,y}_coarse by default. The SPIR-V spec

[Mesa-dev] [PATCH 10/12] vbo: Remove vbo_save_vertex_list::start_vertex.

From: Mathias Fröhlich Replace last use on replay with _vbo_save_get_{min,max}_index. Appart from that it is not used anymore. Signed-off-by: Mathias Fröhlich --- src/mesa/vbo/vbo_save.h | 1 - src/mesa/vbo/vbo_save_api.c | 3 ---

[Mesa-dev] [PATCH 11/12] vbo: Remove vbo_save_vertex_list::buffer_offset.

From: Mathias Fröhlich The buffer_offset is used in aligned_vertex_buffer_offset. But now that most of these decisions are done in compile_vertex_list we can work on local variables instead of struct members in the display list code. Clean that up and remove

[Mesa-dev] [PATCH 07/12] vbo: Remove vbo_save_vertex_list::enabled.

From: Mathias Fröhlich Is not used anymore on replay. Signed-off-by: Mathias Fröhlich --- src/mesa/vbo/vbo_save.h | 1 - src/mesa/vbo/vbo_save_api.c | 3 +-- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git

[Mesa-dev] [PATCH 09/12] vbo: Remove vbo_save_vertex_list::attrsz.

From: Mathias Fröhlich Is not used anymore on replay, move the last use in display list compilation to the original array in the display list compiler. Signed-off-by: Mathias Fröhlich --- src/mesa/vbo/vbo_save.h | 1 -

[Mesa-dev] [PATCH 01/12] vbo: Remove unused vbo_save_vertex_list::dangling_attr_ref.

From: Mathias Fröhlich Signed-off-by: Mathias Fröhlich --- src/mesa/vbo/vbo_save.h | 2 -- src/mesa/vbo/vbo_save_api.c | 1 - 2 files changed, 3 deletions(-) diff --git a/src/mesa/vbo/vbo_save.h b/src/mesa/vbo/vbo_save.h index

[Mesa-dev] [PATCH 03/12] vbo: Use a local variable for the dlist offsets.

From: Mathias Fröhlich The master value is now stored inside the VAO already present in struct vbo_save_vertex_list. Remove the unneeded copy from dlist storage. Signed-off-by: Mathias Fröhlich --- src/mesa/vbo/vbo_save.h | 1 -

[Mesa-dev] [PATCH 02/12] vbo: Remove unused vbo_save_context::wrap_count.

From: Mathias Fröhlich Signed-off-by: Mathias Fröhlich --- src/mesa/vbo/vbo_save.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mesa/vbo/vbo_save.h b/src/mesa/vbo/vbo_save.h index ee3de0fedb..414a477f31 100644 ---

[Mesa-dev] [PATCH 04/12] vbo: Implement vbo_loopback_vertex_list in terms of the VAO.

From: Mathias Fröhlich Use the information already present in the VAO to replay a display list node using immediate mode draw commands. Use a hand full of helper methods that will be useful for the next patches also. Signed-off-by: Mathias Fröhlich

[Mesa-dev] [PATCH 12/12] vbo: Remove vbo_save_vertex_list::vertex_size.

From: Mathias Fröhlich Like before use local variables from compile_vertex_list instead. Remove vertex_size from struct vbo_save_vertex_list. Signed-off-by: Mathias Fröhlich --- src/mesa/vbo/vbo_save.h | 1 - src/mesa/vbo/vbo_save_api.c

[Mesa-dev] [PATCH 00/12] Display list cleanup past the recent changes.

From: Mathias Fröhlich Hi all, The series cleans up duplicated information that is present in the display list nodes since the recent vbo changes. There is again more cleanup and optimization for the dlist draw path available, but that helps for the most obvious. If

[Mesa-dev] [PATCH 06/12] vbo: Remove reference to the vertex_store from the dlist node.

From: Mathias Fröhlich Since we now store a set of VAOs in the display list, use these object to get the reference to the VBO in several places. Signed-off-by: Mathias Fröhlich --- src/mesa/vbo/vbo_save.c | 11 +--

[Mesa-dev] [PATCH 05/12] vbo: Implement current values update in terms of the VAO.

From: Mathias Fröhlich Use the information already present in the VAO to update the current values after display list replay. Set GL_OUT_OF_MEMORY on allocation failure for the current value update storage. Signed-off-by: Mathias Fröhlich ---

[Mesa-dev] [PATCH 08/12] vbo: Remove vbo_save_vertex_list::attrtype.

From: Mathias Fröhlich Is not used anymore on replay, move the last use in display list compilation to the original array in the display list compiler. Signed-off-by: Mathias Fröhlich --- src/mesa/vbo/vbo_save.h | 1 -

Re: [Mesa-dev] Allocator Nouveau driver, Mesa EXT_external_objects, and DRM metadata import interfaces

On 02/22/2018 01:16 PM, Alex Deucher wrote: On Thu, Feb 22, 2018 at 1:49 PM, Bas Nieuwenhuizen wrote: On Thu, Feb 22, 2018 at 7:04 PM, Kristian Høgsberg wrote: On Wed, Feb 21, 2018 at 4:00 PM Alex Deucher wrote: On Wed,

[Mesa-dev] [PATCH] ac: fix nir_op_fdd{x,y} handling

radeonsi, i965 and anv all treat fdd{x,y} opcodes the same as fdd{x,y}_coarse by default. The SPIR-V spec lets the implementation decide how it should be handled and radv was previously going for the higher quality option. Here we change the shared amd code to match how nir_op_fdd{x,y} is expected

Re: [Mesa-dev] [PATCH] Vulkan: Android.mk: Android build fix

On 02/27/2018 05:00 AM, Harish Krupo wrote: Hi Tapani, Tapani Pälli writes: On 02/20/2018 10:10 AM, Harish Krupo wrote: Signed-off-by: Harish Krupo --- src/intel/Android.vulkan.mk | 3 ++- 1 file changed, 2 insertions(+), 1

Re: [Mesa-dev] [PATCH] glsl: Fix memory leak with known glsl_type instances

On 02/26/2018 07:55 PM, Emil Velikov wrote: On 15 February 2018 at 09:12, Tapani Pälli wrote: From: Simon Hausmann When looking up known glsl_type instances in the various hash tables, we end up leaking the key instances used for the lookup, as

Re: [Mesa-dev] [PATCH v3 03/13] intel/genxml: Use a single field for clear color address on gen10.

Reviewed-by: Jordan Justen On 2018-02-21 13:45:12, Rafael Antognolli wrote: > genxml does not support having two address fields with different names > but same position in the state struct. Both "Clear Color Address" > and "Clear Depth Address Low" mean the same thing,

Re: [Mesa-dev] [PATCH v3 06/13] intel/isl: Add support to emit clear value address.

On Mon, Feb 26, 2018 at 8:12 PM, Jordan Justen wrote: > On 2018-02-26 17:08:12, Jason Ekstrand wrote: > > On Mon, Feb 26, 2018 at 1:14 PM, Jordan Justen < > jordan.l.jus...@intel.com> > > wrote: > > > > > On 2018-02-21 13:45:15, Rafael Antognolli wrote: > > > > +

Re: [Mesa-dev] [PATCH] mesa: Update vertex processing mode on _mesa_UseProgram.

Hi Clayton, On Friday, 23 February 2018 22:44:09 CET Clayton Craft wrote: > On Fri, Feb 23, 2018 at 09:01:17PM +0100, mathias.froehl...@gmx.net wrote: > >From: Mathias Fröhlich > > > >Hi Clayton, > > > >The following change fixes the reported problem on my site. >

[Mesa-dev] [PATCH] st/mesa: ensure that images don't try to reference non-existent levels

Ideally the st_finalize_texture call would take care of that, but it doesn't seem to with KHR-GL45.shader_image_size.advanced-nonMS-*. This assertions makes sure that no such values are passed to the driver. Signed-off-by: Ilia Mirkin --- This will trigger asserts in CTS,

[Mesa-dev] [PATCH] trace: allow image resource to be null

Signed-off-by: Ilia Mirkin --- src/gallium/drivers/trace/tr_dump_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/trace/tr_dump_state.c b/src/gallium/drivers/trace/tr_dump_state.c index e7e32237c4c..2d12720ddd9 100644 ---

Re: [Mesa-dev] [PATCH] mesa: Update vertex processing mode on _mesa_UseProgram.

Hi, On Friday, 23 February 2018 22:26:21 CET Ilia Mirkin wrote: > >> Fixes: KHR-GLES31.core.shader_image_load_store.advanced-sso-simple > > > > The "Fixes:" tag is supposed to indicate the git commit which regresses > > Mesa. Release automation processes it when preparing branches for the > >

[Mesa-dev] [PATCH] radv: remove device pointer from buffer.

From: Dave Airlie This is never used. Signed-off-by: Dave Airlie --- src/amd/vulkan/radv_private.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index aa38106..50801e8 100644 ---

Re: [Mesa-dev] [PATCH v3 06/13] intel/isl: Add support to emit clear value address.

On 2018-02-26 17:08:12, Jason Ekstrand wrote: > On Mon, Feb 26, 2018 at 1:14 PM, Jordan Justen > wrote: > > > On 2018-02-21 13:45:15, Rafael Antognolli wrote: > > > + bool use_clear_address; > > > > I'm still wondering about this field. I think at the end we can just

Re: [Mesa-dev] [PATCH] Vulkan: Android.mk: Android build fix

Hi Tapani, Tapani Pälli writes: > On 02/20/2018 10:10 AM, Harish Krupo wrote: >> Signed-off-by: Harish Krupo >> --- >> src/intel/Android.vulkan.mk | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git

Re: [Mesa-dev] [PATCH] RFC: gallium: increase PIPE_MAX_SHADER_SAMPLER_VIEWS to 128

Am 27.02.2018 um 03:38 schrieb srol...@vmware.com: > From: Roland Scheidegger > > Some state trackers require 128. > (There are no plans to increase PIPE_MAX_SAMPLERS too, since with gl > state tracker it's unlikely more than 32 will be needed, if you need > more use

[Mesa-dev] [PATCH] RFC: gallium: increase PIPE_MAX_SHADER_SAMPLER_VIEWS to 128

From: Roland Scheidegger Some state trackers require 128. (There are no plans to increase PIPE_MAX_SAMPLERS too, since with gl state tracker it's unlikely more than 32 will be needed, if you need more use bindless.) --- src/gallium/include/pipe/p_state.h | 2 +- 1 file

[Mesa-dev] [PATCH] ac/shader: fix vertex input with components.

From: Dave Airlie This fixes: dEQP-VK.glsl.440.linkage.varying.component.* Fixes: 1c57a6da5e3 (ac/shader: scan vertex inputs usage mask) Signed-off-by: Dave Airlie --- src/amd/common/ac_shader_info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[Mesa-dev] [PATCH] draw: don't needlessly iterate through all sampler view slots

From: Roland Scheidegger We already stored the highest (potentially) used number. --- src/gallium/auxiliary/draw/draw_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/draw/draw_context.c

[Mesa-dev] [PATCH 2/2] radeonsi/nir: disable vertex_id_zero_based lowering

The lowering is incompatable with how the radeonsi backend works. Fixes piglit test: ./bin/arb_shader_draw_parameters-basevertex vertexid-zerobased -auto --- src/gallium/drivers/radeonsi/si_get.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_get.c

[Mesa-dev] [PATCH 1/2] ac: add support for handling nir_intrinsic_load_vertex_id

This will be used by radeonsi. --- src/amd/common/ac_nir_to_llvm.c | 4 1 file changed, 4 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index c277ed5322..0e38b0b370 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [Bug 104302] Wolfenstein 2 (2017) under wine graphical artifacting on RADV

https://bugs.freedesktop.org/show_bug.cgi?id=104302 --- Comment #7 from gloriouseggr...@gmail.com --- thats what I meant by the distance render blackness - it's fixed in cutscenes. gun shooting and the weird light rays are fixed also. The remaining problem is the facial animations are a bit melty

Re: [Mesa-dev] [PATCH v3 07/13] intel/blorp: Add suport for fast clear address.

On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > On gen10+, if surface->clear_color_addr is present, use it directly > intead of copying it to the surface state. > > Signed-off-by: Rafael Antognolli > --- >

Re: [Mesa-dev] [PATCH v3 06/13] intel/isl: Add support to emit clear value address.

On Mon, Feb 26, 2018 at 1:14 PM, Jordan Justen wrote: > On 2018-02-21 13:45:15, Rafael Antognolli wrote: > > gen10 can emit the clear color by setting it on a buffer somewhere, and > > then adding only the address to the surface state. > > > > This commit add support

Re: [Mesa-dev] [PATCH v3 05/13] intel/genxml: Add Clear Color struct.

On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > The size of the clear color struct (expected by the hardware) is 8 > dwords (isl_dev.ss.clear_value_state_size here). But we still need to > track the size of the clear color, used when memcopying it

[Mesa-dev] [AppVeyor] mesa master #7030 failed

Build mesa 7030 failed Commit 784d81e97e by Emil Velikov on 2/27/2018 12:32 AM: docs: update calendar, add news and link release notes to 17.3.6\n\nSigned-off-by: Emil Velikov Configure your notification preferences

[Mesa-dev] [ANNOUNCE] mesa 17.3.6

Mesa 17.3.6 is now available. This is a emergency release, addressing GPU lockups in the i965 driver. The issue itself is a regression which crept during the 17.3 development cycle. Fingers crossed, this will be the final emergency release in a while. Emil Velikov (3): docs: add sha256

Re: [Mesa-dev] [PATCH v3 03/13] intel/genxml: Use a single field for clear color address on gen10.

Reviewed-by: Jason Ekstrand On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > genxml does not support having two address fields with different names > but same position in the state struct. Both "Clear Color Address" > and "Clear

Re: [Mesa-dev] [PATCH v3 04/13] intel/isl: Update size of clear color value.

This doesn't work. Well, I mean, it sort-of works. At this point in the series, it will break things because Vulkan will start copying 8 dwords into your surface state and over-write the start of another surface state. Later on, I'm sure it's all good because we no longer copy things around. I

[Mesa-dev] Google Summer of Code 2018

Hi everyone, Just a quick word to remind you that the X.Org Foundation got accepted to the Google Summer of Code 2018! As a potential mentor, if you have a project falling under the foundation's (large) umbrella that you would like to kick start or get help finishing, please add it to the list

Re: [Mesa-dev] [PATCH v3 02/13] genxml: Preserve fields that share dword space with addresses.

On Mon, Feb 26, 2018 at 3:10 PM, Jason Ekstrand wrote: > This patch would be much easier to review if the commit message had an > example of the change. > > On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli < > rafael.antogno...@intel.com> wrote: > >> Some instructions

Re: [Mesa-dev] [RFC] opencl: mega-cl

On Mon, Feb 26, 2018 at 6:12 PM, Francisco Jerez wrote: > Rob Clark writes: > >> On Sun, Feb 25, 2018 at 3:00 PM, Francisco Jerez >> wrote: >>> Seems like a serious hack to me to work around broken linking... IMO we >>> should

[Mesa-dev] [AppVeyor] mesa 17.3 #7027 completed

Build mesa 7027 completed Commit b3e5a3f35b by Emil Velikov on 2/27/2018 12:18 AM: docs: add release notes for 17.3.6\n\nSigned-off-by: Emil Velikov Configure your notification preferences

Re: [Mesa-dev] [PATCH] radv: expose async compute on SI

Acked-by: Bas Nieuwenhuizen On Tue, Feb 27, 2018 at 12:58 AM, Dave Airlie wrote: > From: Dave Airlie > > It looks like we had all the pieces in place for this, > just never tested it and turned it on. > > I don't see any CTS

[Mesa-dev] [PATCH] i965: Allow 48-bit addressing on Gen8+.

This allows most GPU objects to use the full 48-bit address space offered by Gen8+ platforms, rather than being stuck with 32-bit. This expands the available GPU memory from 4G to 256TB or so. A few objects - instruction, scratch, and vertex buffers - need to remain pinned in the low 4GB of the

[Mesa-dev] [PATCH] radv: expose async compute on SI

From: Dave Airlie It looks like we had all the pieces in place for this, just never tested it and turned it on. I don't see any CTS regressions and the computeshader demo runs. Signed-off-by: Dave Airlie --- src/amd/vulkan/radv_device.c | 2 -- 1 file

[Mesa-dev] [PATCH 1/2] i965: Add debugging code to dump the validation list.

When anything goes wrong with this code, dumping the validation list is a useful way to figure out what's happening. --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 20 1 file changed, 20 insertions(+) I've now used this code on multiple occasions to debug issues.

[Mesa-dev] [PATCH 2/2] i965: Shorten the name of the workaround BO.

This makes the name shorter in debug printouts. If "workaround_bo" is good enough for the code, it's probably good enough for debugging. --- src/mesa/drivers/dri/i965/brw_pipe_control.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git

[Mesa-dev] [Bug 105207] The Talos Principle freezes system using radv

https://bugs.freedesktop.org/show_bug.cgi?id=105207 pritzl3...@gmail.com changed: What|Removed |Added Attachment #137625|0 |1 is obsolete|

[Mesa-dev] [Bug 105207] The Talos Principle freezes system using radv

https://bugs.freedesktop.org/show_bug.cgi?id=105207 pritzl3...@gmail.com changed: What|Removed |Added Attachment #137624|0 |1 is obsolete|

[Mesa-dev] [Bug 105255] Waiting for fences without waitAll is not implemented

https://bugs.freedesktop.org/show_bug.cgi?id=105255 --- Comment #1 from Bas Nieuwenhuizen --- https://patchwork.freedesktop.org/patch/206938/ should fix this. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the

[Mesa-dev] [PATCH 2/4] radv: Implement waiting on non-submitted fences.

Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver" --- src/amd/vulkan/radv_device.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index ca99ba50ba..3355fd0b4b 100644 ---

[Mesa-dev] [PATCH 3/4] radv: Implement more efficient !waitAll fence waiting.

--- src/amd/vulkan/radv_device.c | 36 +++ src/amd/vulkan/radv_radeon_winsys.h | 5 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 34 + 3 files changed, 75 insertions(+) diff --git a/src/amd/vulkan/radv_device.c

[Mesa-dev] [PATCH 1/4] radv: Implement WaitForFences with !waitAll.

Nothing to do except using a busy wait loop. At least for old kernels. A better implementation for newer kernels to come later. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105255 Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver" --- src/amd/vulkan/radv_device.c

[Mesa-dev] [PATCH 4/4] radv: Use the syncobj wait ioctl to wait on fences if possible.

Handles the !waitAll and signal after the start of the wait cases correctly. --- src/amd/vulkan/radv_device.c | 24 src/amd/vulkan/radv_radeon_winsys.h | 3 ++- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 8 3 files changed, 26

Re: [Mesa-dev] [PATCH] disk cache: Link with -latomic if necessary

On Fri, 23 Feb 2018 at 13:18 Thierry Reding wrote: > From: Thierry Reding > > The disk cache implementation uses 64-bit atomic operations. For some > architectures, such as 32-bit ARM, GCC will not be able to translate > these operations into

Re: [Mesa-dev] [RFC] opencl: mega-cl

Rob Clark writes: > On Sun, Feb 25, 2018 at 3:00 PM, Francisco Jerez > wrote: >> Seems like a serious hack to me to work around broken linking... IMO we >> should just fix the linking issue. The symbols for the various GLSL >> types need to be

Re: [Mesa-dev] [PATCH v3 02/13] genxml: Preserve fields that share dword space with addresses.

This patch would be much easier to review if the commit message had an example of the change. On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > Some instructions contain fields that are either an address or a value > of some type based on the content of

Re: [Mesa-dev] [PATCH 11/22] nir: Recognize some more open-coded fmin / fmax

Am 26.02.2018 um 23:21 schrieb Ian Romanick: > On 02/23/2018 05:14 PM, Jason Ekstrand wrote: >> On Fri, Feb 23, 2018 at 3:55 PM, Ian Romanick > > wrote: >> >> From: Ian Romanick >

Re: [Mesa-dev] [PATCH] radv/gfx9: add a workaround for viewing a slice of 3D as a 2D image

On 26 February 2018 at 23:04, Samuel Pitoiset wrote: > Ported from RadeonSI. > > That doesn't fix anything known but I think we need it. I'd really like it to fix something :-) How come we don't also need it for the TXF path? Dave. > > Signed-off-by: Samuel Pitoiset

[Mesa-dev] [Bug 105207] The Talos Principle freezes system using radv

https://bugs.freedesktop.org/show_bug.cgi?id=105207 --- Comment #9 from pritzl3...@gmail.com --- Created attachment 137625 --> https://bugs.freedesktop.org/attachment.cgi?id=137625=edit backtrace -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact

[Mesa-dev] [Bug 105207] The Talos Principle freezes system using radv

https://bugs.freedesktop.org/show_bug.cgi?id=105207 pritzl3...@gmail.com changed: What|Removed |Added Attachment #137546|0 |1 is obsolete|

[Mesa-dev] [Bug 105207] The Talos Principle freezes system using radv

https://bugs.freedesktop.org/show_bug.cgi?id=105207 --- Comment #7 from pritzl3...@gmail.com --- Managed to get a core dump finally. I am now on LLVM 6.0.0-rc3 and Mesa 18.0.0-rc4 and the hang still happens. Attaching a new tracefile and a backtrace from the same crash. I compiled LLVM and Mesa

Re: [Mesa-dev] [PATCH 11/22] nir: Recognize some more open-coded fmin / fmax

On 02/26/2018 02:43 PM, Jason Ekstrand wrote: > On Mon, Feb 26, 2018 at 2:21 PM, Ian Romanick > wrote: > > On 02/23/2018 05:14 PM, Jason Ekstrand wrote: > > On Fri, Feb 23, 2018 at 3:55 PM, Ian Romanick

Re: [Mesa-dev] [PATCH] i965/sbe: fix number of inputs for active components

On 02/26/2018 02:39 AM, Iago Toral Quiroga wrote: > In 16631ca30ea6 we fixed gen9 active components to account for padded > inputs in the URB, which we can have with SSO programs. To do that, > instead of going through the bitfield of inputs (which doesn't include > padding information), we

Re: [Mesa-dev] [PATCH 11/22] nir: Recognize some more open-coded fmin / fmax

On Mon, Feb 26, 2018 at 2:21 PM, Ian Romanick wrote: > On 02/23/2018 05:14 PM, Jason Ekstrand wrote: > > On Fri, Feb 23, 2018 at 3:55 PM, Ian Romanick > > wrote: > > > > From: Ian Romanick

Re: [Mesa-dev] Patch submit question

It’s a commit that needs to be slightly different in master and 18.0, hence 2x the # of commits. Thanks for the 662cff8f pointer. Perfect example! George > On Feb 26, 2018, at 4:14 PM, Emil Velikov wrote: > > On 26 February 2018 at 20:18, Kyriazis, George >

Re: [Mesa-dev] [PATCH 11/22] nir: Recognize some more open-coded fmin / fmax

On 02/23/2018 05:14 PM, Jason Ekstrand wrote: > On Fri, Feb 23, 2018 at 3:55 PM, Ian Romanick > wrote: > > From: Ian Romanick > > > shader-db results: > > Haswell,

[Mesa-dev] [PATCH shaderdb 3/3] run: shader program file created via GetProgramBinary (v3)

extraction of linked binary program to a file using glGetProgramBinary. This file is intended to be loaded by glProgramBinary in the graphic application running on the target system. To enable this feature, a new option '--bin' has to be passed to the program execution. v2: 1. define MAX_LOG_LEN

Re: [Mesa-dev] [PATCH v3 05/13] intel/genxml: Add Clear Color struct.

On Mon, Feb 26, 2018 at 01:07:54PM -0800, Jordan Justen wrote: > On 2018-02-21 13:45:14, Rafael Antognolli wrote: > > The size of the clear color struct (expected by the hardware) is 8 > > dwords (isl_dev.ss.clear_value_state_size here). But we still need to > > track the size of the clear color,

Re: [Mesa-dev] Patch submit question

On 26 February 2018 at 20:18, Kyriazis, George wrote: > Thanks Jordan, > > Since I won’t be checking this in to mesa master, what do I need to do to > actually push it to the stable branch, after I get a review on mesa-dev? > When possible, please refrain from pushing

Re: [Mesa-dev] [PATCH v3 07/13] intel/blorp: Add suport for fast clear address.

On 2018-02-21 13:45:16, Rafael Antognolli wrote: > On gen10+, if surface->clear_color_addr is present, use it directly > intead of copying it to the surface state. > > Signed-off-by: Rafael Antognolli > --- > src/intel/blorp/blorp_genX_exec.h | 12 +--- > 1

Re: [Mesa-dev] [PATCH v3 06/13] intel/isl: Add support to emit clear value address.

On 2018-02-21 13:45:15, Rafael Antognolli wrote: > gen10 can emit the clear color by setting it on a buffer somewhere, and > then adding only the address to the surface state. > > This commit add support for that on isl_surf_fill_state, and if that is > requested, skip setting the clear value

Re: [Mesa-dev] [PATCH v3 05/13] intel/genxml: Add Clear Color struct.

On 2018-02-21 13:45:14, Rafael Antognolli wrote: > The size of the clear color struct (expected by the hardware) is 8 > dwords (isl_dev.ss.clear_value_state_size here). But we still need to > track the size of the clear color, used when memcopying it to/from the > state buffer. For that we keep

Re: [Mesa-dev] [PATCH] i965/sbe: fix number of inputs for active components

Please add the Fixes: tag, so this patch gets applied to the appropriate stable branches. Iago Toral Quiroga writes: > In 16631ca30ea6 we fixed gen9 active components to account for padded > inputs in the URB, which we can have with SSO programs. To do that, > instead of

[Mesa-dev] [PATCH v2] swr/rast: Fix index buffer overfetch issue for non-indexed draws

Populate pLastIndex, even for the non-indexed case. A zero pLastIndex can cause the index offsets inside the fetcher to have non-sensical values that can be either very large positive or very large negative numbers. v2 remove cc mesa-stable, since the stable patch needs to be different from this

Re: [Mesa-dev] Patch submit question

Thanks Jordan, Since I won’t be checking this in to mesa master, what do I need to do to actually push it to the stable branch, after I get a review on mesa-dev? George > On Feb 23, 2018, at 5:43 PM, Justen, Jordan L > wrote: > > On 2018-02-23 13:20:21, Kyriazis,

Re: [Mesa-dev] [PATCH 08/15] glsl: Switch ast_type_qualifier to a 128-bit bitset.

It also fixes the errors that I was getting with gcc 5.4.0 with configure build on ubuntu 16.04. Tested-By: George Kyriazis > On Feb 25, 2018, at 6:52 PM, Roland Scheidegger > wrote: Am

Re: [Mesa-dev] [PATCH] disk cache: Link with -latomic if necessary

Quoting Thierry Reding (2018-02-23 05:18:28) > From: Thierry Reding > > The disk cache implementation uses 64-bit atomic operations. For some > architectures, such as 32-bit ARM, GCC will not be able to translate > these operations into lock-free instructions and will instead

Re: [Mesa-dev] [PATCH v3 01/13] anv/image: Do not override lower bits of dword.

On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > The lower bits seem to have extra fields in every platform but gen8 > (even though we don't use them in gen9). So just go ahead and avoid > using them for the address. > > Signed-off-by: Rafael Antognolli

Re: [Mesa-dev] [PATCH 12/17] intel/compiler/fs: Implement ddy without using align16 for Gen11+

On Fri, Feb 23, 2018 at 4:42 PM, Kenneth Graunke wrote: > On Tuesday, February 20, 2018 9:15:19 PM PST Matt Turner wrote: >> Align16 is no more. We previously generated an align16 ADD instruction >> to calculate DDY: >> >>add(8) g11<1>F -g10<4>.xyxyF g10<4>.zwzwF {

Re: [Mesa-dev] [PATCH 11/17] intel/compiler/fs: Simplify ddx/ddy code generation

On Fri, Feb 23, 2018 at 4:37 PM, Kenneth Graunke wrote: > On Tuesday, February 20, 2018 9:15:18 PM PST Matt Turner wrote: >> The brw_reg() constructor just obfuscates things here, in my opinion. >> --- >> src/intel/compiler/brw_fs_generator.cpp | 77 >>

Re: [Mesa-dev] [PATCH 1/7] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit (v2)

On Mon, Feb 26, 2018 at 10:09 AM, Chema Casanova wrote: > On 26/02/18 18:20, Jason Ekstrand wrote: > > I've lost track of what's reviewed and what's not. Could you either > > just send a status list or do a resend once all the current comments are > > handled? > >

Re: [Mesa-dev] [PATCH] disk cache: Link with -latomic if necessary

On Fri, Feb 23, 2018 at 5:18 AM, Thierry Reding wrote: > From: Thierry Reding > > The disk cache implementation uses 64-bit atomic operations. For some > architectures, such as 32-bit ARM, GCC will not be able to translate > these operations into

Re: [Mesa-dev] [PATCH 3/3] build: Move wayland-scanner check into platform

On 23 February 2018 at 11:22, Daniel Stone wrote: > Also only check for wayland-scanner if building for the Wayland > platform. > > Signed-off-by: Daniel Stone > Fixes: bfa22266cd4d ("vulkan/wsi/wayland: Add support for zwp_dmabuf") > Cc: Emil

Re: [Mesa-dev] [PATCH 1/7] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit (v2)

On 26/02/18 18:20, Jason Ekstrand wrote: > I've lost track of what's reviewed and what's not.  Could you either > just send a status list or do a resend once all the current comments are > handled? Reviewed-by and all feedback addressed -- [1/7] anv/spirv:

Re: [Mesa-dev] Mesa (master): glsl: Switch ast_type_qualifier to a 128-bit bitset.

Am 26.02.2018 um 18:52 schrieb Kyriazis, George: > Hello Francisco, > > This change breaks my ubuntu 16.04 build with gcc 5.4.0. Here’t where it > breaks: > > CXX glsl/glsl_lexer.lo > In file included from ../../../src/compiler/glsl/glsl_lexer.ll:27:0: >

Re: [Mesa-dev] [PATCH] glsl: Fix memory leak with known glsl_type instances

On 15 February 2018 at 09:12, Tapani Pälli wrote: > From: Simon Hausmann > > When looking up known glsl_type instances in the various hash tables, we > end up leaking the key instances used for the lookup, as the glsl_type > constructor allocates

Re: [Mesa-dev] Mesa (master): glsl: Switch ast_type_qualifier to a 128-bit bitset.

Hello Francisco, This change breaks my ubuntu 16.04 build with gcc 5.4.0. Here’t where it breaks: CXX glsl/glsl_lexer.lo In file included from ../../../src/compiler/glsl/glsl_lexer.ll:27:0: ../../../src/compiler/glsl/ast.h:643:16: error: member ‘ast_type_qualifier::bitset_t

Re: [Mesa-dev] [PATCH 3/7] i965/fs: Support 16-bit store_ssbo with VK_KHR_relaxed_block_layout

On 23/02/18 21:23, Jason Ekstrand wrote: > On Fri, Feb 23, 2018 at 1:26 AM, Jose Maria Casanova Crespo > > wrote: > > Restrict the use of untyped_surface_write with 16-bit pairs in > ssbo to the cases where we can guarantee that offset

Re: [Mesa-dev] [PATCH] meson: fix building without GL

Quoting Emil Velikov (2018-02-26 09:11:35) > On 26 February 2018 at 16:46, Dylan Baker wrote: > > libgl will be undefined if with_glx == 'disabled', so move that check > > inside the `if with_glx == 'disabled'` block immediately after that > > check. > > > There's some of

Re: [Mesa-dev] [PATCH] meson: fix building without GL

Quoting Eric Engestrom (2018-02-26 09:13:47) > On Monday, 2018-02-26 16:56:46 +, Eric Engestrom wrote: > > On Monday, 2018-02-26 08:46:54 -0800, Dylan Baker wrote: > > > libgl will be undefined if with_glx == 'disabled', so move that check > > > inside the `if with_glx == 'disabled'` block

Re: [Mesa-dev] [PATCH 1/7] isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bit (v2)

I've lost track of what's reviewed and what's not. Could you either just send a status list or do a resend once all the current comments are handled? --Jason On February 26, 2018 09:08:01 Chema Casanova wrote: On 26/02/18 16:54, Jason Ekstrand wrote: On Mon, Feb

Re: [Mesa-dev] [PATCH] meson: fix building without GL

On Monday, 2018-02-26 16:56:46 +, Eric Engestrom wrote: > On Monday, 2018-02-26 08:46:54 -0800, Dylan Baker wrote: > > libgl will be undefined if with_glx == 'disabled', so move that check > > inside the `if with_glx == 'disabled'` block immediately after that > typo: s/==/!=/^^ >

Re: [Mesa-dev] [PATCH] meson: fix building without GL

On 26 February 2018 at 16:46, Dylan Baker wrote: > libgl will be undefined if with_glx == 'disabled', so move that check > inside the `if with_glx == 'disabled'` block immediately after that > check. > There's some of repetition, making this hard to read. Perhaps: "libgl

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