Re: [Mesa-dev] [PATCH 00/26] RadeonSI: Primitive culling with async compute

On 13/02/2019 06:15, Marek Olšák wrote: I decided to enable this optimization on all Pro graphics cards. The reason is that I haven't had time to benchmark games. This decision may be changed based on community feedback, etc. Could the decision to run the optimization be based on some perf

Re: [Mesa-dev] [PATCH 1/3] mesa: add explicit enable for EXT_float_blend, and error condition

Patches 1 and 3 are Reviewed-by: Tapani Pälli On 2/13/19 5:40 AM, Ilia Mirkin wrote: If EXT_float_blend is not supported, error out on blending of FP32 attachments in an ES2 context. Signed-off-by: Ilia Mirkin --- src/mesa/main/draw_validate.c| 19 +++

Re: [Mesa-dev] [PATCH v4 39/40] anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+

On Tue, 2019-02-12 at 08:43 -0600, Jason Ekstrand wrote: > On February 12, 2019 05:57:09 Iago Toral Quiroga > wrote: > > > v2: > > - Merge Float16 and Int8 capabilities into a single patch (Jason) > > - Merged patch that enabled SPIR-V front-end checks for these caps > >(except for Int8,

[Mesa-dev] [PATCH 26/26] radeonsi: cull primitives with async compute for large draw calls

From: Marek Olšák --- src/gallium/drivers/radeonsi/Makefile.sources |1 + src/gallium/drivers/radeonsi/meson.build |1 + .../radeonsi/si_compute_prim_discard.c| 1537 + src/gallium/drivers/radeonsi/si_debug.c | 32 +-

[Mesa-dev] [PATCH 08/26] winsys/amdgpu: add a parallel compute IB coupled with a gfx IB

From: Marek Olšák --- src/amd/common/ac_gpu_info.c | 6 + src/amd/common/ac_gpu_info.h | 2 + src/gallium/drivers/r600/r600_pipe_common.c | 4 +- src/gallium/drivers/radeon/radeon_winsys.h| 36 ++- src/gallium/drivers/radeonsi/si_fence.c |

[Mesa-dev] [PATCH 24/26] radeonsi: add si_vs_prolog_bits::unpack_instance_id_from_vertex_id:1

From: Marek Olšák The prim discard compute shader bakes InstanceID into the output index buffer. --- src/gallium/drivers/radeonsi/si_shader.c | 25 ++-- src/gallium/drivers/radeonsi/si_shader.h | 1 + 2 files changed, 24 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 20/26] radeonsi: allow si_shader_select_with_key to return an optimized shader or fail

From: Marek Olšák If a prim discard compute shader hasn't finished compilation, we don't want to any shader. --- src/gallium/drivers/radeonsi/si_state.h | 7 .../drivers/radeonsi/si_state_shaders.c | 38 +-- 2 files changed, 33 insertions(+), 12 deletions(-)

[Mesa-dev] [PATCH 18/26] radeonsi: add threadgroups_per_cu param into si_get_compute_resource_limits

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_compute.c | 9 ++--- src/gallium/drivers/radeonsi/si_pipe.h| 3 ++- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index

[Mesa-dev] [PATCH 23/26] radeonsi: add helper si_get_minimum_num_gfx_cs_dwords

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_gfx_cs.c | 8 +--- src/gallium/drivers/radeonsi/si_pipe.h | 11 +++ 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index

[Mesa-dev] [PATCH 22/26] radeonsi: add a cs parameter into si_cp_copy_data

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_compute.c | 2 +- src/gallium/drivers/radeonsi/si_cp_dma.c | 9 - src/gallium/drivers/radeonsi/si_perfcounter.c | 2 +- src/gallium/drivers/radeonsi/si_pipe.h| 2 +- src/gallium/drivers/radeonsi/si_state_draw.c | 2

[Mesa-dev] [PATCH 25/26] ac: add LLVM code for triangle culling

From: Marek Olšák --- src/amd/Makefile.sources | 2 + src/amd/common/ac_llvm_cull.c | 275 ++ src/amd/common/ac_llvm_cull.h | 59 src/amd/common/meson.build| 2 + 4 files changed, 338 insertions(+) create mode 100644

[Mesa-dev] [PATCH 07/26] winsys/amdgpu: reorder chunks, make BO_HANDLES first, IB and FENCE last

From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 36 +++ 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index 319741f7d0b..4a588d52930 100644 ---

[Mesa-dev] [PATCH 12/26] radeonsi: return the last part's return value from @wrapper

From: Marek Olšák The primitive discard compute shader will get the position output this way. --- src/gallium/drivers/radeonsi/si_shader.c | 29 +--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c

[Mesa-dev] [PATCH 17/26] radeonsi: use pipe_draw_info::instance_count indirectly

From: Marek Olšák It will be modified by compute shader culling. --- src/gallium/drivers/radeonsi/si_state_draw.c | 36 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c

[Mesa-dev] [PATCH 19/26] radeonsi: add a cs parameter into si_cp_release_mem

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_fence.c | 5 ++--- src/gallium/drivers/radeonsi/si_perfcounter.c | 2 +- src/gallium/drivers/radeonsi/si_pipe.h| 2 +- src/gallium/drivers/radeonsi/si_query.c | 6 +++--- src/gallium/drivers/radeonsi/si_state_draw.c | 4

[Mesa-dev] [PATCH 21/26] radeonsi: make some functions non-static

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_state.c | 20 ++- src/gallium/drivers/radeonsi/si_state.h | 15 ++ .../drivers/radeonsi/si_state_shaders.c | 8 3 files changed, 25 insertions(+), 18 deletions(-) diff --git

[Mesa-dev] [PATCH 16/26] radeonsi: make functions for creating LLVM functions non-static

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_shader.c | 30 +-- .../drivers/radeonsi/si_shader_internal.h | 25 2 files changed, 32 insertions(+), 23 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c

[Mesa-dev] [PATCH 14/26] radeonsi: make si_initialize_compute reusable

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_compute.c | 14 +++--- src/gallium/drivers/radeonsi/si_pipe.h| 1 + 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index

[Mesa-dev] [PATCH 15/26] radeonsi: move si_*_descriptors_idx functions into si_state.h

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_descriptors.c | 14 -- src/gallium/drivers/radeonsi/si_state.h | 14 ++ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c

[Mesa-dev] [PATCH 01/26] tgsi/scan: add uses_drawid

From: Marek Olšák --- src/gallium/auxiliary/tgsi/tgsi_scan.c | 3 +++ src/gallium/auxiliary/tgsi/tgsi_scan.h | 1 + src/gallium/drivers/radeonsi/si_shader_nir.c | 3 +++ 3 files changed, 7 insertions(+) diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c

[Mesa-dev] [PATCH 04/26] ac: add ac_get_i1_sgpr_mask

From: Marek Olšák --- src/amd/common/ac_llvm_build.c | 16 src/amd/common/ac_llvm_build.h | 2 ++ 2 files changed, 18 insertions(+) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 9395bd1bbda..7adca596943 100644 ---

[Mesa-dev] [PATCH 10/26] radeonsi: add si_cp_copy_data

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_compute.c | 21 -- src/gallium/drivers/radeonsi/si_cp_dma.c | 28 +++ src/gallium/drivers/radeonsi/si_perfcounter.c | 13 ++--- src/gallium/drivers/radeonsi/si_pipe.h| 3 ++

[Mesa-dev] [PATCH 09/26] winsys/amdpgu: retry after ENOMEM to work around a GDS memory management bug

From: Marek Olšák If GDS/GWS/OA resources are being used by IBs that are currently busy, the kernel driver returns -ENOMEM instead of waiting until those resources are idle. --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 17 + 1 file changed, 13 insertions(+), 4 deletions(-)

[Mesa-dev] [PATCH 13/26] radeonsi: extract COMPUTE_RESOURCE_LIMITS code into a helper

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_compute.c | 32 ++- src/gallium/drivers/radeonsi/si_pipe.h| 3 +++ 2 files changed, 23 insertions(+), 12 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c

[Mesa-dev] [PATCH 06/26] winsys/amdgpu: make IBs writable and expose their address

From: Marek Olšák --- src/gallium/drivers/radeon/radeon_winsys.h | 1 + src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 5 - 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index

[Mesa-dev] [PATCH 11/26] radeonsi: use pipe_draw_info::prim and primitive_restart indirectly

From: Marek Olšák so that the fields can be changed by the driver. --- src/gallium/drivers/radeonsi/si_state_draw.c | 73 +++- 1 file changed, 41 insertions(+), 32 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c

[Mesa-dev] [PATCH 05/26] ac: add REWIND and GDS registers to register headers

From: Marek Olšák --- src/amd/common/sid.h | 16 1 file changed, 16 insertions(+) diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h index 5c8eee0124d..3c0b7001d2b 100644 --- a/src/amd/common/sid.h +++ b/src/amd/common/sid.h @@ -206,6 +206,7 @@ #define PKT3_RELEASE_MEM

[Mesa-dev] [PATCH 02/26] ac: add radeon_info::marketing_name, replacing the winsys callback

From: Marek Olšák --- src/amd/common/ac_gpu_info.c | 2 ++ src/amd/common/ac_gpu_info.h | 1 + src/gallium/drivers/r600/r600_pipe_common.c | 13 + src/gallium/drivers/radeon/radeon_winsys.h| 2 -- src/gallium/drivers/radeonsi/si_get.c

[Mesa-dev] [PATCH 00/26] RadeonSI: Primitive culling with async compute

Hi, This patch series uses async compute to do primitive culling before the vertex shader. It significantly improves performance for applications that use a lot of geometry that is invisible because primitives don't intersect sample points or there are a lot of back faces, etc. It passes

[Mesa-dev] [PATCH 03/26] ac: add radeon_info::is_pro_graphics

From: Marek Olšák --- src/amd/common/ac_gpu_info.c | 3 +++ src/amd/common/ac_gpu_info.h | 1 + 2 files changed, 4 insertions(+) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 4e3190015e7..6971e4f0a8e 100644 --- a/src/amd/common/ac_gpu_info.c +++

Re: [Mesa-dev] [PATCH 2/3] st/mesa: enable GL_EXT_float_blend when possible

On Tue, Feb 12, 2019 at 11:13 PM Jason Ekstrand wrote: > > On February 12, 2019 21:40:49 Ilia Mirkin wrote: > > > If the driver supports PIPE_BIND_BLENABLE on RGBA32F, flip > > EXT_float_blend on (which will affect ES3 contexts). > > > > Signed-off-by: Ilia Mirkin > > --- > >

Re: [Mesa-dev] [PATCH 2/3] st/mesa: enable GL_EXT_float_blend when possible

On February 12, 2019 21:40:49 Ilia Mirkin wrote: If the driver supports PIPE_BIND_BLENABLE on RGBA32F, flip EXT_float_blend on (which will affect ES3 contexts). Signed-off-by: Ilia Mirkin --- src/mesa/state_tracker/st_extensions.c | 10 ++ 1 file changed, 10 insertions(+) diff --git

[Mesa-dev] [PATCH 3/3] i965: always enable EXT_float_blend

From the table in isl_format.c, it appears that all generations support blending on 32-bit float surfaces. Signed-off-by: Ilia Mirkin --- src/mesa/drivers/dri/i965/intel_extensions.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c

[Mesa-dev] [PATCH 1/3] mesa: add explicit enable for EXT_float_blend, and error condition

If EXT_float_blend is not supported, error out on blending of FP32 attachments in an ES2 context. Signed-off-by: Ilia Mirkin --- src/mesa/main/draw_validate.c| 19 +++ src/mesa/main/extensions_table.h | 2 +- src/mesa/main/fbobject.c | 4

[Mesa-dev] [PATCH 2/3] st/mesa: enable GL_EXT_float_blend when possible

If the driver supports PIPE_BIND_BLENABLE on RGBA32F, flip EXT_float_blend on (which will affect ES3 contexts). Signed-off-by: Ilia Mirkin --- src/mesa/state_tracker/st_extensions.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/src/mesa/state_tracker/st_extensions.c

[Mesa-dev] [Bug 109107] gallium/st/va: change va max_profiles when using Radeon VCN Hardware

https://bugs.freedesktop.org/show_bug.cgi?id=109107 zhoulei changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

Re: [Mesa-dev] [PATCH] nir: fix example in opt_peel_loop_initial_if description

Rb On February 12, 2019 12:48:58 Caio Marcelo de Oliveira Filho wrote: --- src/compiler/nir/nir_opt_if.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c index 9afb901be14..170caaad89d 100644 ---

Re: [Mesa-dev] [PATCH] nir: move ALU instruction before the jump instruction

On February 12, 2019 18:22:36 Ian Romanick wrote: On 2/12/19 12:58 AM, Juan A. Suarez Romero wrote: opt_split_alu_of_phi moves ALU instruction to the end of continue block. But if the continue block ends with a jump instruction (an explicit "continue" instruction) then the ALU must be

Re: [Mesa-dev] [PATCH] nir: move ALU instruction before the jump instruction

On 2/12/19 12:58 AM, Juan A. Suarez Romero wrote: > opt_split_alu_of_phi moves ALU instruction to the end of continue block. > > But if the continue block ends with a jump instruction (an explicit > "continue" instruction) then the ALU must be inserted before the jump, > as it is illegal to add

[Mesa-dev] [Bug 109617] [oland, clover, llvm5] While-If Problem with Booleans

https://bugs.freedesktop.org/show_bug.cgi?id=109617 --- Comment #3 from Jan Vesely --- This looks like clang/llvm kernel miscompile. Can you reproduce using more recent llvm version (ideally git)? -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee

[Mesa-dev] [Bug 109617] [oland, clover, llvm5] While-If Problem with Booleans

https://bugs.freedesktop.org/show_bug.cgi?id=109617 Jan Vesely changed: What|Removed |Added Blocks||99553 Summary|Gallium OpenCL:

[Mesa-dev] [Bug 99553] Tracker bug for runnning OpenCL applications on Clover

https://bugs.freedesktop.org/show_bug.cgi?id=99553 Jan Vesely changed: What|Removed |Added Depends on||109617 Referenced Bugs:

[Mesa-dev] [Bug 109617] [oland, clover, llvm5] While-If Problem with Booleans

https://bugs.freedesktop.org/show_bug.cgi?id=109617 --- Comment #2 from Jan Vesely --- results: xxx Correct executionxx xxx --- bool flag = false;

[Mesa-dev] [Bug 109617] Gallium OpenCL: While-If Problem with Booleans

https://bugs.freedesktop.org/show_bug.cgi?id=109617 Bug ID: 109617 Summary: Gallium OpenCL: While-If Problem with Booleans Product: Mesa Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW

[Mesa-dev] [ANNOUNCE] mesa 19.0.0-rc3

Hi List, Mesa 19.0-rc3 is now available. Due to a bug I discovered in the script that scrapes for stable nominations (after uploading the tarball) there is basically nothing in the -rc3 release. As a result I'm planning to make a -rc4 tomorrow. You can see the staging/19.0 branch to see the

Re: [Mesa-dev] [PATCH] radeonsi: Fix guardband computation for large render targets

Pushed, thanks! Marek On Tue, Feb 12, 2019 at 2:55 PM Oscar Blumberg wrote: > Stop using 12.12 quantization for viewports that are not contained in > the lower 4k corner of the render target as the hardware needs to keep > both absolute and relative coordinates representable. > --- >

[Mesa-dev] [PATCH v2 6/6] glsl/linker: check for xfb_offset aliasing

From page 76 (page 80 of the PDF) of the GLSL 4.60 v.5 spec: " No aliasing in output buffers is allowed: It is a compile-time or link-time error to specify variables with overlapping transform feedback offsets." Currently, this is expected to fail, but it succeeds: " ...

[Mesa-dev] radeonsi: NIR - Polaris triangle sprinkling running UH SOLVED - finally

Hello Marek, Timo, Nicolai, Timo SOLVED this long-standing NIR corruption on Polaris with his 'nir: rewrite varying component packing' commit. It was triggered with commit 86b52d42368ac496fe24bc6674e754c323381635 Author: Marek Olšák Date: Fri Jul 13 00:23:36 2018 -0400 radeonsi:

[Mesa-dev] [Bug 109107] gallium/st/va: change va max_profiles when using Radeon VCN Hardware

https://bugs.freedesktop.org/show_bug.cgi?id=109107 --- Comment #6 from Michael Eagle --- I can confirm that now chrome is no longer printing ERROR:vaapi_wrapper.cc(568)] : vaQueryConfigProfiles returned: 14 in terminal, and chrome://media-internals/ reports: video_decoder GpuVideoDecoder So,

[Mesa-dev] [PATCH] radeonsi: Fix guardband computation for large render targets

Stop using 12.12 quantization for viewports that are not contained in the lower 4k corner of the render target as the hardware needs to keep both absolute and relative coordinates representable. --- .../drivers/radeonsi/si_state_viewport.c | 30 +-- 1 file changed, 28

[Mesa-dev] [PATCH v6 5/5] gallium/auxiliary/vl: Add video compositor compute shader render

Add compute shader initilization, assign and cleanup in vl_compositor API. Set video compositor compute shader render as default when pipe support it. Signed-off-by: James Zhu Reviewed-by: Christian König --- src/gallium/auxiliary/vl/vl_compositor.c | 106 +++

[Mesa-dev] [PATCH] nir/xfb: Properly align 64-bit values

Fixes: 19064b8c "nir: Add a pass for gathering transform feedback info" Cc: Alejandro Piñeiro --- src/compiler/nir/nir_gather_xfb_info.c | 44 ++ 1 file changed, 44 insertions(+) diff --git a/src/compiler/nir/nir_gather_xfb_info.c

[Mesa-dev] [PATCH] nir: fix example in opt_peel_loop_initial_if description

--- src/compiler/nir/nir_opt_if.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c index 9afb901be14..170caaad89d 100644 --- a/src/compiler/nir/nir_opt_if.c +++ b/src/compiler/nir/nir_opt_if.c @@ -96,7 +96,7 @@

[Mesa-dev] [Bug 109201] Deep Rock Galactic: GPU Hang (Steam Play) (DXVK)

https://bugs.freedesktop.org/show_bug.cgi?id=109201 --- Comment #15 from Alexander --- unfortunately still the same -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list

Re: [Mesa-dev] [PATCH] nir: remove jump from two merging jump-ending blocks

On Tue, Feb 12, 2019 at 04:38:04PM +0100, Juan A. Suarez Romero wrote: > In opt_peel_initial_if optimization, when moving the continue list to > end of the continue block, before the jump, could happen that the > continue list itself also ends with a jump. > > This would mean that we would have

Re: [Mesa-dev] [PATCH] nir: allow stitching of non-empty block

Just saw your patch. I'll review that one then :-) On Tue, Feb 12, 2019 at 09:38:32AM -0800, Caio Marcelo de Oliveira Filho wrote: > Hi Juan, > > On Tue, Feb 12, 2019 at 04:37:23PM +0100, Juan A. Suarez Romero wrote: > > On Fri, 2019-02-08 at 15:39 -0600, Jason Ekstrand wrote: > > > I had a

[Mesa-dev] [PATCH 2/2] gallium/u_tests: use a compute-only context to test GCN compute ring

From: Marek Olšák --- src/gallium/auxiliary/util/u_tests.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/gallium/auxiliary/util/u_tests.c b/src/gallium/auxiliary/util/u_tests.c index 365d4fa8f17..7b87337bb98 100644 --- a/src/gallium/auxiliary/util/u_tests.c

Re: [Mesa-dev] [PATCH] nir: allow stitching of non-empty block

On Tue, 2019-02-12 at 09:38 -0800, Caio Marcelo de Oliveira Filho wrote: > Hi Juan, > > On Tue, Feb 12, 2019 at 04:37:23PM +0100, Juan A. Suarez Romero wrote: > > On Fri, 2019-02-08 at 15:39 -0600, Jason Ekstrand wrote: > > > I had a chat with Caio about this and I'm skeptical. In general, users

[Mesa-dev] [PATCH 1/2] radeonsi: always use compute rings for clover on CI and newer (v2)

From: Marek Olšák initialize all non-compute context functions to NULL. v2: fix SI --- src/gallium/drivers/radeonsi/si_blit.c| 14 ++- src/gallium/drivers/radeonsi/si_clear.c | 7 +- src/gallium/drivers/radeonsi/si_compute.c | 15 +--

Re: [Mesa-dev] [PATCH] anv/cmd_buffer: check for NULL framebuffer

On Tue, 2019-02-12 at 11:31 -0600, Jason Ekstrand wrote: > On Tue, Feb 12, 2019 at 10:48 AM Juan A. Suarez Romero > wrote: > > This can happen when we record a VkCmdDraw in a secondary buffer that > > > > was created inheriting from the primary buffer, but with the framebuffer > > > > set to

[Mesa-dev] [PATCH v4 34/40] intel/compiler: validate region restrictions for half-float conversions

--- src/intel/compiler/brw_eu_validate.c| 64 - src/intel/compiler/test_eu_validate.cpp | 122 2 files changed, 185 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index

[Mesa-dev] [PATCH] anv/cmd_buffer: check for NULL framebuffer

This can happen when we record a VkCmdDraw in a secondary buffer that was created inheriting from the primary buffer, but with the framebuffer set to NULL in the VkCommandBufferInheritanceInfo. Vulkan 1.1.81 spec says that "the application must ensure (using scissor if neccesary) that all

[Mesa-dev] [PATCH v4 03/40] intel/compiler: split float to 64-bit opcodes from int to 64-bit

Going forward having these split is a bit more convenient since these two groups have different restrictions. v2: - Rebased on top of new regioning lowering pass. Reviewed-by: Topi Pohjolainen (v1) Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_fs_nir.cpp | 7 +++ 1 file changed,

Re: [Mesa-dev] [PATCH v4 5/5] gallium/auxiliary/vl: Add video compositor compute shader render

Thank you for the advice. James From: Marek Olšák Sent: Monday, February 11, 2019 4:56 PM To: Zhu, James Cc: mesa-dev@lists.freedesktop.org; jzh...@gmail.com Subject: Re: [Mesa-dev] [PATCH v4 5/5] gallium/auxiliary/vl: Add video compositor compute shader

[Mesa-dev] [Bug 109535] [Tracker] Mesa 19.0 release tracker

https://bugs.freedesktop.org/show_bug.cgi?id=109535 Bug 109535 depends on bug 109543, which changed state. Bug 109543 Summary: After upgrade mesa to 19.0.0~rc1 all vulkan based application stop working ["vulkan-cube" received SIGSEGV in radv_pipeline_init_blend_state at

[Mesa-dev] [PATCH] mesa: INVALID_VALUE for wrong type or format in Clear*Buffer*Data

Instead of generating a GL_INVALID_ENUM error when the type or format is incorrect while using glClear{Named}Buffer{Sub}Data, generate GL_INVALID_VALUE. From page 72 (page 94 of the PDF) of the OpenGL 4.6 spec: " An INVALID_VALUE error is generated if type is not one of the types in table

[Mesa-dev] [PATCH v4 24/40] intel/compiler: implement isign for int8

Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_fs_nir.cpp | 25 + 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 3a6e4a2eb60..40c0481ac53 100644 ---

[Mesa-dev] [PATCH v4 15/40] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits

We are now using these bits, so don't assert that they are not set. In gen8, if these bits are set compaction is not possible. On gen9 and CHV platforms set_3src_control_index() checks these bits (and others) against a table to validate if the particular bit combination is eligible for compaction

[Mesa-dev] [PATCH v4 17/40] intel/compiler: set correct precision fields for 3-source float instructions

Source0 and Destination extract the floating-point precision automatically from the SrcType and DstType instruction fields respectively when they are set to types :F or :HF. For Source1 and Source2 operands, we use the new 1-bit fields Src1Type and Src2Type, where 0 means normal precision and 1

[Mesa-dev] [PATCH 2/4] radv: use MAX_{VBS, VERTEX_ATTRIBS} when defining max vertex input limits

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 0fef92773e1..9778b13ce86 100644 --- a/src/amd/vulkan/radv_device.c +++

[Mesa-dev] [PATCH] nir: remove jump from two merging jump-ending blocks

In opt_peel_initial_if optimization, when moving the continue list to end of the continue block, before the jump, could happen that the continue list itself also ends with a jump. This would mean that we would have two jump instructions in a row: the first one from the continue list and the

[Mesa-dev] [PATCH] radv: always export gl_SampleMask when the fragment shader uses it

For some reasons, this breaks trees rendering in Project Cars. Fixes: 85010585cde ("radv: only enable gl_SampleMask if MSAA is enabled too") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109401 Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_pipeline.c | 8 1 file

[Mesa-dev] [Bug 109532] ir_variable has maximum access out of bounds -- but it's not out of bounds

https://bugs.freedesktop.org/show_bug.cgi?id=109532 --- Comment #26 from asimiklit --- (In reply to Ian Romanick from comment #17) > (In reply to asimiklit from comment #6) > > Created attachment 143288 [details] > > this simple program helps me to reproduce this issue. > > > > just share my

[Mesa-dev] [Bug 109575] Mesa-19.0.0-rc1 : Computer Crashes trying to run anything Vulkan

https://bugs.freedesktop.org/show_bug.cgi?id=109575 --- Comment #10 from Samuel Pitoiset --- Interesting, thanks for bisecting. I will investigate. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the

[Mesa-dev] [PATCH v4 08/40] intel/compiler: implement 16-bit fsign

v2: - make 16-bit be its own separate case (Jason) v3: - Drop the result_int temporary (Jason) Reviewed-by: Topi Pohjolainen (v1) Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_fs_nir.cpp | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH v4 13/40] intel/compiler: add instruction setters for Src1Type and Src2Type.

The original SrcType is a 3-bit field that takes a subset of the types supported for the hardware for 3-source instructions. Since gen8, when the half-float type was added, 3-source floating point operations can use use mixed precision mode, where not all the operands have the same floating-point

[Mesa-dev] [PATCH v4 01/40] compiler/nir: add an is_conversion field to nir_op_info

This is set to True only for numeric conversion opcodes. --- src/compiler/nir/nir.h| 3 ++ src/compiler/nir/nir_opcodes.py | 73 +-- src/compiler/nir/nir_opcodes_c.py | 1 + 3 files changed, 44 insertions(+), 33 deletions(-) diff --git

[Mesa-dev] [PATCH v4 37/40] intel/compiler: validate region restrictions for mixed float mode

--- src/intel/compiler/brw_eu_validate.c| 256 ++ src/intel/compiler/test_eu_validate.cpp | 618 2 files changed, 874 insertions(+) diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index ed9c8fe59dd..a61d4c46e81 100644

[Mesa-dev] [PATCH 3/3] intel/fs: Drop the fs_surface_builder

All of the actual abstraction (except possibly setting size_written) happens as part of the logical opcodes. The only thing that the surface builder is providing at this point is extra levels of functions to call through. I'm going to be adding bindless image support soon and all the extra

Re: [Mesa-dev] [PATCH 0/4] RadeonSI: Upload constants to VRAM via SDMA

Sorry that I step in so late, but the whole family recover slowly from a bad flu... Tried your 'latest" three series altogether with my Polaris 20 (NIR!). UH and UV hang after some seconds reliable. VM faults. Have to dig deeper in (remote) to get some logs. But my reported Polaris triangle

[Mesa-dev] [PATCH] st/va:Add support for indirect manner by returning VA_STATUS_ERROR_OPERATION_FAILED

Based on VA Spec,DeriveImage() returns VA_STATUS_ERROR_OPERATION_FAILED if driver dont have support for internal surface formats.Currently vaDeriveImage() failed for non-contiguous planes and operation failed error string is required to support indirect manner i.e. vaCreateImage()+vaPutImage()

Re: [Mesa-dev] [PATCH] nir: allow stitching of non-empty block

Hi Juan, On Tue, Feb 12, 2019 at 04:37:23PM +0100, Juan A. Suarez Romero wrote: > On Fri, 2019-02-08 at 15:39 -0600, Jason Ekstrand wrote: > > I had a chat with Caio about this and I'm skeptical. In general, users of > > the CF manipulation code shouldn't be stitching two blocks together where

Re: [Mesa-dev] [PATCH] anv/cmd_buffer: check for NULL framebuffer

On Tue, Feb 12, 2019 at 10:48 AM Juan A. Suarez Romero wrote: > This can happen when we record a VkCmdDraw in a secondary buffer that > was created inheriting from the primary buffer, but with the framebuffer > set to NULL in the VkCommandBufferInheritanceInfo. > > Vulkan 1.1.81 spec says that

Re: [Mesa-dev] [PATCH 00/38] radv, ac: 16-bit and 8-bit arithmetic and 8-bit storage

How about splitting this series in four different parts? One for every extension? Is this doable without too much troubles? On 2/12/19 6:02 PM, Rhys Perry wrote: It currently requires review (and possibly rebasing). Marek Olšák send some feedback for a few of the patches but other than that,

Re: [Mesa-dev] [PATCH 00/38] radv, ac: 16-bit and 8-bit arithmetic and 8-bit storage

It currently requires review (and possibly rebasing). Marek Olšák send some feedback for a few of the patches but other than that, it hasn't gotten much attention. Also patch 35 seems to vectorize 32-bit code which can help or hurt shaders quite a bit and seems to hurt shaders overall. I'm not

[Mesa-dev] [MR] nir: move pixel_center_integer/origin_upper_left to shader_info.fs

https://gitlab.freedesktop.org/mesa/mesa/merge_requests/237 New version of the thread that I sent recently, showing two initial versions to solve the regression I found on MR #144: https://lists.freedesktop.org/archives/mesa-dev/2019-February/214808.html This MR includes a v2 of the second

[Mesa-dev] [Bug 109575] Mesa-19.0.0-rc1 : Computer Crashes trying to run anything Vulkan

https://bugs.freedesktop.org/show_bug.cgi?id=109575 Samuel Pitoiset changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Mesa-dev] [Bug 109107] gallium/st/va: change va max_profiles when using Radeon VCN Hardware

https://bugs.freedesktop.org/show_bug.cgi?id=109107 --- Comment #5 from leoxs...@gmail.com --- The fixe is in Mesa master branch, also includes fix for playing VP9 with Chromium. Please make sure run with "allow_rgb10_configs=false" for now. -- You are receiving this mail because: You are the

[Mesa-dev] [Bug 109575] Mesa-19.0.0-rc1 : Computer Crashes trying to run anything Vulkan

https://bugs.freedesktop.org/show_bug.cgi?id=109575 --- Comment #13 from LunarG --- Yes! this patch worked for me on my Ubuntu 18.04 - AMD R9 380 system! I will check with my other AMD systems today. -- You are receiving this mail because: You are the QA Contact for the bug. You are the

Re: [Mesa-dev] [PATCH 00/38] radv, ac: 16-bit and 8-bit arithmetic and 8-bit storage

What's the status of this? On 12/7/18 6:21 PM, Rhys Perry wrote: This series add support for: - VK_KHR_shader_float16_int8 - VK_AMD_gpu_shader_half_float - VK_AMD_gpu_shader_int16 - VK_KHR_8bit_storage on VI+. Half floats are currently disabled on LLVM 7 because of a bug causing large memory

Re: [Mesa-dev] [PATCH v5 5/5] gallium/auxiliary/vl: Add video compositor compute shader render

On 2/12/19 10:35 AM, Zhu, James wrote: > Add compute shader initilization, assign and cleanup in vl_compositor API. > Set video compositor compute shader render as default when pipe support it. > > Signed-off-by: James Zhu > Reviewed-by: Christian König > --- >

Re: [Mesa-dev] [PATCH] nir: allow stitching of non-empty block

On Fri, 2019-02-08 at 15:39 -0600, Jason Ekstrand wrote: > I had a chat with Caio about this and I'm skeptical. In general, users of > the CF manipulation code shouldn't be stitching two blocks together where the > first contains a jump and the second is non-empty. If the caller knows that >

[Mesa-dev] [PATCH v5 5/5] gallium/auxiliary/vl: Add video compositor compute shader render

Add compute shader initilization, assign and cleanup in vl_compositor API. Set video compositor compute shader render as default when pipe support it. Signed-off-by: James Zhu Reviewed-by: Christian König --- src/gallium/auxiliary/vl/vl_compositor.c | 108 +++

Re: [Mesa-dev] [PATCH v4 39/40] anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+

On February 12, 2019 05:57:09 Iago Toral Quiroga wrote: v2: - Merge Float16 and Int8 capabilities into a single patch (Jason) - Merged patch that enabled SPIR-V front-end checks for these caps (except for Int8, which was already merged) Reviewed-by: Jason Ekstrand (v1) ---

Re: [Mesa-dev] [ANNOUNCE] Mesa 18.3.3 release candidate

On Mon, 11 Feb 2019 11:41:08 -0800 Eric Anholt said: > Carsten Haitzler writes: > > > On Mon, 04 Feb 2019 16:31:57 -0800 Eric Anholt said: > > > >> Carsten Haitzler writes: > >> > >> > On Fri, 1 Feb 2019 11:08:07 + Emil Velikov > >> > said: > >> > > >> >> Hi Carsten, > >> >> > >> >>

[Mesa-dev] [PATCH 4/4] radv: reduce the number of loaded channels for vertex input fetches

It's unnecessary to load more channels than the vertex attribute format. The remaining channels are filled with 0 for y and z, and 1 for w. 29077 shaders in 15096 tests Totals: SGPRS: 1321605 -> 1318869 (-0.21 %) VGPRS: 935236 -> 932252 (-0.32 %) Spilled SGPRs: 24860 -> 24776 (-0.34 %) Code Size:

[Mesa-dev] [PATCH 1/4] ac: make use of ac_build_expand_to_vec4() in visit_image_store()

And make ac_build_expand() a static function. Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_llvm_build.c | 9 + src/amd/common/ac_llvm_build.h | 3 --- src/amd/common/ac_nir_to_llvm.c | 2 +- 3 files changed, 6 insertions(+), 8 deletions(-) diff --git

[Mesa-dev] [PATCH 3/4] radv: store vertex attribute formats as pipeline keys

The formats will be used for reducing the number of loaded channels. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_pipeline.c | 22 +++--- src/amd/vulkan/radv_private.h | 1 + src/amd/vulkan/radv_shader.h | 1 + 3 files changed, 21 insertions(+), 3 deletions(-)

[Mesa-dev] [Bug 109543] After upgrade mesa to 19.0.0~rc1 all vulkan based application stop working ["vulkan-cube" received SIGSEGV in radv_pipeline_init_blend_state at ../src/amd/vulkan/radv_pipeline.

https://bugs.freedesktop.org/show_bug.cgi?id=109543 Samuel Pitoiset changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Mesa-dev] [Bug 109615] 19.0.0_rc2 fails u_format_test on ppc64

https://bugs.freedesktop.org/show_bug.cgi?id=109615 --- Comment #2 from erhar...@mailbox.org --- The "44/47 mesa:gallium / u_format_test" failing here is new in 19.0.0_rc. 18.3.x passes core tests just fine on ppc64 (not so the llvmpipe tests, see bug #106644). -- You are receiving this mail

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