Re: [Mesa-dev] radeonsi: NIR - Polaris triangle sprinkling running UH SOLVED - finally

On 13/2/19 8:28 am, Dieter Nützel wrote: Hello Marek, Timo, Nicolai, Timo SOLVED this long-standing NIR corruption on Polaris with his 'nir: rewrite varying component packing' commit. It was triggered with commit 86b52d42368ac496fe24bc6674e754c323381635 Author: Marek Olšák Date:   Fri

[Mesa-dev] [PATCH v2 31/41] ac/nir: implement 16-bit pack/unpack opcodes

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 24 1 file changed, 24 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index bad1c2a990e..f6ad1aa7e77 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH v2 32/41] ac/nir: add 8-bit types to glsl_base_to_llvm_type

v2: remove 16-bit additions and rebase Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index f6ad1aa7e77..defbfdf4297 100644 ---

[Mesa-dev] [PATCH v2 25/41] nir: make bitfield_reverse and ifind_msb work with all integers

Signed-off-by: Rhys Perry --- src/compiler/nir/nir_opcodes.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index dc4cd9ac63d..0f40bd6c548 100644 --- a/src/compiler/nir/nir_opcodes.py +++

[Mesa-dev] [PATCH v2 33/41] ac/nir, radv: create an array of varying output types

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 68 +++ src/amd/common/ac_shader_abi.h| 1 + src/amd/vulkan/radv_nir_to_llvm.c | 3 ++ 3 files changed, 72 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH] panfrost: Fix clipping region

Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/pan_context.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/panfrost/pan_context.c b/src/gallium/drivers/panfrost/pan_context.c index 97df92258da..a4d0719fdc5 100644 ---

[Mesa-dev] [PATCH v2 35/41] radv: store all fragment shader inputs as f32

v2: rebase Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_nir_to_llvm.c | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 2002a744545..01b8b097ea1 100644 ---

Re: [Mesa-dev] [PATCH v2 37/41] radv, ac: implement 16-bit interpolation

This patch can be ignored. I forgot to delete it and it ended up getting sent. "[PATCH v2 37/41] WIP: radv, ac: implement 16-bit interpolation" is the correct one. On Sat, 16 Feb 2019 at 00:23, Rhys Perry wrote: > > v2: add to patch series > > Signed-off-by: Rhys Perry > --- >

[Mesa-dev] [PATCH v2 34/41] ac/nir: store all outputs as f32

v2: rebase v2: fix 64-bit visit_load_var() Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 14 ++ src/amd/vulkan/radv_nir_to_llvm.c | 22 +- 2 files changed, 19 insertions(+), 17 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH v2 37/41] WIP: radv, ac: implement 16-bit interpolation

v2: add to patch series Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 33 +--- src/amd/common/ac_llvm_build.h | 3 ++- src/amd/common/ac_nir_to_llvm.c | 14 +++--- src/amd/vulkan/radv_nir_to_llvm.c| 27

[Mesa-dev] [PATCH v2 37/41] radv, ac: implement 16-bit interpolation

v2: add to patch series Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 33 +--- src/amd/common/ac_llvm_build.h | 3 ++- src/amd/common/ac_nir_to_llvm.c | 14 +++--- src/amd/vulkan/radv_nir_to_llvm.c| 27

[Mesa-dev] [PATCH v2 38/41] WIP: ac, radv: run LLVM's SLP vectorizer

v2: rebase v2: move LLVMAddSLPVectorizePass to after LLVMAddEarlyCSEMemSSAPass v2: run unconditionally on GFX9 and later v2: mark as WIP because it can make 32-bit code much worse Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_util.c | 8 ++-- 1 file changed, 6 insertions(+), 2

[Mesa-dev] [PATCH v2 39/41] ac/nir: generate better code for nir_op_f2f16_rtz

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 939b8eb13de..8bfc63958ca 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH v2 41/41] radv, docs: expose float16, int16 and int8 features and extensions

v2: rebase v2: mark VK_KHR_8bit_storage as DONE in features.txt Signed-off-by: Rhys Perry --- docs/features.txt | 2 +- src/amd/vulkan/radv_device.c | 17 + src/amd/vulkan/radv_extensions.py | 4 src/amd/vulkan/radv_shader.c | 3 +++ 4 files

[Mesa-dev] [PATCH v2 40/41] ac/nir: have nir_op_f2f16 round to zero

In the hope that one day LLVM will then be able to generate code with vectorized v_cvt_pkrtz_f16_f32 instructions. Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH v2 28/41] ac/nir: implement 8 and 16 bit ac_build_imsb

v2: fix C++ style comment Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 4 1 file changed, 4 insertions(+) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index ec87a7b9343..c986f800fa4 100644 --- a/src/amd/common/ac_llvm_build.c +++

[Mesa-dev] [PATCH v2 10/41] ac/nir: make ac_build_clamp work on all bit sizes

v2: don't use ac_get_zerof() and ac_get_onef() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index b53d9c7ff8c..667f9700764 100644 ---

[Mesa-dev] [PATCH v2 14/41] ac/nir: make ac_build_fdiv support 16-bit floats

v2: don't use ac_get_onef() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 23e454385d7..fb871a47400 100644 --- a/src/amd/common/ac_llvm_build.c

[Mesa-dev] [PATCH v2 21/41] ac/nir: implement 16-bit shifts

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 75bb19031bf..bad1c2a990e 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH v2 11/41] ac/nir: make ac_build_fract work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 13 +++-- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 667f9700764..db937eb66fb 100644 --- a/src/amd/common/ac_llvm_build.c +++

[Mesa-dev] [PATCH v2 16/41] ac/nir: implement half-float nir_op_frsq

v2: don't use ac_get_onef() Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index cba0cec3e8f..8b0e07d2930 100644 ---

[Mesa-dev] [PATCH v2 15/41] ac/nir: implement half-float nir_op_frcp

v2: don't use ac_get_onef() Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 741059b5f1a..cba0cec3e8f 100644 ---

[Mesa-dev] [PATCH v2 18/41] radv: lower 16-bit flrp

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_shader.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 1dcb0606246..adba730ad8b 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -53,6 +53,7 @@

[Mesa-dev] [PATCH v2 17/41] ac/nir: implement half-float nir_op_ldexp

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 8b0e07d2930..0e5946dfdb3 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH v2 26/41] ac/nir: make ac_find_lsb work on all bit sizes

v2: don't use ac_get_zero() and ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 33 ++--- 1 file changed, 6 insertions(+), 27 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index

[Mesa-dev] [PATCH v2 12/41] ac/nir: make ac_build_isign work on all bit sizes

v2: don't use ac_get_zero(), ac_get_one() and ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 27 --- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index

[Mesa-dev] [PATCH v2 19/41] ac/nir: support half floats in emit_b2f

This seems to generate fine code, even though the IR is a bit ugly. Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index

[Mesa-dev] [PATCH v2 27/41] ac/nir: make ac_build_umsb work on all bit sizes

v2: don't use ac_get_zero() and ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 38 +++--- 1 file changed, 7 insertions(+), 31 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index

[Mesa-dev] [PATCH v2 24/41] ac/nir: implement 8 and 16 bit ac_build_readlane

v2: don't use ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 71eaac4b7bd..aa92c55c822 100644 ---

[Mesa-dev] [PATCH v2 30/41] ac/nir: make ac_build_bitfield_reverse work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 46738faea9d..dff369aae7f 100644 --- a/src/amd/common/ac_llvm_build.c

[Mesa-dev] [PATCH v2 23/41] ac/nir: implement 16-bit ac_build_ddxy

v2: rebase Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 20 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index fb871a47400..71eaac4b7bd 100644 ---

[Mesa-dev] [PATCH v2 29/41] ac/nir: make ac_build_bit_count work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 33 +++-- 1 file changed, 7 insertions(+), 26 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index c986f800fa4..46738faea9d 100644 ---

[Mesa-dev] [PATCH v2 36/41] radv: handle all fragment output types

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_nir_to_llvm.c | 55 --- 1 file changed, 35 insertions(+), 20 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 01b8b097ea1..c46eabf3656 100644 ---

[Mesa-dev] [PATCH v2 22/41] compiler/nir: add lowering option for 16-bit ffma

The lowering needs to be disabled for sufficient precision to pass deqp-vk's 16-bit fma test on radv. Signed-off-by: Rhys Perry --- src/broadcom/compiler/nir_to_vir.c| 1 + src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 4 +++-

[Mesa-dev] [PATCH v2 20/41] ac/nir: make emit_b2i work on all bit sizes

v2: don't use ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index e459001c1cf..75bb19031bf 100644 ---

[Mesa-dev] [PATCH v2 05/41] ac/nir: implement 8-bit ssbo stores

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 17d952d1ae8..89a78b43c6f 100644 --- a/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH v2 03/41] ac: add various helpers for float16/int16/int8

v2: remove ac_get_one(), ac_get_zero(), ac_get_onef() and ac_get_zerof() v2: remove ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 55 ++--- src/amd/common/ac_llvm_build.h | 15 +++-- src/amd/common/ac_nir_to_llvm.c | 30

[Mesa-dev] [PATCH v2 09/41] ac/nir: fix 64-bit nir_op_f2f16_rtz

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 691d444db05..741059b5f1a 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH v2 07/41] ac/nir: implement 8-bit nir_load_const_instr

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 4 1 file changed, 4 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index b260142c177..f39232b91a1 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH v2 13/41] ac/nir: make ac_build_fsign work on all bit sizes

v2: don't use ac_get_zerof() and ac_get_onef() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 16 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 3b2257e8bf0..23e454385d7 100644

[Mesa-dev] [PATCH v2 08/41] ac/nir: implement 8-bit conversions

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index f39232b91a1..691d444db05 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH v2 02/41] radv: ensure export arguments are always float

So that the signature is correct and consistent, the inputs to a export intrinsic should always be 32-bit floats. This and the previous commit fixes a large amount crashes from dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_* tests Fixes: b722b29f10d ('radv: add

[Mesa-dev] [PATCH v2 04/41] ac/nir: implement 8-bit push constant, ssbo and ubo loads

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 37 +++-- 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index bed52490bad..17d952d1ae8 100644 ---

[Mesa-dev] [PATCH v2 06/41] ac/nir: fix 16-bit ssbo stores

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 89a78b43c6f..b260142c177 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH 00/38] radv, ac: 16-bit and 8-bit arithmetic and 8-bit storage

This series add support for: - VK_KHR_shader_float16_int8 - VK_AMD_gpu_shader_half_float - VK_AMD_gpu_shader_int16 - VK_KHR_8bit_storage on VI+. Half floats are disabled on LLVM 7 because of a bug causing large memory usage and long (or unbounded) compilation times with some CTS tests. It is

[Mesa-dev] [PATCH v2 01/41] radv: bitcast 16-bit outputs to integers

16-bit outputs are stored as 16-bit floats in the outputs array, so they have to be bitcast. Fixes: b722b29f10d ('radv: add support for 16bit input/output') Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_nir_to_llvm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

Re: [Mesa-dev] [PATCH v5 02/40] intel/compiler: add a NIR pass to lower conversions

On Fri, Feb 15, 2019 at 2:22 AM Iago Toral Quiroga wrote: > Some conversions are not directly supported in hardware and need to be > split in two conversion instructions going through an intermediary type. > Doing this at the NIR level simplifies a bit the complexity in the backend. > > v2: > -

Re: [Mesa-dev] [PATCH v6 2/5] i965: Faking the ETC2 compression on Gen < 8 GPUs using two miptrees.

On Fri, Feb 15, 2019 at 03:29:41PM +0200, Eleni Maria Stea wrote: > GPUs Gen < 8 cannot sample ETC2 formats. So far, they converted the > compressed EAC/ETC2 images to non-compressed RGBA images. When > GetCompressed* functions were called, the pixels were returned in this > RGBA format and not

Re: [Mesa-dev] [PATCH] Revert "glsl: relax input->output validation for SSO programs"

Reviewed-by: Timothy Arceri But I think you should add something like the following to the commit message: "This was fixed properly by commit ..." Once you push "glsl/linker: don't fail non static used inputs without matching outputs" On 9/2/19 4:06 am, Andres Gomez wrote: This reverts

Re: [Mesa-dev] [PATCH v2 4/6] glsl/linker: don't fail non static used inputs without matching outputs

Actually you probably want to add this to the commit message also since it will also be needed if the revert patch gets picked up by stable: Fixes: 1aa5738e666 ("glsl: relax input->output validation for SSO programs") On 7/2/19 2:58 am, Andres Gomez wrote: If there is no Static Use of an

Re: [Mesa-dev] [PATCH v2 4/6] glsl/linker: don't fail non static used inputs without matching outputs

If the updated piglit tests pass on the Nvidia blob as per my reply to those patches and this patch passes on the new and old piglit tests. Then this patch is: Reviewed-by: Timothy Arceri Thanks for fixing this! On 7/2/19 2:58 am, Andres Gomez wrote: If there is no Static Use of an input

[Mesa-dev] [Bug 109107] gallium/st/va: change va max_profiles when using Radeon VCN Hardware

https://bugs.freedesktop.org/show_bug.cgi?id=109107 Michael Eagle changed: What|Removed |Added See Also||https://bugs.freedesktop.or

[Mesa-dev] [PATCH] panfrost: Fix various leaks unmapping resources

v2: Don't check for NULL before free() Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/pan_resource.c | 19 +++ src/gallium/drivers/panfrost/pan_screen.h | 4 +++- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git

Re: [Mesa-dev] [PATCH v6 0/5] improved the support for ETC2 formats on Gen 7

On Fri, Feb 15, 2019 at 03:29:39PM +0200, Eleni Maria Stea wrote: > Intel Gen7 GPUs don't support the ETC2 formats natively and in order to > show the pixels properly we decompress them and create decompressed > miptrees. The problem with that is that the functions that map the > miptrees for

Re: [Mesa-dev] [PATCH 3/3] panfrost: Swap order of tiled texture (de)alloc

> Am I reading this correctly, that now we free a slab [for a tiled > texture] before allocating new one? The commit message seems rather > cryptic. Yeah, it's a super minor fix. Rather than allocating a new slab for the texture and then freeing the old slab, we free then allocate. Practically,

[Mesa-dev] [Bug 109646] New video compositor compute shader render glitches mpv

https://bugs.freedesktop.org/show_bug.cgi?id=109646 --- Comment #4 from bmil...@gmail.com --- Ok, some updates: 1. The stutter/framedrop was related to the codec, not your patches. Switching to dav1d improved it. 2. The last patch you posted fixed the black UI issues. 3. Got a comparison shot of

[Mesa-dev] [Bug 109201] Deep Rock Galactic: GPU Hang (Steam Play) (DXVK)

https://bugs.freedesktop.org/show_bug.cgi?id=109201 Alexander changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Mesa-dev] [Bug 109599] small shadows are not drawn in Heroes of the Storm

https://bugs.freedesktop.org/show_bug.cgi?id=109599 --- Comment #8 from tempel.jul...@gmail.com --- Regarding the "hedges regression": Sorry, false alarm. It looks the same on Windows DX11, the game developer apparently has recently downgraded the game's visuals. -- You are receiving this mail

[Mesa-dev] [Bug 109532] ir_variable has maximum access out of bounds -- but it's not out of bounds

https://bugs.freedesktop.org/show_bug.cgi?id=109532 --- Comment #30 from Mark Janes --- (In reply to Mark Janes from comment #28) > https://android-review.googlesource.com/c/platform/external/deqp/+/901894 Mesa still asserts with this fix. I also tested Andrii's mesa patch with the dEQP fix

Re: [Mesa-dev] [PATCH 1/3] panfrost: Fix various leaks unmapping resources

> Nit: staying consistent with "foo != NULL" vs "foo" checks helps a > lot. Which form is preferred? > free(NULL); is perfectly valid. Huh, TIL, thank you. > The function pointer seems to be NULL. Did you forget to git add the > file which sets it? See my comment in the other mail about the

[Mesa-dev] [Bug 109647] /usr/include/xf86drm.h:40:10: fatal error: drm.h: No such file or directory

https://bugs.freedesktop.org/show_bug.cgi?id=109647 Bug ID: 109647 Summary: /usr/include/xf86drm.h:40:10: fatal error: drm.h: No such file or directory Product: Mesa Version: git Hardware: x86-64 (AMD64)

Re: [Mesa-dev] [PATCH] panfrost: Backport driver to Mali T600/T700

> - about 1/5 of the patch seems to be white space changes ...Oops. Any tips for avoiding this type of diff churn in the future? I suppose it's not inherently harmful, but maybe it could make merging more difficult than strictly necessary. > - doesn't seem like BIFROST is defined anywhere

Re: [Mesa-dev] [PATCH] panfrost: Fix build; depend on libdrm

> Feel free to reuse: > meson: panfrost: add missing libdrm dependency Hmm? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/3] panfrost: Free imported BOs

> Seems like a file is missing - git add pan_screen.c perhaps? Neither > the function pointer nor the imported/imported_size are set anywhere. This is defined in the out-of-tree overlay with working with the vendor kernel. When the DRM driver gains support for these features (Rob and Tomeu are

[Mesa-dev] [PATCH v3] gallium/auxiliary/vl: Fix transparent issue on compute shader with rgba

Fixes: 9364d66cb7f7 (Add video compositor compute shader render) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109646 Problem 1,4: they are caused by imcomplete blend comute shader implementation. So Reverts rgba back to frament shader. Signed-off-by: James Zhu ---

[Mesa-dev] [PATCH v2] gallium/auxiliary/vl: Fix transparent issue on compute shader with rgba

Bugzilla bug 109646 - New video compositor compute shader render glitches mpv https://bugs.freedesktop.org/show_bug.cgi?id=109646 Problem 1,4: they are caused by imcomplete blend comute shader implementation. So Reverts rgba back to frament shader from commit

Re: [Mesa-dev] [PATCH] gallium/auxiliary/vl: Revert rgba back to frament shader

On 2/15/19 3:42 PM, Zhu, James wrote: > Bugzilla Bug 109646 - New video compositor compute shader render glitches mpv > Problem 1,4: they are caused by imcomplete blend compute shader > implementation. So Revert rgba back to frament shader. Please refer to other commit message to put Bugzilla

[Mesa-dev] [Bug 109646] New video compositor compute shader render glitches mpv

https://bugs.freedesktop.org/show_bug.cgi?id=109646 --- Comment #3 from bmil...@gmail.com --- (In reply to jam...@amd.com from comment #2) > bmil...@gmail.com: > Problem 1,4: the blend implementation seems incomplete with compute shader. > Problem 3: could you provide the clip and the screen

[Mesa-dev] [Bug 109532] ir_variable has maximum access out of bounds -- but it's not out of bounds

https://bugs.freedesktop.org/show_bug.cgi?id=109532 --- Comment #31 from andrii simiklit --- (In reply to Mark Janes from comment #30) > (In reply to Mark Janes from comment #28) > > https://android-review.googlesource.com/c/platform/external/deqp/+/901894 > > Mesa still asserts with this

[Mesa-dev] [PATCH] gallium/auxiliary/vl: Revert rgba back to frament shader

Bugzilla Bug 109646 - New video compositor compute shader render glitches mpv Problem 1,4: they are caused by imcomplete blend compute shader implementation. So Revert rgba back to frament shader. Signed-off-by: James Zhu --- src/gallium/auxiliary/vl/vl_compositor.c | 17 +++-- 1

[Mesa-dev] [Bug 109646] New video compositor compute shader render glitches mpv

https://bugs.freedesktop.org/show_bug.cgi?id=109646 --- Comment #2 from jam...@amd.com --- bmil...@gmail.com: Problem 1,4: the blend implementation seems incomplete with compute shader. Problem 3: could you provide the clip and the screen capture? I want to check on my bench. Problem 2: So far

[Mesa-dev] [Bug 109646] New video compositor compute shader render glitches mpv

https://bugs.freedesktop.org/show_bug.cgi?id=109646 --- Comment #1 from leoxs...@gmail.com --- Thanks for the testing. We'll have a look. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___

[Mesa-dev] [Bug 109646] New video compositor compute shader render glitches mpv

https://bugs.freedesktop.org/show_bug.cgi?id=109646 Bug ID: 109646 Summary: New video compositor compute shader render glitches mpv Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All)

Re: [Mesa-dev] [PATCH] panfrost: Fix build; depend on libdrm

On Fri, 15 Feb 2019 at 08:55, Alyssa Rosenzweig wrote: > > Signed-off-by: Alyssa Rosenzweig > --- > src/gallium/drivers/panfrost/meson.build | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/gallium/drivers/panfrost/meson.build > b/src/gallium/drivers/panfrost/meson.build > index

Re: [Mesa-dev] [PATCH 3/3] panfrost: Swap order of tiled texture (de)alloc

On Fri, 15 Feb 2019 at 08:50, Alyssa Rosenzweig wrote: > > Signed-off-by: Alyssa Rosenzweig > --- > src/gallium/drivers/panfrost/pan_resource.c | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/src/gallium/drivers/panfrost/pan_resource.c >

[Mesa-dev] [Bug 109645] build error on arm64: tegra_screen.c:33: /usr/include/xf86drm.h:41:10: fatal error: drm.h: No such file or directory

https://bugs.freedesktop.org/show_bug.cgi?id=109645 Bug ID: 109645 Summary: build error on arm64: tegra_screen.c:33: /usr/include/xf86drm.h:41:10: fatal error: drm.h: No such file or directory Product: Mesa

[Mesa-dev] [Bug 109535] [Tracker] Mesa 19.0 release tracker

https://bugs.freedesktop.org/show_bug.cgi?id=109535 Mark Janes changed: What|Removed |Added Depends on||109594 Referenced Bugs:

Re: [Mesa-dev] [PATCH 2/3] panfrost: Free imported BOs

On Fri, 15 Feb 2019 at 08:50, Alyssa Rosenzweig wrote: > > Signed-off-by: Alyssa Rosenzweig > --- > src/gallium/drivers/panfrost/pan_resource.c | 4 > src/gallium/drivers/panfrost/pan_resource.h | 6 ++ > src/gallium/drivers/panfrost/pan_screen.h | 2 ++ > 3 files changed, 12

Re: [Mesa-dev] [PATCH 1/3] panfrost: Fix various leaks unmapping resources

Hi Alyssa, On Fri, 15 Feb 2019 at 08:50, Alyssa Rosenzweig wrote: > > Signed-off-by: Alyssa Rosenzweig > --- > src/gallium/drivers/panfrost/pan_resource.c | 22 - > src/gallium/drivers/panfrost/pan_screen.h | 4 +++- > 2 files changed, 16 insertions(+), 10 deletions(-) >

Re: [Mesa-dev] [PATCH] panfrost: Backport driver to Mali T600/T700

Hi Alyssa, On Thu, 14 Feb 2019 at 01:58, Alyssa Rosenzweig wrote: > > There are a few differenes between Mali T860 (Panfrost's primary > reference target) and the older Midgard generations (T600/T700): > > - Miscellaneous different magic numbers. It's not clear what these > numbers mean on

Re: [Mesa-dev] [PATCH v2] egl/dri2: try to bind old context if bindContext failed

On Wed, 13 Feb 2019 at 09:32, Luigi Santivetti wrote: > > Hello Emil, > > thanks for your feedback, I agree, dri2_make_current() looks complex. > I'll comment inline. > > Emil Velikov writes: > > > Hi all, > > > > Haven't looked it this has landed or not. > > > > On Tue, 5 Feb 2019 at 16:41,

[Mesa-dev] [Bug 109532] ir_variable has maximum access out of bounds -- but it's not out of bounds

https://bugs.freedesktop.org/show_bug.cgi?id=109532 --- Comment #29 from Mark Janes --- *** Bug 109260 has been marked as a duplicate of this bug. *** -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list

[Mesa-dev] [Bug 109532] ir_variable has maximum access out of bounds -- but it's not out of bounds

https://bugs.freedesktop.org/show_bug.cgi?id=109532 --- Comment #28 from Mark Janes --- Chris Forbes at google found a patch that explains at least some of the reason for this test regression: https://android-review.googlesource.com/c/platform/external/deqp/+/901894 I just realized that this

Re: [Mesa-dev] [PATCH 3/3] egl/sl: use kms_swrast with vgem instead of a random GPU

On Tue, 5 Feb 2019 at 15:35, Emil Velikov wrote: > > From: Emil Velikov > > VGEM and kms_swrast were introduced to work with one another. > > All we do is CPU rendering to dumb buffers. There is no reason to carve > out GPU memory, increasing the memory pressure on a device that could > make a

[Mesa-dev] [ANNOUNCE] Mesa 18.3.4 release candidate

Hello list, The candidate for the Mesa 18.3.4 is now available. Currently we have: - 34 queued - 1 nominated (outstanding) - and 16 rejected patches The current queue consists of: A fix in the XvMC state-tracker, which was causing some video attributes to not take affect. On the video front

Re: [Mesa-dev] [PATCH] radv: fix invalid element type when filling vertex input default values

Reviewed-by: Bas Nieuwenhuizen On Fri, Feb 15, 2019 at 3:57 PM Samuel Pitoiset wrote: > > The elements added into a vector should have the same type as the > first one, otherwise this hits an assertion in LLVM. > > Fixes: 4b3549c0846 ("radv: reduce the number of loaded channels for vertex >

[Mesa-dev] [Bug 109333] mesa, meson: Need ability to remember PKG_CONFIG_PATH

https://bugs.freedesktop.org/show_bug.cgi?id=109333 --- Comment #5 from Emil Velikov --- Food for though: AFAICT the concept of reproducible builds relies heavily of having consistent environment. It even suggests to explicitly set SOURCE_DATE_EPOCH although there could be others. Be that

[Mesa-dev] [Bug 109064] temp_comp_access::get_required_live_range: enclosing_scope_first_write is NULL

https://bugs.freedesktop.org/show_bug.cgi?id=109064 --- Comment #1 from Alex Xu (Hello71) --- Still broken in 19.0.0_rc4. #0 0x7f0322468821 in get_temp_registers_required_live_ranges(void*, exec_list*, int, register_live_range*, int, array_live_range*) () from

[Mesa-dev] [PATCH] radv: write the alpha channel of MRT0 when alpha coverage is enabled

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109597 Cc: 18.3 19.0 Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_pipeline.c | 8 1 file changed, 8 insertions(+) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index

[Mesa-dev] [Bug 109333] mesa, meson: Need ability to remember PKG_CONFIG_PATH

https://bugs.freedesktop.org/show_bug.cgi?id=109333 --- Comment #4 from Jan Vesely --- (In reply to Dylan Baker from comment #3) > What exactly are you wanting? We (meson) have been trying not to use > environment variables when possible because they are so awful to use on > Windows. Our goal

Re: [Mesa-dev] [PATCH] nir: remove simple dead if detection from nir_opt_dead_cf()

Reviewed-by: Connor Abbott I agree that if we ever need to bring this back, we should just check for both branches empty and no phis afterwards. On Thu, Feb 14, 2019 at 2:38 AM Timothy Arceri wrote: > This was probably useful when it was first written, however it > looks to be no longer

[Mesa-dev] [Bug 109641] GLX swrast driver leaks shared memory segments

https://bugs.freedesktop.org/show_bug.cgi?id=109641 Bug ID: 109641 Summary: GLX swrast driver leaks shared memory segments Product: Mesa Version: 18.0 Hardware: All OS: Linux (All) Status: NEW Severity:

[Mesa-dev] [PATCH v6 2/5] i965: Faking the ETC2 compression on Gen < 8 GPUs using two miptrees.

GPUs Gen < 8 cannot sample ETC2 formats. So far, they converted the compressed EAC/ETC2 images to non-compressed RGBA images. When GetCompressed* functions were called, the pixels were returned in this RGBA format and not the compressed format that was expected. Trying to fix this problem, we use

[Mesa-dev] [PATCH 2/2] anv/image: fix offset's alignment to the surface alignment

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_image.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index 3999c7399d0..f4a65044a3b 100644 --- a/src/intel/vulkan/anv_image.c +++

[Mesa-dev] [PATCH v6 1/5] i965: Rename intel_mipmap_tree::r8stencil_* -> ::shadow_*

From: Nanley Chery Use more generic field names. We'll reuse these fields for a workaround with ASTC miptrees. Reviewed-by: Eleni Maria Stea --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 8 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 16

[Mesa-dev] [PATCH 1/2] isl: remove the cache line size alignment requirement

There are formats which bpp are not aligned to a power-of-two and that can cause problems in the checks we do. The cacheline size was a requirement for using the BLT engine, which we don't use anymore except for a few things on old HW, so we drop it. Fixes CTS's CL#3500 test:

[Mesa-dev] [Bug 109532] ir_variable has maximum access out of bounds -- but it's not out of bounds

https://bugs.freedesktop.org/show_bug.cgi?id=109532 --- Comment #27 from asimiklit --- (In reply to Ilia Mirkin from comment #24) > """ > But according to next comment it should be 0 because of the BlockB[0] was > optimized > and there is the BlockB[1] only: > >/* The

Re: [Mesa-dev] [PATCH 2/2] i965: Be resilient in the face of GPU hangs

Quoting Chris Wilson (2019-02-14 12:05:00) > If we hang the GPU and end up banning our context, we will no longer be > able to submit and abort with an error (exit(1) no less). As we submit > minimal incremental batches that rely on the logical context state of > previous batches, we can not rely

Re: [Mesa-dev] [RFC] gpu/docs: Clarify what userspace means for gl

On Thu, Feb 14, 2019 at 05:47:06PM -0500, Rob Clark wrote: > On Thu, Feb 14, 2019 at 4:00 AM Daniel Vetter wrote: > > > > Clear rules avoid arguing. > > > > I think it'd be good to have an equally solid list on the kms side. > > But kms is much more meant to be a standard, and the list of

[Mesa-dev] [PATCH v6 5/5] i965: Removed the field etc_format from the struct intel_mipmap_tree

After the previous changes to emulate the ETC/EAC formats using the secondary shadow miptree, the etc_format field of the intel_mipmap_tree struct became redundant and the remaining check that used it has been replaced. (Nanley Chery) --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +-

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