[Mesa-dev] [Bug 110847] occlusion-query.c:190:45: error: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Werror, -Wformat]
https://bugs.freedesktop.org/show_bug.cgi?id=110847 Mark Janes changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|mesa-dev@lists.freedesktop. |mark.a.ja...@intel.com |org | --- Comment #1 from Mark Janes --- Vinson: I don't know how to reproduce this build error, but I think this patch should fix it: https://gitlab.freedesktop.org/majanes/mesa/commit/c421d1533f86c5bcd18974164c4e8bf2457e7b96 Can you test the patch and let me know if there are any other printf security issues in your build configuration? -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110847] occlusion-query.c:190:45: error: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Werror, -Wformat]
https://bugs.freedesktop.org/show_bug.cgi?id=110847
Bug ID: 110847
Summary: occlusion-query.c:190:45: error: format specifies type
'unsigned long' but the argument has type 'uint64_t'
(aka 'unsigned long long') [-Werror,-Wformat]
Product: Mesa
Version: unspecified
Hardware: x86-64 (AMD64)
OS: All
Status: NEW
Keywords: bisected, regression
Severity: normal
Priority: medium
Component: Other
Assignee: mesa-dev@lists.freedesktop.org
Reporter: v...@freedesktop.org
QA Contact: mesa-dev@lists.freedesktop.org
CC: mark.a.ja...@intel.com
../src/gallium/tests/graw/occlusion-query.c:190:45: error: format specifies
type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long
long') [-Werror,-Wformat]
printf("result1 = %lu result2 = %lu\n", res1.u64, res2.u64);
~~~^~~~
%llu
commit c9c1e26106478258d8a91fe8fc5c69d8c3fa5206
Author: Mark Janes
Date: Mon Jun 3 16:59:45 2019 -0700
mesa: prevent common string formatting security issues
Adds a compile-time error for obvious security issues like:
printf(string_var);
The proposed flag is more tolerant than -Wformat-nonliteral.
Specifically, it tolerates common mesa formatting like:
static const char *shader_template = "really long string %d";
printf(shader_template, uniform_number);
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110833
Reviewed-by: Eric Anholt
Reviewed-by: Eric Engestrom
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Re: [Mesa-dev] [PATCH 6/8] radv: handle sample locations during automatic layout transitions
On Wed, Jun 5, 2019 at 12:04 PM Samuel Pitoiset
wrote:
>
>
> On 6/5/19 2:51 AM, Bas Nieuwenhuizen wrote:
> > On Thu, May 30, 2019 at 4:02 PM Samuel Pitoiset
> > wrote:
> >> From the Vulkan spec 1.1.109:
> >>
> >> "Some implementations may need to evaluate depth image values
> >> while performing image layout transitions. To accommodate this,
> >> instances of the VkSampleLocationsInfoEXT structure can be
> >> specified for each situation where an explicit or automatic
> >> layout transition has to take place. [...] and
> >> VkRenderPassSampleLocationsBeginInfoEXT can be chained from
> >> VkRenderPassBeginInfo to provide sample locations for layout
> >> transitions performed implicitly by a render pass instance."
> >>
> >> Signed-off-by: Samuel Pitoiset
> >> ---
> >> src/amd/vulkan/radv_cmd_buffer.c | 155 ---
> >> src/amd/vulkan/radv_private.h| 9 ++
> >> 2 files changed, 150 insertions(+), 14 deletions(-)
> >>
> >> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> >> b/src/amd/vulkan/radv_cmd_buffer.c
> >> index 570acaa0905..81b3f5f9886 100644
> >> --- a/src/amd/vulkan/radv_cmd_buffer.c
> >> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> >> @@ -2645,11 +2645,55 @@ void radv_subpass_barrier(struct radv_cmd_buffer
> >> *cmd_buffer,
> >>NULL);
> >> }
> >>
> >> +static uint32_t
> >> +radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
> >> +{
> >> + struct radv_cmd_state *state = _buffer->state;
> >> + uint32_t subpass_id = state->subpass - state->pass->subpasses;
> >> +
> >> + /* The id of this subpass shouldn't exceed the number of subpasses
> >> in
> >> +* this render pass minus 1.
> >> +*/
> >> + assert(subpass_id < state->pass->subpass_count);
> >> + return subpass_id;
> >> +}
> >> +
> >> +static struct radv_sample_locations_state *
> >> +radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
> >> +uint32_t att_idx)
> >> +{
> >> + struct radv_cmd_state *state = _buffer->state;
> >> + uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
> > On the start of the first subpass this may not work as the subpass is
> > not set yet?
> Yes, this patch needs https://patchwork.freedesktop.org/series/61387/
> >
> >> + struct radv_image_view *view =
> >> state->framebuffer->attachments[att_idx].attachment;
> >> +
> >> + if (view->image->info.samples == 1)
> >> + return NULL;
> >> +
> >> + if (state->pass->attachments[att_idx].first_subpass_idx ==
> >> subpass_id) {
> >> + /* Return the initial sample locations if this is the
> >> initial
> >> +* layout transition of the given subpass attachemnt.
> >> +*/
> >> + if (state->attachments[att_idx].sample_location.count > 0)
> >> + return
> >> >attachments[att_idx].sample_location;
> >> + } else {
> >> + /* Otherwise return the subpass sample locations if
> >> defined. */
> >> + if (state->subpass_sample_locs) {
> >> + for (uint32_t i = 0; i <
> >> state->num_subpass_sample_locs; i++) {
> >> + if
> >> (state->subpass_sample_locs[i].subpass_idx == subpass_id)
> >> + return
> >> >subpass_sample_locs[i].sample_location;
I think there is an off-by-1 here with the subpass patch applied.
For the transition from subpass 0 to subpass 1, we should be using the
locations from subpass 0, but by setting the subpass before the
transitions, the subpass_id is 1.
> >> + }
> >> + }
> >> + }
> >> +
> >> + return NULL;
> >> +}
> >> +
> >> static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
> >> *cmd_buffer,
> >> struct
> >> radv_subpass_attachment att)
> >> {
> >> unsigned idx = att.attachment;
> >> struct radv_image_view *view =
> >> cmd_buffer->state.framebuffer->attachments[idx].attachment;
> >> + struct radv_sample_locations_state *sample_locs;
> >> VkImageSubresourceRange range;
> >> range.aspectMask = 0;
> >> range.baseMipLevel = view->base_mip;
> >> @@ -2668,10 +2712,15 @@ static void
> >> radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buf
> >> range.layerCount =
> >> util_last_bit(cmd_buffer->state.subpass->view_mask);
> >> }
> >>
> >> + /* Get the subpass sample locations for the given attachment, if
> >> NULL
> >> +* is returned the driver will use the default HW locations.
> >> +*/
> >> + sample_locs = radv_get_attachment_sample_locations(cmd_buffer,
> >> idx);
> >> +
> >> radv_handle_image_transition(cmd_buffer,
> >>
Re: [Mesa-dev] [PATCH] radv: set the subpass before any initial subpass transitions
r-b
On Mon, Jun 3, 2019 at 3:45 PM Bas Nieuwenhuizen
wrote:
>
> While it is not wrong, I don't think this is the right fix, as the
> current_layout is not necessarily accurate.
>
> Will try to get something better.
>
> On Thu, May 30, 2019 at 3:10 PM Samuel Pitoiset
> wrote:
> >
> > This might fix initial subpass transitions when multiview is used.
> > Noticed while implementing sample locations during layout transitions.
> >
> > Signed-off-by: Samuel Pitoiset
> > ---
> > src/amd/vulkan/radv_cmd_buffer.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> > b/src/amd/vulkan/radv_cmd_buffer.c
> > index 7744ef48d06..abf454595f5 100644
> > --- a/src/amd/vulkan/radv_cmd_buffer.c
> > +++ b/src/amd/vulkan/radv_cmd_buffer.c
> > @@ -2658,7 +2658,7 @@ static void
> > radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buf
> > range.baseArrayLayer = view->base_layer;
> > range.layerCount = cmd_buffer->state.framebuffer->layers;
> >
> > - if (cmd_buffer->state.subpass &&
> > cmd_buffer->state.subpass->view_mask) {
> > + if (cmd_buffer->state.subpass->view_mask) {
> > /* If the current subpass uses multiview, the driver might
> > have
> > * performed a fast color/depth clear to the whole image
> > * (including all layers). To make sure the driver will
> > @@ -3761,6 +3761,8 @@ radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer
> > *cmd_buffer,
> >
> > radv_subpass_barrier(cmd_buffer, >start_barrier);
> >
> > + radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
> > +
> > for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
> > const uint32_t a = subpass->attachments[i].attachment;
> > if (a == VK_ATTACHMENT_UNUSED)
> > @@ -3770,7 +3772,6 @@ radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer
> > *cmd_buffer,
> >
> > subpass->attachments[i]);
> > }
> >
> > - radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
> > radv_cmd_buffer_clear_subpass(cmd_buffer);
> >
> > assert(cmd_buffer->cs->cdw <= cdw_max);
> > --
> > 2.21.0
> >
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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[Mesa-dev] [Bug 110811] radv: Assassin's Creed Unity glitches when compiled with recent LLVM 9 (DXVK)
https://bugs.freedesktop.org/show_bug.cgi?id=110811 --- Comment #7 from Yury Zhuravlev --- I have the same issue. Also, before was GPU just hung, now it's working stable but with artifacts. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [ANNOUNCE] mesa 19.0.6
Hi list, Sorry for the brief message, but I'm on a time crunch. Things are chugging along with the 19.0.6 release. This was planned to be the last release of the 19.0 series, but I'm planning to have another one in two weeks due to a longer RC cycle for 19.1. Dylan Shortlog Alok Hota (2): gallium/swr: Param defaults for unhandled PIPE_CAPs gallium/aux: add PIPE_CAP_MAX_VARYINGS to u_screen Bas Nieuwenhuizen (1): nir: Actually propagate progress in nir_opt_move_load_ubo. Chenglei Ren (1): anv/android: fix missing dependencies issue during parallel build Christian Gmeiner (1): etnaviv: use the correct uniform dirty bits Dave Airlie (1): Revert "mesa: unreference current winsys buffers when unbinding winsys buffers" Deepak Rawat (1): winsys/drm: Fix out of scope variable usage Dylan Baker (7): docs: Add Sha256 sums for 19.0.5 cherry-ignore: Add a commit that was manually backported cherry-ignore: add another 19.1 only patch cherry-ignore: add another 19.1 only patch gallium: wrap u_screen in extern "C" for c++ VERSION: bump to 19.0.6 docs: Add relnotes for 19.0.6 Emil Velikov (1): egl/dri: flesh out and use dri2_create_drawable() Jan Zielinski (1): swr/rast: fix 32-bit compilation on Linux Lionel Landwerlin (1): vulkan: fix build dependency issue with generated files Marek Olšák (2): u_blitter: don't fail mipmap generation for depth formats containing stencil ac: fix a typo in ac_build_wg_scan_bottom Philipp Zabel (1): etnaviv: fill missing offset in etna_resource_get_handle Rob Clark (3): freedreno/ir3: dynamic UBO indexing vs 64b pointers freedreno/ir3: set more barrier bits freedreno/a6xx: fix GPU crash on small render targets Sagar Ghuge (1): intel/compiler: Fix assertions in brw_alu3 Samuel Pitoiset (2): radv: allocate more space in the CS when emitting events radv: do not use gfx fast depth clears for layered depth/stencil images Timothy Arceri (2): Revert "st/mesa: expose 0 shader binary formats for compat profiles for Qt" st/glsl: make sure to propagate initialisers to driver storage git tag: mesa-19.0.6 https://mesa.freedesktop.org/archive/mesa-19.0.6.tar.gz MD5: 62c1afa7abcfb7e60640f48feecc5396 mesa-19.0.6.tar.gz SHA1: a5d0e6a0a118bb95f85535baa23aed618f2bea04 mesa-19.0.6.tar.gz SHA256: ac8e9ea388ec5c69f5a690190edf8ede602afdbaeea62d49e108057737430ac7 mesa-19.0.6.tar.gz SHA512: 8f3077384ca504d1375fad8bead103fcb1e71c203c4b15d051ba0205bede58ad34d6f60726c1d571e9fbf80a9f06d8191080e36f59436f7604b94798d6030eae mesa-19.0.6.tar.gz PGP: https://mesa.freedesktop.org/archive/mesa-19.0.6.tar.gz.sig https://mesa.freedesktop.org/archive/mesa-19.0.6.tar.xz MD5: b97159690eba564311d88a818bdbd64d mesa-19.0.6.tar.xz SHA1: d57360ade1b7a5406de2f560829d6ec7783217b1 mesa-19.0.6.tar.xz SHA256: 2db2f2fcaa4048b16e066fad76b8a93944f7d06d329972b0f5fd5ce692ce3d24 mesa-19.0.6.tar.xz SHA512: 320fd6b12ccd5e4a40dfc93546354848a38da09d90e4d5a1dae5d100b8106942acfc25ac3f705a2d3ab3b355162c74c7dfadbdb99a46cf2e5e0761f8542bfeb1 mesa-19.0.6.tar.xz PGP: https://mesa.freedesktop.org/archive/mesa-19.0.6.tar.xz.sig signature.asc Description: signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 6/6] panfrost/midgard: Disambiguate register mode
We postfix instructions by their size if a destination override is in
place (a la AT assembly), disambiguating instruction sizes.
Previously, "16-bit instruction, 16-bit dest, 16-bit sources"
disassembled identically to "32-bit instruction, 16-bit dest, 16-bit
sources", which is semantically distinct due to the lessened opportunity
for parallelism but (potentially) greater precision. Adding a postfix
removes the ambiguity and relieves mental gymnastics reading weird
disassemblies even in some cases that are not ambiguous.
Signed-off-by: Alyssa Rosenzweig
---
src/gallium/drivers/panfrost/midgard/disassemble.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/panfrost/midgard/disassemble.c
b/src/gallium/drivers/panfrost/midgard/disassemble.c
index 565ec4276cb..70ca5a35dfc 100644
--- a/src/gallium/drivers/panfrost/midgard/disassemble.c
+++ b/src/gallium/drivers/panfrost/midgard/disassemble.c
@@ -445,14 +445,25 @@ print_vector_field(const char *name, uint16_t *words,
uint16_t reg_word,
midgard_reg_info *reg_info = (midgard_reg_info *)_word;
midgard_vector_alu *alu_field = (midgard_vector_alu *) words;
midgard_reg_mode mode = alu_field->reg_mode;
+unsigned override = alu_field->dest_override;
/* For now, prefix instruction names with their unit, until we
* understand how this works on a deeper level */
printf("%s.", name);
print_alu_opcode(alu_field->op);
+
+/* Postfix with the size to disambiguate if necessary */
+char postfix = prefix_for_bits(bits_for_mode(mode));
+bool size_ambiguous = override != midgard_dest_override_none;
+
+if (size_ambiguous)
+printf("%c", postfix ? postfix : 'r');
+
+/* Print the outmod, if there is one */
print_outmod(alu_field->outmod,
midgard_is_integer_out_op(alu_field->op));
+
printf(" ");
/* Mask denoting status of 8-lanes */
@@ -463,7 +474,6 @@ print_vector_field(const char *name, uint16_t *words,
uint16_t reg_word,
print_dest(reg_info->out_reg, mode, alu_field->dest_override);
/* Apply the destination override to the mask */
-unsigned override = alu_field->dest_override;
if (mode == midgard_reg_mode_32 || mode == midgard_reg_mode_64) {
if (override == midgard_dest_override_lower)
--
2.20.1
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[Mesa-dev] [PATCH 5/6] panfrost/midgard: Expose vec8/vec16 modes
Midgard ALUs can operate in one of four modes: vec2 64-bit, vec4 32-bit,
vec8 16-bit, or vec16 8-bit. Our compiler (and indeed, any OpenGL ES
shader) only uses 32-bit (and eventually vec4 16-bit) modes in normal
circumstances. Nevertheless, the other modes do exist and are easily
accessible through OpenCL; they also come up in cases like blend
shaders.
While we have had minimal support for decoding 8-bit/64-bit modes, we
did so pretending they were vec4 in each case; 16-bit registers had a
synthetically duplicated register file to separate lo/hi halves, etc.
This works for GL, but it doesn't map to what the hardware is -actually-
doing, which can cause some headscratchingly bizarre disassemblies from
OpenCL. So, we dive in the deep end and support these other modes
natively in the disassembler, using absurdly long masks/swizzles, since
the hardware is considerably more flexible than what was exposed before.
Outside of some fixed routines for blending, none of the above is
supported in the compiler yet. But it's better to have it in the ISA
definitions and disassembler than not, for future use if nothing else.
Signed-off-by: Alyssa Rosenzweig
---
.../drivers/panfrost/midgard/disassemble.c| 509 ++
1 file changed, 273 insertions(+), 236 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/disassemble.c
b/src/gallium/drivers/panfrost/midgard/disassemble.c
index a92fbf174cc..565ec4276cb 100644
--- a/src/gallium/drivers/panfrost/midgard/disassemble.c
+++ b/src/gallium/drivers/panfrost/midgard/disassemble.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include
#include "midgard.h"
#include "midgard-parse.h"
@@ -88,15 +89,9 @@ print_reg(unsigned reg, unsigned bits)
{
/* Perform basic static analysis for expanding constants correctly */
-if ((bits == 16) && (reg >> 1) == 26) {
-is_embedded_constant_half = true;
+if (reg == 26) {
is_embedded_constant_int = is_instruction_int;
-} else if ((bits == 32) && reg == 26) {
-is_embedded_constant_int = is_instruction_int;
-} else if (bits == 8) {
-/* TODO */
-} else if (bits == 64) {
-/* TODO */
+is_embedded_constant_half = (bits < 32);
}
char prefix = prefix_for_bits(bits);
@@ -146,110 +141,167 @@ print_quad_word(uint32_t *words, unsigned tabs)
printf("\n");
}
+static const char components[16] = "xyzwefghijklmnop";
+
+/* Helper to print 4 chars of a swizzle */
static void
-print_vector_src(unsigned src_binary, bool out_high,
- midgard_reg_mode mode, unsigned reg,
- bool is_int)
+print_swizzle_helper(unsigned swizzle, bool upper)
{
-midgard_vector_alu_src *src = (midgard_vector_alu_src *)_binary;
+for (unsigned i = 0; i < 4; ++i) {
+unsigned c = (swizzle >> (i * 2)) & 3;
+c += upper*4;
+printf("%c", components[c]);
+}
+}
-/* Modifiers change meaning depending on the op's context */
+/* Helper to print 8 chars of a swizzle, duplicating over */
+static void
+print_swizzle_helper_8(unsigned swizzle, bool upper)
+{
+for (unsigned i = 0; i < 4; ++i) {
+unsigned c = (swizzle >> (i * 2)) & 3;
+c *= 2;
+c += upper*8;
+printf("%c%c", components[c], components[c+1]);
+}
+}
-midgard_int_mod int_mod = src->mod;
+static void
+print_swizzle_vec16(unsigned swizzle, bool rep_high, bool rep_low,
+midgard_dest_override override)
+{
+printf(".");
-if (is_int) {
-printf("%s", srcmod_names_int[int_mod]);
-} else {
-if (src->mod & MIDGARD_FLOAT_MOD_NEG)
-printf("-");
+if (override == midgard_dest_override_upper) {
+if (rep_high)
+printf(" /* rep_high */ ");
+if (rep_low)
+printf(" /* rep_low */ ");
-if (src->mod & MIDGARD_FLOAT_MOD_ABS)
-printf("abs(");
+if (!rep_high && rep_low)
+print_swizzle_helper_8(swizzle, true);
+else
+print_swizzle_helper_8(swizzle, false);
+} else {
+print_swizzle_helper_8(swizzle, rep_high & 1);
+print_swizzle_helper_8(swizzle, !rep_low & 1);
}
+}
-//register
-
-if (mode == midgard_reg_mode_8) {
-if (src->half)
-printf(" /* half */ ");
+static void
+print_swizzle_vec8(unsigned swizzle, bool rep_high, bool rep_low)
+{
+printf(".");
-unsigned quarter_reg = reg * 2;
+print_swizzle_helper(swizzle, rep_high & 1);
+print_swizzle_helper(swizzle, !rep_low & 1);
+}
-if
[Mesa-dev] [PATCH 1/6] panfrost/midgard: Add rounding mode specific opcodes
This adds a set of opcodes for performing moves and type conversions
with respect to particular rounding modes, required for OpenCL.
Signed-off-by: Alyssa Rosenzweig
---
.../drivers/panfrost/midgard/midgard.h| 27 ++-
.../panfrost/midgard/midgard_compile.c| 18 ++---
.../drivers/panfrost/midgard/midgard_ops.c| 24 +
3 files changed, 49 insertions(+), 20 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/midgard.h
b/src/gallium/drivers/panfrost/midgard/midgard.h
index 7bf17321ccb..c25f10c4028 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard.h
+++ b/src/gallium/drivers/panfrost/midgard/midgard.h
@@ -61,7 +61,10 @@ typedef enum {
midgard_alu_op_fmin = 0x28,
midgard_alu_op_fmax = 0x2C,
-midgard_alu_op_fmov = 0x30,
+midgard_alu_op_fmov = 0x30, /* fmov_rte */
+midgard_alu_op_fmov_rtz = 0x31,
+midgard_alu_op_fmov_rtn = 0x32,
+midgard_alu_op_fmov_rtp = 0x33,
midgard_alu_op_froundeven = 0x34,
midgard_alu_op_ftrunc = 0x35,
midgard_alu_op_ffloor = 0x36,
@@ -122,9 +125,15 @@ typedef enum {
midgard_alu_op_fbany_neq = 0x91, /* bvec4(0) also */
midgard_alu_op_fbany_lt = 0x92, /* any(lessThan(.., ..)) */
midgard_alu_op_fbany_lte = 0x93, /* any(lessThanEqual(.., ..)) */
-midgard_alu_op_f2i= 0x99,
-midgard_alu_op_f2u8 = 0x9C,
-midgard_alu_op_f2u= 0x9D,
+
+midgard_alu_op_f2i_rte= 0x98,
+midgard_alu_op_f2i_rtz= 0x99,
+midgard_alu_op_f2i_rtn= 0x9A,
+midgard_alu_op_f2i_rtp= 0x9B,
+midgard_alu_op_f2u_rte= 0x9C,
+midgard_alu_op_f2u_rtz= 0x9D,
+midgard_alu_op_f2u_rtn= 0x9E,
+midgard_alu_op_f2u_rtp= 0x9F,
midgard_alu_op_ieq= 0xA0,
midgard_alu_op_ine= 0xA1,
@@ -145,8 +154,14 @@ typedef enum {
midgard_alu_op_ubany_lte = 0xB3,
midgard_alu_op_ibany_lt = 0xB4, /* any(lessThan(.., ..)) */
midgard_alu_op_ibany_lte = 0xB5, /* any(lessThanEqual(.., ..)) */
-midgard_alu_op_i2f= 0xB8,
-midgard_alu_op_u2f= 0xBC,
+midgard_alu_op_i2f_rte= 0xB8,
+midgard_alu_op_i2f_rtz= 0xB9,
+midgard_alu_op_i2f_rtn= 0xBA,
+midgard_alu_op_i2f_rtp= 0xBB,
+midgard_alu_op_u2f_rte= 0xBC,
+midgard_alu_op_u2f_rtz= 0xBD,
+midgard_alu_op_u2f_rtn= 0xBE,
+midgard_alu_op_u2f_rtp= 0xBF,
midgard_alu_op_icsel_v= 0xC0, /* condition code r31 */
midgard_alu_op_icsel = 0xC1, /* condition code r31.w */
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index dd86e8bceee..a0e4d05fd05 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -723,10 +723,10 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
ALU_CASE(fexp2, fexp2);
ALU_CASE(flog2, flog2);
-ALU_CASE(f2i32, f2i);
-ALU_CASE(f2u32, f2u);
-ALU_CASE(i2f32, i2f);
-ALU_CASE(u2f32, u2f);
+ALU_CASE(f2i32, f2i_rtz);
+ALU_CASE(f2u32, f2u_rtz);
+ALU_CASE(i2f32, i2f_rtz);
+ALU_CASE(u2f32, u2f_rtz);
ALU_CASE(fsin, fsin);
ALU_CASE(fcos, fcos);
@@ -1055,7 +1055,7 @@ emit_fb_read_blend_scalar(compiler_context *ctx, unsigned
reg)
.inline_constant = true
},
.alu = {
-.op = midgard_alu_op_u2f,
+.op = midgard_alu_op_u2f_rtz,
.reg_mode = midgard_reg_mode_16,
.dest_override = midgard_dest_override_none,
.mask = 0xF,
@@ -2059,12 +2059,12 @@ emit_blend_epilogue(compiler_context *ctx)
emit_mir_instruction(ctx, scale);
-/* vadd.f2u8.pos.low hr0, hr48, #0 */
+/* vadd.f2u_rte.pos.low hr0, hr48, #0 */
midgard_vector_alu_src alu_src = blank_alu_src;
alu_src.half = true;
-midgard_instruction f2u8 = {
+midgard_instruction f2u_rte = {
.type = TAG_ALU_4,
.ssa_args = {
.src0 = SSA_FIXED_REGISTER(24),
@@ -2073,7 +2073,7 @@ emit_blend_epilogue(compiler_context *ctx)
.inline_constant = true
},
.alu = {
-.op = midgard_alu_op_f2u8,
+.op = midgard_alu_op_f2u_rte,
.reg_mode = midgard_reg_mode_16,
.dest_override = midgard_dest_override_lower,
[Mesa-dev] [PATCH 4/6] panfrost/midgard: Add shifting int modifiers
As a source modifier, shift allows shifting a value left by the bit
size, useful in conjunction with a greater register mode, for instance
to implement `upsample`. As a concrete example, the following OpenCL:
ushort hr0 = /* ... */, uint r1 = /* ... */;
uint r2 = (convert_uint(hr0) << 16) ^ b;
compiles to the following Midgard assembly:
ixor r, (hr0) << 16, b
In reverse, the ".hi" output modifier shifts the value right by the bit
size, leaving just the carry/overflow at the bottom. To implement *_hi
functions in OpenCL (for <64-bit), we do arithmetic in the 2x higher
mode with the .hi modifier. (For 64-bit, things are hairier, since there
is not an 128-bit int mode).
Signed-off-by: Alyssa Rosenzweig
---
.../drivers/panfrost/midgard/disassemble.c| 28 ---
.../drivers/panfrost/midgard/midgard.h| 4 +--
2 files changed, 14 insertions(+), 18 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/disassemble.c
b/src/gallium/drivers/panfrost/midgard/disassemble.c
index 1a25d0565f4..a92fbf174cc 100644
--- a/src/gallium/drivers/panfrost/midgard/disassemble.c
+++ b/src/gallium/drivers/panfrost/midgard/disassemble.c
@@ -118,7 +118,14 @@ static char *outmod_names_int[4] = {
".isat",
".usat",
"",
-".unk3"
+".hi"
+};
+
+static char *srcmod_names_int[4] = {
+"sext(",
+"zext(",
+"",
+"("
};
static void
@@ -151,20 +158,7 @@ print_vector_src(unsigned src_binary, bool out_high,
midgard_int_mod int_mod = src->mod;
if (is_int) {
-switch (int_mod) {
-case midgard_int_sign_extend:
-printf("sext(");
-break;
-case midgard_int_zero_extend:
-printf("zext(");
-break;
-case midgard_int_reserved:
-printf("unk(");
-break;
-case midgard_int_normal:
-/* Implicit */
-break;
-}
+printf("%s", srcmod_names_int[int_mod]);
} else {
if (src->mod & MIDGARD_FLOAT_MOD_NEG)
printf("-");
@@ -259,7 +253,9 @@ print_vector_src(unsigned src_binary, bool out_high,
/* Since we wrapped with a function-looking thing */
-if ((is_int && (int_mod != midgard_int_normal))
+if (is_int && int_mod == midgard_int_shift)
+printf(") << %d", bits);
+else if ((is_int && (int_mod != midgard_int_normal))
|| (!is_int && src->mod & MIDGARD_FLOAT_MOD_ABS))
printf(")");
}
diff --git a/src/gallium/drivers/panfrost/midgard/midgard.h
b/src/gallium/drivers/panfrost/midgard/midgard.h
index b4eb788f813..9038644c684 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard.h
+++ b/src/gallium/drivers/panfrost/midgard/midgard.h
@@ -195,7 +195,7 @@ typedef enum {
midgard_outmod_int_saturate = 0,
midgard_outmod_uint_saturate = 1,
midgard_outmod_int_wrap = 2,
-/* 0x3 unknown */
+midgard_outmod_int_high = 3, /* Overflowed portion */
} midgard_outmod_int;
typedef enum {
@@ -215,7 +215,7 @@ typedef enum {
midgard_int_sign_extend = 0,
midgard_int_zero_extend = 1,
midgard_int_normal = 2,
-midgard_int_reserved = 3
+midgard_int_shift = 3
} midgard_int_mod;
#define MIDGARD_FLOAT_MOD_ABS (1 << 0)
--
2.20.1
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[Mesa-dev] [PATCH 0/6] panfrost/midgard: Improve disassembler per OpenCL
This series is the culmination of quite a bit of poking at OpenCL kernels, exposing a bunch of details about integer and reduced-precision modes that don't normally come up in OpenGL (but come up in enough truly bizarre corners, i.e. blend shaders, that without this knowledge, debugging can be herculean). Alyssa Rosenzweig (6): panfrost/midgard: Add rounding mode specific opcodes panfrost/midgard: Note floating compares type convert panfrost/midgard: Add integer outmods panfrost/midgard: Add shifting int modifiers panfrost/midgard: Expose vec8/vec16 modes panfrost/midgard: Disambiguate register mode .../drivers/panfrost/midgard/disassemble.c| 559 ++ .../drivers/panfrost/midgard/midgard.h| 46 +- .../panfrost/midgard/midgard_compile.c| 64 +- .../drivers/panfrost/midgard/midgard_ops.c| 32 +- 4 files changed, 404 insertions(+), 297 deletions(-) -- 2.20.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/6] panfrost/midgard: Note floating compares type convert
OP_TYPE_CONVERTS denotes an opcode that returns a different type than is
source (going from int-domain to float-domain or vice versa), named
after the f2i/i2f family of opcodes it covers. We care because source
mods are determined by the source type (i/f) but output modifiers are
determined by the output type (equals the source type, unless the op
type converts, in which case it's the opposite).
The upshot is that floating-point compares (feq/fne/etc) actually do
type-convert. That is, that take in floating-points and output in
integer space (a boolean), so we mark them off this way to ensure the
correct output modifiers are used.
Signed-off-by: Alyssa Rosenzweig
---
src/gallium/drivers/panfrost/midgard/midgard_ops.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_ops.c
b/src/gallium/drivers/panfrost/midgard/midgard_ops.c
index 058b21fab4c..f617ce407bc 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_ops.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_ops.c
@@ -76,10 +76,10 @@ struct mir_op_props alu_opcode_props[256] = {
[midgard_alu_op_imov] = {"imov", UNITS_MOST |
QUIRK_FLIPPED_R24},
/* For vector comparisons, use ball etc */
-[midgard_alu_op_feq]= {"feq", UNITS_MOST | OP_COMMUTES},
-[midgard_alu_op_fne]= {"fne", UNITS_MOST | OP_COMMUTES},
-[midgard_alu_op_fle]= {"fle", UNITS_MOST},
-[midgard_alu_op_flt]= {"flt", UNITS_MOST},
+[midgard_alu_op_feq]= {"feq", UNITS_MOST | OP_TYPE_CONVERT
| OP_COMMUTES},
+[midgard_alu_op_fne]= {"fne", UNITS_MOST | OP_TYPE_CONVERT
| OP_COMMUTES},
+[midgard_alu_op_fle]= {"fle", UNITS_MOST |
OP_TYPE_CONVERT},
+[midgard_alu_op_flt]= {"flt", UNITS_MOST |
OP_TYPE_CONVERT},
[midgard_alu_op_ieq]= {"ieq", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_ine]= {"ine", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_ilt]= {"ilt", UNITS_MOST},
--
2.20.1
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[Mesa-dev] [PATCH 3/6] panfrost/midgard: Add integer outmods
For floats, output modifiers determine clamping behaviour. For integers,
they determine wrapping/saturation behaviour (or shifting -- see next
commit). These are very different; they are conceptually two unrelated
enums union'ed together; the distinction is responsible for many-a-bug.
While clamping behaviour for floats was clear from GL, the int behaviour
is only known From OpenCL contortion with convert_*_sat() functions.
With the underlying functions known, clean up the codebase, likely
fixing outmod type related bugs in the process.
Signed-off-by: Alyssa Rosenzweig
---
.../drivers/panfrost/midgard/disassemble.c| 22 ++---
.../drivers/panfrost/midgard/midgard.h| 17 +--
.../panfrost/midgard/midgard_compile.c| 46 +--
3 files changed, 60 insertions(+), 25 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/disassemble.c
b/src/gallium/drivers/panfrost/midgard/disassemble.c
index c467e94fc29..1a25d0565f4 100644
--- a/src/gallium/drivers/panfrost/midgard/disassemble.c
+++ b/src/gallium/drivers/panfrost/midgard/disassemble.c
@@ -107,17 +107,25 @@ print_reg(unsigned reg, unsigned bits)
printf("r%u", reg);
}
-static char *outmod_names[4] = {
+static char *outmod_names_float[4] = {
"",
".pos",
-".int",
+".unk2",
".sat"
};
+static char *outmod_names_int[4] = {
+".isat",
+".usat",
+"",
+".unk3"
+};
+
static void
-print_outmod(midgard_outmod outmod)
+print_outmod(unsigned outmod, bool is_int)
{
-printf("%s", outmod_names[outmod]);
+printf("%s", is_int ? outmod_names_int[outmod] :
+ outmod_names_float[outmod]);
}
static void
@@ -352,7 +360,8 @@ print_vector_field(const char *name, uint16_t *words,
uint16_t reg_word,
printf("%s.", name);
print_alu_opcode(alu_field->op);
-print_outmod(alu_field->outmod);
+print_outmod(alu_field->outmod,
+midgard_is_integer_out_op(alu_field->op));
printf(" ");
bool out_high = false;
@@ -478,7 +487,8 @@ print_scalar_field(const char *name, uint16_t *words,
uint16_t reg_word,
printf("%s.", name);
print_alu_opcode(alu_field->op);
-print_outmod(alu_field->outmod);
+print_outmod(alu_field->outmod,
+midgard_is_integer_out_op(alu_field->op));
printf(" ");
if (alu_field->output_full)
diff --git a/src/gallium/drivers/panfrost/midgard/midgard.h
b/src/gallium/drivers/panfrost/midgard/midgard.h
index c25f10c4028..b4eb788f813 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard.h
+++ b/src/gallium/drivers/panfrost/midgard/midgard.h
@@ -187,15 +187,22 @@ typedef enum {
typedef enum {
midgard_outmod_none = 0,
midgard_outmod_pos = 1,
-midgard_outmod_int = 2,
+/* 0x2 unknown */
midgard_outmod_sat = 3
-} midgard_outmod;
+} midgard_outmod_float;
+
+typedef enum {
+midgard_outmod_int_saturate = 0,
+midgard_outmod_uint_saturate = 1,
+midgard_outmod_int_wrap = 2,
+/* 0x3 unknown */
+} midgard_outmod_int;
typedef enum {
midgard_reg_mode_8 = 0,
midgard_reg_mode_16 = 1,
midgard_reg_mode_32 = 2,
-midgard_reg_mode_64 = 3 /* TODO: verify */
+midgard_reg_mode_64 = 3
} midgard_reg_mode;
typedef enum {
@@ -239,7 +246,7 @@ __attribute__((__packed__))
unsigned src1 : 13;
unsigned src2 : 13;
midgard_dest_override dest_override : 2;
-midgard_outmod outmod : 2;
+midgard_outmod_float outmod : 2;
unsigned mask : 8;
}
midgard_vector_alu;
@@ -261,7 +268,7 @@ __attribute__((__packed__))
unsigned src1 : 6;
unsigned src2 : 11;
unsigned unknown : 1;
-midgard_outmod outmod : 2;
+unsigned outmod : 2;
bool output_full : 1;
unsigned output_component : 3;
}
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index a0e4d05fd05..585c9fa7a75 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -540,14 +540,14 @@ emit_condition(compiler_context *ctx, nir_src *src, bool
for_branch, unsigned co
.unit = for_branch ? UNIT_SMUL : UNIT_SADD,
.ssa_args = {
-
.src0 = condition,
.src1 = condition,
.dest = SSA_FIXED_REGISTER(31),
},
+
.alu = {
.op = midgard_alu_op_iand,
-.outmod = midgard_outmod_int,
+.outmod = midgard_outmod_int_wrap,
.reg_mode =
[Mesa-dev] [PATCH] panfrost/midgard: Verify SSA claims when pipelining
The pipeline register creation algorithm is only valid for SSA indices;
NIR registers and such cannot be pipelined without more complex
analysis. However, there are the ocassional class of "liars" -- indices
that claim to be SSA but are not. This occurs in the blend shader
prologue, for example. Detect this and just bail quietly for now.
Eventually we need to rewrite the blend shader prologue to occur in NIR
anyway (which would mitigate the issue), but that's more involved and
depends on a better understanding of pixel formats in blend shaders (for
non-RGBA/UNORM cases).
Fixes some blend shader regressions.
Signed-off-by: Alyssa Rosenzweig
---
src/gallium/drivers/panfrost/midgard/compiler.h | 1 +
.../drivers/panfrost/midgard/midgard_liveness.c | 16
.../panfrost/midgard/midgard_ra_pipeline.c | 7 +++
3 files changed, 24 insertions(+)
diff --git a/src/gallium/drivers/panfrost/midgard/compiler.h
b/src/gallium/drivers/panfrost/midgard/compiler.h
index 1191c5cc7b8..e15afca688e 100644
--- a/src/gallium/drivers/panfrost/midgard/compiler.h
+++ b/src/gallium/drivers/panfrost/midgard/compiler.h
@@ -429,6 +429,7 @@ struct ra_graph;
struct ra_graph* allocate_registers(compiler_context *ctx);
void install_registers(compiler_context *ctx, struct ra_graph *g);
bool mir_is_live_after(compiler_context *ctx, midgard_block *block,
midgard_instruction *start, int src);
+bool mir_has_multiple_writes(compiler_context *ctx, int src);
void mir_create_pipeline_registers(compiler_context *ctx);
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_liveness.c
b/src/gallium/drivers/panfrost/midgard/midgard_liveness.c
index e4c89556162..a18d8b9f8ad 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_liveness.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_liveness.c
@@ -96,3 +96,19 @@ mir_is_live_after(compiler_context *ctx, midgard_block
*block, midgard_instructi
return succ;
}
+
+/* Just a quick check -- is it written more than once? (I.e. are we definitely
+ * not SSA?) */
+
+bool
+mir_has_multiple_writes(compiler_context *ctx, int dest)
+{
+unsigned write_count = 0;
+
+mir_foreach_instr_global(ctx, ins) {
+if (ins->ssa_args.dest == dest)
+write_count++;
+}
+
+return write_count > 1;
+}
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_ra_pipeline.c
b/src/gallium/drivers/panfrost/midgard/midgard_ra_pipeline.c
index 07952b63ffc..d4187edc0c8 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_ra_pipeline.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_ra_pipeline.c
@@ -1,5 +1,6 @@
/*
* Copyright (C) 2019 Alyssa Rosenzweig
+ * Copyright (C) 2019 Collabora
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -57,6 +58,12 @@ mir_pipeline_ins(
if ((dest < 0) || (dest >= ctx->func->impl->ssa_alloc))
return false;
+/* Make sure they're not lying to us. Blend shaders lie. TODO: Fix your
+ * bad code Alyssa */
+
+if (mir_has_multiple_writes(ctx, dest))
+return false;
+
/* We want to know if we live after this bundle, so check if
* we're live after the last instruction of the bundle */
--
2.20.1
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[Mesa-dev] [PATCH] panfrost/midgard: Don't assign var locations ourselves
This piece of code was cargo-culted from the ir3 standalone compiler and made sense when we were a standalone compiler ourselves. Unfortunately, for the online compiler, mesa/st *already handles this for us* and if we duplicate it here, we're duplicating it *incorrectly*. So just delete these lines and fix a heck of a lot of tests. Signed-off-by: Alyssa Rosenzweig --- .../drivers/panfrost/ci/expected-failures.txt | 412 -- .../panfrost/midgard/midgard_compile.c| 6 - 2 files changed, 418 deletions(-) diff --git a/src/gallium/drivers/panfrost/ci/expected-failures.txt b/src/gallium/drivers/panfrost/ci/expected-failures.txt index 0ae11321ff4..6be9c83f4af 100644 --- a/src/gallium/drivers/panfrost/ci/expected-failures.txt +++ b/src/gallium/drivers/panfrost/ci/expected-failures.txt @@ -320,24 +320,6 @@ dEQP-GLES2.functional.polygon_offset.fixed16_render_with_units dEQP-GLES2.functional.polygon_offset.fixed16_result_depth_clamp dEQP-GLES2.functional.rasterization.limits.points dEQP-GLES2.functional.shaders.builtin_variable.fragcoord_w -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat2_to_mat2_fragment -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat2_to_mat2_vertex -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat2_to_mat3_fragment -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat2_to_mat3_vertex -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat2_to_mat4_fragment -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat2_to_mat4_vertex -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat3_to_mat2_fragment -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat3_to_mat2_vertex -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat3_to_mat3_fragment -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat3_to_mat3_vertex -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat3_to_mat4_fragment -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat3_to_mat4_vertex -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat4_to_mat2_fragment -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat4_to_mat2_vertex -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat4_to_mat3_fragment -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat4_to_mat3_vertex -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat4_to_mat4_fragment -dEQP-GLES2.functional.shaders.conversions.matrix_to_matrix.mat4_to_mat4_vertex dEQP-GLES2.functional.shaders.conversions.scalar_to_matrix.bool_to_mat3_vertex dEQP-GLES2.functional.shaders.conversions.scalar_to_matrix.float_to_mat3_vertex dEQP-GLES2.functional.shaders.conversions.scalar_to_matrix.int_to_mat3_vertex @@ -345,19 +327,6 @@ dEQP-GLES2.functional.shaders.functions.control_flow.return_after_continue_verte dEQP-GLES2.functional.shaders.functions.control_flow.return_after_loop_sequence_vertex dEQP-GLES2.functional.shaders.functions.control_flow.return_in_loop_if_fragment dEQP-GLES2.functional.shaders.functions.control_flow.return_in_loop_if_vertex -dEQP-GLES2.functional.shaders.functions.datatypes.float_mat2_fragment -dEQP-GLES2.functional.shaders.functions.datatypes.float_mat2_vertex -dEQP-GLES2.functional.shaders.functions.datatypes.float_mat3_fragment -dEQP-GLES2.functional.shaders.functions.datatypes.float_mat3_vertex -dEQP-GLES2.functional.shaders.functions.datatypes.float_mat4_fragment -dEQP-GLES2.functional.shaders.functions.datatypes.float_mat4_vertex -dEQP-GLES2.functional.shaders.functions.datatypes.mat2_fragment -dEQP-GLES2.functional.shaders.functions.datatypes.mat2_vertex -dEQP-GLES2.functional.shaders.functions.datatypes.mat3_fragment -dEQP-GLES2.functional.shaders.functions.datatypes.mat3_vertex -dEQP-GLES2.functional.shaders.functions.datatypes.mat4_fragment -dEQP-GLES2.functional.shaders.functions.datatypes.mat4_vertex -dEQP-GLES2.functional.shaders.indexing.matrix_subscript.mat4_dynamic_loop_write_dynamic_loop_read_vertex dEQP-GLES2.functional.shaders.indexing.tmp_array.float_dynamic_loop_write_dynamic_loop_read_fragment dEQP-GLES2.functional.shaders.indexing.tmp_array.float_dynamic_loop_write_dynamic_loop_read_vertex dEQP-GLES2.functional.shaders.indexing.tmp_array.vec2_dynamic_loop_write_dynamic_loop_read_fragment @@ -382,387 +351,6 @@ dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec4_dynamic_loop_subscr dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec4_dynamic_loop_subscript_write_static_loop_subscript_read_vertex dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec4_dynamic_loop_subscript_write_static_subscript_read_fragment dEQP-GLES2.functional.shaders.indexing.vector_subscript.vec4_dynamic_loop_subscript_write_static_subscript_read_vertex -dEQP-GLES2.functional.shaders.linkage.varying_type_mat2 -dEQP-GLES2.functional.shaders.linkage.varying_type_mat3 -dEQP-GLES2.functional.shaders.linkage.varying_type_mat4
Re: [Mesa-dev] [PATCH 0/2] panfrost/midgard: Fix regressions
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Re: [Mesa-dev] [PATCH] radeonsi: Don't force dcc disable for loads
Reviewed-by: Marek Olšák
Marek
On Wed, Jun 5, 2019 at 6:49 AM Connor Abbott wrote:
> When e9d935ed0e2 added force_dcc_off(), we forced it off for any
> preloaded image descriptor which had stores associated with them, since
> the same preloaded descriptors were used for loads and stores. However,
> when the preloading was removed in 16be87c9042, the existing logic was
> kept despite it not being necessary anymore. The comment above
> force_dcc_off() only mentions stores, so only force DCC off for stores.
>
> Cc: Nicolai Hähnle
> Cc: Marek Olšák
> ---
> src/gallium/drivers/radeonsi/si_shader_nir.c | 6 --
> src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c | 7 ---
> 2 files changed, 13 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c
> b/src/gallium/drivers/radeonsi/si_shader_nir.c
> index 72e6ffbac8a..a852283aff0 100644
> --- a/src/gallium/drivers/radeonsi/si_shader_nir.c
> +++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
> @@ -997,16 +997,10 @@ si_nir_load_sampler_desc(struct ac_shader_abi *abi,
> bool write, bool bindless)
> {
> struct si_shader_context *ctx = si_shader_context_from_abi(abi);
> - const struct tgsi_shader_info *info = >shader->selector->info;
> LLVMBuilderRef builder = ctx->ac.builder;
> unsigned const_index = base_index + constant_index;
> bool dcc_off = write;
>
> - /* TODO: images_store and images_atomic are not set */
> - if (!dynamic_index && image &&
> - (info->images_store | info->images_atomic) & (1 <<
> const_index))
> - dcc_off = true;
> -
> assert(!descriptor_set);
> assert(!image || desc_type == AC_DESC_IMAGE || desc_type ==
> AC_DESC_BUFFER);
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
> b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
> index c5704bc0eae..53075f1b546 100644
> --- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
> +++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
> @@ -218,15 +218,8 @@ image_fetch_rsrc(
> bool dcc_off = is_store;
>
> if (!image->Register.Indirect) {
> - const struct tgsi_shader_info *info = bld_base->info;
> - unsigned images_writemask = info->images_store |
> - info->images_atomic;
> -
> index = LLVMConstInt(ctx->i32,
>
> si_get_image_slot(image->Register.Index), 0);
> -
> - if (images_writemask & (1 << image->Register.Index))
> - dcc_off = true;
> } else {
> /* From the GL_ARB_shader_image_load_store extension spec:
> *
> --
> 2.17.2
>
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[Mesa-dev] [Bug 110846] VA-API st doesn't expose NOISE_REDUCTION/SHARPNESS, while they exposed via VDPAU st
https://bugs.freedesktop.org/show_bug.cgi?id=110846 Bug ID: 110846 Summary: VA-API st doesn't expose NOISE_REDUCTION/SHARPNESS, while they exposed via VDPAU st Product: Mesa Version: git Hardware: x86 (IA32) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Other Assignee: mesa-dev@lists.freedesktop.org Reporter: rand...@mail.ru QA Contact: mesa-dev@lists.freedesktop.org Well, I was playing with VA-API some more, and found few strange things... Here is vdpauinfo for my system (mesa/nv50): vdpauinfo display: :0 screen: 0 API version: 1 Information string: G3DVL VDPAU Driver Shared Library version 1.0 Video surface: name width height types --- 420 8192 8192 NV12 YV12 422 8192 8192 UYVY YUYV 444 8192 8192 Y8U8V8A8 V8U8Y8A8 Decoder capabilities: namelevel macbs width height MPEG1 0 16384 2048 2048 MPEG2_SIMPLE3 16384 2048 2048 MPEG2_MAIN 3 16384 2048 2048 H264_BASELINE --- not supported --- H264_MAIN --- not supported --- H264_HIGH --- not supported --- VC1_SIMPLE --- not supported --- VC1_MAIN --- not supported --- VC1_ADVANCED --- not supported --- MPEG4_PART2_SP --- not supported --- MPEG4_PART2_ASP--- not supported --- DIVX4_QMOBILE --- not supported --- DIVX4_MOBILE --- not supported --- DIVX4_HOME_THEATER --- not supported --- DIVX4_HD_1080P --- not supported --- DIVX5_QMOBILE --- not supported --- DIVX5_MOBILE --- not supported --- DIVX5_HOME_THEATER --- not supported --- DIVX5_HD_1080P --- not supported --- H264_CONSTRAINED_BASELINE --- not supported --- H264_EXTENDED --- not supported --- H264_PROGRESSIVE_HIGH --- not supported --- H264_CONSTRAINED_HIGH --- not supported --- H264_HIGH_444_PREDICTIVE --- not supported --- HEVC_MAIN --- not supported --- HEVC_MAIN_10 --- not supported --- HEVC_MAIN_STILL--- not supported --- HEVC_MAIN_12 --- not supported --- HEVC_MAIN_444 --- not supported --- Output surface: name width height nat types B8G8R8A8 8192 8192y NV12 YV12 UYVY YUYV Y8U8V8A8 V8U8Y8A8 A4I4 I4A4 A8I8 I8A8 R8G8B8A8 8192 8192y NV12 YV12 UYVY YUYV Y8U8V8A8 V8U8Y8A8 A4I4 I4A4 A8I8 I8A8 R10G10B10A2 8192 8192y NV12 YV12 UYVY YUYV Y8U8V8A8 V8U8Y8A8 A4I4 I4A4 A8I8 I8A8 B10G10R10A2 8192 8192y NV12 YV12 UYVY YUYV Y8U8V8A8 V8U8Y8A8 A4I4 I4A4 A8I8 I8A8 Bitmap surface: name width height -- B8G8R8A8 8192 8192 R8G8B8A8 8192 8192 R10G10B10A2 8192 8192 B10G10R10A2 8192 8192 A88192 8192 Video mixer: feature namesup DEINTERLACE_TEMPORAL y DEINTERLACE_TEMPORAL_SPATIAL - INVERSE_TELECINE - NOISE_REDUCTION y SHARPNESSy LUMA_KEY y HIGH QUALITY SCALING - L1y HIGH QUALITY SCALING - L2- HIGH QUALITY SCALING - L3- HIGH QUALITY SCALING - L4- HIGH QUALITY SCALING - L5- HIGH QUALITY SCALING - L6- HIGH QUALITY SCALING - L7- HIGH QUALITY SCALING - L8- HIGH QUALITY SCALING - L9- parameter name sup min max - VIDEO_SURFACE_WIDTH y48 2048 VIDEO_SURFACE_HEIGHT y48 2048 CHROMA_TYPE y LAYERS y 04 attribute name sup min max - BACKGROUND_COLOR y CSC_MATRIX y NOISE_REDUCTION_LEVELy 0.00 1.00 SHARPNESS_LEVEL y -1.00 1.00 LUMA_KEY_MIN_LUMAy LUMA_KEY_MAX_LUMAy as you can see, in theory noise reduction/sharpness (from vl layer in gallium) exposed here. Still, if I look at https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/state_trackers/va/surface.c I can see in vlVaQueryVideoProcFilterCaps() case VAProcFilterNoiseReduction: case VAProcFilterSharpening: case VAProcFilterColorBalance: case
[Mesa-dev] [ANNOUNCE] mesa 19.1.0-rc5
Hello, list. The fifth release candidate for Mesa 19.1.0 is now available. We have extended the release candidates because there are two bugs blocking the final release: #110302 - [bisected][regression] piglit egl-create-pbuffer-surface and egl-gl-colorspace regressions #110357 - [REGRESSION] [BISECTED] [OpenGL CTS] cts-runner --type=gl46 fails in new attempted "41" configuration We hope to unblock them as soon as possible. Axel Davy (1): d3dadapter9: Revert to old throttling limit value Bas Nieuwenhuizen (1): nir: Actually propagate progress in nir_opt_move_load_ubo. Jan Zielinski (1): swr/rast: fix 32-bit compilation on Linux Jason Ekstrand (4): iris: Don't assume UBO indices are constant intel/fs,vec4: Use g0 as the header for MFENCE intel/fs: Do a stalling MFENCE in endInvocationInterlock() nir/dead_cf: Call instructions aren't dead Jonathan Marek (1): freedreno/ir3: fix input ncomp for vertex shaders Juan A. Suarez Romero (1): Update version to 19.1.0-rc5 Lionel Landwerlin (1): nir/lower_non_uniform: safely iterate over blocks Marek Olšák (2): u_blitter: don't fail mipmap generation for depth formats containing stencil ac: fix a typo in ac_build_wg_scan_bottom Pierre-Eric Pelloux-Prayer (1): radeonsi: init sctx->dma_copy before using it Rhys Perry (1): ac/nir: mark some texture intrinsics as convergent Rob Clark (2): freedreno/ir3: set more barrier bits freedreno/a6xx: fix GPU crash on small render targets Sagar Ghuge (1): intel/compiler: Fix assertions in brw_alu3 Samuel Pitoiset (2): radv: allocate more space in the CS when emitting events radv: do not use gfx fast depth clears for layered depth/stencil images Timothy Arceri (1): st/glsl: make sure to propagate initialisers to driver storage Vinson Lee (1): freedreno: Fix GCC build error. git tag: mesa-19.1.0-rc5 https://mesa.freedesktop.org/archive/mesa-19.1.0-rc5.tar.xz MD5: e18f28edd04c36e1a4fc0ac7026187b9 mesa-19.1.0-rc5.tar.xz SHA1: 90bd39c330ece4e795fe5dfeefb0bc5703f36bbc mesa-19.1.0-rc5.tar.xz SHA256: a753a8f1fd72b98d47eb99e1c5fb880b1046b05b6504346c5f947c40d9c32486 mesa-19.1.0-rc5.tar.xz SHA512: 033920bbbf395104bfb6ffe9482e0f504b5cb0009be25bb1b0a4269bc6cf9c737de82350e994d568f454ed5b3206fc23927122032b3702122fe7edbc2d749e6d mesa-19.1.0-rc5.tar.xz PGP: https://mesa.freedesktop.org/archive/mesa-19.1.0-rc5.tar.xz.sig signature.asc Description: This is a digitally signed message part ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [Mesa-stable] [PATCH 6/8] egl/dri: flesh out and use dri2_create_drawable()
On Mon, 3 Jun 2019 at 23:52, Marek Olšák wrote: > > Would you please review this fixed version: > https://cgit.freedesktop.org/~mareko/mesa/commit/?h=master=40e4702ef815410f74130f349e2b40cc0524e422 > > It trivially solves the GBM crash by checking that gbm_surf != NULL before > using it. > Makes sense. Thanks for following up Marek. Fwiw the patch is Reviewed-by: Emil Velikov Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] mapi: add static_date offset to MaxShaderCompilerThreadsKHR
From: Emil Velikov
As elaborated in the next patch, there is some hidden ABI that
effectively require most entrypoints to be listed in the file.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110302
Cc: Marek Olšák
Fixes: c5c38e831ee ("mesa: implement ARB/KHR_parallel_shader_compile")
Signed-off-by: Emil Velikov
---
src/mapi/glapi/gen/static_data.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mapi/glapi/gen/static_data.py
b/src/mapi/glapi/gen/static_data.py
index bc49324348f..dc1926327da 100644
--- a/src/mapi/glapi/gen/static_data.py
+++ b/src/mapi/glapi/gen/static_data.py
@@ -1453,6 +1453,7 @@ offsets = {
"TexParameterxv": 1417,
"BlendBarrier": 1418,
"PrimitiveBoundingBox": 1419,
+"MaxShaderCompilerThreadsKHR": 1420,
}
functions = [
--
2.20.1
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[Mesa-dev] [PATCH 2/2] mapi: correctly handle the full offset table
From: Emil Velikov
Earlier commit converted ES1 and ES2 to a new, much simpler, dispatch
generator. At the same time, GL/glapi and the driver side are still
using the old code.
There is a hidden ABI between GL*.so and glapi.so, former referencing
entry-points by offset in the _glapi_table. Hence earlier commit added
the full table of entry-points, alongside a marker for other cases like
indirect GL(X) and driver-size remapping.
Yet the patches did not handle things fully, thus it was possible to
get different interpretations of the dispatch table after the marker.
This commit fixes that adding an indicative error message to catch
future bugs.
While here correct the marker (MAX_OFFSETS) comment.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110302
Fixes: cf317bf0937 ("mapi: add all _glapi_table entrypoints tostatic_data.py")
Signed-off-by: Emil Velikov
---
src/mapi/glapi/gen/gl_XML.py | 8 ++--
src/mapi/glapi/gen/static_data.py | 2 +-
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/mapi/glapi/gen/gl_XML.py b/src/mapi/glapi/gen/gl_XML.py
index 478f82ca314..2854a9a5688 100644
--- a/src/mapi/glapi/gen/gl_XML.py
+++ b/src/mapi/glapi/gen/gl_XML.py
@@ -49,7 +49,7 @@ def parse_GL_API( file_name, factory = None ):
# that are not part of the ABI.
for func in api.functionIterateByCategory():
-if func.assign_offset:
+if func.assign_offset and func.offset < 0:
func.offset = api.next_offset;
api.next_offset += 1
@@ -683,8 +683,12 @@ class gl_function( gl_item ):
if name in static_data.offsets and static_data.offsets[name] <=
static_data.MAX_OFFSETS:
self.offset = static_data.offsets[name]
+elif name in static_data.offsets and static_data.offsets[name] >
static_data.MAX_OFFSETS:
+self.offset = static_data.offsets[name]
+self.assign_offset = True
else:
-self.offset = -1
+if self.exec_flavor != "skip":
+raise RuntimeError("Entry-point %s is missing offset in
static_data.py. Add one at the bottom of the list." % (name))
self.assign_offset = self.exec_flavor != "skip" or name in
static_data.unused_functions
if not self.name:
diff --git a/src/mapi/glapi/gen/static_data.py
b/src/mapi/glapi/gen/static_data.py
index dc1926327da..5044e0f78cf 100644
--- a/src/mapi/glapi/gen/static_data.py
+++ b/src/mapi/glapi/gen/static_data.py
@@ -29,7 +29,7 @@ MAX_OFFSETS = 407
"""Table of functions that have ABI-mandated offsets in the dispatch table.
The first MAX_OFFSETS entries are required by indirect GLX. The rest are
-required to preserve the glapi <> drivers ABI. This is to be addressed shortly.
+required to preserve the glapi <> GL/GLES ABI. This is to be addressed shortly.
This list will never change."""
offsets = {
--
2.20.1
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[Mesa-dev] [PATCH 2/2] panfrost/midgard: Always break up fragment writeout
In a fragment shader, r0 is written out with a special branch sequence.
r0 is not a real register here, but essentially a pipeline register --
as such, it needs to be written out in full and on time, with hanging
dependencies in the bundle. Otherwise, we break up the bundle, which
costs an extra ALU cycle and adds a move.
When the scheduler ran last thing, we could do this analysis within the
scheduler. Now that RA can run after scheduling, that's no longer valid,
so we remove the analysis and always break it up (at a performance
penalty). Future work can add a post-RA/post-schedule pass to merge
writeout blocks if possible. It's a bit of a low-priority next to fixing
conformance regressions, of course.
Signed-off-by: Alyssa Rosenzweig
---
.../panfrost/midgard/midgard_schedule.c | 89 +--
1 file changed, 21 insertions(+), 68 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
index 1a562af8142..9d4ce2a97d5 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
@@ -288,75 +288,28 @@ schedule_bundle(compiler_context *ctx, midgard_block
*block, midgard_instruction
* the branch writeout */
if (ains->writeout) {
-if (index == 0) {
-/* Inject a move */
-midgard_instruction ins =
v_fmov(0, blank_alu_src, SSA_FIXED_REGISTER(0));
-ins.unit = UNIT_VMUL;
-control |= ins.unit;
-
-/* TODO don't leak */
-midgard_instruction *move =
-mem_dup(,
sizeof(midgard_instruction));
-bytes_emitted +=
sizeof(midgard_reg_info);
-bytes_emitted +=
sizeof(midgard_vector_alu);
-
bundle.instructions[packed_idx++] = move;
-} else {
-/* Analyse the group to see if
r0 is written in full, on-time, without hanging dependencies */
-bool written_late = false;
-bool components[4] = { 0 };
-uint16_t register_dep_mask = 0;
-uint16_t written_mask = 0;
-
-midgard_instruction *qins =
ins;
-for (int t = 0; t < index;
++t) {
-if
(qins->registers.out_reg != 0) {
-/* Mark down
writes */
-
-written_mask
|= (1 << qins->registers.out_reg);
-} else {
-/* Mark down
the register dependencies for errata check */
-
-if
(qins->registers.src1_reg < 16)
-
register_dep_mask |= (1 << qins->registers.src1_reg);
-
-if
(qins->registers.src2_reg < 16)
-
register_dep_mask |= (1 << qins->registers.src2_reg);
-
-int mask =
qins->alu.mask;
-
-for (int c =
0; c < 4; ++c)
-if
(mask & (0x3 << (2 * c)))
-
components[c] = true;
-
-/* ..but if
the writeout is too late, we have to break up anyway... for some reason */
-
-if (qins->unit
== UNIT_VLUT)
-
written_late = true;
-}
-
-/* Advance instruction
pointer */
-qins =
mir_next_op(qins);
-}
-
-
[Mesa-dev] [PATCH 0/2] panfrost/midgard: Fix regressions
The RA rewrite / schedler refactor series changed huge portions of the Midgard codebase. Inevitably, that introduced a few hundred regressions or so on dEQP. Fix them before anyone noticed. Nothing to see here, folks. Alyssa Rosenzweig (2): panfrost/midgard: Fix cubemap regression panfrost/midgard: Always break up fragment writeout .../drivers/panfrost/midgard/midgard_ra.c | 11 ++- .../panfrost/midgard/midgard_schedule.c | 89 +-- 2 files changed, 30 insertions(+), 70 deletions(-) -- 2.20.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] panfrost/midgard: Fix cubemap regression
Fixes: 2d9802233 ("panfrost/midgard: Extend RA to non-vec4 sources")
Signed-off-by: Alyssa Rosenzweig
---
src/gallium/drivers/panfrost/midgard/midgard_ra.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_ra.c
b/src/gallium/drivers/panfrost/midgard/midgard_ra.c
index c9a6c6e4710..7fd5e5b49e3 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_ra.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_ra.c
@@ -1,5 +1,6 @@
/*
* Copyright (C) 2018-2019 Alyssa Rosenzweig
+ * Copyright (C) 2019 Collabora
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -478,11 +479,17 @@ install_registers_instr(
}
case TAG_LOAD_STORE_4: {
-if (OP_IS_STORE(ins->load_store.op)) {
+if (OP_IS_STORE_VARY(ins->load_store.op)) {
/* TODO: use ssa_args for st_vary */
ins->load_store.reg = 0;
} else {
-struct phys_reg src = index_to_reg(ctx, g, args.dest);
+/* Which physical register we read off depends on
+ * whether we are loading or storing -- think about the
+ * logical dataflow */
+
+unsigned r = OP_IS_STORE(ins->load_store.op) ?
+args.src0 : args.dest;
+struct phys_reg src = index_to_reg(ctx, g, r);
ins->load_store.reg = src.reg;
--
2.20.1
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Re: [Mesa-dev] [PATCH 0/3] panfrost/midgard: Integer division
Patch series Reviewed-By: Ryan Houdek On Wed, Jun 5, 2019 at 8:41 AM Alyssa Rosenzweig < alyssa.rosenzw...@collabora.com> wrote: > This series adds some new ALU ops from OpenCL (cherry-picked from my > downstream tree -- the full set of OpenCL-related ISA additions should > be coming soon). In particular, it identifies iabs as iabsdiff/#0, > allowing an iabs bug to be fixed. From there, all prereqs are in place > to enable integer division lowering. > > Alyssa Rosenzweig (3): > panfrost/midgard: Add a bunch of new ALU ops > panfrost/midgard: Fix 1-arg ALU memory corruption > panfrost/midgard: Lower integer division > > .../drivers/panfrost/ci/expected-failures.txt | 144 -- > .../drivers/panfrost/midgard/midgard.h| 14 +- > .../panfrost/midgard/midgard_compile.c| 9 +- > .../drivers/panfrost/midgard/midgard_ops.c| 17 ++- > 4 files changed, 35 insertions(+), 149 deletions(-) > > -- > 2.20.1 > > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110763] Rendering problem and fps decrease
https://bugs.freedesktop.org/show_bug.cgi?id=110763 Michel Dänzer changed: What|Removed |Added Version|unspecified |19.0 QA Contact|xorg-t...@lists.x.org |mesa-dev@lists.freedesktop. ||org Component|Driver/AMDgpu |Gallium/StateTracker/Clover Assignee|xorg-driver-...@lists.x.org |mesa-dev@lists.freedesktop. ||org Product|xorg|Mesa --- Comment #4 from Michel Dänzer --- Please attach files here directly instead of referencing external pastebin sites. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/3] panfrost/midgard: Fix 1-arg ALU memory corruption
Certain ops that only take one argument have an imaginary "zero"
constant for their second argument. For instance, conversions:
i2f [dest], [source], #0
Memory corruption meant that #0 was instead random noise. For some ops,
that doesn't matter (manifested as abnormally large code size and poor
scheduling due to extra constants in random places). But for others,
where a 1-op is emulated by a 2-op with an implicit 0 second argument,
that broke things.
Fixes iabs (emulated by iabsdiff).
Signed-off-by: Alyssa Rosenzweig
---
src/gallium/drivers/panfrost/midgard/midgard_compile.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 96f3e525b4a..99a648788ef 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -930,7 +930,8 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
}
ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_);
-} else if (instr->op == nir_op_f2b32 || instr->op == nir_op_i2b32) {
+} else if (nr_inputs == 1 && !quirk_flipped_r24) {
+/* Lots of instructions need a 0 plonked in */
ins.ssa_args.inline_constant = false;
ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
ins.has_constants = true;
--
2.20.1
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[Mesa-dev] [PATCH 1/3] panfrost/midgard: Add a bunch of new ALU ops
These ops are used to accelerate various functions exposed in OpenCL.
This commit only includes the routine additions to the table. They are
not wired through the compiler; rather, they are just here to keep a
reference for the disassembler.
Signed-off-by: Alyssa Rosenzweig
---
src/gallium/drivers/panfrost/midgard/midgard.h | 14 +-
.../drivers/panfrost/midgard/midgard_compile.c | 5 -
.../drivers/panfrost/midgard/midgard_ops.c | 17 +++--
3 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/midgard.h
b/src/gallium/drivers/panfrost/midgard/midgard.h
index f5cd59cbfb1..7bf17321ccb 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard.h
+++ b/src/gallium/drivers/panfrost/midgard/midgard.h
@@ -75,6 +75,10 @@ typedef enum {
midgard_alu_op_iadd = 0x40,
midgard_alu_op_ishladd= 0x41,
midgard_alu_op_isub = 0x46,
+midgard_alu_op_iaddsat= 0x48,
+midgard_alu_op_uaddsat= 0x49,
+midgard_alu_op_isubsat= 0x4E,
+midgard_alu_op_usubsat= 0x4F,
midgard_alu_op_imul = 0x58,
@@ -82,6 +86,10 @@ typedef enum {
midgard_alu_op_umin = 0x61,
midgard_alu_op_imax = 0x62,
midgard_alu_op_umax = 0x63,
+midgard_alu_op_ihadd = 0x64,
+midgard_alu_op_uhadd = 0x65,
+midgard_alu_op_irhadd = 0x66,
+midgard_alu_op_urhadd = 0x67,
midgard_alu_op_iasr = 0x68,
midgard_alu_op_ilsr = 0x69,
midgard_alu_op_ishl = 0x6E,
@@ -97,7 +105,9 @@ typedef enum {
midgard_alu_op_iclz = 0x78, /* Number of zeroes on left */
midgard_alu_op_ibitcount8 = 0x7A, /* Counts bits in 8-bit increments */
midgard_alu_op_imov = 0x7B,
-midgard_alu_op_iabs = 0x7C,
+midgard_alu_op_iabsdiff = 0x7C,
+midgard_alu_op_uabsdiff = 0x7D,
+midgard_alu_op_ichoose= 0x7E, /* vector, component number - dupe
for shuffle() */
midgard_alu_op_feq= 0x80,
midgard_alu_op_fne= 0x81,
@@ -146,6 +156,8 @@ typedef enum {
midgard_alu_op_fatan_pt2 = 0xE8,
midgard_alu_op_fpow_pt1 = 0xEC,
+midgard_alu_op_fpown_pt1 = 0xED,
+midgard_alu_op_fpowr_pt1 = 0xEE,
midgard_alu_op_frcp = 0xF0,
midgard_alu_op_frsqrt = 0xF2,
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 0f3331d923b..96f3e525b4a 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -682,7 +682,10 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
ALU_CASE(iadd, iadd);
ALU_CASE(isub, isub);
ALU_CASE(imul, imul);
-ALU_CASE(iabs, iabs);
+
+/* Zero shoved as second-arg */
+ALU_CASE(iabs, iabsdiff);
+
ALU_CASE(mov, imov);
ALU_CASE(feq32, feq);
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_ops.c
b/src/gallium/drivers/panfrost/midgard/midgard_ops.c
index cffa3c20fdf..97c12feec00 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_ops.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_ops.c
@@ -40,6 +40,11 @@ struct mir_op_props alu_opcode_props[256] = {
[midgard_alu_op_imax] = {"imax", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_umin] = {"umin", UNITS_MOST | OP_COMMUTES},
[midgard_alu_op_umax] = {"umax", UNITS_MOST | OP_COMMUTES},
+[midgard_alu_op_ihadd] = {"ihadd", UNITS_ADD | OP_COMMUTES},
+[midgard_alu_op_uhadd] = {"uhadd", UNITS_ADD | OP_COMMUTES},
+[midgard_alu_op_irhadd] = {"irhadd", UNITS_ADD |
OP_COMMUTES},
+[midgard_alu_op_urhadd] = {"urhadd", UNITS_ADD |
OP_COMMUTES},
+
[midgard_alu_op_fmov] = {"fmov", UNITS_ALL |
QUIRK_FLIPPED_R24},
[midgard_alu_op_fround] = {"fround", UNITS_ADD},
[midgard_alu_op_froundeven] = {"froundeven", UNITS_ADD},
@@ -56,8 +61,14 @@ struct mir_op_props alu_opcode_props[256] = {
/* Incredibly, iadd can run on vmul, etc */
[midgard_alu_op_iadd] = {"iadd", UNITS_MOST | OP_COMMUTES},
-[midgard_alu_op_iabs] = {"iabs", UNITS_ADD},
+[midgard_alu_op_iaddsat]= {"iaddsat", UNITS_ADD | OP_COMMUTES},
+[midgard_alu_op_uaddsat]= {"uaddsat", UNITS_ADD | OP_COMMUTES},
+[midgard_alu_op_iabsdiff] = {"iabsdiff", UNITS_ADD},
+[midgard_alu_op_uabsdiff] = {"uabsdiff", UNITS_ADD},
+[midgard_alu_op_ichoose]= {"ichoose", UNITS_ADD},
[midgard_alu_op_isub] = {"isub", UNITS_MOST},
+
[Mesa-dev] [PATCH 3/3] panfrost/midgard: Lower integer division
We use the shared nir_lower_idiv pass to lower integer division, fixing 144 dEQP tests. This pass was not applied in the past due to breakage from iabs fixed earlier in the series. Signed-off-by: Alyssa Rosenzweig --- .../drivers/panfrost/ci/expected-failures.txt | 144 -- .../panfrost/midgard/midgard_compile.c| 1 + 2 files changed, 1 insertion(+), 144 deletions(-) diff --git a/src/gallium/drivers/panfrost/ci/expected-failures.txt b/src/gallium/drivers/panfrost/ci/expected-failures.txt index 762ceaffd5a..0ae11321ff4 100644 --- a/src/gallium/drivers/panfrost/ci/expected-failures.txt +++ b/src/gallium/drivers/panfrost/ci/expected-failures.txt @@ -763,150 +763,6 @@ dEQP-GLES2.functional.shaders.matrix.unary_addition.dynamic_mediump_mat3_fragmen dEQP-GLES2.functional.shaders.matrix.unary_addition.dynamic_mediump_mat3_vertex dEQP-GLES2.functional.shaders.matrix.unary_addition.dynamic_mediump_mat4_fragment dEQP-GLES2.functional.shaders.matrix.unary_addition.dynamic_mediump_mat4_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_int_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_int_ivec2_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_int_ivec2_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_int_ivec3_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_int_ivec3_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_int_ivec4_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_int_ivec4_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_int_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_ivec2_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_ivec2_int_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_ivec2_int_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_ivec2_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_ivec3_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_ivec3_int_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_ivec3_int_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_ivec3_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_ivec4_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_ivec4_int_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_ivec4_int_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_ivec4_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_int_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_int_ivec2_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_int_ivec2_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_int_ivec3_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_int_ivec3_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_int_ivec4_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_int_ivec4_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_int_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_ivec2_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_ivec2_int_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_ivec2_int_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_ivec2_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_ivec3_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_ivec3_int_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_ivec3_int_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_ivec3_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_ivec4_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_ivec4_int_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_ivec4_int_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.lowp_ivec4_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.mediump_int_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.mediump_int_ivec2_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.mediump_int_ivec2_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.mediump_int_ivec3_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.mediump_int_ivec3_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.mediump_int_ivec4_fragment -dEQP-GLES2.functional.shaders.operator.binary_operator.div.mediump_int_ivec4_vertex -dEQP-GLES2.functional.shaders.operator.binary_operator.div.mediump_int_vertex
[Mesa-dev] [PATCH 0/3] panfrost/midgard: Integer division
This series adds some new ALU ops from OpenCL (cherry-picked from my downstream tree -- the full set of OpenCL-related ISA additions should be coming soon). In particular, it identifies iabs as iabsdiff/#0, allowing an iabs bug to be fixed. From there, all prereqs are in place to enable integer division lowering. Alyssa Rosenzweig (3): panfrost/midgard: Add a bunch of new ALU ops panfrost/midgard: Fix 1-arg ALU memory corruption panfrost/midgard: Lower integer division .../drivers/panfrost/ci/expected-failures.txt | 144 -- .../drivers/panfrost/midgard/midgard.h| 14 +- .../panfrost/midgard/midgard_compile.c| 9 +- .../drivers/panfrost/midgard/midgard_ops.c| 17 ++- 4 files changed, 35 insertions(+), 149 deletions(-) -- 2.20.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] ac/nir: Remove stale TODO
Reviewed-by: Samuel Pitoiset
On 6/5/19 5:09 PM, Connor Abbott wrote:
While we're here, copy the comment explaining this from radeonsi.
---
src/amd/common/ac_nir_to_llvm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 833b1e54abc..11de22a8cbd 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3878,7 +3878,13 @@ static void visit_tex(struct ac_nir_context *ctx,
nir_tex_instr *instr)
args.offset = NULL;
}
- /* TODO TG4 support */
+ /* DMASK was repurposed for GATHER4. 4 components are always
+* returned and DMASK works like a swizzle - it selects
+* the component to fetch. The only valid DMASK values are
+* 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
+* (red,red,red,red) etc.) The ISA document doesn't mention
+* this.
+*/
args.dmask = 0xf;
if (instr->op == nir_texop_tg4) {
if (instr->is_shadow)
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[Mesa-dev] [PATCH] ac/nir: Remove stale TODO
While we're here, copy the comment explaining this from radeonsi.
---
src/amd/common/ac_nir_to_llvm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 833b1e54abc..11de22a8cbd 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3878,7 +3878,13 @@ static void visit_tex(struct ac_nir_context *ctx,
nir_tex_instr *instr)
args.offset = NULL;
}
- /* TODO TG4 support */
+ /* DMASK was repurposed for GATHER4. 4 components are always
+* returned and DMASK works like a swizzle - it selects
+* the component to fetch. The only valid DMASK values are
+* 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
+* (red,red,red,red) etc.) The ISA document doesn't mention
+* this.
+*/
args.dmask = 0xf;
if (instr->op == nir_texop_tg4) {
if (instr->is_shadow)
--
2.17.2
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Re: [Mesa-dev] [PATCH] Revert "radv: fix color conversions for normalized uint/sint formats"
r-b
On Wed, Jun 5, 2019 at 12:02 PM Samuel Pitoiset
wrote:
>
> For some reasons, this actually introduced rendering issues with
> Far Cry 3 (and probably Far Cry 4). I'm reverting it for now
> until I figure out the right fix.
>
> See the following link for reference:
> https://github.com/ValveSoftware/Proton/issues/727#issuecomment-498638025
>
> Cc: 19.0 19.1
> This reverts commit e03e7c510f571a8867ab7a8604058c075c601a70.
> ---
> src/amd/vulkan/radv_formats.c | 20
> 1 file changed, 4 insertions(+), 16 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
> index d7b560082f6..0434c0641d8 100644
> --- a/src/amd/vulkan/radv_formats.c
> +++ b/src/amd/vulkan/radv_formats.c
> @@ -1034,22 +1034,10 @@ bool radv_format_pack_clear_color(VkFormat format,
> assert(channel->size == 8);
>
> v =
> util_format_linear_float_to_srgb_8unorm(value->float32[c]);
> - } else {
> - float f = MIN2(value->float32[c], 1.0f);
> -
> - if (channel->type == VK_FORMAT_TYPE_UNSIGNED)
> {
> - f = MAX2(f, 0.0f) * ((1ULL <<
> channel->size) - 1);
> - } else {
> - f = MAX2(f, -1.0f) * ((1ULL <<
> (channel->size - 1)) - 1);
> - }
> -
> - /* The hardware rounds before conversion. */
> - if (f > 0)
> - f += 0.5f;
> - else
> - f -= 0.5f;
> -
> - v = (uint64_t)f;
> + } else if (channel->type == VK_FORMAT_TYPE_UNSIGNED) {
> + v = MAX2(MIN2(value->float32[c], 1.0f), 0.0f)
> * ((1ULL << channel->size) - 1);
> + } else {
> + v = MAX2(MIN2(value->float32[c], 1.0f),
> -1.0f) * ((1ULL << (channel->size - 1)) - 1);
> }
> } else if (channel->type == VK_FORMAT_TYPE_FLOAT) {
> if (channel->size == 32) {
> --
> 2.21.0
>
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[Mesa-dev] [PATCH] radeonsi: Don't force dcc disable for loads
When e9d935ed0e2 added force_dcc_off(), we forced it off for any
preloaded image descriptor which had stores associated with them, since
the same preloaded descriptors were used for loads and stores. However,
when the preloading was removed in 16be87c9042, the existing logic was
kept despite it not being necessary anymore. The comment above
force_dcc_off() only mentions stores, so only force DCC off for stores.
Cc: Nicolai Hähnle
Cc: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader_nir.c | 6 --
src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c | 7 ---
2 files changed, 13 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 72e6ffbac8a..a852283aff0 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -997,16 +997,10 @@ si_nir_load_sampler_desc(struct ac_shader_abi *abi,
bool write, bool bindless)
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
- const struct tgsi_shader_info *info = >shader->selector->info;
LLVMBuilderRef builder = ctx->ac.builder;
unsigned const_index = base_index + constant_index;
bool dcc_off = write;
- /* TODO: images_store and images_atomic are not set */
- if (!dynamic_index && image &&
- (info->images_store | info->images_atomic) & (1 << const_index))
- dcc_off = true;
-
assert(!descriptor_set);
assert(!image || desc_type == AC_DESC_IMAGE || desc_type ==
AC_DESC_BUFFER);
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
index c5704bc0eae..53075f1b546 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
@@ -218,15 +218,8 @@ image_fetch_rsrc(
bool dcc_off = is_store;
if (!image->Register.Indirect) {
- const struct tgsi_shader_info *info = bld_base->info;
- unsigned images_writemask = info->images_store |
- info->images_atomic;
-
index = LLVMConstInt(ctx->i32,
si_get_image_slot(image->Register.Index),
0);
-
- if (images_writemask & (1 << image->Register.Index))
- dcc_off = true;
} else {
/* From the GL_ARB_shader_image_load_store extension spec:
*
--
2.17.2
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Re: [Mesa-dev] [PATCH 6/8] radv: handle sample locations during automatic layout transitions
On 6/5/19 2:51 AM, Bas Nieuwenhuizen wrote:
On Thu, May 30, 2019 at 4:02 PM Samuel Pitoiset
wrote:
From the Vulkan spec 1.1.109:
"Some implementations may need to evaluate depth image values
while performing image layout transitions. To accommodate this,
instances of the VkSampleLocationsInfoEXT structure can be
specified for each situation where an explicit or automatic
layout transition has to take place. [...] and
VkRenderPassSampleLocationsBeginInfoEXT can be chained from
VkRenderPassBeginInfo to provide sample locations for layout
transitions performed implicitly by a render pass instance."
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 155 ---
src/amd/vulkan/radv_private.h| 9 ++
2 files changed, 150 insertions(+), 14 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 570acaa0905..81b3f5f9886 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2645,11 +2645,55 @@ void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer,
NULL);
}
+static uint32_t
+radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
+{
+ struct radv_cmd_state *state = _buffer->state;
+ uint32_t subpass_id = state->subpass - state->pass->subpasses;
+
+ /* The id of this subpass shouldn't exceed the number of subpasses in
+* this render pass minus 1.
+*/
+ assert(subpass_id < state->pass->subpass_count);
+ return subpass_id;
+}
+
+static struct radv_sample_locations_state *
+radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer,
+uint32_t att_idx)
+{
+ struct radv_cmd_state *state = _buffer->state;
+ uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
On the start of the first subpass this may not work as the subpass is
not set yet?
Yes, this patch needs https://patchwork.freedesktop.org/series/61387/
+ struct radv_image_view *view =
state->framebuffer->attachments[att_idx].attachment;
+
+ if (view->image->info.samples == 1)
+ return NULL;
+
+ if (state->pass->attachments[att_idx].first_subpass_idx == subpass_id) {
+ /* Return the initial sample locations if this is the initial
+* layout transition of the given subpass attachemnt.
+*/
+ if (state->attachments[att_idx].sample_location.count > 0)
+ return >attachments[att_idx].sample_location;
+ } else {
+ /* Otherwise return the subpass sample locations if defined. */
+ if (state->subpass_sample_locs) {
+ for (uint32_t i = 0; i <
state->num_subpass_sample_locs; i++) {
+ if (state->subpass_sample_locs[i].subpass_idx
== subpass_id)
+ return
>subpass_sample_locs[i].sample_location;
+ }
+ }
+ }
+
+ return NULL;
+}
+
static void radv_handle_subpass_image_transition(struct radv_cmd_buffer
*cmd_buffer,
struct
radv_subpass_attachment att)
{
unsigned idx = att.attachment;
struct radv_image_view *view =
cmd_buffer->state.framebuffer->attachments[idx].attachment;
+ struct radv_sample_locations_state *sample_locs;
VkImageSubresourceRange range;
range.aspectMask = 0;
range.baseMipLevel = view->base_mip;
@@ -2668,10 +2712,15 @@ static void radv_handle_subpass_image_transition(struct
radv_cmd_buffer *cmd_buf
range.layerCount =
util_last_bit(cmd_buffer->state.subpass->view_mask);
}
+ /* Get the subpass sample locations for the given attachment, if NULL
+* is returned the driver will use the default HW locations.
+*/
+ sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx);
+
radv_handle_image_transition(cmd_buffer,
view->image,
cmd_buffer->state.attachments[idx].current_layout,
-att.layout, 0, 0, , NULL);
+att.layout, 0, 0, , sample_locs);
cmd_buffer->state.attachments[idx].current_layout = att.layout;
@@ -2687,6 +2736,89 @@ radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer,
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
}
+static VkResult
+radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_render_pass *pass,
+ const VkRenderPassBeginInfo *info)
+{
+ const struct VkRenderPassSampleLocationsBeginInfoEXT *sample_locs =
+
Re: [Mesa-dev] [PATCH 1/8] radv: allow to save/restore sample locations during meta operations
On 6/5/19 2:37 AM, Bas Nieuwenhuizen wrote:
On Thu, May 30, 2019 at 4:02 PM Samuel Pitoiset
wrote:
This will be used for the depth decompress pass that might need
to emit variable sample locations during layout transitions.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta.c | 20
src/amd/vulkan/radv_meta.h | 2 ++
2 files changed, 22 insertions(+)
diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index 3bfe49b4dab..44715483565 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -73,6 +73,15 @@ radv_meta_save(struct radv_meta_saved_state *state,
1 << VK_DYNAMIC_STATE_SCISSOR;
}
+ if (state->flags & RADV_META_SAVE_SAMPLE_LOCATIONS) {
+ state->sample_location.per_pixel =
cmd_buffer->state.dynamic.sample_location.per_pixel;
+ state->sample_location.grid_size =
cmd_buffer->state.dynamic.sample_location.grid_size;
+ state->sample_location.count =
cmd_buffer->state.dynamic.sample_location.count;
+ typed_memcpy(state->sample_location.locations,
+
cmd_buffer->state.dynamic.sample_location.locations,
+MAX_SAMPLE_LOCATIONS);
Why not copy the entire radv_sample_locations_state struct in a single
statement if you're going to copy all locations anyway? Same during
the restore.
Otherwise, r-b
Yep, looks good.
+ }
+
if (state->flags & RADV_META_SAVE_COMPUTE_PIPELINE) {
assert(!(state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE));
@@ -131,6 +140,17 @@ radv_meta_restore(const struct radv_meta_saved_state
*state,
RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
}
+ if (state->flags & RADV_META_SAVE_SAMPLE_LOCATIONS) {
+ cmd_buffer->state.dynamic.sample_location.per_pixel =
state->sample_location.per_pixel;
+ cmd_buffer->state.dynamic.sample_location.grid_size =
state->sample_location.grid_size;
+ cmd_buffer->state.dynamic.sample_location.count =
state->sample_location.count;
+
typed_memcpy(cmd_buffer->state.dynamic.sample_location.locations,
+state->sample_location.locations,
+MAX_SAMPLE_LOCATIONS);
+
+ cmd_buffer->state.dirty |=
RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS;
+ }
+
if (state->flags & RADV_META_SAVE_COMPUTE_PIPELINE) {
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
VK_PIPELINE_BIND_POINT_COMPUTE,
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 4a7c37be9b3..66c8df6b9e9 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -39,6 +39,7 @@ enum radv_meta_save_flags {
RADV_META_SAVE_DESCRIPTORS = (1 << 2),
RADV_META_SAVE_GRAPHICS_PIPELINE = (1 << 3),
RADV_META_SAVE_COMPUTE_PIPELINE = (1 << 4),
+ RADV_META_SAVE_SAMPLE_LOCATIONS = (1 << 5),
};
struct radv_meta_saved_state {
@@ -48,6 +49,7 @@ struct radv_meta_saved_state {
struct radv_pipeline *old_pipeline;
struct radv_viewport_state viewport;
struct radv_scissor_state scissor;
+ struct radv_sample_locations_state sample_location;
char push_constants[128];
--
2.21.0
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[Mesa-dev] [PATCH] Revert "radv: fix color conversions for normalized uint/sint formats"
For some reasons, this actually introduced rendering issues with
Far Cry 3 (and probably Far Cry 4). I'm reverting it for now
until I figure out the right fix.
See the following link for reference:
https://github.com/ValveSoftware/Proton/issues/727#issuecomment-498638025
Cc: 19.0 19.1
This reverts commit e03e7c510f571a8867ab7a8604058c075c601a70.
---
src/amd/vulkan/radv_formats.c | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index d7b560082f6..0434c0641d8 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -1034,22 +1034,10 @@ bool radv_format_pack_clear_color(VkFormat format,
assert(channel->size == 8);
v =
util_format_linear_float_to_srgb_8unorm(value->float32[c]);
- } else {
- float f = MIN2(value->float32[c], 1.0f);
-
- if (channel->type == VK_FORMAT_TYPE_UNSIGNED) {
- f = MAX2(f, 0.0f) * ((1ULL <<
channel->size) - 1);
- } else {
- f = MAX2(f, -1.0f) * ((1ULL <<
(channel->size - 1)) - 1);
- }
-
- /* The hardware rounds before conversion. */
- if (f > 0)
- f += 0.5f;
- else
- f -= 0.5f;
-
- v = (uint64_t)f;
+ } else if (channel->type == VK_FORMAT_TYPE_UNSIGNED) {
+ v = MAX2(MIN2(value->float32[c], 1.0f), 0.0f) *
((1ULL << channel->size) - 1);
+ } else {
+ v = MAX2(MIN2(value->float32[c], 1.0f), -1.0f)
* ((1ULL << (channel->size - 1)) - 1);
}
} else if (channel->type == VK_FORMAT_TYPE_FLOAT) {
if (channel->size == 32) {
--
2.21.0
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[Mesa-dev] [Bug 110811] radv: Assassin's Creed Unity glitches when compiled with recent LLVM 9 (DXVK)
https://bugs.freedesktop.org/show_bug.cgi?id=110811 --- Comment #6 from Andrew Sheldon --- (In reply to Samuel Pitoiset from comment #5) > Does https://reviews.llvm.org/D62614 help? No change, unfortunately. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110815] Segfault vkCreateDescriptorPool in The-Forge on RADV
https://bugs.freedesktop.org/show_bug.cgi?id=110815 --- Comment #7 from Alex Fuller --- Hello again, I didn't realise it was so simple to build debug versions of Mesa/RADV so I went ahead and did this. I've found the bug: https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/amd/vulkan/radv_descriptor_set.c#L656 It is due to RADV not anticipating VK_DESCRIPTOR_TYPE_ACCELERATION_STRUCTURE_NV which makes sense. I put a bug report onto The-Forge about it, as I doubt there would be a clean way to fix this on RADV. I'll leave this bug open if you think otherwise. Cheers! -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] panfrost: bifrost: Fix format string in disassembler
Awesome, thanks for the fix.
Reviewed-By: Ryan Houdek
On Tue, Jun 4, 2019 at 11:55 PM Tomeu Vizoso
wrote:
> The compiler configuration was hardened to fail on format warnings and
> things stopped building.
>
> Fixes: c9c1e2610647 ("mesa: prevent common string formatting security
> issues")
> Signed-off-by: Tomeu Vizoso
> ---
> src/gallium/drivers/panfrost/bifrost/disassemble.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/panfrost/bifrost/disassemble.c
> b/src/gallium/drivers/panfrost/bifrost/disassemble.c
> index daadf2578965..03ade19a689d 100644
> --- a/src/gallium/drivers/panfrost/bifrost/disassemble.c
> +++ b/src/gallium/drivers/panfrost/bifrost/disassemble.c
> @@ -2195,7 +2195,7 @@ bool dump_clause(uint32_t *words, unsigned *size,
> unsigned offset, bool verbose)
>
> if (verbose) {
> for (unsigned i = 0; i < num_consts; i++) {
> -printf("# const%d: %08lx\n", 2 * i, consts[i] &
> 0x);
> +printf("# const%d: %08" PRIx64 "\n", 2 * i,
> consts[i] & 0x);
> printf("# const%d: %08" PRIx64 "\n", 2 * i + 1,
> consts[i] >> 32);
> }
> }
> --
> 2.20.1
>
>
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[Mesa-dev] [PATCH] panfrost: Don't flip scanout
The mesa/st flips the viewport, so we respect that rather than
trying to flip the framebuffer itself and ignoring the viewport and
using a messy heuristic.
However, this brings an underlying disagreement about the interpretation
of winding order to light. The blob uses a different strategy than Mesa
for handling viewport Y flipping, so the meanings of the winding order
bit are flipped for it. To keep things clean on our end, we rename to
explicitly use Gallium (rather than flipped OpenGL) conventions.
Fixes upside-down Xwayland/egl windows.
v2: Adjust lowering configuration to correctly flip gl_PointCoord.y and
gl_FragCoord.y.
Suggested-by: Rob Clark
Signed-off-by: Alyssa Rosenzweig
Cc: Tomeu Vizoso
---
.../drivers/panfrost/include/panfrost-job.h | 8 +--
.../panfrost/midgard/midgard_compile.h| 2 +
src/gallium/drivers/panfrost/pan_context.c| 54 +++
src/gallium/drivers/panfrost/pan_context.h| 7 +--
src/gallium/drivers/panfrost/pan_fragment.c | 7 +--
src/gallium/drivers/panfrost/pan_mfbd.c | 16 ++
src/gallium/drivers/panfrost/pan_screen.c | 6 ++-
src/gallium/drivers/panfrost/pan_sfbd.c | 17 ++
.../drivers/panfrost/pandecode/decode.c | 12 ++---
9 files changed, 47 insertions(+), 82 deletions(-)
diff --git a/src/gallium/drivers/panfrost/include/panfrost-job.h
b/src/gallium/drivers/panfrost/include/panfrost-job.h
index f4f145890de..8a4a7644070 100644
--- a/src/gallium/drivers/panfrost/include/panfrost-job.h
+++ b/src/gallium/drivers/panfrost/include/panfrost-job.h
@@ -73,9 +73,11 @@ enum mali_draw_mode {
#define MALI_OCCLUSION_QUERY(1 << 3)
#define MALI_OCCLUSION_PRECISE (1 << 4)
-#define MALI_FRONT_FACE(v) (v << 5)
-#define MALI_CCW (0)
-#define MALI_CW (1)
+/* Set for a glFrontFace(GL_CCW) in a Y=0=TOP coordinate system (like Gallium).
+ * In OpenGL, this would corresponds to glFrontFace(GL_CW). Mesa and the blob
+ * disagree about how to do viewport flipping, so the blob actually sets this
+ * for GL_CW but then has a negative viewport stride */
+#define MALI_FRONT_CCW_TOP (1 << 5)
#define MALI_CULL_FACE_FRONT(1 << 6)
#define MALI_CULL_FACE_BACK (1 << 7)
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.h
b/src/gallium/drivers/panfrost/midgard/midgard_compile.h
index 6f02b3662f6..9e6ac02f84f 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.h
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.h
@@ -99,6 +99,8 @@ static const nir_shader_compiler_options midgard_nir_options
= {
.lower_fpow = true,
.lower_find_lsb = true,
+.lower_wpos_pntc = true,
+
/* TODO: We have native ops to help here, which we'll want to look into
* eventually */
.lower_fsign = true,
diff --git a/src/gallium/drivers/panfrost/pan_context.c
b/src/gallium/drivers/panfrost/pan_context.c
index 6dab13de1f2..337faaca0f7 100644
--- a/src/gallium/drivers/panfrost/pan_context.c
+++ b/src/gallium/drivers/panfrost/pan_context.c
@@ -1174,15 +1174,6 @@ panfrost_emit_for_draw(struct panfrost_context *ctx,
bool with_vertex_data)
const struct pipe_viewport_state *vp = >pipe_viewport;
-/* For flipped-Y buffers (signaled by negative scale), the translate is
- * flipped as well */
-
-bool invert_y = vp->scale[1] < 0.0;
-float translate_y = vp->translate[1];
-
-if (invert_y)
-translate_y = ctx->pipe_framebuffer.height - translate_y;
-
for (int i = 0; i <= PIPE_SHADER_FRAGMENT; ++i) {
struct panfrost_constant_buffer *buf =
>constant_buffer[i];
@@ -1202,11 +1193,11 @@ panfrost_emit_for_draw(struct panfrost_context *ctx,
bool with_vertex_data)
if (sysval == PAN_SYSVAL_VIEWPORT_SCALE) {
uniforms[4*i + 0] = vp->scale[0];
-uniforms[4*i + 1] = fabsf(vp->scale[1]);
+uniforms[4*i + 1] = vp->scale[1];
uniforms[4*i + 2] = vp->scale[2];
} else if (sysval == PAN_SYSVAL_VIEWPORT_OFFSET) {
uniforms[4*i + 0] = vp->translate[0];
-uniforms[4*i + 1] = translate_y;
+uniforms[4*i + 1] = vp->translate[1];
uniforms[4*i + 2] = vp->translate[2];
} else {
assert(0);
@@ -1276,24 +1267,28 @@ panfrost_emit_for_draw(struct panfrost_context *ctx,
bool with_vertex_data)
view.viewport0[0] = (int) (vp->translate[0] - vp->scale[0]);
view.viewport1[0] = MALI_POSITIVE((int) (vp->translate[0] +
vp->scale[0]));
-view.viewport0[1] = (int) (translate_y - fabs(vp->scale[1]));
-view.viewport1[1] = MALI_POSITIVE((int) (translate_y +
fabs(vp->scale[1])));
+int miny = (int)
[Mesa-dev] [PATCH] panfrost: bifrost: Fix format string in disassembler
The compiler configuration was hardened to fail on format warnings and
things stopped building.
Fixes: c9c1e2610647 ("mesa: prevent common string formatting security issues")
Signed-off-by: Tomeu Vizoso
---
src/gallium/drivers/panfrost/bifrost/disassemble.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/panfrost/bifrost/disassemble.c
b/src/gallium/drivers/panfrost/bifrost/disassemble.c
index daadf2578965..03ade19a689d 100644
--- a/src/gallium/drivers/panfrost/bifrost/disassemble.c
+++ b/src/gallium/drivers/panfrost/bifrost/disassemble.c
@@ -2195,7 +2195,7 @@ bool dump_clause(uint32_t *words, unsigned *size,
unsigned offset, bool verbose)
if (verbose) {
for (unsigned i = 0; i < num_consts; i++) {
-printf("# const%d: %08lx\n", 2 * i, consts[i] &
0x);
+printf("# const%d: %08" PRIx64 "\n", 2 * i, consts[i]
& 0x);
printf("# const%d: %08" PRIx64 "\n", 2 * i + 1,
consts[i] >> 32);
}
}
--
2.20.1
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