You're right, that looks completely bogus.
I only have compiler tests and eyeballs for the shadow variants at
this point -- I'll sort that out :)
-- Chris
On Fri, Oct 11, 2013 at 9:33 AM, Eric Anholt e...@anholt.net wrote:
Chris Forbes chr...@ijw.co.nz writes:
gather4_c's argument layout
Yes; fortunately we don't have to support offset and shadow together on them.
On Fri, Oct 11, 2013 at 10:13 AM, Eric Anholt e...@anholt.net wrote:
Chris Forbes chr...@ijw.co.nz writes:
The 1D array case doesn't actually exist -- there is no 1D texture
support for gather.
For 2D arrays
- gsampler2DRect
- optional `comp` parameter
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/builtin_functions.cpp | 16
1 file changed, 16 insertions(+)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index d40888d..aa40876 100644
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 45 ++--
1 file changed, 42 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index
This series adds support for the following textureGather* enhancements
that are part of ARB_gpu_shader5:
- new textureGatherOffset variants
- nonconstant offset for all textureGatherOffset variants, when GLSL 4.00 or
ARB_gpu_shader5 is in use. If only ARB_texture_gather is enabled, const
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 0cf8277
Prior to ARB_gpu_shader5 / GLSL 4.0, the offset is required to be
a constant expression.
With that extension, it is relaxed to be any dynamically uniform
expression. If the value is not dynamically uniform, the results
are undefined.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 61c4bf5..19500d1 100644
--- a/src/mesa/drivers/dri/i965
The generator code ends up clearer this way than if we had to sniff
via mlen. Implemented via the gather4_po message in hardware, which is
present in Gen7 and later.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
src/mesa/drivers/dri/i965
Some texturing ops are about to have nonconstant offset support; the
offset in the header in these cases should be zero.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers
The commit message is wrong -- there is no requirement for the offset
to be dynamically uniform, either in the spec or in the i965
implementation in later patches.
On Tue, Oct 8, 2013 at 10:34 PM, Chris Forbes chr...@ijw.co.nz wrote:
Prior to ARB_gpu_shader5 / GLSL 4.0, the offset is required
Sorry, that was a bit sloppy on my part..
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Wed, Oct 9, 2013 at 10:00 AM, Eric Anholt e...@anholt.net wrote:
---
src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965
I haven't tested this thoroughly, but this is how it looks like
it ought to work from the PRM.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/gen7_wm_state.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 80073cd..7ddeb6e 100644
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 52076f7..6f024b4 100644
--- a/src/mesa/drivers/dri
Eek -- so I am. Thanks for spotting this.
On Sat, Oct 5, 2013 at 8:07 PM, Christoph Brill egore...@egore911.de wrote:
2013/10/5 Chris Forbes chr...@ijw.co.nz
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 15 ++-
1 file changed
This series adds some of the new textureGather variants from ARB_gpu_shader5,
and implementation for i965 Gen7+.
- Use with gsampler2DRect
- Component select in the shader
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
ARB_gpu_shader5 introduces new variants of textureGather* which have an
explicit component selector, rather than relying purely on the sampler's
swizzle state.
This patch adds the GLSL plumbing for the extra parameter.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl
- gsampler2DRect support
- optional `comp` parameter
Future patches will add shadow sampler support and
textureGatherOffsets().
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/builtin_functions.cpp | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff
-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 6141009..5508cdc 100644
--- a/src
-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 224524e..4307125 100644
As of ARB_gpu_shader5, textureGather doesn't always read the
post-swizzle RED channel -- so we can't just look at the red swizzle
state.
Theoretically we could only flag the quirk if *some* green swizzle is in
use, but that's probably more trouble than it's worth.
Signed-off-by: Chris Forbes chr
Yes, that's clearer; what I had was a strange artifact of how it grew :)
-- Chris
On Sun, Oct 6, 2013 at 6:54 AM, Kenneth Graunke kenn...@whitecape.org wrote:
On 10/05/2013 03:38 AM, Chris Forbes wrote:
ARB_gpu_shader5 introduces new variants of textureGather* which have an
explicit component
...@whitecape.org wrote:
On 10/05/2013 03:38 AM, Chris Forbes wrote:
- For HSW: Select the channel based on the component selected (swizzle
is done in HW)
- For IVB: Select the channel based on the swizzle state for the
component selected. Only apply the RG32F w/a if we actually want
green -- we're
This series adds support for ARB_texture_query_levels on i965 Gen6+. The fourth
channel of the resinfo message (used for textureSize()) includes the correct
value for textureQueryLevels().
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/extensions.c | 1 +
src/mesa/main/mtypes.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index c0f17c5..2507fdf 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/builtin_functions.cpp | 56 +
src/glsl/glcpp/glcpp-parse.y| 3 ++
src/glsl/glsl_parser_extras.cpp | 1 +
src/glsl/glsl_parser_extras.h | 2 ++
src/glsl/ir.cpp
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index a8ad659
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 9e6cc78
Theoretically would work on Gen5 as well but requires GLSL 1.30, which
is not (yet) enabled by default there.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965
Hi Paul,
Sorry, I should have run make check first.
I'll fix this when I get home.
-- Chris
On Thu, Oct 3, 2013 at 1:06 PM, Paul Berry stereotype...@gmail.com wrote:
On 30 September 2013 03:08, Chris Forbes chr...@ijw.co.nz wrote:
From: Maxence Le Dore maxence.led...@gmail.com
Reviewed
Clean up inconsistency in enum decoration:
- Use the undecorated enums where possible.
- MAX_PROGRAM_TEXTURE_GATHER_COMPONENTS_ARB remains decorated, since it
has no undecorated equivalent in GL4.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mapi/glapi/gen/ARB_texture_gather.xml | 6
With those fixes:
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Wed, Oct 2, 2013 at 6:38 AM, Ian Romanick i...@freedesktop.org wrote:
On 09/30/2013 10:54 PM, Chia-I Wu wrote:
From: Chia-I Wu o...@lunarg.com
I agree with both of Ken's comments. With those fixed, this patch is
Reviewed
Acked-by: Chris Forbes chr...@ijw.co.nz
On Wed, Oct 2, 2013 at 8:38 AM, Paul Berry stereotype...@gmail.com wrote:
Previously, we computed dFdy() using the following instruction:
add(8) dst1F src4,4,0)F -src.24,4,0F { align1 1Q }
That had the disadvantage that it computed the same value
We have the destination framebuffer object passed in; there's no need to
go digging around in the context.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers
cube
arrays in the VS.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Cc: 9.2 mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/brw_cubemap_normalize.cpp | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cubemap_normalize.cpp
b
This series adds support for ARB_texture_gather in core mesa and in i965 for
Gen7+.
Notable changes from V3:
- Only emit extra surface state, recompiles, etc if the shader actually uses
gather4.
- Use SCS to accomplish the workaround on Haswell [will need testing]
Cc: Kenneth Graunke
From: Maxence Le Dore maxence.led...@gmail.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mapi/glapi/gen/ARB_texture_gather.xml | 14 ++
src/mapi/glapi/gen/gl_API.xml | 2 +-
src/mesa/main/context.c | 4
src/mesa/main/extensions.c
From: Maxence Le Dore maxence.led...@gmail.com
V2 [Chris Forbes]:
- Add new pattern, fixup parameter reading.
V3: Rebase onto new builtins machinery
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/builtin_functions.cpp | 35 +++
src/glsl
Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and
low-level support for emitting it via generate_tex().
V3: Updated for changes in master.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_defines.h
), and then don't do
anything afterward in the shader.
* For 0/1 swizzles blast the appropriate constant over all the output
channels instead of sampling.
V2: Avoid duplicating header enabling block
V3: Avoid sampling at all, for degenerate swizzles.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Pretty much the same as the FS case. Channel select goes in the header,
V2: Less mangling.
V3: Avoid sampling at all, for degenerate swizzles.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
---
src/glsl/ir_set_program_inouts.cpp | 9 +
src/mesa/main/mtypes.h | 2 ++
2 files changed, 11 insertions(+)
diff --git a/src/glsl/ir_set_program_inouts.cpp
b/src/glsl/ir_set_program_inouts.cpp
index 1267d6d..ab23538 100644
--- a/src/glsl/ir_set_program_inouts.cpp
+++
V4: Only flag quirks if there are any uses of gather in the shader,
to avoid spurious recompiles just because someone happened to use
RG32F.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4
src/mesa/drivers/dri/i965/brw_program.h
gather4 GREEN channel against a surface with format R32G32_FLOAT doesn't work
correctly on IVB. w/a from bspec:
- use R32G32_FLOAT_LD = 0x97 instead, for gather4 only.
- select BLUE channel to read GREEN
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965
Worst-case is that *every* texunit uses a format that needs overriding.
V4: Place the gather slots last, so shaders which don't use gather don't
get penalized by having a huge binding table.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_context.h | 20
what w/a to apply.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_context.h | 3 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 38 +++
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 6 +++-
3 files changed, 39
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_context.c | 1 +
src/mesa/drivers/dri/i965/intel_extensions.c | 4
2 files changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 8 ++--
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 8 ++--
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa
The new surface channel select bits allow us to avoid having to
recompile the shader for this workaround.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_wm.c| 5 +++--
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 14 --
2 files
Fixed and landed on master now.
On Mon, Sep 23, 2013 at 8:05 AM, Eric Anholt e...@anholt.net wrote:
Chris Forbes chr...@ijw.co.nz writes:
Hardware requires the magnitude of the largest component to not exceed
1; brw_cubemap_normalize ensures that this is the case.
Unfortunately, we would
This is useful when working on the drivers, since falling back to
indirect rendering means we broke our driver's ability to load somehow.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
docs/envvars.html | 1 +
src/glx/glxext.c | 10 --
2 files changed, 9 insertions(+), 2 deletions
This series adds support for ARB_texture_gather.
Patches 1-2 add the core mesa and GLSL compiler scaffolding for the extension;
Patches 3-5 add basic support to the i965 driver;
Patches 6-10 work around a hardware bug which causes incorrect sampling of
R32G32_FLOAT surfaces;
Patch 11 turns
From: Maxence Le Dore maxence.led...@gmail.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mapi/glapi/gen/ARB_texture_gather.xml | 14 ++
src/mapi/glapi/gen/gl_API.xml | 2 +-
src/mesa/main/context.c | 4
src/mesa/main/extensions.c
From: Maxence Le Dore maxence.led...@gmail.com
V2 [Chris Forbes]:
- Add new pattern, fixup parameter reading.
V3: Rebase onto new builtins machinery
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/builtin_functions.cpp | 35 +++
src/glsl
Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and
low-level support for emitting it via generate_tex().
V3: Updated for changes in master.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_defines.h
), and then don't do
anything afterward in the shader.
* For 0/1 swizzles blast the appropriate constant over all the output
channels instead of sampling.
V2: Avoid duplicating header enabling block
V3: Avoid sampling at all, for degenerate swizzles.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Pretty much the same as the FS case. Channel select goes in the header,
V2: Less mangling.
V3: Avoid sampling at all, for degenerate swizzles.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4
src/mesa/drivers/dri/i965/brw_program.h| 5 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 4
src/mesa/drivers/dri/i965/brw_wm.c | 9 +
4 files
gather4 GREEN channel against a surface with format R32G32_FLOAT doesn't work
correctly on IVB. w/a from bspec:
- use R32G32_FLOAT_LD = 0x97 instead, for gather4 only.
- select BLUE channel to read GREEN
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 8 ++--
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 8 ++--
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
b/src/mesa/drivers/dri
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_context.c | 1 +
src/mesa/drivers/dri/i965/intel_extensions.c | 4
2 files changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index
adjusted to provoke this behavior.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Cc: 9.2 mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/brw_cubemap_normalize.cpp | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
Can we make this approximation conditional on an image-quality control
in driconf [or somewhere else]?
On Thu, Sep 12, 2013 at 5:00 PM, Chia-I Wu olva...@gmail.com wrote:
From: Chia-I Wu o...@lunarg.com
Replicate the gradient of the top-left pixel to the other three pixels in the
subspan, as
. In a *very* quick look I haven't found
anything equivalent -- but I might just be being blind.
CC'ing Ian -- any opinion? Is there any conformance issue here?
-- Chris
On Thu, Sep 12, 2013 at 8:41 PM, Chia-I Wu olva...@gmail.com wrote:
On Thu, Sep 12, 2013 at 2:06 PM, Chris Forbes chr...@ijw.co.nz
Sounds good to me.
On Fri, Sep 13, 2013 at 3:11 PM, Chia-I Wu olva...@gmail.com wrote:
On Thu, Sep 12, 2013 at 10:48 PM, Ian Romanick i...@freedesktop.org wrote:
On 09/12/2013 01:06 AM, Chris Forbes wrote:
Can we make this approximation conditional on an image-quality control
in driconf
This is a fair bit saner :)
For the series:
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Tue, Sep 10, 2013 at 11:00 AM, Kenneth Graunke kenn...@whitecape.org wrote:
We can easily compute these without loops, resulting in simpler and
shorter code.
Signed-off-by: Kenneth Graunke kenn
.
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Tue, Sep 10, 2013 at 6:38 AM, Kenneth Graunke kenn...@whitecape.org wrote:
Otherwise, coordinates with four components would result in a MOV
with a destination writemask that has no channels enabled:
mov(8) g1151.F 0D { align16 WE_normal NoDDChk 1Q
In the commit message:
Fortunately, OpenGL only requires separate streams to be supported
when the output type is points, and EndPrimitive() only has an effect
when the input type is line_strip or triangle_strip, so it's not a...
Shouldn't this say 'output type' ?
-- Chris
On Tue, Sep 10,
A possible explanation for the perf change is that Xonotic uses
anisotropic filtering at this quality level. Lowering to txl defeats
it.
It would be worth doing an image quality comparison before and after the change.
-- Chris
On Thu, Sep 5, 2013 at 8:35 PM, Chia-I Wu olva...@gmail.com wrote:
For the series,
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Thu, Sep 5, 2013 at 6:29 AM, Ian Romanick i...@freedesktop.org wrote:
From: Ian Romanick ian.d.roman...@intel.com
The change is very small. Do seamless filtering if either the context
enable is set or the sampler enable is set
Fixes broken rendering if these MRFs contained anything other than zero.
NOTE: This is a candidate for stable branches.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/mesa
Sorry, saw the bogus comment style just after I sent this out.
-- Chris
On Tue, Aug 27, 2013 at 9:45 PM, Chris Forbes chr...@ijw.co.nz wrote:
Fixes broken rendering if these MRFs contained anything other than zero.
NOTE: This is a candidate for stable branches.
Signed-off-by: Chris Forbes
It's just a simple, portable way to make the `unused parameter`
warning shut up, when you're deliberately ignoring your parameters.
There are other ways [__attribute__(( unused )), etc] but they cease
to be simple or portable fairly quickly.
-- Chris
On Mon, Aug 26, 2013 at 5:07 PM, Liu Xin
Ken,
I think the big win from using pass-by-pointer is that you can see
what's happening at the call site. References' value syntax and
pointer semantics is a weird mix.
But that might just be the C programmer talking, as you suggested.
-- Chris
___
This series adds support for GLSL-1.30 clip distances on Gen4/5, and
extends max clip planes to match the 1.30 requirement on Cantiga and later.
Passes 2000/2004 glsl-1.30 piglits on Ironlake. The missing 4 tests here are
bugs in handling unusual `switch` control flow, and affect all gens.
V2: We don't particularly care where they fall in the VUE map, as long
as they are allocated somewhere, and occupy two contiguous slots. Don't
fiddle with the SF layout at all -- there's no need.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vs.c | 5 +
1
We need to produce clip flags for the vertex header on Gen4/5, so
clip plane lowering has to be done before we try to emit the flags/psiz
attribute.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_vec4.h
Previously we had disabled interpolation of the clip distances as a
special case, since they were unused.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_clip_util.c | 10 +++---
1 file changed, 3 insertions(+), 7
Splits the bottom 8 bits of f0.0 for further wrangling
in a SIMD4x2 program. The 4 bits corresponding to the channels in each
program flow are copied to the LSBs of dst.x visible to each flow.
This is useful for working with clipping flags in the VS.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index f80777b
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_clip.h | 3 +++
src/mesa/drivers/dri/i965/brw_clip_tri.c | 9 +
2 files changed, 12 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_clip.h
b/src
Soon the dp4 is only going to be used for fixed clip planes.
V2: Remove old inaccurate comment about the behavior of this function;
add a better explanation above.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965
V2: Adjust explanation of load_clip_distance()
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_clip_tri.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
Nothing in the clipper uses gl_ClipVertex any more, so we don't care
where it is.
V2: Don't bother fishing out the clipvertex offset either.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_clip_tri.c | 15
This does the same thing as we do for triangle clipping -- select the
appropriate source (either dot(hpos,fixed plane) or a clipdistance
slot).
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_clip_line.c | 66 ++-
1 file changed, 47
---
src/mesa/drivers/dri/i965/brw_clip.c | 3 +-
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 40 +-
src/mesa/drivers/dri/i965/brw_vs.c | 14 ++---
src/mesa/drivers/dri/i965/brw_vs.h | 9 --
4 files changed, 11 insertions(+),
.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_clip.h | 6 +-
src/mesa/drivers/dri/i965/brw_clip_state.c | 8 +++-
src/mesa/drivers/dri/i965/brw_clip_tri.c | 4 ++--
src/mesa/drivers/dri/i965
You're right, that's completely bogus, and I meant to read the flags instead.
Thanks :)
On Tue, Aug 6, 2013 at 9:09 AM, Paul Berry stereotype...@gmail.com wrote:
On 3 August 2013 19:59, Chris Forbes chr...@ijw.co.nz wrote:
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers
This is what I started with, but brw_ENDIF destroys the flags.
On Tue, Aug 6, 2013 at 9:40 AM, Paul Berry stereotype...@gmail.com wrote:
On 3 August 2013 19:59, Chris Forbes chr...@ijw.co.nz wrote:
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_clip_tri.c | 7
Actually, that justification sounds like nonsense after thinking about
it a bit more -- we're in SPF mode.
On Tue, Aug 6, 2013 at 9:47 AM, Chris Forbes chr...@ijw.co.nz wrote:
This is what I started with, but brw_ENDIF destroys the flags.
On Tue, Aug 6, 2013 at 9:40 AM, Paul Berry stereotype
Forbes chr...@ijw.co.nz wrote:
Also adjust the SF URB read offset to account for there being two
additional slots of stuff it doesn't care about.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_sf.h | 2 +-
src/mesa/drivers/dri/i965/brw_vs.c | 2 ++
2 files
This does the same thing as we do for triangle clipping -- select the
appropriate source (either dot(hpos,fixed plane) or a clipdistance
slot).
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_clip_line.c | 66 ++-
1 file changed, 47
Turns out this patch is rubbish, and only fixes the layout for the
interpolation tests at the cost of breaking a bunch of other stuff.
-- Chris
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mesa-dev mailing list
mesa-dev@lists.freedesktop.org
INTEL_DEBUG=vue now emits a listing of each slot in the VUE map,
and the corresponding interpolation mode.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_interpolation_map.c | 28 +++
src/mesa/drivers/dri/i965/intel_context.c | 1
Makes this flag appear in the output for INTEL_DEBUG=state
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_state_upload.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
b/src/mesa/drivers/dri/i965
This series adds support for GLSL-1.30-style clipping using gl_ClipDistance on
Gen4/5.
All of the interpolation piglits now pass, but there are still a couple of
things I need to do:
* Get rid of clip plane compaction
* Add similar support for clipping lines
There's no need to use a clip flag for NEGW on these gens, so
no reason we can't just enable 8 planes.
V2: Bump (and document!) MAX_VERTS in the clip code.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_clip.h | 6 +-
src/mesa/drivers/dri/i965
The SF never gets to see the clip distances. If we didn't ignore them
here, we got confused about the correct offsets for any varyings laid
out after them. (user-defined varyings would break, but gl_FrontColor
etc worked properly).
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa
Also adjust the SF URB read offset to account for there being two
additional slots of stuff it doesn't care about.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_sf.h | 2 +-
src/mesa/drivers/dri/i965/brw_vs.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion
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