In order to reduce later churn, move a few parameters from the general
brw_context into the intel_batchbuffer.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 20 ++
src/mesa/drivers/dri/i965/brw_blorp.cpp | 2 +-
src/mesa/drivers/dri/i965
Since we always flush the intel_batchbuffer before calling
intel_front_flush(), simply more that call into intel_front_flush()
itself.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_context.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/src/mesa
adderss into the state with a convenient helper.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 22 +++
src/mesa/drivers/dri/i965/brw_cc.c| 15 ++---
src/mesa/drivers/dri/i965/brw_clip_state.c| 14 ++---
src/mesa/drivers/dri/i965
Provide a common routine for doing conditional batch flushes.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 6 ++
src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 +--
src/mesa/drivers/dri/i965/brw_compute.c | 3 +--
src/mesa/drivers/dri/i965/brw_draw.c| 3 +--
4
Simple rename and parameter passing changes now to avoid doing so inside
a much larger patch.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 5 +
src/mesa/drivers/dri/i965/brw_context.c | 3 ++-
src/mesa/drivers/dri/i965/brw_context.h | 2
situation.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_structs.h | 33 +++--
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h
b/src/mesa/drivers/dri/i965/brw_structs.h
index 55338c0..b09d4ba 100644
In preparation for the next patch, just transplant some functions
between header files.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 41 +++
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 40 --
2 files changed
No external users, so no need to export the symbol outside of our
compilation unit.
Signed-off-by: Chris Wilson
Reviewed-by: Kenneth Graunke
Reviewed-by: Martin Peres
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 56 +--
src/mesa/drivers/dri/i965
Rather than spend an instruction deciding whether we need to, just zero
out the single integer to reset the HW binding tables.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 6 --
src/mesa/drivers/dri/i965/brw_context.c| 3 +--
src/mesa/drivers/dri
Refactor the aperture test, roll back and retry logic to a common idiom.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 9 +
src/mesa/drivers/dri/i965/brw_blorp.cpp | 43 +--
src/mesa/drivers/dri/i965/brw_compute.c | 39
Just to ease the next intermediate patch.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 1 +
src/mesa/drivers/dri/i965/brw_blorp.cpp| 10 +++---
src/mesa/drivers/dri/i965/brw_compute.c| 6 ++--
src/mesa/drivers/dri/i965/brw_draw.c
Since we can distinguish when mapping between READ and WRITE, we can
pass along the map mode to avoid stalls and flushes where possible.
Signed-off-by: Chris Wilson
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 28 ++-
1 file changed
Rather than split the render batch setup between two hooks, coalesce it
into a single callback. To simplify this, move some of the state
dirtying from the start to the finish hook hook.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 6 ++---
src/mesa/drivers
Process the postdraw resolves (including setting the buffer dirty flag)
before any conditional batch flush as that flush will want to clear the
dirty flag.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_draw.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff
To ease intermediate patches.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 2 ++
src/mesa/drivers/dri/i965/brw_compute.c | 4 ++--
src/mesa/drivers/dri/i965/brw_context.h | 1 -
src/mesa/drivers/dri/i965/brw_draw.c | 4 ++--
src/mesa
Simple non-functional change to ease later patches.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h | 22 ++
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 22 --
2 files changed, 22 insertions(+), 22 deletions(-)
diff
treat brw_performance_monitor.c
separately as it deserves more careful attention.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_conditional_render.c | 5 +
src/mesa/drivers/dri/i965/brw_queryobj.c | 15 +++
src/mesa/drivers/dri/i965/brw_state_upload.c
With mesa/drm commit cd2f91e18db087edf93fed828e568ee53b887860
Author: Kristian Høgsberg Kristensen
Date: Fri Jul 31 10:47:50 2015 -0700
intel: Drop aub dumping functionality
the drm_intel_aub routines are mere stubs and do nothing. Likewise
remove our invocations.
Signed-off-by: Chris
If we have to flush the batchbuffer early that has performance
implications, and if it is a result of user action we should report that
through the perf_debug interface.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.h| 3 ++
src/mesa/drivers/dri/i965
We have many flushes outside of the batch buffer critical sections that
need wrapping. Introduce a simple function to wrap the brw_emit_mi_flush()
with the begin/end.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_clear.c | 4 ++--
src/mesa/drivers/dri/i965
In order to reduce future churn, move the callbacks for starting and
finishing the batch from intel_batchbuffer to the brw_context.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_context.c | 84 +++
src/mesa/drivers/dri/i965/brw_context.h | 3
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_context.c | 1 -
src/mesa/drivers/dri/i965/brw_context.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index ad8ddee..117cce4 100644
--- a/src
oa_users into the critical sections.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_context.c| 3 ++
.../drivers/dri/i965/brw_performance_monitor.c | 38 ++
2 files changed, 20 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
Rather than allocating a fresh page every time we clear a buffer, keep
that page around between invocations by tracking the last used offset
and only allocating a fresh page when we wrap.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 17 ++---
1
Since we use fences internally for tracking buffer busyness within
brw_batch.c, we can expose those directly for GL/DRI2 sync objects.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.c | 41 +-
src/mesa/drivers/dri/i965/brw_batch.h | 23 +++-
src/mesa
Remove the old hashtable approach and switch over to the inline write
tracking with brw-batch.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.c| 71 +++-
src/mesa/drivers/dri/i965/brw_batch.h| 9 +---
src/mesa/drivers/dri/i965
Reuse the common upload bo for the temporary blitter storage to try and
minimise resource usage.
Caveats: this may impose a read-read relationship on the buffer between
the blitter and render engines, and may add stalls on old kernels.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 16 +---
src/mesa/drivers/dri/i965/brw_clear.c | 11 +--
src/mesa/drivers/dri/i965/brw_context.c | 4 +++-
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src
Since the purpose of transform feedback tends to be for the client to
act upon the results to change the geometry in the scene, it is likely
that the client will soon be waiting upon the results. Flush the batch
early so that we don't build up a long queue of commands afterwards that
could delay th
Avoid unrequired synchronization if the user requests to map an unused
range on active buffer, equivalent to BufferSubData.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 76 +---
1 file changed, 42 insertions(+), 34 deletions(-)
diff
On LLC, all buffers are normally cache coherent between the CPU and the
GPU, giving both parties fast access to shared data.
However, older architectures or Atoms, do not implement LLC between the
CPU and GPU. Instead they utilise a snooping architecture where the GPU
can snoop the CPU cache when
internal GPU state and also keep the explicit flush for operating on
random buffers (as we only track flushes required for certain sources
like the texture, if the user blits into a buffer bound elsewhere (like
the vertex buffer) we have to explicitly flush).
Signed-off-by: Chris Wilson
---
src/mesa
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c
b/src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c
index f13a8b7..4d1473a 100644
--- a/src
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index 2b18e2c..e0566b0 100644
lobal GTT workaround, essentially 2 bits of information. We can therefore
trim a parameter by coalescing the relocation domains to a single unsigned
bitfield (i.e. 32 bits of read/write domains rather than 64 bits) without
loss of generality.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri
may exceed the coordinate limit.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90734
Signed-off-by: Chris Wilson
Cc: Kenneth Graunke
Cc: Ian Romanick
Cc: Anuj Phogat
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/intel_blit.c | 72
The GL format/datatype for GL_DEPTH_STENCIL_EXT (GL_UNSIGNED_INT_24_8_EXT)
was lacking a translation to the internal MESA format (Z24_UNORM_S8_UINT),
and similarly for the packed floating point DEPTH_STENCIL.
Signed-off-by: Chris Wilson
---
src/mesa/main/glformats.c | 8
1 file changed
Similar to glReadPixels, using the GPU to blit back into the client's
buffer is preferrable to using a coherent mmaping (but not manual
detiling for several reasons).
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/intel_tex_image.c | 129
1 file ch
GL_DEPTH_COMPONENT and GL_STENCIL_INDEX are simple array formats of the
indiciated types, but were absent from the get_swizzle_from_format()
table causing them to be neglect and triggering
unreachable("Unsupported format").
Signed-off-by: Chris Wilson
---
src/mesa/main/glformats.c
erent mmapping.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/intel_pixel_read.c | 117 +++
1 file changed, 117 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c
b/src/mesa/drivers/dri/i965/intel_pixel_read.c
index 5765027..16a04fb 100644
We only need the batch promotion for secure dispatch if we need to
modify privileged registers, so only request it when we do register
loads and stores.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.c | 12 ++--
src/mesa/drivers/dri/i965/brw_batch.h
is suitable
for any general usage (e.g. vertex data, texture data) and so only on
LLC can we offer that extension.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.c| 36 +
src/mesa/drivers/dri/i965/brw_batch.h| 8 +
src/mesa
Since the introduction of reporting alphaless winsys buffers, the
GL_IMPLEMENTATION_COLOR_READ_FORMAT_OES query started reporting GL_RGBA
instead of the preferred GL_BGRA format (demos/readpix reports a
difference of almost 1000x for picking the wrong format).
Signed-off-by: Chris Wilson
desired
MESA_FORMAT_B8G8R8A8_UNORM format.
Signed-off-by: Chris Wilson
---
src/mesa/main/framebuffer.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index a34cefc..6ab88aa 100644
--- a/src/mesa/main
ead of the
queue and commiting it.
Thanks for the review and gentle poke.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
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mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
On Mon, Aug 10, 2015 at 10:40:29AM +0200, Daniel Vetter wrote:
> On Fri, Aug 07, 2015 at 09:14:01PM +0100, Chris Wilson wrote:
> > Reuse the common upload bo for the temporary blitter storage to try and
> > minimise resource usage.
> >
> > Caveats: this may impose a re
On Fri, Aug 07, 2015 at 09:13:06PM +0100, Chris Wilson wrote:
> GCC's read access for single bits in a bitfield is reasonable (just a
> move + flag comparison), so let's save some cachelines by packing the
> write-once/read-many booleans together.
>
>text dat
On Mon, Aug 10, 2015 at 02:25:41PM +0300, Martin Peres wrote:
> On 07/08/15 23:13, Chris Wilson wrote:
> >Since the workaround bo is used strictly as a write-only buffer, we need
> >only allocate one per screen and use the same one from all contexts.
> >
> >(The cave
used illegal commands. Fix the array
initialisation to be impervious to changes in the gl_shader_stages enum
and add the asserts that would have caught the issue earlier.
Signed-off-by: Chris Wilson
Cc: Abdiel Janulgue
Cc: Jordan Justen
Cc: Matt Turner
Cc: Kenneth Graunke
Reviewed-by: Matt
On Mon, Aug 10, 2015 at 12:49:47PM +0100, Chris Wilson wrote:
> Since the introduction of new gl_shader_stages in
>
> commit a2af956963b6bc4d29f37485e44c98008d2ef077
> Author: Fabian Bieler
> Date: Fri Mar 7 10:19:09 2014 +0100
>
> mesa: add tessellation shader enums
lla: https://bugs.freedesktop.org/show_bug.cgi?id=90264
Signed-off-by: Chris Wilson
Cc: Michel Dänzer
Cc: Kenneth Graunke
Cc: Brian Paul
Cc: Ian Romanick
---
src/glx/dri2_glx.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c
index 5767026..01b5c28 100644
---
On Mon, Aug 10, 2015 at 03:18:09PM +0300, Martin Peres wrote:
> On 07/08/15 23:13, Chris Wilson wrote:
> >intel_update_winsys_renderbuffer_miptree() will release the existing
> >miptree when wrapping a new DRI2 buffer, so we can remove the early
> >release and so prevent
On Mon, Aug 10, 2015 at 03:37:24PM +0300, Martin Peres wrote:
> 10-12 are:
>
> Reviewed-by: Martin Peres
One thing to consider, do we want to do a s/typedef/struct brw_batch/
cleanup after the transition is complete?
brw_batch vs struct brw_batch ?
brw_bo vs struct brw_bo ?
-Chris
r);
> >+ r += intel_detect_pipelined_oacontrol(screen, r);
>
> Not a fan of this construct. How about changing the return types of
> the detect functions to int?.
Do you mean
if (intel_detect_pipelined_so(screen, r))
r++;
or
int index = 0;
index +
On Mon, Aug 10, 2015 at 04:08:07PM +0300, Martin Peres wrote:
>
>
> On 10/08/15 16:00, Chris Wilson wrote:
> >On Mon, Aug 10, 2015 at 03:17:26PM +0300, Martin Peres wrote:
> >>>+static int
> >>>+intel_detect_pipeline
On Thu, Aug 13, 2015 at 09:58:52PM -0700, Kenneth Graunke wrote:
> On Thursday, August 13, 2015 02:57:20 PM Martin Peres wrote:
> > On 07/08/15 23:13, Chris Wilson wrote:
> > > intel_update_winsys_renderbuffer_miptree() will release the existing
> > > miptree when wrappi
post sync circles are complete before executing the
next commend" - the operative word being previous!
Signed-off-by: Chris Wilson
Cc: Neil Roberts
Cc: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_conditional_render.c | 6 ++
src/mesa/drivers/dri/i965/brw_queryobj.c
On Fri, Aug 21, 2015 at 04:14:25PM +0100, Chris Wilson wrote:
> The nv_conditional_render piglits were sporadically failing. Moving
> the control flush from the write and placing it just before the read
> was sufficient to make the piglits pass a 1000/1000 times. The bspec
> says th
cache at that point.
Reported-by: Tomasz C.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91254
Signed-off-by: Chris Wilson
Cc: Jordan Justen
Cc: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src
On Sun, Aug 23, 2015 at 12:37:09PM -0700, Jordan Justen wrote:
> Can you also cc mesa-stable in the commit message?
>
> Cc: "10.6 11.0"
Amendments made and pushed with Thomas' t-b.
Thanks,
-Chris
--
Chris Wilson, Intel Open
From: Jason Ekstrand
If the user is specifying a subregion of a buffer using SKIP_ROWS and
SKIP_PIXELS, we must compute the buffer size carefully as the end of the
last row may be much shorter than stride*image_height*depth. The current
code tries to memcpy from beyond the end of the user data, f
On Mon, Aug 31, 2015 at 02:47:48PM +0100, Chris Wilson wrote:
> From: Jason Ekstrand
Sorry for the confusion Jason, I was messing around with git trying to
reference the right commit easily.
-Chris
--
Chris Wilson, Intel Open Source Technology Cen
On Mon, Aug 31, 2015 at 10:29:51PM -0700, Jason Ekstrand wrote:
>On Aug 31, 2015 6:48 AM, "Chris Wilson" <[1]ch...@chris-wilson.co.uk>
>wrote:
>>
>> From: Jason Ekstrand <[2]jason.ekstr...@intel.com>
>>
>> If the user i
h because piglit tells me I can't just drop
full_height on the floor - as the teximage we create is meant to be
width x full_height x 1. Oops.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
mesa-dev mailing list
mesa-dev@lists.free
> sync is this broken.
Whilst you are looking at the strange mutex here, can I also tmept you
with
https://cgit.freedesktop.org/~ickle/mesa/commit/?h=fence&id=a50b7115defccfd8239eb39c23c7d7bce720eba7
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
__
is ordered after earlier pipe control writes.
Testcase: piglit/arb_query_buffer_object-qbo/*async*
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/gen6_queryobj.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c
APPLE when called with
glObjectUnpurgeable(GL_UNDEFINED_APPLE).
Testcase: piglit/object_purgeable-api-*
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_object_purgeable.c | 36 ++--
1 file changed, 27 insertions(+), 9 deletions(-)
diff --git a/src/mesa/driver
APPLE when called with
glObjectUnpurgeable(GL_UNDEFINED_APPLE).
Testcase: piglit/object_purgeable-api-*
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_object_purgeable.c | 36 ++--
1 file changed, 27 insertions(+), 9 deletions(-)
diff --git a/src/mesa/driver
On Sat, Aug 13, 2016 at 12:59:46PM +0100, Chris Wilson wrote:
> If the buffer has been freed by the kernel under memory pressure, it is
> invalid to try and access the backing storage for that buffer in the
> future - the backing storage is not recreated automatically. As such we
>
rime(image->bo, value) == 0)
> - return true;
> - return false;
> + return drm_intel_bo_gem_export_to_prime(image->bo, value) == 0;
Elsewhere in this block we have
return !drm_intel_bo_flink(image->bo, (uint32_t *)value);
so choose betwe
On Mon, Aug 15, 2016 at 03:51:21PM +0100, Eric Engestrom wrote:
> if (x) return true; else return false;
> can be simplified as:
> return x;
> since `x` is already a boolean expression.
>
> Signed-off-by: Eric Engestrom
Both Reviewed-by: Chris Wilson
-Chris
--
C
On Mon, Aug 17, 2015 at 03:17:30PM -0700, Eric Anholt wrote:
> Chris Wilson writes:
>
> > "X rendering calls made prior to glXWaitX are guaranteed to be
> > executed before GL rendering calls made after glXWaitX."
> >
> > The goal is to implement
able, before the backend will use the
surface (either as a texture or as a renderable) it will do a
DRI2GetBuffers() round trip. (It is also likely that the buffer will
have been invalidated in the meantime and alreadly pending the round
trip.) That provides the server with a definite point at which
On Wed, Aug 17, 2016 at 01:34:48PM -0400, Adam Jackson wrote:
> On Wed, 2016-08-17 at 17:50 +0100, Chris Wilson wrote:
> > On Wed, Aug 17, 2016 at 12:13:23PM -0400, Adam Jackson wrote:
> > >
> > > On Wed, 2016-08-17 at 08:17 -0700, Eric Anholt wrote:
> > >
On Wed, Aug 17, 2016 at 06:51:24PM +0100, Chris Wilson wrote:
> However, X will always send a fake front if the real front is requested,
> and the real front buffer is requested if either the read or write
> buffer is GL_FRONT. So the fake front copy should suffice to trigger the
> fl
Now that we have working partial VMA and faulting support for all
objects, including fence support, advertise to userspace that it can
take advantage of unlimited GGTT mmaps.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 8
include/uapi/drm/i915_drm.h | 1 +
2
From about kernel 4.9, GTT mmaps are virtually unlimited. A new
parameter, I915_PARAM_MMAP_GTT_VERSION, is added to advertise the
feature so query it and use it to avoid limiting tiled allocations to
only fit within the mappable aperture.
Signed-off-by: Chris Wilson
Cc: Kenneth Graunke
---
src
On Thu, Aug 25, 2016 at 11:00:54AM +0300, Joonas Lahtinen wrote:
> On ke, 2016-08-24 at 20:42 +0100, Chris Wilson wrote:
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -355,6 +355,14 @@ static int i915_getparam(struct drm_device *dev, void
> > *data,
> > cas
On Thu, Aug 25, 2016 at 01:43:53PM -0700, Ian Romanick wrote:
> On 08/24/2016 12:42 PM, Chris Wilson wrote:
> > +#define I915_PARAM_MMAP_GTT_VERSION 40 /* XXX delete me with new libdrm */
> > + if (intel_get_integer(intelScreen, I915_PARAM_MMAP_GTT_VERSION) >= 1) {
> >
and now we do a quick
probe from mesa and use the GL context everywhere, see kernel commit
f7978a0c581a ("drm/i915: Allow the user to pass a context to any ring")
Signed-off-by: Chris Wilson
Cc: Kenneth Graunke
Cc: Daniel Vetter
---
src/mesa/drivers/dri/i965/brw_context.c |
ll not be removed, especially
whitelisted registers, or that all platforms will implement the same set.
-Chris
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-off-by: Chris Wilson
---
include/GL/internal/dri_interface.h | 12 -
src/glx/dri2_glx.c | 16 ++--
src/mesa/drivers/dri/common/dri_util.c | 6 +
src/mesa/drivers/dri/common/dri_util.h | 4 +++
src/mesa/drivers/dri/i965/brw_context.c
the
texture-from-pixmap. This works in DRI2 as texture binding flushes the
rendering to the Pixmap.
Signed-off-by: Chris Wilson
---
src/loader/loader_dri3_helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
index
glXWaitX().
References: https://bugs.freedesktop.org/show_bug.cgi?id=97914
Signed-off-by: Chris Wilson
---
src/loader/loader_dri3_helper.c | 44 -
src/loader/loader_dri3_helper.h | 3 +++
2 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/src
On Tue, Oct 25, 2016 at 05:57:14PM +0200, Daniel Vetter wrote:
> On Wed, Oct 19, 2016 at 02:26:15PM -0700, Kenneth Graunke wrote:
> > On Wednesday, October 19, 2016 8:35:11 PM PDT Chris Wilson wrote:
> > > On Wed, Oct 19, 2016 at 12:25:51PM -0700, Kenneth Graunke wrote:
>
driver as a function parameter.
Issues:
* How to pass back the priority of the create context (as it may be
modified by the driver) back to EGL?
Signed-off-by: Chris Wilson
---
include/GL/internal/dri_interface.h| 6 +
src/egl/drivers/dri2/egl_dri2.c| 36
e!
Signed-off-by: Chris Wilson
---
src/egl/drivers/dri2/egl_dri2.c | 1 +
src/egl/main/eglapi.c | 2 ++
src/egl/main/eglcontext.c | 30 ++
src/egl/main/eglcontext.h | 1 +
src/egl/main/egldisplay.h | 2 ++
5 files changed, 36 insertion
Pass along the context priority provided through eglCreateContext to the
kernel, where it will be used for priority sorting of batches.
Signed-off-by: Chris Wilson
---
src/mesa/drivers/dri/i965/brw_batch.c | 43 -
src/mesa/drivers/dri/i965/brw_batch.h | 3
kernel. You already have the buffers
coherently mapped, the kernel doesn't, the kernel needs to copy the
entire relocation tree if even one relocation is wrong, etc.
> Signed-off-by: Jason Ekstrand
> Cc: Kristian Høgsberg
> Cc: Ben Widawsky
> Cc: Daniel Vetter
> Cc: Chri
On Tue, Nov 01, 2016 at 08:07:36AM +, Chris Wilson wrote:
> On Mon, Oct 31, 2016 at 09:48:15PM -0700, Jason Ekstrand wrote:
> > + * By doing relocations on the CPU, we can tell the kernel that it doesn't
> > + * need to bother. We want to do this because the sur
e next MSC, which is the commonly
expected behaviour of apps using glXSwapBuffers() when not overriding the
vblank_mode / swap_interval. To force the frame to be displayed on the
next vblank, we want to pass divisor 1 to the backend.
Signed-off-by: Chris Wilson
Cc: Adam Jackson
---
src/glx/glxcmds.c
On Tue, Nov 01, 2016 at 08:39:16AM -0700, Jason Ekstrand wrote:
>On Tue, Nov 1, 2016 at 1:07 AM, Chris Wilson <[1]ch...@chris-wilson.co.uk>
>wrote:
>
> On Mon, Oct 31, 2016 at 09:48:15PM -0700, Jason Ekstrand wrote:
> > From: Kristian Høgsbe
On Tue, Nov 01, 2016 at 12:58:22PM -0400, Adam Jackson wrote:
> On Sat, 2016-10-22 at 11:00 +0100, Chris Wilson wrote:
>
> > @@ -113,6 +113,11 @@ loader_dri3_drawable_fini(struct loader_dri3_drawable
> > *draw)
> > dri3_free_render_buff
Valgrind reports that we use cfg.cycle_count uninitialised, so zero the
cfg_t on construction.
Fixes: 52d2b28f7f10 ("ralloc: use rzalloc where it's necessary")
Signed-off-by: Chris Wilson
Cc: Kenneth Graunke
Cc: Marek Olšák
Cc: Edmondo Tommasina
Cc: Nicolai Hähnle
---
src/m
On Wed, Nov 02, 2016 at 12:14:32PM +0900, Michel Dänzer wrote:
> On 01/11/16 08:10 PM, Chris Wilson wrote:
> > glXSwapBuffers() is translated internally into glXSwapBuffersMsc() with
> > a target and divisor of 0.
> >
> > https://www.opengl.org/registry/spe
On Wed, Nov 02, 2016 at 10:09:26AM +0900, Michel Dänzer wrote:
> On 22/10/16 07:00 PM, Chris Wilson wrote:
> > This applies a synchronisation point to GetBuffers() such that binding a
> > texture-from-pixmap its rendering is serialised with X. This matches the
> > synchronisat
On Wed, Nov 02, 2016 at 04:16:55PM +0900, Michel Dänzer wrote:
> On 02/11/16 04:13 PM, Chris Wilson wrote:
> > On Wed, Nov 02, 2016 at 10:09:26AM +0900, Michel Dänzer wrote:
> >> On 22/10/16 07:00 PM, Chris Wilson wrote:
> >>> This applies a synchronisation point to
p;(*bbo)->relocs,
> + cmd_buffer->device, &(*bbo)->bo);
> + }
> +
> + for (uint32_t i = 0; i < cmd_buffer->execbuf2.bo_count; i++) {
> + struct anv_bo *bo = cmd_buffer->execbuf2.bos[i];
> +
> + cmd_buffer->execbuf2.objects[i].offset = bo->offset;
/* bo->offset = last execobj.offset */
*reloc.offset = bo->offset + delta;
reloc.presumed_offset = bo->offset;
execobj.offset = bo->offset;
Looks good.
-Chris
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_buffer->execbuf2.bos);
> + return anv_device_execbuf(device, &execbuf, cmd_buffer->execbuf2.bos);
> }
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index c40598c..a650212 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -1097,6 +1097,8 @@ VkResult anv_QueueSubmit(
> struct anv_device *device = queue->device;
> VkResult result = VK_SUCCESS;
/* Take a lock on all shared surface_state in order to perform relocations. */
> + pthread_mutex_lock(&device->mutex);
I think locking inside Vulkan is so rare, that it is worth explaining :)
-Chris
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if (time_elapsed > timeout) {
> + pthread_mutex_unlock(&device->mutex);
> + return VK_TIMEOUT;
> +}
> +
> +timeout -= time_elapsed;
Adjusts the bool and not the int64_t nanosecond counter.
Looks
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