Re: [Mesa-dev] [PATCH 2/2] i965/nir: Use nir_system_value_from_intrinsic to reduce duplication.

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Mon, 2015-09-07 at 00:30 -0700, Kenneth Graunke wrote: > This code is all pretty much identical. We just needed the translation > from one enum value to the other. > > Signed-off-by: Kenneth Graunke <kenn...@whitecape.o

Re: [Mesa-dev] [PATCH] i965: Disallow fast blit paths for CopyTexImage with PixelTransfer ops

Looks correct, based on the previous discussion about the same fix for ReadPixels and TexImage. CopyTexImage has the same requirements. Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Sun, 2015-09-06 at 17:37 +0100, Chris Wilson wrote: > glCopyTexImage behaves similarly to glR

Re: [Mesa-dev] [PATCH 1/2] nir: Add a nir_system_value_from_intrinsic() function.

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Mon, 2015-09-07 at 00:30 -0700, Kenneth Graunke wrote: > This converts NIR intrinsics that load system values into Mesa's > SYSTEM_VALUE_* enumerations. > > Signed-off-by: Kenneth Graunke <kenn...@whitecape.org> >

Re: [Mesa-dev] [PATCH 0/4] Resolve GCC missing field initializer warnings

Thanks! I think I would have squashed these together in one patch, it is the same one-line fix in 4 consecutive lines after all. In any case, this series is: Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Tue, 2015-09-08 at 20:21 +1000, Rhys Kidd wrote: > Resolve a series o

Re: [Mesa-dev] [PATCH v3 4/4] i965/vec4: Don't unspill the same register in consecutive instructions

On Wed, 2015-09-02 at 17:53 +0300, Francisco Jerez wrote: > Iago Toral <ito...@igalia.com> writes: > > > On Wed, 2015-09-02 at 14:29 +0300, Francisco Jerez wrote: > >> Iago Toral <ito...@igalia.com> writes: > >> > >> > Hi Curro, > >&

Re: [Mesa-dev] [PATCH v2 6/6] i965: Add a debug option for spilling everything in vec4 code

On Wed, 2015-09-02 at 14:32 +0300, Francisco Jerez wrote: > Iago Toral <ito...@igalia.com> writes: > > > On Thu, 2015-07-30 at 16:13 +0300, Francisco Jerez wrote: > >> Iago Toral <ito...@igalia.com> writes: > >> > >> > On Thu, 2015-07-30 at

Re: [Mesa-dev] [PATCH 13/17 v2] glsl: Silence unused parameter warnings

const char *name) You also want to remove the reference to 'name_as_gs_input' in the comment right above this function too. Other than this, Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> > { > switch (state->stage) { > case MESA_SHADER_TESS_CTRL: > @@ -1094,

Re: [Mesa-dev] [PATCH v3 4/4] i965/vec4: Don't unspill the same register in consecutive instructions

On Thu, 2015-09-03 at 13:15 +0300, Francisco Jerez wrote: > Iago Toral <ito...@igalia.com> writes: > > > On Wed, 2015-09-02 at 17:53 +0300, Francisco Jerez wrote: > >> Iago Toral <ito...@igalia.com> writes: > >> > >> > On Wed, 2015-09-02 at

Re: [Mesa-dev] [PATCH 1/2] dri/common: embed drirc into driver binaries

Both patches do what they advertise and seem to work, so they are Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> That said, I imagine that probably you want to get at least a few ACKs from other devs, like Illia did, to make sure that your changes have enough support. Iago On Wed, 2

Re: [Mesa-dev] [PATCH v3 4/4] i965/vec4: Don't unspill the same register in consecutive instructions

Hi Curro, I have been a couple of weeks on holidays and have just come back to this: On Thu, 2015-08-06 at 18:27 +0300, Francisco Jerez wrote: > Iago Toral Quiroga <ito...@igalia.com> writes: > > > If we have spilled/unspilled a register in the current instruction, avoid >

Re: [Mesa-dev] [PATCH v2 6/6] i965: Add a debug option for spilling everything in vec4 code

On Thu, 2015-07-30 at 16:13 +0300, Francisco Jerez wrote: > Iago Toral <ito...@igalia.com> writes: > > > On Thu, 2015-07-30 at 15:58 +0300, Francisco Jerez wrote: > >> Iago Toral Quiroga <ito...@igalia.com> writes: > >> > >> > --- > &g

Re: [Mesa-dev] [PATCH v4 (part2) 04/56] i965: set ARB_shader_storage_buffer_object related constant values

On Thu, 2015-09-03 at 13:52 +0300, Tapani Pälli wrote: > > On 09/03/2015 01:40 PM, Samuel Iglesias Gonsálvez wrote: > > > > > > On 03/09/15 12:30, Tapani Pälli wrote: > >> Hi; > >> > >> On 07/23/2015 09:42 AM, Samuel Iglesias Gonsalvez wrote: > >>> v2: > >>> - Add tessellation shader constants

Re: [Mesa-dev] [PATCH 2/3] texcompress_s3tc: fix stride checks

and Alignment of 4, then > that shuoldn't match. Typo in shouldn't > align the rowlength to the pack alignment before comparing. Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> BTW, it seems that at least _mesa_texstore_rgb_fxt1 in texcompress_fxt1.c has the same issue, right? > T

Re: [Mesa-dev] [PATCH 1/3] st/readpixels: fix accel path for skipimages.

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Tue, 2015-09-01 at 16:41 +1000, Dave Airlie wrote: > From: Dave Airlie <airl...@redhat.com> > > We don't need to use the 3d image address here as that will > include SKIP_IMAGES, and we are only blitting a single &

Re: [Mesa-dev] [PATCH 3/3] mesa/readpixels: check strides are equal before skipping conversion

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Tue, 2015-09-01 at 16:41 +1000, Dave Airlie wrote: > From: Dave Airlie <airl...@redhat.com> > > The CTS packed_pixels test checks that readpixels doesn't write > into the space between rows, however we fail tha

Re: [Mesa-dev] [PATCH v2 6/6] i965: Add a debug option for spilling everything in vec4 code

On Thu, 2015-09-03 at 15:37 +0300, Francisco Jerez wrote: > Iago Toral <ito...@igalia.com> writes: > > > On Wed, 2015-09-02 at 14:32 +0300, Francisco Jerez wrote: > >> Iago Toral <ito...@igalia.com> writes: > >> > >> > On Thu, 2015-07-30 at

Re: [Mesa-dev] [PATCH v3 4/4] i965/vec4: Don't unspill the same register in consecutive instructions

On Wed, 2015-09-02 at 14:29 +0300, Francisco Jerez wrote: > Iago Toral <ito...@igalia.com> writes: > > > Hi Curro, > > > > I have been a couple of weeks on holidays and have just come back to > > this: > > > > On Thu, 2015-08-06 at 18:27 +0300, Fra

Re: [Mesa-dev] [PATCH v2 6/6] i965: Add a debug option for spilling everything in vec4 code

On Thu, 2015-09-03 at 15:37 +0300, Francisco Jerez wrote: > Iago Toral <ito...@igalia.com> writes: > > > On Wed, 2015-09-02 at 14:32 +0300, Francisco Jerez wrote: > >> Iago Toral <ito...@igalia.com> writes: > >> > >> > On Thu, 2015-07-30 at

Re: [Mesa-dev] [PATCH 2/7] glsl/cs: Add gl_LocalInvocationID variable

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Mon, 2015-08-03 at 23:00 -0700, Jordan Justen wrote: > Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> > --- > src/glsl/builtin_variables.cpp | 2 ++ > src/glsl/shader_enums.h| 9 + > 2 f

Re: [Mesa-dev] [PATCH 3/7] nir: Add gl_LocalInvocationID variable

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Mon, 2015-08-03 at 23:00 -0700, Jordan Justen wrote: > Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> > --- > src/glsl/nir/nir_intrinsics.h | 1 + > src/glsl/nir/nir_lower_system_values.c | 3 +

Re: [Mesa-dev] [PATCH 2/7] glsl/cs: Add gl_LocalInvocationID variable

On Thu, 2015-09-10 at 16:38 +0200, Iago Toral wrote: > Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> > > On Mon, 2015-08-03 at 23:00 -0700, Jordan Justen wrote: > > Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> > > --- > > src/glsl/bui

Re: [Mesa-dev] [PATCH 1/3] glsl: shader-enum to name debug fxns

Thanks for all the explanations, this is: Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Tue, 2015-09-15 at 19:33 -0400, Rob Clark wrote: > From: Rob Clark <robcl...@freedesktop.org> > > Signed-off-by: Rob Clark <robcl...@freedesktop.org> > --- >

Re: [Mesa-dev] [PATCH 3/3] nir/print: print symbolic names from shader-enum

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Tue, 2015-09-15 at 19:33 -0400, Rob Clark wrote: > From: Rob Clark <robcl...@freedesktop.org> > > v2: split out moving of FILE *fp into state structure into it's own > (more complete patch) to reduce the noise in

Re: [Mesa-dev] [PATCH] nir: add lowering for ffract

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Tue, 2015-09-15 at 17:40 -0400, Rob Clark wrote: > From: Rob Clark <robcl...@freedesktop.org> > > Signed-off-by: Rob Clark <robcl...@freedesktop.org> > --- > src/glsl/nir/nir.h| 3 +++ > s

Re: [Mesa-dev] [PATCH 2/3] nir/print: bit of state refactoring

Looks good, Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Wed, 2015-09-16 at 08:25 -0400, Rob Clark wrote: > From: Rob Clark <robcl...@freedesktop.org> > > Rename print_var_state to print_state, and stuff FILE ptr into the state > object. This avoids passing a

Re: [Mesa-dev] [PATCH v5 01/70] mesa: set MAX_SHADER_STORAGE_BUFFERS to 15.

On Thu, 2015-09-10 at 15:17 -0400, Ilia Mirkin wrote: > On Thu, Sep 10, 2015 at 2:52 PM, Ian Romanick <i...@freedesktop.org> wrote: > > On 09/10/2015 10:45 AM, Ilia Mirkin wrote: > >> On Thu, Sep 10, 2015 at 9:35 AM, Iago Toral Quiroga <ito...@igalia.com> > >

Re: [Mesa-dev] [PATCH 4/7] i965/cs: Reserve local invocation id in payload regs

gt; + payload.num_regs += local_id_regs; > + } > + } As it is now, local_id_regs can't be zero. I suppose that it could be possible for it to be zero in the future if we end up implementing the first of the optimizations you suggest above for the case where all the component

Re: [Mesa-dev] [PATCH] nir: Fix output variable names

On Fri, 2015-09-11 at 09:24 +0200, Eduardo Lima Mitev wrote: > Commit 1dbe4af9c9e318525fc082b542b93fb7f1e5efba > "nir: Add a pass to lower outputs to temporary variables" messed up output > variable names. The issue can be reproduced by dumping the NIR shaders > with INTEL_DEBUG="vs,fs". > --- >

Re: [Mesa-dev] [PATCH 2/4] svga: remove useless MAX2() call

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Thu, 2015-09-10 at 09:04 -0600, Brian Paul wrote: > The sum of two unsigned ints is always >= 0. Found with Coverity. > --- > src/gallium/drivers/svga/svga_state_tss.c | 2 +- > 1 file changed, 1 insertion(+), 1 deleti

Re: [Mesa-dev] [PATCH 04/11] nir/print: print symbolic names from shader-enum

On Sun, 2015-09-13 at 11:51 -0400, Rob Clark wrote: > From: Rob Clark > > Signed-off-by: Rob Clark > --- > src/glsl/nir/nir_print.c | 73 > ++-- > 1 file changed, 59 insertions(+), 14 deletions(-)

Re: [Mesa-dev] [PATCH 03/11] glsl: shader-enum to name debug fxns

On Sun, 2015-09-13 at 11:51 -0400, Rob Clark wrote: > From: Rob Clark > > Signed-off-by: Rob Clark > --- > src/Makefile.am | 1 + > src/glsl/shader_enums.c | 202 > ++ >

Re: [Mesa-dev] [RFC 0/3] i965: Enable up to 24 MRF registers in gen6

On Wed, 2015-09-16 at 12:32 -0700, Kenneth Graunke wrote: > On Wednesday, September 16, 2015 11:17:53 AM Iago Toral Quiroga wrote: > > It seems that we have some bugs where we fail to compile shaders in gen6 > > because we do not having enough MRF registers available (see bugs 8646

Re: [Mesa-dev] [PATCH] i965: fix textureGrad for cubemaps

Hi Tapani, Kevin, awesome work! I was curious about how to fix this, at least when I was looking at the specs for this stuff it was not obvious that the Math involved for this was so different, I only recall seeing the reference that texure coordinates had to be normalized to a [-1, 1] space

Re: [Mesa-dev] [PATCH 03/11] glsl: shader-enum to name debug fxns

On Tue, 2015-09-15 at 08:07 -0400, Rob Clark wrote: > On Tue, Sep 15, 2015 at 2:55 AM, Iago Toral <ito...@igalia.com> wrote: > > On Sun, 2015-09-13 at 11:51 -0400, Rob Clark wrote: > >> From: Rob Clark <robcl...@freedesktop.org> > >> > >> Si

Re: [Mesa-dev] [PATCH 04/11] nir/print: print symbolic names from shader-enum

On Tue, 2015-09-15 at 08:27 -0400, Rob Clark wrote: > On Tue, Sep 15, 2015 at 3:18 AM, Iago Toral <ito...@igalia.com> wrote: > > On Sun, 2015-09-13 at 11:51 -0400, Rob Clark wrote: > >> From: Rob Clark <robcl...@freedesktop.org> > >> > >> Si

Re: [Mesa-dev] SSBO's in UniformBlocks list?

Hi ilia, On Tue, 2015-09-29 at 03:53 -0400, Ilia Mirkin wrote: > Hi Samuel, and any other onlookers, > > I was wondering why the decision was made to stick SSBO's onto the > same list as constbufs. Seems like they're entirely separate entities, > no? Perhaps I'm missing something? The reason

Re: [Mesa-dev] [PATCH V6 13/27] glsl: fix whitespace

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Tue, 2015-09-29 at 12:42 +1000, Timothy Arceri wrote: > --- > src/glsl/ast_to_hir.cpp | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp > index

Re: [Mesa-dev] [PATCH] nir: Use a system value for gl_PrimitiveIDIn.

6766a0 100644 > --- a/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp > +++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp > @@ -72,6 +72,9 @@ > vec4_gs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr) > dst_reg *reg; > > switch (instr->in

Re: [Mesa-dev] SSBO's in UniformBlocks list?

On Tue, 2015-09-29 at 11:19 -0400, Ilia Mirkin wrote: > On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral <ito...@igalia.com> wrote: > > Hi ilia, > > > > On Tue, 2015-09-29 at 03:53 -0400, Ilia Mirkin wrote: > >> Hi Samuel, and any other onlookers, > >> &

Re: [Mesa-dev] SSBO's in UniformBlocks list?

On Wed, 2015-09-30 at 02:34 -0400, Ilia Mirkin wrote: > On Wed, Sep 30, 2015 at 2:26 AM, Iago Toral <ito...@igalia.com> wrote: > > On Tue, 2015-09-29 at 11:19 -0400, Ilia Mirkin wrote: > >> On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral <ito...@igalia.com> wrote: > &

Re: [Mesa-dev] SSBO's in UniformBlocks list?

On Tue, 2015-09-29 at 18:41 +0300, Francisco Jerez wrote: > Ilia Mirkin <imir...@alum.mit.edu> writes: > > > On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral <ito...@igalia.com> wrote: > >> Hi ilia, > >> > >> On Tue, 2015-09-29 at 03:53 -0400

Re: [Mesa-dev] SSBO's in UniformBlocks list?

On Wed, 2015-09-30 at 11:54 +0300, Francisco Jerez wrote: > Iago Toral <ito...@igalia.com> writes: > > > On Tue, 2015-09-29 at 18:41 +0300, Francisco Jerez wrote: > >> Ilia Mirkin <imir...@alum.mit.edu> writes: > >> > >> > On Tue, Sep 29,

Re: [Mesa-dev] [PATCH] mesa: add GL_UNSIGNED_INT_24_8 to _mesa_pack_depth_span

On Thu, 2015-10-01 at 08:28 +0300, Tapani Pälli wrote: > Patch adds missing type (used with NV_read_depth) so that it gets > handled correctly. Also add type to _mesa_problem output to aid > debugging. > > Signed-off-by: Tapani Pälli > --- > src/mesa/main/pack.c | 4 +++-

Re: [Mesa-dev] [PATCH] glsl: emit row_major matrix's SSBO stores only for components in writemask

bled components in the writemask, saving some > store instructions plus avoid storing wrong data on each disabled > component. Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> > Signed-off-by: Samuel Iglesias Gonsalvez <sigles...@igalia.com> > --- > src/glsl/lower_ubo_ref

Re: [Mesa-dev] [PATCH 03/11] i965: Pull stage_prog_data.nr_params out of the NIR shader

On Thu, 2015-10-01 at 07:58 -0700, Jason Ekstrand wrote: > On Thu, Oct 1, 2015 at 7:52 AM, Iago Toral <ito...@igalia.com> wrote: > > On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote: > >> Previously, we had a bunch of code in each stage to figure out how m

Re: [Mesa-dev] [PATCH 02/11] i965/vs: Move lazy NIR creation to codegen_vs_prog

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote: > The next commit will add code to codegen_vs_prog that requires the NIR > shader to be there in all cases. It doesn't hurt anything to just move it > from brw_vs_emit to

Re: [Mesa-dev] [PATCH 01/11] glsl/types: Make subroutine types have a single matrix column

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote: > That way, if we do the usual thing of multiplying vector_elements by > matrix_columns we get the actual number of components in the type as per > component_slots(). &

Re: [Mesa-dev] [PATCH 03/11] i965: Pull stage_prog_data.nr_params out of the NIR shader

On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote: > Previously, we had a bunch of code in each stage to figure out how many > slots we needed in stage_prog_data.param. This code was mostly identical > across the stages and had been copied and pasted around. Unfortunately, > this meant

Re: [Mesa-dev] SSBO's in UniformBlocks list?

On Wed, 2015-09-30 at 11:27 -0400, Ilia Mirkin wrote: > On Wed, Sep 30, 2015 at 3:18 AM, Iago Toral <ito...@igalia.com> wrote: > > On Wed, 2015-09-30 at 02:34 -0400, Ilia Mirkin wrote: > >> On Wed, Sep 30, 2015 at 2:26 AM, Iago Toral <ito...@igalia.com> wrote: >

Re: [Mesa-dev] [PATCH] main: Fix block index when mixing UBO and SSBO blocks

On Thu, 2015-10-01 at 09:13 +0300, Tapani Pälli wrote: > > On 09/29/2015 05:38 PM, Iago Toral Quiroga wrote: > > Since we store both in UniformBlocks, we can't just compute the index by > > subtracting the array address start, we need to count the number of > > buffer

Re: [Mesa-dev] SSBO's in UniformBlocks list?

On Thu, 2015-10-01 at 02:18 -0400, Ilia Mirkin wrote: > On Thu, Oct 1, 2015 at 2:12 AM, Iago Toral <ito...@igalia.com> wrote: > > However, I think this can be a problem in your case, because you can't > > remap the block index if you don't know how many blocks in UniformBloc

Re: [Mesa-dev] SSBO's in UniformBlocks list?

On Thu, 2015-10-01 at 02:30 -0400, Ilia Mirkin wrote: > On Thu, Oct 1, 2015 at 2:24 AM, Iago Toral <ito...@igalia.com> wrote: > > On Thu, 2015-10-01 at 02:18 -0400, Ilia Mirkin wrote: > >> On Thu, Oct 1, 2015 at 2:12 AM, Iago Toral <ito...@igalia.com> wrote: &g

Re: [Mesa-dev] [RFC 2/2] mesa: Add {Num}UniformBlocks and {Num}ShaderStorageBlocks to gl_shader_program

On Thu, 2015-10-01 at 14:01 -0400, Ilia Mirkin wrote: > On Thu, Oct 1, 2015 at 7:09 AM, Iago Toral Quiroga <ito...@igalia.com> wrote: > > These arrays provide backends with separate index spaces for UBOS and SSBOs. > > --- > > src/glsl/link

Re: [Mesa-dev] [PATCH] mesa: avoid leaking closure when iterating over a string_to_uint_map

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Thu, 2015-10-01 at 20:19 -0400, Ilia Mirkin wrote: > Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu> > --- > src/mesa/program/hash_table.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/mesa/p

Re: [Mesa-dev] [PATCH] glsl: avoid leaking hiddenUniforms map when there are no uniforms

, bail out. > */ > if (num_uniforms == 0) >return; > > - /* assign hidden uniforms a slot id */ > - hiddenUniforms->iterate(assign_hidden_uniform_slot_id, _size); > - delete hiddenUniforms; > - I suppose there is no much gain in simply adding the de

Re: [Mesa-dev] [PATCH] i965: don't forget to free image_param on prog_data free

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Thu, 2015-10-01 at 20:27 -0400, Ilia Mirkin wrote: > Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu> > --- > src/mesa/drivers/dri/i965/brw_program.c | 1 + > 1 file changed, 1 insertion(+) > > diff --g

Re: [Mesa-dev] [PATCH v2] nir: split SSBO min/max atomic instrinsics into signed/unsigned versions

Hi Markus, I noticed that you did not reply to mesa-dev in your original e-mail so I am CCing the list now so we keep the discussion here. On Mon, 2015-10-05 at 08:07 +0200, Iago Toral wrote: > Hi Markus, > > On Sun, 2015-10-04 at 18:15 +0200, Markus Wick wrote: > > Hi Iago, >

Re: [Mesa-dev] [PATCH 11/11] i965/nir: Simplify uniform setup

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote: > --- > src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 19 --- > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 21 - > 2 files chan

Re: [Mesa-dev] [PATCH 09/11] i965/nir: Pull common ARB program uniform handling into a common function

ants; matrices and other larger types should have been > broken > - * down earlier. > - */ > - assert(plist->Parameters[p].Size <= 4); > + brw_nir_setup_arb_uniforms(shader, prog, stage_prog_data); > > - unsigned i

Re: [Mesa-dev] [PATCH 06/11] i965/shader: Pull setup_image_uniform_values out of backend_shader

On Fri, 2015-10-02 at 10:29 +0200, Iago Toral wrote: > On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote: > > I tried to do this once before but Curro pointed out that having it in > > backend_shader meant it could use the setup_vec4_uniform_values helper > > which

Re: [Mesa-dev] [PATCH 08/11] i965/vec4: Use the uniform count from nir_assign_var_locations

p_uniform(nir_variable *var) > * order we'd walk the type, so walk the list of storage and find anything > * with our name, or the prefix of a component that starts with our name. > */ > +unsigned index = var->data.driver_location * 4; Maybe call this uniform_index for consisten

Re: [Mesa-dev] [PATCH 07/11] i965/shader: Get rid of the setup_vec4_uniform_value helper

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote: > It's not used by anything anymore > --- > src/mesa/drivers/dri/i965/brw_fs.cpp | 14 -- > src/mesa/drivers/dri/i965/brw_fs.h |

Re: [Mesa-dev] [PATCH 10/11] i965/nir: Pull GLSL uniform handling into a common function

r_size = storage->type->vector_elements; > + > + for (unsigned s = 0; s < vector_count; s++) { > +unsigned i; > +for (i = 0; i < vector_size; i++) { > + stage_prog_data->param[index++] = components++; > +} >

Re: [Mesa-dev] [PATCH 06/11] i965/shader: Pull setup_image_uniform_values out of backend_shader

atic const gl_constant_value zero = { 0 }; > + > + for (unsigned i = 0; i < n; ++i) > + params[i] = [i]; > + > + for (unsigned i = n; i < 4; ++i) > + params[i] = > +} I actually liked the version that received an offset into params better, since that all

Re: [Mesa-dev] [PATCH 1/2] glsl/opt_array_splitting: Fix crash when doing array indexing into other arrays

I think this never got a review, anyone willing to take it? Iago On Mon, 2015-09-14 at 13:49 +0200, Iago Toral Quiroga wrote: > When we find indirect indexing into an array, the current implementation > of the array spliiting optimization pass does not look further into the > expres

Re: [Mesa-dev] [PATCH 04/11] i965/vec4: Use the actual channels used in pack_uniform_registers

gt; + case BRW_OPCODE_DP2: > +readmask = 0x3; > +break; I don't know if there are other opcodes that could also be special-handled like these, but if there are we are only missing the opportunity to do tighter packing for them (which

Re: [Mesa-dev] [PATCH 05/11] i965/vec4: Get rid of the uniform_vector_size array

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote: > The uniform_vector_size array was only ever used by pack_uniform_registers > which no longer needs it. > --- > src/mesa/drivers/dri/i965/brw_vec4.cpp

Re: [Mesa-dev] ssbo support missing imin/umin dinstinction

On Fri, 2015-09-25 at 21:15 -0400, Ilia Mirkin wrote: > Hi Samuel, > > It seems like there's only a single atomic_min intrinsic for ssbo > (same for max), but the ssbo spec actually calls for both signed and > unsigned semantics: > > uint atomicMin(inout uint mem, uint data); >

Re: [Mesa-dev] [PATCH v5 45/70] glsl: atomic counters can be declared as buffer-qualified variables

On Mon, 2015-09-28 at 13:13 +0300, Francisco Jerez wrote: > Iago Toral Quiroga <ito...@igalia.com> writes: > > > From: Kristian Høgsberg <k...@bitplanet.net> > > > > --- > > src/glsl/ast_to_hir.cpp | 6 +++--- > > 1 file changed, 3 insertions(

Re: [Mesa-dev] [PATCH v5 45/70] glsl: atomic counters can be declared as buffer-qualified variables

On Mon, 2015-09-28 at 13:45 +0200, Iago Toral wrote: > On Mon, 2015-09-28 at 13:13 +0300, Francisco Jerez wrote: > > Iago Toral Quiroga <ito...@igalia.com> writes: > > > > > From: Kristian Høgsberg <k...@bitplanet.net> > > > > > > --- &

Re: [Mesa-dev] [PATCH 3/3] glsl: Fix forward NULL dereference coverity warning

CCing Ian... On Mon, 2015-09-28 at 13:02 +0200, Iago Toral wrote: > Ian, you wrote the original code, so you might want to have a look at > this one just in case I missed something even if piglit does not > complain. In any case, I guess that either the code or the comment > sho

Re: [Mesa-dev] [PATCH 3/3] glsl: Fix forward NULL dereference coverity warning

Ian, you wrote the original code, so you might want to have a look at this one just in case I missed something even if piglit does not complain. In any case, I guess that either the code or the comment should be fixed. Iago On Mon, 2015-09-28 at 12:59 +0200, Iago Toral Quiroga wrote

Re: [Mesa-dev] [PATCH v5 45/70] glsl: atomic counters can be declared as buffer-qualified variables

On Mon, 2015-09-28 at 15:23 +0300, Francisco Jerez wrote: > Iago Toral <ito...@igalia.com> writes: > > > On Mon, 2015-09-28 at 13:13 +0300, Francisco Jerez wrote: > >> Iago Toral Quiroga <ito...@igalia.com> writes: > >> > >

Re: [Mesa-dev] [PATCH 5/5] i965: Maximum allowed size of SEND messages is 15 (4 bits)

On Fri, 2015-09-18 at 09:09 -0700, Kenneth Graunke wrote: > On Friday, September 18, 2015 10:08:52 AM Iago Toral Quiroga wrote: > > Until now we only used MRFs 1..15 for regular SEND messages, so the > > message length could not possibly exceed the maximum size. Now that > >

Re: [Mesa-dev] [PATCH] nir: Don't fuse fmul into ffma if used by more than 4 fadds.

ion counts may not be the best thing to do. However, if ffma operations are more expensive that fadd, a higher instruction count should always lead to worse performance, so that should be ok. Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> > src/glsl/nir/nir_opt_peephole_ffma.c |

Re: [Mesa-dev] [PATCH 7/7] doc: Set GL_OES_geometry_shader as started

On Wed, 2015-09-23 at 14:07 +0200, Eduardo Lima Mitev wrote: > On 09/23/2015 10:42 AM, Marta Lofstedt wrote: > > From: Marta Lofstedt > > > > Signed-off-by: Marta Lofstedt > > --- > > docs/GL3.txt | 2 +- > > 1 file changed, 1

Re: [Mesa-dev] [PATCH 7/7] doc: Set GL_OES_geometry_shader as started

On Wed, 2015-09-23 at 14:34 +, Lofstedt, Marta wrote: > > -Original Message- > > From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On > > Behalf Of Iago Toral > > Sent: Wednesday, September 23, 2015 3:18 PM > > To: Eduardo Lima Mitev > >

Re: [Mesa-dev] [PATCH 0/5] Enable up to 24 MRF registers in gen6

On Mon, 2015-09-21 at 09:21 -0700, Matt Turner wrote: > On Mon, Sep 21, 2015 at 8:00 AM, Iago Toral <ito...@igalia.com> wrote: > > On Mon, 2015-09-21 at 07:49 -0700, Kenneth Graunke wrote: > >> On Monday, September 21, 2015 09:46:24 AM Mark Janes wrote: > >> >

Re: [Mesa-dev] [PATCH v5 00/70] ARB_shader_storage_buffer_object (mesa, i965)

On Wed, 2015-09-23 at 10:38 -0700, Kristian Høgsberg wrote: > On Wed, Sep 23, 2015 at 12:06 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com> wrote: > > > > > > On 19/09/15 01:56, Kristian Høgsberg wrote: > >> On Thu, Sep 10, 2015 at 03:35:16PM +0

Re: [Mesa-dev] [PATCH 0/5] Enable up to 24 MRF registers in gen6

form I guess that's a good sign, but I'll let Ken make that call. Iago > thanks, > > Mark > > Iago Toral Quiroga <ito...@igalia.com> writes: > > > There are some bug reports about shaders failing to compile in gen6 > > because MRF 14 is used when we need to s

Re: [Mesa-dev] [PATCH 0/3] Make pull constant loads in gen6 start at MRFs 16/17

On Tue, 2015-09-22 at 14:00 +0200, Iago Toral Quiroga wrote: > Originally, these could conflict with our spills, but now that we moved the > latter to MRFs 21..23, that is no longer the case. Still, in gen6 we > now use MRFs 1..15 for URB writes, so we probably want to make our pull &

Re: [Mesa-dev] [PATCH v5 38/70] i965/nir/vec4: Implement nir_intrinsic_store_ssbo

On Fri, 2015-09-18 at 13:02 -0700, Kristian Høgsberg wrote: > On Thu, Sep 10, 2015 at 03:35:54PM +0200, Iago Toral Quiroga wrote: > > --- > > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 148 > > + > > 1 file changed, 148 insertions(+) >

Re: [Mesa-dev] [RFC 0/3] i965: Enable up to 24 MRF registers in gen6

On Wed, 2015-09-16 at 12:32 -0700, Kenneth Graunke wrote: > On Wednesday, September 16, 2015 11:17:53 AM Iago Toral Quiroga wrote: > > It seems that we have some bugs where we fail to compile shaders in gen6 > > because we do not having enough MRF registers available (see bugs 8646

Re: [Mesa-dev] [PATCH 0/5] Enable up to 24 MRF registers in gen6

On Tue, 2015-09-22 at 08:10 +0200, Iago Toral wrote: > Hi Mark, > > On Mon, 2015-09-21 at 17:45 -0700, Mark Janes wrote: > > Hi Iago, > > > > According to my tests, this patch series fixes the gles2/gles3 > > "functional.uniform_api.random.23" tests i

Re: [Mesa-dev] [PATCH] glsl: bail out early in _mesa_ShaderSource if no shaderobj

ession from commit: >04e201d0c02cd30ace5c6fe80e9f021ebb733682 > > Additions in v2 also fix following failing deqp test: >dEQP-GLES[2|3].functional.negative_api.shader.shader_source Nice! I wasn't expecting that :) Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> > v2: c

Re: [Mesa-dev] [PATCH v2] i965: fix textureGrad for cubemaps

On Fri, 2015-09-18 at 15:02 +0300, Tapani Pälli wrote: > Fixes bugs exposed by commit > 2b1cdb0eddb73f62e4848d4b64840067f1f70865 in: >ES3-CTS.gtf.GL3Tests.shadow.shadow_execution_frag > > No regressions observed in deqp, CTS or Piglit. > > v2: address review fee

Re: [Mesa-dev] [PATCH v5 00/70] ARB_shader_storage_buffer_object (mesa, i965)

Hi Kristian, On Fri, 2015-09-18 at 16:56 -0700, Kristian Høgsberg wrote: > On Thu, Sep 10, 2015 at 03:35:16PM +0200, Iago Toral Quiroga wrote: > > Hi, > > > > this is the latest version of the ARB_shader_storage_buffer_object > > implementation. A goo

Re: [Mesa-dev] [PATCH 0/5] Enable up to 24 MRF registers in gen6

On Mon, 2015-09-21 at 07:49 -0700, Kenneth Graunke wrote: > On Monday, September 21, 2015 09:46:24 AM Mark Janes wrote: > > This series hits an assertion on ILK and G45: > > > > src/mesa/drivers/dri/i965/brw_eu_emit.c:150: brw_set_dest: Assertion > > `dest.nr < (devinfo->gen == 6 ? 24 : 16)'

Re: [Mesa-dev] [PATCH] glsl: do not attempt to dump_shader if no shaderobj

On Mon, 2015-09-21 at 09:15 +0300, Tapani Pälli wrote: > Patch fixes a crash in conformance test that tries out different > invalid arguments for glShaderSource and glGetShaderSource: > >ES2-CTS.gtf.GL.glGetShaderSource.getshadersource_programhandle > > This is a regression from commit: >

Re: [Mesa-dev] [PATCH] i965: Make vec4_visitor's destructor virtual

On Mon, 2015-10-05 at 13:08 +0300, Francisco Jerez wrote: > Iago Toral Quiroga <ito...@igalia.com> writes: > > > We need a virtual destructor when at least one of the class' methods is > > virtual. > > Failure to do so leads to undefined behavior when destructing d

Re: [Mesa-dev] [PATCH 4/6] i965: dump scheduling cycle estimates

On Fri, 2015-10-02 at 17:43 -0400, Connor Abbott wrote: > On Fri, Oct 2, 2015 at 5:37 PM, Connor Abbott wrote: > > The heuristic we're using is rather lame, since it assumes everything is > > non-uniform and loops execute 50 times, but it should be enough for > > measuring

Re: [Mesa-dev] [PATCH v4] i965/fs: Handle nir shared variable store intrinsic

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Tue, 2015-12-01 at 14:35 -0800, Jordan Justen wrote: > v4: > * Apply similar optimization for shared variable stores as >0cb7d7b4b7c32246d4c4225a1d17d7ff79a7526d. This was causing a >OpenGL

Re: [Mesa-dev] [PATCH v3 00/44] Computer shader shared variables

> i965: Implement L3 state atom. > i965: Add debug flag to print out the new L3 state during transitions. > i965: Work around L3 state leaks during context switches. > i965: Hook up L3 partitioning state atom. > > Iago Toral Quiroga (1): > glsl: Don't assert on shared

Re: [Mesa-dev] [PATCH v3 30/44] i965/fs: Handle nir shared variable store intrinsic

On Tue, 2015-12-01 at 13:00 -0800, Jordan Justen wrote: > On 2015-12-01 04:45:05, Iago Toral wrote: > > On Tue, 2015-12-01 at 00:19 -0800, Jordan Justen wrote: > > > Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> > > > --- > > > src

Re: [Mesa-dev] [RFC PATCH 5/5] i965: Skip execution size adjustment for instructions of width 4

On Wed, 2015-12-09 at 08:10 -0800, Jason Ekstrand wrote: > > On Dec 9, 2015 4:16 AM, "Iago Toral Quiroga" <ito...@igalia.com> > wrote: > > > > This code in brw_set_dest adjusts the execution size of any > instruction > > with a dst.width < 8. Howe

Re: [Mesa-dev] [RFC PATCH 5/5] i965: Skip execution size adjustment for instructions of width 4

On Wed, 2015-12-09 at 23:51 -0800, Jason Ekstrand wrote: > > On Dec 9, 2015 11:47 PM, "Iago Toral" <ito...@igalia.com> wrote: > > > > On Wed, 2015-12-09 at 08:10 -0800, Jason Ekstrand wrote: > > > > > > On Dec 9, 2015 4:16 AM,

Re: [Mesa-dev] [RFC PATCH 1/5] i965/eu: set correct execution size in brw_NOP

On Wed, 2015-12-09 at 10:38 -0800, Matt Turner wrote: > On Wed, Dec 9, 2015 at 4:15 AM, Iago Toral Quiroga <ito...@igalia.com> wrote: > > --- > > src/mesa/drivers/dri/i965/brw_eu_emit.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/src/mes

Re: [Mesa-dev] [PATCH v2] i965/gen8/cs: Gen8 requires 64 byte alignment for push constant data

On Wed, 2015-12-16 at 11:39 -0800, Kenneth Graunke wrote: > On Wednesday, December 16, 2015 10:02:16 AM Iago Toral Quiroga wrote: > > The BDW PRM Vol2a: Command Reference: Instructions, section > > MEDIA_CURBE_LOAD, > > says that 'CURBE Total Data Length' and 'CURBE Data Star

Re: [Mesa-dev] [PATCH v2] i965/gen8/cs: Gen8 requires 64 byte alignment for push constant data

On Wed, 2015-12-16 at 14:48 -0800, Jordan Justen wrote: > On 2015-12-16 11:39:00, Kenneth Graunke wrote: > > On Wednesday, December 16, 2015 10:02:16 AM Iago Toral Quiroga wrote: > > > The BDW PRM Vol2a: Command Reference: Instructions, section > > > MEDIA_CURBE_LOAD, &

Re: [Mesa-dev] [PATCH v2 1/2] mesa: Add a _mesa_active_fragment_shader_has_side_effects helper

On Thu, 2015-12-17 at 16:29 +0200, Francisco Jerez wrote: > Iago Toral Quiroga <ito...@igalia.com> writes: > > > Some drivers can disable the FS unit if there is nothing in the shader code > > that writes to an output (i.e. color, depth, etc). Right now, mesa has

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