Re: [Mesa-dev] [PATCH] nir/glsl_to_nir: use _mesa_fls() to compute num_textures

On Fri, 2015-11-13 at 07:37 -0800, Jason Ekstrand wrote: > I didn't want to pull a non-inline mesa function into NIR and add a > link dependency and I was too lazy to move it into util. But at this moment _mesa_fls() is an inline function. So I guess it is safe to push it, isn't it?

[Mesa-dev] [PATCH] nir/glsl_to_nir: use _mesa_fls() to compute num_textures

gt;SamplersUsed is 1. Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/glsl/nir/glsl_to_nir.cpp | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp index 57aba5b..5c3fcd1 100644 --- a/src/gls

Re: [Mesa-dev] [PATCH] nir/glsl_to_nir: use _mesa_fls() to compute num_textures

On Fri, 2015-11-06 at 12:21 -0800, Matt Turner wrote: > On Fri, Nov 6, 2015 at 8:27 AM, Juan A. Suarez Romero > Looks good to me, and we use _mesa_fls elsewhere to do this same > calculation. > > Reviewed-by: Matt Turner <matts...@gmail.com> > > Jason, was there s

Re: [Mesa-dev] [PATCH v2 0/1] Do not require all components to apply opt_vector_float()

On Wed, 2015-12-02 at 16:43 +0100, Juan A. Suarez Romero wrote: > This patch, based on Matt suggestion, replaces the former two ones, > as it gets > better results. This patch replaces the ones sent in http://lists.freedesktop.org/archives/mesa-dev/2015-November/101448.htm l entitled

Re: [Mesa-dev] [PATCH 2/2] i965: run brw_vec4 optimizations in loop

On Wed, 2015-11-25 at 16:16 -0800, Matt Turner wrote: > I had a look at a helped shader from shader-db (borderlands-2/3701) > > Its vec4 IR at the time we call opt_vector_float() contains: > >    0: mov vgrf2.0.x:D, 1073741824D >    1: mov vgrf3.0.xy:D, 0D >    2: mov vgrf3.0.w:D, 1065353216D >  

[Mesa-dev] [PATCH v2 1/1] i965: add opportunistic behaviour to opt_vector_float()

(-2.01%) total loops in shared programs:1971 -> 1971 (0.00%) helped:3980 HURT: 0 GAINED:3 LOST: 0 Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>

[Mesa-dev] [PATCH v2 0/1] Do not require all components to apply opt_vector_float()

a future improvement. * I commented about a wrong application of opt_vector_float() in an example Matt found. He told that probably it lacks resetting last_reg to -1. This patch is covering that error. Juan A. Suarez Romero (1): i965: add opportunistic behaviour to opt_vector_float() src/mes

Re: [Mesa-dev] [PATCH v2 0/1] Do not require all components to apply opt_vector_float()

On Thu, 2015-12-03 at 11:04 -0800, Matt Turner wrote: > The GAINED: 3 is almost certainly because of a sporadic failure in > shader-db (or Mesa...?) during the baseline shader-db run. When you > ran shader-db with your patch applied, the same failure didn't occur, > so report.py thinks this means

Re: [Mesa-dev] [PATCH v2 1/1] i965: add opportunistic behaviour to opt_vector_float()

On Thu, 2015-12-03 at 11:04 -0800, Matt Turner wrote: > > The improvement obtained regarding current upstream (56aff6bb4eaf) > is: > > > > total instructions in shared programs: 6819484 -> 6811698 (-0.11%) > > instructions in affected programs: 387245 -> 379459 (-2.01%) > > total loops in

[Mesa-dev] [PATCH v3 1/1] i965: add opportunistic behaviour to opt_vector_float()

igned-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 61 ++ src/mesa/drivers/dri/i965/brw_vec4.h | 4 +++ 2 files changed, 43 insertions(+), 22 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.

Re: [Mesa-dev] [PATCH v4 1/1] i965: Do not overwrite optimizer dumps

On Mon, 2015-11-30 at 12:26 +0100, Juan A. Suarez Romero wrote: > When using INTEL_DEBUG=optimizer, each optimizing step is dump to > disk, > in a separate file. Any news on this? Can be considered as reviewed? Thanks in advance

Re: [Mesa-dev] [PATCH v4 1/1] i965: Do not overwrite optimizer dumps

On Thu, 2015-12-10 at 09:47 -0800, Matt Turner wrote: > Assuming that the cause is indeed non-orthogonal state changes, yes. > But I never saw an answer to that question. > > Reviewed-by: Matt Turner After rebasing and testing against master (11.1-branchpoint-653- g5c5ad4d)

[Mesa-dev] [PATCH v4 1/1] i965: add opportunistic behaviour to opt_vector_float()

v3: take in account predicates (Juan). Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 62 ++ src/mesa/drivers/dri/i965/brw_vec4.h | 4 +++ 2 files changed, 44 insertions(+), 22 deletions(-) diff -

[Mesa-dev] [PATCH v4 0/1] i965: add opportunistic behaviour to opt_vector_float()

in the result it is always 0. Problem is that when applying the optimization, it was ignoring the predicate. The next patch updates the previous version to fix this problem. *** BLURB HERE *** Juan A. Suarez Romero (1): i965: add opportunistic behaviour to opt_vector_float() src/mesa/drivers/dri

[Mesa-dev] [PATCH v3 1/1] i965: Do not overwrite optimizer dumps

variable that tracks the global iteration across the entire life of the program running. v2: use atomic_inc() for the static variable (Jason). v3: define local variable as const (Jason). Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/mesa/drivers/dri/i965/brw_fs.cpp

[Mesa-dev] [PATCH 0/1] Do not loose steps when dumping to file with INTEL_DEBUG=optimizer

iteration) make it easier to indentify for each file in which call it was generated. As example, in original master I get 138 files for FS/VS optimizations when running a piglit test, while now I get 225, meaning I'm recovering 87 missing steps. Juan A. Suarez Romero (1): i965: Do not overwrite

[Mesa-dev] [PATCH 1/1] i965: Do not overwrite optimizer dumps

When using INTEL_DEBUG=optimizer, each optimizing step is dump to disk, in a separate file. But as fs_visitor::optimize() and vec4_visitor::run() are called more than once, it ends up overwriting the files already on disk, loosing then previous optimizer steps. To avoid this, add a new static

Re: [Mesa-dev] [PATCH 1/1] i965: Do not overwrite optimizer dumps

On Wed, 2015-11-25 at 13:15 +0100, Juan A. Suarez Romero wrote: > When using INTEL_DEBUG=optimizer, each optimizing step is dump to > disk, > in a separate file. > > But as fs_visitor::optimize() and vec4_visitor::run() are called more > than once, it ends up overwriting the fil

[Mesa-dev] [PATCH] i965: Do not overwrite optimizer dumps

variable that tracks the global iteration across the entire life of the program running. Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/mesa/drivers/dri/i965/brw_fs.cpp | 13 + src/mesa/drivers/dri/i965/brw_vec4.cpp | 11 +++ 2 files changed, 16 inse

[Mesa-dev] [PATCH 0/2] Run post opt_vector_float() opts in a loop

0 LOST: 0 Juan A. Suarez Romero (2): i965: Do not apply CSE opt to MOV immediate i965: run brw_vec4 optimizations in loop src/mesa/drivers/dri/i965/brw_vec4.cpp | 10 +++--- src/mesa/drivers/dri/i965/brw_vec4_cse.cpp | 13

[Mesa-dev] [PATCH 2/2] i965: run brw_vec4 optimizations in loop

0 LOST: 0 Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 10 +++--- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/sr

[Mesa-dev] [PATCH 1/2] i965: Do not apply CSE opt to MOV immediate

than once, that doesn't happen when we have a constant. So this commit ensures CSE is not applied to MOV immediate (as it provides no gain, and it is reverted later by copy-propagation optimization). Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/mesa/drivers/dri/i965/

[Mesa-dev] [PATCH v4 1/1] i965: Do not overwrite optimizer dumps

variable that tracks the global iteration across the entire life of the program running. v2: use atomic_inc() for the static variable (Jason). v3: define local variable as const (Jason). v4: undo empty line removal (Jason). Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- sr

Re: [Mesa-dev] [PATCH 2/2] i965: run brw_vec4 optimizations in loop

On Wed, 2015-11-25 at 16:16 -0800, Matt Turner wrote: > I think in this case a better solution -- at least until we learn > something more -- would be to initialize opt_vector_float()'s > remaining_channels to only the live components of the register. Do > you > want to try that? Sure! There's a

Re: [Mesa-dev] [PATCH 1/1] i965: Do not overwrite optimizer dumps

On Wed, 2015-11-25 at 11:05 -0800, Jason Ekstrand wrote: > Right.  I didn't pay that much attention to the exact implementation. > But we could do something like. > > atomic int global_iteration_atomic = 0; > > const int global_iteration = atomic_inc(global_iteration_atomic); > > // use

[Mesa-dev] [PATCH v2 1/1] i965: Do not overwrite optimizer dumps

variable that tracks the global iteration across the entire life of the program running. v2: use atomic_inc() for the static variable (Jason). Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/mesa/drivers/dri/i965/brw_fs.cpp | 15 +++ src/mesa/drivers/dr

Re: [Mesa-dev] [PATCH 2/2] i965: run brw_vec4 optimizations in loop

On Wed, 2015-11-25 at 16:16 -0800, Matt Turner wrote: > In the piglit test you cited, opt_vector_float() does this to the > relevant code: > >  cmp.nz.f0.0 null:F, vgrf6.xyzz:F, vgrf14.xyzz:F > -mov vgrf2.0.x:D, 0D >  (+f0.0.any4h) mov vgrf2.0.x:D, -1D > -mov vgrf2.0.yzw:D, 0D > +mov vgrf2.0:F,

Re: [Mesa-dev] How to get uniform components used by uniform variables

On Mon, 2016-02-22 at 13:47 +0200, Tapani Pälli wrote: > Maybe one way would be to include these matrices in UBO or SSBO and > then  > query BUFFER_DATA_SIZE for that buffer. That should return  > "implementation-dependent minimum total buffer object size". > >

[Mesa-dev] How to get uniform components used by uniform variables

Hello. I'm working on providing piglit with tests for the GL_ARB_gpu_shader_fp64 extension[1]. One of the modifications it does is referring uniform variables: "Modify Section 2.14.4, Uniform Variables, p. 89 (modify third paragraph, p. 90) ... uniform variable storage for vertex shader.  A

Re: [Mesa-dev] How to get uniform components used by uniform variables

On Mon, 2016-02-22 at 14:13 +0200, Tapani Pälli wrote: > > So rather than reporting the number of uniform components it is > > consuming, is reporting the bytes used in the layout. > > > > Ah right, I see. Maybe you can query OFFSET then, this should differ  > then when matrix has a different

[Mesa-dev] [PATCH] doc: add 'vec4' option in INTEL_DEBUG

--- docs/envvars.html | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/envvars.html b/docs/envvars.html index 06aa0ac..e21b7c1 100644 --- a/docs/envvars.html +++ b/docs/envvars.html @@ -163,6 +163,7 @@ See the Xlib software driver page for details. blorp - emit messages about the

[Mesa-dev] [PATCH v5] i965: add opportunistic behaviour to opt_vector_float()

LOST: 0 GAINED: 0 v2: change vectorize_mov() signature (Matt). v3: take in account predicates (Juan). Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 62 ++ src/mesa/drivers/dri/i965/brw_vec4.h |

Re: [Mesa-dev] [PATCH v5] i965: add opportunistic behaviour to opt_vector_float()

On Wed, 2016-03-02 at 13:21 +0100, Juan A. Suarez Romero wrote: > opt_vector_float() transforms several scalar MOV operations to a > single > vectorial MOV. > I had sent this patch a couple of months ago, but seems I lost its track. So I've rebased it, check it still gets some

Re: [Mesa-dev] [PATCH 11/15] i965: abort linking if we exhaust the registers

On Fri, 2016-04-29 at 11:15 +0200, Ian Romanick wrote: > I don't see where you get 19.  I get 3 array elements * 2 matrix > columns > * 2 for value0, 2 array elements * 3 matrix columns * 2 for value1, > and > 1 for piglit_vertex.  That's 25. > > This overcounts because by naive doubling the

Re: [Mesa-dev] [PATCH 11/15] i965: abort linking if we exhaust the registers

On Thu, 2016-04-28 at 15:29 +0200, Ian Romanick wrote: > On 04/28/2016 01:40 PM, Antia Puentes wrote: > > > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > Even when the number of vertex attributes is under the limit, for > > shade

Re: [Mesa-dev] [PATCH 11/15] i965: abort linking if we exhaust the registers

On Fri, 2016-04-29 at 11:15 +0200, Ian Romanick wrote: > The driver supports up to 16 vertex attributes. > > ARB_vertex_attrib_64bit > > states that attribute variables of type dvec3, dvec4, dmat2x3, > > dmat2x4, > > dmat3, dmat3x4, dmat4x3, and dmat4 *may* count as consuming twice > > as > > many

[Mesa-dev] [PATCH] i965: fix double-precision vertex inputs measurement

For double-precision vertex inputs we need to measure them in dvec4 terms, and for single-precision vertex inputs we need to measure them in vec4 terms. For the later case, we use type_size_vec4() function. For the former case, we had a wrong implementation based on type_size_vec4(). This commit

Re: [Mesa-dev] [PATCH] i965: fix double-precision vertex inputs measurement

On Fri, 2016-05-20 at 16:56 +0200, Juan A. Suarez Romero wrote: > For double-precision vertex inputs we need to measure them in dvec4 > terms, and for single-precision vertex inputs we need to measure them > in > vec4 terms. Please, ignore this version. It has a typo. I'm sending a

[Mesa-dev] [PATCH] i965: fix double-precision vertex inputs measurement

For double-precision vertex inputs we need to measure them in dvec4 terms, and for single-precision vertex inputs we need to measure them in vec4 terms. For the later case, we use type_size_vec4() function. For the former case, we had a wrong implementation based on type_size_vec4(). This commit

Re: [Mesa-dev] [PATCH 11/15] i965: abort linking if we exhaust the registers

On Fri, 2016-04-29 at 14:23 +0200, Juan A. Suarez Romero wrote: > On Fri, 2016-04-29 at 11:15 +0200, Ian Romanick wrote: > > > > The driver supports up to 16 vertex attributes. > > > > > > ARB_vertex_attrib_64bit > > > states that attribute variables of

Re: [Mesa-dev] [PATCH 05/15] i965/fs: shuffle 32bits into 64bits for doubles

On Tue, 2016-05-10 at 13:18 -0700, Kenneth Graunke wrote: > On Thursday, April 28, 2016 1:40:35 PM PDT Antia Puentes wrote: > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > >  > > VS Thread Payload handles attributes in URB as vec4, no matter if >

Re: [Mesa-dev] [PATCH v2 11/15] glsl/linker: dvec3/dvec4 may consume twice input vertex attributes

On Thu, 2016-05-12 at 15:42 -0700, Kenneth Graunke wrote: > I'm a bit confused - it looks like we already do this check slightly > earlier in the function.  Why do we need to do it again (or later?)? In the earlier case, we are using explicit location. So we already know how many locations we

Re: [Mesa-dev] [PATCH v2 11/15] glsl/linker: dvec3/dvec4 may consume twice input vertex attributes

On Fri, 2016-05-13 at 05:34 +1000, Dave Airlie wrote: > On 13 May 2016 4:28 AM, "Antia Puentes" <apuen...@igalia.com> wrote: > > > > > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > From the GL 4.5 core spec, secti

[Mesa-dev] [PATCH v3] glsl/linker: dvec3/dvec4 consume twice input vertex attributes

sion types. v3: count doubles as consuming two attributes (Dave Airlie) Signed-off-by: Antia Puentes <apuen...@igalia.com> Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/compiler/glsl/linker.cpp | 19 +++ 1 file changed, 19 insertions(+) diff --g

[Mesa-dev] [PATCH v4] glsl/linker: dvec3/dvec4 consume twice input vertex attributes

sion types. v3: count doubles as consuming two attributes (Dave Airlie) v4: make reference to spec (Michael Schellenberger Costa) Signed-off-by: Antia Puentes <apuen...@igalia.com> Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/compiler/glsl/linker.cpp | 20 ++

Re: [Mesa-dev] [PATCH v3] glsl/linker: dvec3/dvec4 consume twice input vertex attributes

On Wed, 2016-05-18 at 13:30 +0200, Michael Schellenberger Costa wrote: > Would you mind citing the spec section from the commit message here > (only reference not the text)? Sure. J.A. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org

[Mesa-dev] [PATCH] glsl: Copy propagate in array index function parameters

Copy propagate is not applied in function parameters when they are out or inout. But if the parameter is an array, we can copy propagate the index array. This also fixes several shaders@out-parameter-indexing piglit tests, that exposes a wrong handling of inout function parameters in Mesa. This

Re: [Mesa-dev] [PATCH 12/15] i965: abort linking if URB read length greater than 15

On Wed, 2016-05-04 at 03:43 -0700, Kenneth Graunke wrote: > On Thursday, April 28, 2016 1:40:42 PM PDT Antia Puentes wrote: > > > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > In scalar mode, URB read length limit is 15. Abort if we go b

Re: [Mesa-dev] [PATCH] glsl: correctly handle inout parameters post function inlining

On Fri, 2016-05-06 at 08:49 -0400, Lars Hamre wrote: > Inout parameters which depended on other inout parameters > where not assigned in the correct order. > > Fixes the following piglit tests in shaders/out-parameter-indexing: > vs-inout-index-inout-float-array > vs-inout-index-inout-mat2-col >

Re: [Mesa-dev] [PATCH] glsl: correctly handle inout parameters post function inlining

On Fri, 2016-05-06 at 10:39 -0400, Lars Hamre wrote: > Hi Juan, > > Sorry I missed that. > > It looks like your patch doesn't fix the out parameter indexing for: > vs-inout-index-inout-mat2-col > vs-inout-index-inout-vec4-array > > I was able to extend your patch to get these tests passing by:

[Mesa-dev] [PATCH v2] glsl: Copy propagate in array index function parameters

Copy propagate is not applied in function parameters when they are out or inout. But if the parameter is an array, we can copy propagate the index array. This also fixes shaders@out-parameter-indexing piglit tests, that exposes a wrong handling of inout function parameters in Mesa. This commit

[Mesa-dev] [PATCH] glsl: use var with initializer on global var validation

Currently, when cross validating global variables, all global variables seen in the shaders that are part of a program are saved in a table. When checking a variable this already exist in the table, we check both are initialized to the same value. If the already saved variable does not have an

Re: [Mesa-dev] [PATCH 08/15] i965/vec4: use attribute slots to calculate URB read length

On Mon, 2016-05-09 at 23:37 -0700, Kenneth Graunke wrote: > void *log_data, > > const unsigned *assembly = NULL; > >   > > unsigned nr_attributes = _mesa_bitcount_64(prog_data- > >inputs_read); > > +   unsigned nr_attribute_slots = 0; > > Can't you just do: > >     nir_shader *nir =

Re: [Mesa-dev] [PATCH 05/15] i965/fs: shuffle 32bits into 64bits for doubles

On Tue, 2016-05-10 at 00:15 -0700, Kenneth Graunke wrote: > On Thursday, April 28, 2016 1:40:35 PM PDT Antia Puentes wrote: > > > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > VS Thread Payload handles attributes in URB as vec4, no

Re: [Mesa-dev] [PATCH v2] glsl: Copy propagate in array index function parameters

On Fri, 2016-05-06 at 12:23 -0400, Ilia Mirkin wrote: > Could you add something to piglit which tries this with AoA to make > sure that your logic is right? Sure. I've submitted a couple of tests that use another array for array indexing.

Re: [Mesa-dev] [PATCH 10/95] i965/vec4: handle 32 and 64 bit channels in liveness analysis

On Fri, 2016-07-29 at 12:59 -0700, Francisco Jerez wrote: > Iago Toral Quiroga <ito...@igalia.com> writes: > > > > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > Our current data flow analysis does not take into account

Re: [Mesa-dev] [PATCH 10/95] i965/vec4: handle 32 and 64 bit channels in liveness analysis

On Mon, 2016-08-08 at 16:12 +0200, Juan A. Suarez Romero wrote: > Hmm... what about the case of exec_size == 4 and writing just a > float?  > > I understand in this case we only should mark one word, so the loop > should  not be 2*inst->regs_written. > > Note th

Re: [Mesa-dev] [PATCH 10/95] i965/vec4: handle 32 and 64 bit channels in liveness analysis

On Fri, 2016-07-29 at 12:59 -0700, Francisco Jerez wrote: > |   for (unsigned i = 0; i < 2 * inst->regs_written; i++) > { > |  for (int c = 0; c < 4; c++) > | result_live[c] |= BITSET_TEST( > |    live, var_from_reg(alloc,

Re: [Mesa-dev] [PATCH 1/2] anv: allow blue in alpha component in swizzle for render

On Wed, 2017-02-08 at 09:27 -0800, Nanley Chery wrote: > On Wed, Feb 08, 2017 at 01:31:54PM +0100, Juan A. Suarez Romero wrote: > > In pre-Broadwell devices, as B4G4R4A4 is not supported natively, we > > workaround it by using a format with a more complex swizzle, that uses &g

[Mesa-dev] [PATCH 0/2] Fixes for B4G4R4A4 vulkan tests in Haswell

ing.clear_color_image.1d_b4g4r4a4_unorm_pack16 - dEQP-VK.api.image_clearing.clear_color_image.2d_b4g4r4a4_unorm_pack16 - dEQP-VK.api.image_clearing.clear_color_image.3d_b4g4r4a4_unorm_pack16 *** BLURB HERE *** Juan A. Suarez Romero (2): anv: allow blue in alpha component in swizzle for render isl: apply REND

[Mesa-dev] [PATCH 2/2] isl: apply RENDER_SURFACE_STATE::Shader Channel assertions to gen>=8

We are applying several assertions to RENDER_SURFACE_STATE's shader channels selection to gen>=8 and haswell devices. But this assertions are not listed in Haswell PRMs. Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/intel/isl/isl_surface_state.c | 5 - 1 file c

[Mesa-dev] [PATCH 1/2] anv: allow blue in alpha component in swizzle for render

In pre-Broadwell devices, as B4G4R4A4 is not supported natively, we workaround it by using a format with a more complex swizzle, that uses blue in alpha component. Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/intel/vulkan/anv_private.h | 14 ++ 1 file c

[Mesa-dev] [PATCH] anv/pipeline: set ThreadDispatchEnable conditionally

Set 3DSTATE_WM/ThreadDispatchEnable bit on/off based on the same conditions as used in the GL version. Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/intel/vulkan/genX_pipeline.c | 49 +--- 1 file changed, 26 insertions(+), 23 del

Re: [Mesa-dev] [PATCH v2] nir/spirv/glsl450: rewrite atan2 to deal with infinities

On Sun, 2017-01-22 at 00:20 -0800, Francisco Jerez wrote: > "Juan A. Suarez Romero" <jasua...@igalia.com> writes: > > > Rewrite atan2(y,x) to cover (+/-)INF values. > > > > This fixes several test cases in Vulkan CTS > > (dEQP-VK.glsl.builtin.precis

Re: [Mesa-dev] [PATCH 1/2] spirv: handle OpUndef as part of the variable parsing pass

Reviewed-by: Juan A. Suarez Romero <jasua...@igalia.com> On Thu, 2017-01-26 at 17:08 +, Lionel Landwerlin wrote: > Looking at the following bit of SPIRV shader : > > ... > %zero= OpConstant %i32 0 > %ivec3_0 = OpConstantComposite %ivec3 %zero %zero %zero >

Re: [Mesa-dev] [PATCH 2/2] spirv: handle undefined components for OpVectorShuffle

On Thu, 2017-01-26 at 17:08 +, Lionel Landwerlin wrote: > Fixes: >dEQP-VK.spirv_assembly.instruction.compute.opspecconstantop.vector_related > > dEQP-VK.spirv_assembly.instruction.graphics.opspecconstantop.vector_related* > > Signed-off-by: Lionel Landwerlin

Re: [Mesa-dev] [PATCH 2/2] spirv: handle undefined components for OpVectorShuffle

On Fri, 2017-01-27 at 09:46 +, Lionel Landwerlin wrote: > > But what the test does is calling OpSpecConstantOp[2], which is the > > operation we are patching here. > > > > And according to the spec, "all Operands must be the s of other > > constant instructions", being constant instructions

Re: [Mesa-dev] [PATCH 1/8] mesa/program: Translate csel operation from GLSL IR.

Reviewed-by: Juan A. Suarez Romero <jasua...@igalia.com> On Tue, 2017-01-24 at 15:26 -0800, Francisco Jerez wrote: > This will be used internally by the GLSL front-end in order to > implement some built-in functions. Plumb it through MESA IR for > back-ends that rely on this t

Re: [Mesa-dev] [PATCH 2/8] glsl: Fix constant evaluation of the rcp op.

On Tue, 2017-01-24 at 17:06 -0800, Ian Romanick wrote: > On 01/24/2017 03:26 PM, Francisco Jerez wrote: > > Will avoid a regression in a future commit that introduces some > > additional rcp operations. > > When I converted GLSL IR to ir_expression_operation.py, I was careful to > keep all the

Re: [Mesa-dev] [PATCH 2/8] glsl: Fix constant evaluation of the rcp op.

On Tue, 2017-01-24 at 15:26 -0800, Francisco Jerez wrote: > Will avoid a regression in a future commit that introduces some > additional rcp operations. Reviewed-by: Juan A. Suarez Romero <jasua...@igalia.com> > --- > src/compiler/glsl/ir_expression_operation.py | 2 +- &g

Re: [Mesa-dev] [PATCH 3/8] glsl/ir_builder: Add rcp builder.

Reviewed-by: Juan A. Suarez Romero <jasua...@igalia.com> On Tue, 2017-01-24 at 15:26 -0800, Francisco Jerez wrote: > --- > src/compiler/glsl/ir_builder.cpp | 6 ++ > src/compiler/glsl/ir_builder.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/src/comp

Re: [Mesa-dev] [PATCH 7/8] glsl: Implement IEEE-compliant handling of atan2(±∞, ±∞).

Reviewed-by: Juan A. Suarez Romero <jasua...@igalia.com> On Tue, 2017-01-24 at 15:26 -0800, Francisco Jerez wrote: > --- > src/compiler/glsl/builtin_functions.cpp | 22 +- > 1 file changed, 21 insertions(+), 1 deletion(-) > > diff --gi

Re: [Mesa-dev] [PATCH 8/8] nir/spirv/glsl450: Implement IEEE-compliant handling of atan2(±∞, ±∞).

Reviewed-by: Juan A. Suarez Romero <jasua...@igalia.com> On Tue, 2017-01-24 at 15:26 -0800, Francisco Jerez wrote: > --- > src/compiler/spirv/vtn_glsl450.c | 22 +- > 1 file changed, 21 insertions(+), 1 deletion(-) > > diff --git a/src/compiler/spirv/v

[Mesa-dev] [PATCH] anv: handle VK_ERROR_OUT_OF_POOL_MEMORY_KHR error

This fixes dEQP-VK.api.descriptor_pool.out_of_pool_memory test Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/intel/vulkan/anv_util.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_util.c b/src/intel/vulkan/anv_util.c index 6408ac8..7045a78

Re: [Mesa-dev] [PATCH] anv: handle VK_ERROR_OUT_OF_POOL_MEMORY_KHR error

On Fri, 2017-01-27 at 16:26 +, Eric Engestrom wrote: > Thanks, this is correct, but Lionel Landwerlin already sent [1] a more > complete patch. Didn't realize :) Thanks! J.A. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org

Re: [Mesa-dev] [PATCH 1/2] anv: allow blue in alpha component in swizzle for render

On Wed, 2017-02-08 at 10:53 -0800, Nanley Chery wrote: > On Wed, Feb 08, 2017 at 06:42:44PM +0100, Juan A. Suarez Romero wrote: > > On Wed, 2017-02-08 at 09:27 -0800, Nanley Chery wrote: > > > On Wed, Feb 08, 2017 at 01:31:54PM +0100, Juan A. Suarez Romero wrote: > > >

Re: [Mesa-dev] [PATCH] intel/blorp: Swizzle clear colors on the CPU

s patch from https://lists.freedesktop.org/arc hives/mesa-dev/2017-February/143480.html There's a small typo also in a comment. Other than that, it is: Reviewed-by: Juan A. Suarez Romero <jasua...@igalia.com>. BTW, I've also sent a couple of patches to fix these tests: https://lists.freedeskt

Re: [Mesa-dev] [PATCH v2 15/20] i965/vec4: consider subregister offset in live variables

On Thu, 2017-02-09 at 15:56 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > Take in account the offset value when getting the var from r

Re: [Mesa-dev] [PATCH 2/2] anv/blorp: Don't sanitize the swizzle for blorp_clear

0, 0, level_width, level_height, > vk_to_isl_color(*pColor), color_write_disable); Great! With this patch, now we don't require my patch. Reviewed-by: Juan A. Suarez Romero <jasua...@igalia.com> ___ mesa-dev mailing l

Re: [Mesa-dev] [PATCH 1/2] intel/blorp: Swizzle clear colors on the CPU

Reviewed-by: Juan A. Suarez Romero <jasua...@igalia.com> On Thu, 2017-02-09 at 14:37 -0800, Jason Ekstrand wrote: > It's trivial to swizzle clear colors on the CPU, easily deals with the > hardware restrictions for render target swizzles, and makes swizzled > clears work

Re: [Mesa-dev] [PATCH] anv/formats: handle correctly multisamples in gen7

On Thu, 2017-02-16 at 12:37 +0100, Juan A. Suarez Romero wrote: > On Wed, 2017-02-15 at 10:24 -0800, Jason Ekstrand wrote: > > On Wed, Feb 15, 2017 at 10:09 AM, Juan A. Suarez Romero > > <jasua...@igalia.com> wrote: > > > According to Ivybridge PRM, Volume 4 Part

[Mesa-dev] [PATCH v2] anv/formats: handle correctly multisamples in gen7

and 4x multisampling (Jason) - Add SINT restriction in isl_format_supports_multisampling() (Jason) Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/intel/isl/isl_format.c | 22 +- src/intel/vulkan/anv_formats.c | 4 +++- 2 files changed, 24 inse

Re: [Mesa-dev] [PATCH] anv/formats: handle correctly multisamples in gen7

On Wed, 2017-02-15 at 10:24 -0800, Jason Ekstrand wrote: > On Wed, Feb 15, 2017 at 10:09 AM, Juan A. Suarez Romero <jasua...@igalia.com> > wrote: > > According to Ivybridge PRM, Volume 4 Part 1 p73, signed integer formats > > > > cannot be multisampled. > >

[Mesa-dev] [PATCH] anv/formats: handle correctly multisamples in gen7

-VK.pipeline.multisample.sampled_image.79x31_4.r16g16_sint.samples_8 dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r32g32b32a32_sfloat.samples_4 dEQP-VK.pipeline.multisample.sampled_image.79x31_4.r32g32b32a32_sfloat.samples_8 Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/intel/vulkan/anv_device.c

Re: [Mesa-dev] [PATCH] nir/spirv/glsl450: rewrite atan2 to deal with denorms / infinities

On Tue, 2017-01-17 at 15:07 -0800, Francisco Jerez wrote: > "Juan A. Suarez Romero" <jasua...@igalia.com> writes: > > > On Tue, 2017-01-17 at 11:34 +0100, Juan A. Suarez Romero wrote: > > > > The above does not necessarily sum to "we shouldn't fix it

[Mesa-dev] [PATCH v2] nir/spirv/glsl450: rewrite atan2 to deal with infinities

Rewrite atan2(y,x) to cover (+/-)INF values. This fixes several test cases in Vulkan CTS (dEQP-VK.glsl.builtin.precision.atan2.*) v2: do not flush denorms to 0 (jasuarez) --- src/compiler/spirv/vtn_glsl450.c | 48 +++- 1 file changed, 42 insertions(+), 6

[Mesa-dev] [PATCH v2] i965: check if HiZ buffer is available

Commit 42011be1e disabled HiZ when sharing depth buffer externally, which free HiZ buffer. But in emit_depth_packets() we use that buffer, which generates a crash in "piglit.spec.egl_khr_gl_image.egl_khr_gl_renderbuffer_image-clear-shared-image gl_depth_component24" test when running in Skylake.

Re: [Mesa-dev] [PATCH] nir/spirv/glsl450: rewrite atan2 to deal with denorms / infinities

On Tue, 2017-01-17 at 12:00 +0100, Juan A. Suarez Romero wrote: > On Tue, 2017-01-17 at 11:34 +0100, Juan A. Suarez Romero wrote: > > > The above does not necessarily sum to "we shouldn't fix it" but it > > > probably does mean it's low-priority at

Re: [Mesa-dev] [PATCH] i965: Enable OpenGL 4.5 on Haswell.

On Fri, 2017-01-13 at 22:53 -0800, Kenneth Graunke wrote: > Everything is in place and the test results look solid. > > Signed-off-by: Kenneth Graunke > --- > src/mesa/drivers/dri/i965/intel_extensions.c | 2 +- > src/mesa/drivers/dri/i965/intel_screen.c | 2 +- > 2

[Mesa-dev] [PATCH] nir/spirv/glsl450: rewrite atan2 to deal with denorms / infinities

Rewrite atan2(y,x) to cover (+/-)INF values. Also, in case either 'y' or 'x' is a denorm value, flush it to 0 at the very beginning. The reason is that in other case, the hardware will do the flush in some of the steps, but not in order. So we end up handling in some steps a denorm value and in

[Mesa-dev] [PATCH] i965: check if HiZ buffer is available

Commit 42011be1e disabled HiZ when sharing depth buffer externally, which free HiZ buffer. But in emit_depth_packets() we use that buffer, which generates a crash in "piglit.spec.egl_khr_gl_image.egl_khr_gl_renderbuffer_image-clear-shared-image gl_depth_component24" test when running in Skylake.

Re: [Mesa-dev] [PATCH] nir/spirv/glsl450: rewrite atan2 to deal with denorms / infinities

On Tue, 2017-01-17 at 11:34 +0100, Juan A. Suarez Romero wrote: > > The above does not necessarily sum to "we shouldn't fix it" but it probably > > does mean it's low-priority at best and we need to be careful. > > > > Looking a bit into the math of atan2,

Re: [Mesa-dev] [PATCH] nir/spirv/glsl450: rewrite atan2 to deal with denorms / infinities

l see this all layed out > in a horrifying amount of detail (somewhere around a dozen different cases). > > Yes, originally I only flushed 'x'. But then also flushed 'y' to keep coherence. But didn't think about that corner case you mention. I think we can remove the flush to 0 in 'y'.

Re: [Mesa-dev] [PATCH v2] i965: check if HiZ buffer is available

On Thu, 2017-01-19 at 13:23 -0800, Chad Versace wrote: > On Wed 18 Jan 2017, Juan A. Suarez Romero wrote: > > Commit 42011be1e disabled HiZ when sharing depth buffer externally, > > which free HiZ buffer. > > > > But in emit_depth_packets() we use that buff

Re: [Mesa-dev] [PATCH] i965: Delete pending CCS and HiZ ops in intel_miptree_make_shareable()

t's just a workaround for the real issue. > The real issue is that intel_miptree_make_shareable() didn't fully > disable HiZ. > Reviewed-by: Juan A. Suarez Romero <jasua...@igalia.com> > Please give some reviewed-by's and tested-by's. > > On Wed 04 Jan 2017,

[Mesa-dev] [PATCH] anv: add support for allocating more than 1 block of memory

Current Anv allocator assign memory in terms of a fixed block size. But there can be cases where this block is not enough for a memory request, and thus several blocks must be assigned in a row. This commit adds support for specifying how many blocks of memory must be assigned. This fixes a

[Mesa-dev] [PATCH] glsl: do not show locp information if it is not available

Ignore source file, line number and column in glcpp_error() and glcpp_warning() if those are not available. It fixes 4 piglit tests: spec/glsl-1.10/compiler/version-0.frag: crash pass spec/glsl-1.10/compiler/version-0.vert: crash pass spec/glsl-es-3.00/compiler/version-0.frag: crash pass

Re: [Mesa-dev] [PATCH] glcpp: initializes version to -1

On Tue, 2016-11-08 at 14:19 +0100, Karol Herbst wrote: > well I don't care either way, maybe the spec does say anything about > it. I was re-reading GLSL 1.10 spec about #version directive. #version follows the same convention as __VERSION__ For __VERSION___, spec says "will substitute a

Re: [Mesa-dev] [PATCH] glcpp: initializes version to -1

On Sat, 2016-11-05 at 10:48 +0100, Karol Herbst wrote: > "#version 0512": 0:1(10): error: GLSL 3.30 is not supported. > Supported > versions are: 1.10, 1.20, 1.30, 1.00 ES, and 3.00 ES > > so the issue with this would be, that "0512" is parsed as 3.30, which > isn't right either, but the current

[Mesa-dev] [PATCH] i965/vec4: skip registers already marked as no_spill

Do not evaluate spill costs for registers that were already marked as no_spill. --- src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp

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