Okay, I will take care of that. Thanks for reviewing my patches Ian.
On 08/02/2018 11:33 AM, Ian Romanick wrote:
> This patch should go first in the series. With that changed, this patch is
>
> Reviewed-by: Ian Romanick
>
> On 08/01/2018 08:31 PM, Sagar Ghuge wrote:
>>
I have few comments below, I might be wrong about those but except that
this patch looks good to me. I checked it against Khronos headers.
On 08/01/2018 11:34 AM, Marek Olšák wrote:
From: Marek Olšák
---
include/GL/glcorearb.h | 68 --
include/GL/glext.h | 77
if statement should check return value
of drmSyncobjImportSyncFile function.
Fixes CID 1438127
Signed-off-by: Sagar Ghuge
---
src/gallium/drivers/v3d/v3d_fence.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/v3d/v3d_fence.c
b/src/gallium/drivers/v3d
off-by: Sagar Ghuge
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 21 ---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/dri/i
enable _mesa_PushAttrib() and _mesa_PopAttrib()
to handle GL_DEPTH_CLAMP_NEAR_AMD and
GL_DEPTH_CLAMP_FAR_AMD tokens.
Signed-off-by: Sagar Ghuge
---
src/mesa/main/attrib.c | 16
1 file changed, 16 insertions(+)
diff --git a/src/mesa/main/attrib.c b/src/mesa/main/attrib.c
index
Signed-off-by: Sagar Ghuge
---
src/mesa/main/get.c | 1 +
src/mesa/main/get_hash_params.py | 5 +
2 files changed, 6 insertions(+)
diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index db0079beb5..b310f014b7 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
Add some basic types and storage for the
AMD_depth_clamp_separate extension.
Signed-off-by: Sagar Ghuge
---
include/GL/glcorearb.h | 2 ++
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/mtypes.h | 9 +
3 files changed, 12 insertions(+)
diff --git a/include/GL
Signed-off-by: Sagar Ghuge
---
src/mapi/glapi/gen/AMD_depth_clamp_separate.xml | 15 +++
src/mapi/glapi/gen/Makefile.am | 1 +
src/mapi/glapi/gen/gl_API.xml | 3 +++
src/mapi/glapi/gen/meson.build | 1 +
4 files changed, 20
_mesa_set_enable() and _mesa_IsEnabled() extended
to accept new two tokens GL_DEPTH_CLAMP_NEAR_AMD and
GL_DEPTH_CLAMP_FAR_AMD.
Signed-off-by: Sagar Ghuge
---
src/mesa/main/enable.c | 44 +-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/src
INTEL_DEBUG=hex prints 32 bit hex value
and due to endianness of CPU byte order is
reversed. In order to disassemble binary
files, print each byte instead of 32 bit hex
value.
Signed-off-by: Sagar Ghuge
---
src/intel/compiler/brw_eu.c | 24
1 file changed, 16 insertions
018 at 2:44 PM, Ian Romanick wrote:
>> On 08/02/2018 11:30 AM, Ian Romanick wrote:
>>> On 08/01/2018 08:31 PM, Sagar Ghuge wrote:
>>>> Add some basic types and storage for the
>>>> AMD_depth_clamp_separate extension.
>>
>> I mentioned this on patch 5
On 08/13/2018 03:43 PM, Ian Romanick wrote:
> On 08/09/2018 01:14 PM, Sagar Ghuge wrote:
>>
>>
>> On 08/09/2018 01:09 PM, Marek Olšák wrote:
>>> On Wed, Aug 1, 2018 at 11:31 PM, Sagar Ghuge wrote:
>>>> enable _mesa_PushAttrib() and _mesa_PopAttri
Adds a new i965 instruction disassemble tool
Signed-off-by: Sagar Ghuge
---
src/intel/Makefile.tools.am | 15 +++
src/intel/tools/i965_disasm.c | 202 ++
src/intel/tools/i965_disasm.h | 46
src/intel/tools/meson.build | 11 ++
4 files changed, 274
On 08/09/2018 01:09 PM, Marek Olšák wrote:
> On Wed, Aug 1, 2018 at 11:31 PM, Sagar Ghuge wrote:
>> enable _mesa_PushAttrib() and _mesa_PopAttrib()
>> to handle GL_DEPTH_CLAMP_NEAR_AMD and
>> GL_DEPTH_CLAMP_FAR_AMD tokens.
>>
>> Signed-off-by: Sagar Ghuge
>&
instructions hex value.
(Matt Turner)
Signed-off-by: Sagar Ghuge
---
src/intel/compiler/brw_eu.c | 48 -
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index 6ef0a6a577..ab87ae90e1 100644
nsi driver. Do you have
> a Mesa branch with the final patches?
>
> Marek
>
> On Mon, Aug 13, 2018 at 5:35 PM Sagar Ghuge wrote:
>>
>> Hi everyone,
>>
>> I am kind of stuck on this part actually. I don't have
>> latest AMD graphics card to test follow
On 08/20/2018 11:06 AM, Matt Turner wrote:
> Cool. This looks pretty good to me. A few comments inline.
>
> On Wed, Aug 15, 2018 at 2:00 PM Sagar Ghuge wrote:
>>
>> INTEL_DEBUG=hex prints 32 bit hex value
>> and due to endianness of CPU byte order is
>> reverse
Thanks for reviewing the patch. I will make changes and send v2 accordingly.
On 08/20/2018 11:34 AM, Matt Turner wrote:
> On Thu, Aug 16, 2018 at 1:51 PM Sagar Ghuge wrote:
>>
>> Adds a new i965 instruction disassemble tool
>
> This looks very good. A few comments about
Adds a new i965 instruction disassemble tool
v2: 1) fix a few nits (Matt Turner)
2) Remove i965_disasm header (Matt Turner)
Signed-off-by: Sagar Ghuge
---
src/intel/Makefile.tools.am | 14 +++
src/intel/tools/i965_disasm.c | 199 ++
src/intel/tools
Signed-off-by: Sagar Ghuge
Reviewed-by: Ian Romanick
---
src/mapi/glapi/gen/AMD_depth_clamp_separate.xml | 15 +++
src/mapi/glapi/gen/Makefile.am | 1 +
src/mapi/glapi/gen/gl_API.xml | 3 +++
src/mapi/glapi/gen/meson.build | 1
at
DepthClampNear and DepthClampFar, as suggested by Ian Romanick.
Signed-off-by: Sagar Ghuge
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 11 ++
src/mesa/main/attrib.c| 21 ---
src/mesa/main/enable.c| 9 +---
src/mesa/main
_mesa_set_enable() and _mesa_IsEnabled() extended to accept new two
tokens GL_DEPTH_CLAMP_NEAR_AMD and GL_DEPTH_CLAMP_FAR_AMD.
Signed-off-by: Sagar Ghuge
---
src/mesa/main/enable.c | 36
1 file changed, 36 insertions(+)
diff --git a/src/mesa/main/enable.c b
rate
This series is also available as a branch on GitLab:
https://gitlab.freedesktop.org/sagarghuge/mesa/commits/ext_amd_depth_clamp_sep
Sagar Ghuge (7):
glapi: define AMD_depth_clamp_separate
mesa: Add types for AMD_depth_clamp_separate.
mesa: Add support for AMD_depth_clamp_separate
mesa:
Add some basic types and storage for the AMD_depth_clamp_separate
extension.
Signed-off-by: Sagar Ghuge
---
include/GL/glcorearb.h | 2 ++
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/mtypes.h | 3 +++
3 files changed, 6 insertions(+)
diff --git a/include/GL
Signed-off-by: Sagar Ghuge
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index f1c3aeff13..f07d3ab601 100644
--- a/src/mesa/drivers/dri/i965
Signed-off-by: Sagar Ghuge
Reviewed-by: Ian Romanick
---
src/mesa/main/get.c | 1 +
src/mesa/main/get_hash_params.py | 5 +
2 files changed, 6 insertions(+)
diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index 6b2e3637e6..92020e29a9 100644
--- a/src/mesa/main/get.c
off-by: Sagar Ghuge
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 23 +++
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index dc54cb67af..4e978bed91 100644
--- a/
On 08/21/2018 09:28 PM, Marek Olšák wrote:
> On Tue, Aug 21, 2018 at 8:02 PM Sagar Ghuge wrote:
>>
>> _mesa_set_enable() and _mesa_IsEnabled() extended to accept new two
>> tokens GL_DEPTH_CLAMP_NEAR_AMD and GL_DEPTH_CLAMP_FAR_AMD.
>>
>> Signed-off-by: Saga
On 08/22/2018 04:31 PM, Marek Olšák wrote:
> On Wed, Aug 22, 2018 at 5:52 PM Sagar Ghuge wrote:
>>
>> Enable _mesa_PushAttrib() and _mesa_PopAttrib() to handle
>> GL_DEPTH_CLAMP_NEAR_AMD and GL_DEPTH_CLAMP_FAR_AMD tokens.
>>
>> Remove DepthClamp, because DepthC
Thank you for reviewing the patch.
On 08/23/2018 06:17 PM, Marek Olšák wrote:
> On Thu, Aug 23, 2018 at 8:18 PM, Sagar Ghuge wrote:
>> Enable _mesa_PushAttrib() and _mesa_PopAttrib() to handle
>> GL_DEPTH_CLAMP_NEAR_AMD and GL_DEPTH_CLAMP_FAR_AMD tokens.
>>
>>
separately for near and far Z clipping plane (Marek
Olsak)
v3: Clamp raster position zw to the range [min(n,f), 0] for near plane
and [0, max(n,f)] for far plane (Marek Olsak)
v4: Use MIN2 and MAX2 instead of CLAMP (Marek Olsak)
Signed-off-by: Sagar Ghuge
Reviewed-by: Ian Romanick
separately for near and far Z clipping plane (Marek
Olsak)
v3: Clamp raster position zw to the range [min(n,f), 0] for near plane
and [0, max(n,f)] for far plane (Marek Olsak)
Signed-off-by: Sagar Ghuge
Reviewed-by: Ian Romanick
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 11
Signed-off-by: Sagar Ghuge
---
docs/relnotes/18.3.0.html | 1 +
1 file changed, 1 insertion(+)
diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html
index 71fb41ca86..6e5e3ef93b 100644
--- a/docs/relnotes/18.3.0.html
+++ b/docs/relnotes/18.3.0.html
@@ -51,6 +51,7 @@ Note: some
On 08/13/2018 03:52 PM, Ian Romanick wrote:
> On 08/09/2018 01:09 PM, Marek Olšák wrote:
>> On Wed, Aug 1, 2018 at 11:31 PM, Sagar Ghuge wrote:
>>> enable _mesa_PushAttrib() and _mesa_PopAttrib()
>>> to handle GL_DEPTH_CLAMP_NEAR_AMD and
>>> GL_DEPTH_CLAM
Hey Matt,
Thanks for reviewing the patch.
On 08/27/2018 11:06 AM, Matt Turner wrote:
> On Mon, Aug 20, 2018 at 3:13 PM Sagar Ghuge wrote:
>>
>> Adds a new i965 instruction disassemble tool
>>
>> v2: 1) fix a few nits (Matt Turner)
>> 2) Remove i965_disasm
Add some basic types and storage for the AMD_depth_clamp_separate
extension.
v2: 1) Drop unnecessary definition (Marek Olsak)
2) Expose extension in compatibility profile (Marek Olsak)
Signed-off-by: Sagar Ghuge
---
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/mtypes.h
_mesa_set_enable() and _mesa_IsEnabled() extended to accept new two
tokens GL_DEPTH_CLAMP_NEAR_AMD and GL_DEPTH_CLAMP_FAR_AMD.
v2: Remove unnecessary parentheses (Marek Olsak)
Signed-off-by: Sagar Ghuge
---
src/mesa/main/enable.c | 36
1 file changed, 36
separately for near and far Z clipping plane (Marek
Olsak)
Signed-off-by: Sagar Ghuge
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 11 ++--
src/mesa/main/attrib.c| 40 +++---
src/mesa/main/enable.c| 9 ++-
src/mesa/main/get.c
Use better coding style (Ian Romanick)
Signed-off-by: Sagar Ghuge
Reviewed-by: Ian Romanick
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 20 ++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/
Please ignore this patch. Subject contains extra bracket.
I will resend the patch.
On 08/22/2018 12:54 PM, Sagar Ghuge wrote:
> Add some basic types and storage for the AMD_depth_clamp_separate
> extension.
>
> v2: 1) Drop unnecessary definition (Marek Olsak)
> 2) E
Add some basic types and storage for the AMD_depth_clamp_separate
extension.
v2: 1) Drop unnecessary definition (Marek Olsak)
2) Expose extension in compatibility profile (Marek Olsak)
Signed-off-by: Sagar Ghuge
---
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/mtypes.h
instructions hex value.
(Matt Turner)
v3: Fix line wrap at correct length
Signed-off-by: Sagar Ghuge
---
src/intel/compiler/brw_eu.c | 47 +++--
1 file changed, 30 insertions(+), 17 deletions(-)
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler
The extension requires at least OpenGL 3.0 and
OpenGL ES 3.0.
Fixes two ext_base_instance tests:
arb_base_instance-baseinstance-doesnt-affect-gl-instance-id_gles3
arb_base_instance-drawarrays_gles3
Signed-off-by: Sagar Ghuge
---
src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
1 file
-by: Sagar Ghuge
---
src/intel/Makefile.tools.am | 14 +++
src/intel/tools/i965_disasm.c | 182 ++
src/intel/tools/meson.build | 11 ++
3 files changed, 207 insertions(+)
create mode 100644 src/intel/tools/i965_disasm.c
diff --git a/src/intel/Makefile.tools.am b/src
Signed-off-by: Sagar Ghuge
---
src/intel/tools/aubinator.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 55672fa073..ef0f7650b1 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools
Signed-off-by: Sagar Ghuge
---
src/intel/common/gen_decoder.c | 4
1 file changed, 4 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index dbd060d53c..c44b8f060d 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
construct correct gen xml filename when we try to load hardware xml
description from a given path
Signed-off-by: Sagar Ghuge
---
src/intel/common/gen_decoder.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel
Hi Lionel,
Thanks for reviewing patches and comments.
On 09/05/2018 10:29 AM, Lionel Landwerlin wrote:
> On 05/09/2018 18:19, Sagar Ghuge wrote:
>> Signed-off-by: Sagar Ghuge
>> ---
>> src/intel/common/gen_decoder.c | 4
>> 1 file changed, 4 deletions(-)
&
On 09/05/2018 11:06 AM, Lionel Landwerlin wrote:
> On 05/09/2018 19:02, Sagar Ghuge wrote:
>> Hi Lionel,
>>
>> Thanks for reviewing patches and comments.
>>
>> On 09/05/2018 10:29 AM, Lionel Landwerlin wrote:
>>> On 05/09/2018 18:19, Sagar Gh
.
I am still getting familar with tool so please let me know if I
misunderstood things while fixing the problem.
Sagar Ghuge (4):
intel/decoder: add gen_spec_init method
intel/decoder: Avoid freeing invalid pointer
intel/decoder: construct correct xml filename
intel: aubinator: Fix memory
Initialize gen_spec instance properly when loading hardware xml
description from specifc directory to avoid segmentation fault.
Signed-off-by: Sagar Ghuge
---
src/intel/common/gen_decoder.c | 51 +++---
1 file changed, 35 insertions(+), 16 deletions(-)
diff --git
Initialize gen_spec instance properly when loading hardware xml
description from specifc directory to avoid segmentation fault.
v2: correct function definition (Lionel Landwerlin)
Signed-off-by: Sagar Ghuge
Reviewed-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 51
construct correct gen xml filename when we try to load hardware xml
description from a given path
v2: remove temporary variable (Francesco Ansanelli)
Signed-off-by: Sagar Ghuge
Reviewed-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 15 +++
1 file changed, 7 insertions
v2: Free ctx.spec if error while reading genxml (Lionel Landwerlin)
Signed-off-by: Sagar Ghuge
---
src/intel/common/gen_decoder.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index d4db8b89cc
On 09/06/2018 02:39 AM, Lionel Landwerlin wrote:
> On 06/09/2018 05:12, Sagar Ghuge wrote:
>> v2: Free ctx.spec if error while reading genxml (Lionel Landwerlin)
>>
>> Signed-off-by: Sagar Ghuge
>> ---
>> src/intel/common/gen_decoder.c | 15 ---
&
v2: Free ctx.spec if error while reading genxml (Lionel Landwerlin)
v3: Handle case where genxml is empty (Lionel Landwerlin)
Signed-off-by: Sagar Ghuge
---
src/intel/common/gen_decoder.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/src/intel/common
Please ignore this patch.
On 09/06/2018 11:33 AM, Sagar Ghuge wrote:
> v2: Free ctx.spec if error while reading genxml (Lionel Landwerlin)
>
> v3: Handle case where genxml is empty (Lionel Landwerlin)
>
> Signed-off-by: Sagar Ghuge
> ---
> src/intel/comm
v2: Free ctx.spec if error while reading genxml (Lionel Landwerlin)
v3: Handle case where genxml is empty (Lionel Landwerlin)
Signed-off-by: Sagar Ghuge
---
src/intel/common/gen_decoder.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/src/intel/common
Hi Marek,
Thanks for reviewing but I don't have commit rights yet. :(
-- Sagar
On 08/29/2018 02:34 PM, Marek Olšák wrote:
> Looks good. You can push this without an Rb.
>
> Marek
>
> On Tue, Aug 28, 2018 at 5:53 PM, Sagar Ghuge wrote:
>> Signed-off-by: Sagar Ghuge
>
avoid misinterpretation of encoded immediate values in instruction and
disassembled output.
Signed-off-by: Sagar Ghuge
---
While encoding the immediate floating point values in instruction we use
values upto precision 8, but while disassembling, we print precision to
6 places, which round up
Signed-off-by: Sagar Ghuge
---
src/intel/compiler/brw_eu_emit.c | 36
1 file changed, 27 insertions(+), 9 deletions(-)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 0cbc682ebc..a6b45fcb1a 100644
--- a/src/intel/compiler
Thank you for reviewing the patch.
On 10/22/18 5:02 AM, Samuel Iglesias Gonsálvez wrote:
>
>
> On 20/10/18 3:25, Sagar Ghuge wrote:
>> To have uniform behavior while disassembling send(c) instruction use
>> register type of unsigned doubleword for src1 when message descr
On 10/22/18 10:34 AM, Matt Turner wrote:
> On Fri, Oct 5, 2018 at 11:15 AM Sagar Ghuge wrote:
>>
>> avoid misinterpretation of encoded immediate values in instruction and
>> disassembled output.
>>
>> Signed-off-by: Sagar Ghuge
>> ---
>> While
On 10/22/18 10:14 AM, Matt Turner wrote:
> On Tue, Oct 16, 2018 at 4:57 PM Sagar Ghuge wrote:
>>
>
> Let's describe a little of why we're doing this and how we found it.
> If I recall correctly, we set a NOP (XYZW) swizzle on 3-src
> instructions, except we set a
To have uniform behavior while disassembling send(c) instruction use
register type of unsigned doubleword for src1 when message descriptor is
immediate value. Bspec does not specifiy anything for src1 immediate
default type.
Signed-off-by: Sagar Ghuge
---
src/intel/compiler/brw_eu_emit.c
in instruction
and disassembled output, print hex representation along with floating
point value which can be used by assembler in future.
Signed-off-by: Sagar Ghuge
---
src/intel/compiler/brw_disasm.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/intel
While disassembling send(c) instruction print message descriptor as
immediate source operand along with message descriptor. This allows
assembler to read immediate source operand and set bits accordingly.
Signed-off-by: Sagar Ghuge
---
src/intel/compiler/brw_disasm.c | 9 +++--
1 file
ries/19945/
> * Always print message descriptor and SFID for SEND instructions:
> https://patchwork.freedesktop.org/patch/223750/
>
> ?
>
> - Eero
>
> On 10/25/18 2:25 AM, Sagar Ghuge wrote:
>> While disassembling send(c) instruction print message descr
> On Wednesday, 24 October 2018 22:27:27 (CEST) Sagar Ghuge wrote:
>> While encoding the immediate floating point values in instruction we use
>> values upto precision 9, but while disassembling, we print precision to
>> 6 places, which round up the value and gives wrong interpret
On 10/25/18 12:55 AM, Samuel Iglesias Gonsálvez wrote:
> On Thursday, 25 October 2018 1:25:53 (CEST) Sagar Ghuge wrote:
>> While disassembling send(c) instruction print message descriptor as
>> immediate source operand along with message descriptor. This allows
>> assemb
For 3 source operand instruction with access mode align16, channel
select does not apply when RepCtrl is enabled, So setting it to
BRW_SWIZZLE_ seems more appropriate choice.
Signed-off-by: Sagar Ghuge
---
src/intel/compiler/brw_eu_emit.c | 19 ++-
1 file changed, 18
While disassembling the predicate always print flag subregister number
to keep grammar same across the generation for assembler tool.
Signed-off-by: Sagar Ghuge
---
src/intel/compiler/brw_disasm.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/intel/compiler
Both BRW_SFID_SAMPLER and GEN6_SFID_DATAPORT_SAMPLER_CACHE are getting
disassembled as "sampler", which is misleading for assembler tool.
Signed-off-by: Sagar Ghuge
---
src/intel/compiler/brw_disasm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/inte
Tested-by: Sagar Ghuge
On 11/8/18 5:26 PM, Francisco Jerez wrote:
> This can occur during payload setup of SIMD-split send message
> instructions, which can lead to the emission of header setup
> instructions with a non-zero channel group and fixed SIMD width. Such
> instructions
Ping.
On 9/6/18 12:37 PM, Sagar Ghuge wrote:
> v2: Free ctx.spec if error while reading genxml (Lionel Landwerlin)
>
> v3: Handle case where genxml is empty (Lionel Landwerlin)
>
> Signed-off-by: Sagar Ghuge
> ---
> src/intel/common/gen_decoder.c | 18 +-
When RepCtrl is set, the swizzle field is ignored by the hardware. In
order to ensure a 1-to-1 correspondence between the human-readable
disassembly and the binary instruction encoding always set the swizzle
to (all zeros) when it is unused due to RepCtrl
Signed-off-by: Sagar Ghuge
Reviewed
While disassembling the predicate always print flag subregister number
to keep grammar same across the generation for assembler tool.
v2: Club consecutive format calls (Matt Turner)
Signed-off-by: Sagar Ghuge
---
src/intel/compiler/brw_disasm.c | 13 ++---
1 file changed, 6 insertions
Print quad value same as unsigned quad so that we can distinguish in
between quater control disassembled values for e.g 1/2/3[Q] and
immediate quad value for e.g 1Q. This allows round-tripping through the
assembler/disassembler.
Signed-off-by: Sagar Ghuge
---
src/intel/compiler/brw_disasm.c | 2
Please ignore this patch. Somehow my emails are getting delayed.
This is just a duplicate of the other patch which is on mailing list.
On 3/24/19 10:19 AM, Sagar Ghuge wrote:
> From: Sagar Ghuge
>
> Print quad value same as unsigned quad so that we can distinguish in
> between qu
From: Sagar Ghuge
Print quad value same as unsigned quad so that we can distinguish in
between quater control disassembled values for e.g 1/2/3[Q] and
immediate quad value for e.g 1Q. This allows round-tripping through the
assembler/disassembler.
Signed-off-by: Sagar Ghuge
---
src/intel
Signed-off-by: Sagar Ghuge
---
src/intel/compiler/brw_disasm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index efca3e2ce7d..440e51faa61 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel
If predicate control is set to None, then in that case we can simply set
flag reg/subreg number to zero. This allows round-tripping through the
assembler/disassembler
Signed-off-by: Sagar Ghuge
---
src/intel/compiler/brw_eu_emit.c| 7 +++
src/intel/compiler/brw_fs_generator.cpp | 1
For the W or UW (signed or unsigned word) source types, the 16-bit value
must be replicated in both the low and high words of the 32-bit
immediate value.
Signed-off-by: Sagar Ghuge
---
src/intel/compiler/brw_fs.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/intel/compiler
Thank you for reviewing the patch.
On 3/26/19 4:46 PM, Matt Turner wrote:
> On Tue, Mar 26, 2019 at 3:35 PM Sagar Ghuge wrote:
>>
>> For the W or UW (signed or unsigned word) source types, the 16-bit value
>> must be replicated in both the low and high words of the 32-b
Reviewed-by: Sagar Ghuge
On 3/12/19 3:34 AM, Eleni Maria Stea wrote:
> Enabled the VK_EXT_sample_locations for Intel Gen >= 7.
>
> v2: Replaced device.info->gen >= 7 with True, as Anv doesn't support
> anything below Gen7. (Lionel Landwerlin)
> ---
> src/intel/v
Reviewed-by: Sagar Ghuge
On 3/12/19 3:34 AM, Eleni Maria Stea wrote:
> Added the VK_EXT_sample_locations to the anv_extensions.py list to
> generate the related entrypoints.
> ---
> src/intel/vulkan/anv_extensions.py | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --g
Reviewed-by: Sagar Ghuge
On 3/12/19 3:34 AM, Eleni Maria Stea wrote:
> In src/intel/vulkan/genX_blorp_exec.c we included the file:
> common/gen_sample_positions.h but not use it. Removed.
> ---
> src/intel/vulkan/genX_blorp_exec.c | 1 -
> 1 file changed, 1 deletion(-)
>
Reviewed-by: Sagar Ghuge
On 3/12/19 4:21 PM, Jason Ekstrand wrote:
> We don't care about the information but there's no sense in throwing a
> debug warning about it. It's harmless but annoying to users.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109984
>
Thanks for reviewing the patch.
On 4/8/19 10:34 AM, Anuj Phogat wrote:
> On Wed, Mar 27, 2019 at 4:05 PM Sagar Ghuge wrote:
>>
>> If predicate control is set to None, then in that case we can simply set
>> flag reg/subreg number to zero. This allows round-tripping thr
PixelBits = 4;
> +
> + props->variableSampleLocations = false;
Just for consistency, doesn't make any difference but can we use
VK_FALSE instead of false.
with or without the fix, this patch is:
Reviewed-by: Sagar Ghuge
> +
> + break;
> + }
> +
>
ixelBits = 4;
> +
> + props->variableSampleLocations = false;
Just for consistency, doesn't make any difference but can we use
VK_FALSE instead of false.
with or without the fix, this patch is:
Reviewed-by: Sagar Ghuge
> +
> + break;
> + }
> +
>
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