Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_tex_validate.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c
b/src/mesa/drivers/dri/intel/intel_tex_validate.c
index 4012400
would always choose mag filter(GL_LINEAR) here since MIPCnt was
set to 0 zero, then would make LOD be zero. Then according the formula:
MagMode = (LOD - Base = 0)
Thus hardware choose Mag filter.
This would fix all oglc filtercubemin subcase fail
Signed-off-by: Yuanhan Liu yuanhan
On Tue, Nov 01, 2011 at 05:57:36PM +0800, Yuanhan Liu wrote:
According to bspec, MIPCnt(was set to intelObj-_MaxLevel) was used for
min/mag filter mode determination. For a normal case with no mipmap like
this:
glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_NEAREST
_mesa_validate_pbo_teximage may fail, result the pbo not mapped.
If then unmap function is called, an abort would be triggered by
assert(obj-Pointer).
This would fix: https://bugs.freedesktop.org/show_bug.cgi?id=42268
NOTE: this is just for 7.11 stable branch
Signed-off-by: Yuanhan Liu yuanhan
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/texparam.c | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c
index dc5ee33..b031e18 100644
--- a/src/mesa/main/texparam.c
+++ b/src/mesa
is legal for glTexParameterf(v)
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/texparam.c | 27 +++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c
index b031e18..2ebf383 100644
-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/renderbuffer.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mesa/main/renderbuffer.c b/src/mesa/main/renderbuffer.c
index 70011e6..b6eea79 100644
--- a/src/mesa/main/renderbuffer.c
+++ b/src/mesa
glRenderbufferStorage man page says:
GL_INVALID_VALUE is generated if either of width or height is negative,
or greater than the value of GL_MAX_RENDERBUFFER_SIZE.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/fbobject.c |4 ++--
1 files changed, 2 insertions
remove another long if condition test. I don't feel a strong need of
this patch. But for it make the code a little simpler(I do think so),
I send it out.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/swrast/s_texfilter.c | 22 +-
1 files changed, 9
running the full round of tests, and they've
found one or two regressions (e.g., bug #42268).
Hi Ian, I sent out a patch[0] to fix this issue. Did you see that?
[0]: [PATCH] intel: don't call unmap pbo if pbo is not mapped
Thanks,
Yuanhan Liu
Once those get
resolved, I don't think there's
On Wed, Nov 02, 2011 at 02:18:46PM -0700, Eric Anholt wrote:
On Wed, 2 Nov 2011 11:12:07 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
On Tue, Nov 01, 2011 at 05:57:36PM +0800, Yuanhan Liu wrote:
According to bspec, MIPCnt(was set to intelObj-_MaxLevel) was used for
min/mag
On Wed, Nov 02, 2011 at 07:23:31AM -0600, Brian Paul wrote:
On 11/02/2011 03:56 AM, Yuanhan Liu wrote:
glRenderbufferStorage man page says:
GL_INVALID_VALUE is generated if either of width or height is negative,
or greater than the value of GL_MAX_RENDERBUFFER_SIZE.
Signed-off
Don't call set_unfiform_initializers if link failed, or it would trigger
a GL_INVALID_OPERATION error. That's not an expected behavior of
glLinkProgram function.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/program/ir_to_mesa.cpp |4 +++-
1 files changed, 3 insertions
On Thu, Nov 03, 2011 at 10:16:06AM +0800, Yuanhan Liu wrote:
On Wed, Nov 02, 2011 at 02:18:46PM -0700, Eric Anholt wrote:
On Wed, 2 Nov 2011 11:12:07 +0800, Yuanhan Liu
yuanhan@linux.intel.com wrote:
On Tue, Nov 01, 2011 at 05:57:36PM +0800, Yuanhan Liu wrote:
According to bspec
On Sat, Nov 12, 2011 at 12:54:37PM -0800, Ian Romanick wrote:
On 11/09/2011 01:10 AM, Yuanhan Liu wrote:
The original comments just tell me that I'm doing wrong. Here I sent a
patch for comments and explanation, and I may then try to write the code
to process those built-in uniform variables
On Fri, Nov 11, 2011 at 08:53:13AM -0800, Eric Anholt wrote:
On Thu, 3 Nov 2011 10:16:06 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
On Wed, Nov 02, 2011 at 02:18:46PM -0700, Eric Anholt wrote:
On Wed, 2 Nov 2011 11:12:07 +0800, Yuanhan Liu
yuanhan@linux.intel.com wrote
.pdf, we can skip
attenuation calculation if Ppli.w == 0.
This would fix all the intel oglc l_sed fail subcases and introduces no
intel oglc regressions.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/ffvertex_prog.c | 115 ++---
1 files
Make sure all lighting tables are updated before using the table to
calculate something, say using _SpotExpTable to calculate
_VP_inf_spot_attenuation.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/light.c |3 +++
1 files changed, 3 insertions(+), 0 deletions
On Tue, Nov 15, 2011 at 07:26:52AM -0700, Brian Paul wrote:
On 11/15/2011 12:51 AM, Yuanhan Liu wrote:
Make sure all lighting tables are updated before using the table to
calculate something, say using _SpotExpTable to calculate
_VP_inf_spot_attenuation.
Signed-off-by: Yuanhan Liuyuanhan
On Tue, Nov 15, 2011 at 07:22:29AM -0700, Brian Paul wrote:
On 11/15/2011 12:11 AM, Yuanhan Liu wrote:
glspec doesn't say that we should skip the attenuation and spot
calculation for infinite light(Ppli.w == 0). Instead, it gives a same
formula to do the light calculation for both finite light
The two patches tries to fix an issue that happened while calling glDrawPixels
with texture enabled.
Here I attached a piglit testcase for this issue.
Yuanhan Liu (2):
swrast: simplify the prototype of function texture_combine
swrast: fix unmatched span-array-ChanType
src/mesa/swrast
Parameter n and rgbaChan are both from structure span, thus using span
as paramter to simplify the prototype. Function texture_combine is only
used by _swrast_texture_span, so I guess it's safe to do so.
This patch is mainly for the next patch.
Signed-off-by: Yuanhan Liu yuanhan
texture_combine converts the result rgba to CHAN_TYPE from FLOAT. At the
same time, make sure the span-array-ChanType is changed, too.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/swrast/s_texcombine.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff
On Fri, Nov 18, 2011 at 03:38:46PM +0800, Yuanhan Liu wrote:
The two patches tries to fix an issue that happened while calling glDrawPixels
with texture enabled.
Here I attached a piglit testcase for this issue.
Yuanhan Liu (2):
swrast: simplify the prototype of function
Add a draw-pixel-with-texture testcase to check if texture
sampling is happened while drawing pixels by glDrawPixels.
v2: use piglit_probe_rect_rgba instead of just sampling a
set of pixels(comments from Eric)
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
tests/all.tests
the Elelemnt array buffer to vao.
This would fix most of(3 left) intel oglc vao test fail
[0]: http://www.opengl.org/registry/specs/ARB/vertex_array_object.txt
[1]: http://www.opengl.org/wiki/Vertex_Array_Object
Cc: i...@freedesktop.org
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/api_arrayelt.c |2 +-
src/mesa/main/api_validate.c | 14 ++--
src/mesa/main/arrayobj.c |4 +++
src/mesa/main/attrib.c|7 ++---
src/mesa/main/bufferobj.c |9 ++-
src/mesa/main
According opengl spec 4.2.pdf table 6.12 (Vertex Array Object State) at
page 515: the element buffer object is listed in vertex array object.
Add a testcase to test that.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
tests/all.tests |1 +
tests/general
On Wed, Nov 23, 2011 at 05:27:32PM +0800, Yuanhan Liu wrote:
According opengl spec 4.2.pdf table 6.12 (Vertex Array Object State) at
page 515: the element buffer object is listed in vertex array object.
Add a testcase to test that.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
On Wed, Nov 23, 2011 at 11:12:19AM -0800, Eric Anholt wrote:
On Wed, 23 Nov 2011 17:34:30 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
From 9a1da8748f0faa23f34398213ff7ee45fda6bf36 Mon Sep 17 00:00:00 2001
From: Yuanhan Liu yuanhan@linux.intel.com
Date: Wed, 23 Nov 2011 17:37
On Wed, Nov 23, 2011 at 08:33:00AM -0700, Brian Paul wrote:
On 11/23/2011 02:34 AM, Yuanhan Liu wrote:
+GLuint element;
+GLfloat vertics[] = {
minor nit: s/vertics/vertices/
+-1, -1, 0,
+ 1, -1, 0,
+ 1, 1, 0,
+-1, 1, 0
On Thu, Nov 24, 2011 at 11:25:23AM -0800, Eric Anholt wrote:
On Wed, 23 Nov 2011 12:24:37 -0700, Brian Paul bri...@vmware.com wrote:
On 11/23/2011 12:12 PM, Eric Anholt wrote:
On Wed, 23 Nov 2011 17:34:30 +0800, Yuanhan
Liuyuanhan@linux.intel.com wrote:
From
On Sat, Nov 26, 2011 at 09:01:51AM -0700, Brian Paul wrote:
On 11/23/2011 06:15 PM, Yuanhan Liu wrote:
On Wed, Nov 23, 2011 at 08:25:59AM -0700, Brian Paul wrote:
On 11/23/2011 02:26 AM, Yuanhan Liu wrote:
According opengl spec 4.2.pdf table 6.12 (Vertex Array Object State) at
page 515
Silence the compile warning
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/glx/drisw_glx.c |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/src/glx/drisw_glx.c b/src/glx/drisw_glx.c
index a150c61..7ba491b 100644
--- a/src/glx/drisw_glx.c
+++ b/src/glx
Let if_stack just store the instruction pointer(an index). This is
somehow more flexible than store the instruction memory address.
This patch is mainly for the next patch.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.c |3 +--
src/mesa
Increase the brw eu instruction store size dynamically instead of just
allocating it statically with a constant limit. This would fix something
that 'GL_MAX_PROGRAM_INSTRUCTIONS_ARB was 16384 while the driver would
limit it to 1'.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
On Tue, Nov 29, 2011 at 10:35:42AM -0800, Eric Anholt wrote:
On Tue, 29 Nov 2011 16:08:38 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
Let if_stack just store the instruction pointer(an index). This is
somehow more flexible than store the instruction memory address.
I'd be more
On Tue, Nov 29, 2011 at 10:40:46AM -0800, Eric Anholt wrote:
On Tue, 29 Nov 2011 16:08:39 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
Increase the brw eu instruction store size dynamically instead of just
allocating it statically with a constant limit. This would fix something
Actually the first 5 patches are all prepare work for patch 6.
I checked those patches will all intel oglc testcases, and found no regressions.
What's better, it fixed something.
Yuanhan Liu (6):
i965: let all the brw_OPCODE functions return an instruction index
instead
i965: remove
Let all the brw_OPCODE functions return an instruction index instead,
and use brw_insn_of(p, index) macro to reference the instruction stored
at p-store[].
This is a prepare work of let us increase the instruction store size
dynamically by reralloc.
Signed-off-by: Yuanhan Liu yuanhan
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.h |2 +-
src/mesa/drivers/dri/i965/brw_eu_emit.c |2 +-
src/mesa/drivers/dri/i965/brw_fs_emit.cpp |2 +-
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |2 +-
src/mesa/drivers
Let all the while loop stack just store the instruction index. This is
somehow more flexible than store the instruction memory address.
This is a prepare work of let us increase the instruction store size
dynamically by reralloc.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src
Let if_stack just store the instruction pointer(an index). This is
somehow more flexible than store the instruction memory address.
This is a prepare work of let us increase the instruction store size
dynamically by reralloc.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa
This is a prepare work of let us increase the instruction store size
dynamically by reralloc.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.h |3 +--
src/mesa/drivers/dri/i965/brw_eu_emit.c |4 ++--
src/mesa/drivers/dri/i965
Here is the final patch to increase the brw eu instruction store size
dynamically instead of just allocating it statically with a constant
limit. This would fix something like 'GL_MAX_PROGRAM_INSTRUCTIONS_ARB
was 16384 while the driver would limit it to 1'.
Signed-off-by: Yuanhan Liu yuanhan
brw_DO/JMPI, to let them return the instruction
index.
--
Yuanhan Liu (5):
i965: Add a help function brw_insn_index to get the instruction index
i965: prepare work for dynamic instruction store size on
IF/ELSE/ENDIF
i965: prepare work for dynamic instruction store size on DO/WHILE
i965
The reason to add a help function instead of just use 'insn - p-store'
instead is that this help function includes an assert.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.h |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git
the instruction memory address.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.c |3 +--
src/mesa/drivers/dri/i965/brw_eu.h |4 +++-
src/mesa/drivers/dri/i965/brw_eu_emit.c | 16
3 files changed, 12 insertions(+), 11 deletions
the loop_stack to
store the instruction index instead.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_clip_line.c |2 +-
src/mesa/drivers/dri/i965/brw_clip_tri.c |6 ++--
src/mesa/drivers/dri/i965/brw_clip_unfilled.c |4 +-
src/mesa/drivers/dri
-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.h |8 +---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 17 -
src/mesa/drivers/dri/i965/brw_sf_emit.c |2 +-
src/mesa/drivers/dri/i965/brw_wm_emit.c |2 +-
4 files changed, 15 insertions
it to 1'.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.c |7 +++
src/mesa/drivers/dri/i965/brw_eu.h |7 ---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 22 +++---
3 files changed, 30 insertions(+), 6 deletions
On Fri, Dec 02, 2011 at 11:25:55AM -0800, Eric Anholt wrote:
On Thu, 1 Dec 2011 18:26:50 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
Actually the first 5 patches are all prepare work for patch 6.
I checked those patches will all intel oglc testcases, and found
oglc test cases, and found
no regression. (Sandybridge only).
Thanks,
Yuanhan Liu
--
Eric Anholt (4):
i965: Drop unused do_insn argument from gen6_CONT().
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT
From: Eric Anholt e...@anholt.net
The branch distances get patched up later at the WHILE instruction.
Reviewed-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu_emit.c |3 +--
src/mesa/drivers/dri/i965/brw_fs_emit.cpp |2 +-
src/mesa/drivers/dri/i965
From: Eric Anholt e...@anholt.net
This is a similar cleanup to what we did for brw_IF(), brw_ELSE(),
brw_ENDIF() handling.
Reviewed-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_clip_line.c |5 +--
src/mesa/drivers/dri/i965/brw_clip_tri.c | 15
From: Eric Anholt e...@anholt.net
The EU code itself can just do this work, since all the consumers were
duplicating it.
Reviewed-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 36 +-
src/mesa/drivers/dri/i965
From: Eric Anholt e...@anholt.net
The codegen backends all had this same tracking, so just do it at the
EU level.
Reviewed-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.c |1 +
src/mesa/drivers/dri/i965/brw_eu.h | 10 --
src
address.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.c |3 +--
src/mesa/drivers/dri/i965/brw_eu.h |4 +++-
src/mesa/drivers/dri/i965/brw_eu_emit.c | 22 +++---
3 files changed, 19 insertions(+), 10 deletions
-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_eu.h |8 +---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 17 -
src/mesa/drivers/dri/i965/brw_sf_emit.c |2 +-
src/mesa/drivers/dri/i965/brw_wm_emit.c |2 +-
4 files changed, 15 insertions
On Wed, Dec 21, 2011 at 05:57:35AM -0800, Eric Anholt wrote:
On Wed, 21 Dec 2011 17:33:41 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
If dynamic instruction store size is enabled, while after the brw_JMPI()
and before the brw_land_fwd_jump() function, the eu instruction store
For the case that index data is stored in element array buffer object,
and user called glMultiDrawElements, count the min/max_index before
calling vbo-draw_prims. vbo_get_minmax_index() isn't friendly to this
case. So do it while building the prim info.
Signed-off-by: Yuanhan Liu yuanhan
On Thu, Dec 22, 2011 at 02:37:58PM -0800, Kenneth Graunke wrote:
On 12/21/2011 01:33 AM, Yuanhan Liu wrote:
Hi, this is a new series of patches for dynamic eu instruction store
size. The first 4 is from Eric. I just grabed it to make it rebase to
current repo. The last 4 patch is from mine
On Thu, Dec 22, 2011 at 02:33:03PM -0800, Kenneth Graunke wrote:
On 12/21/2011 01:33 AM, Yuanhan Liu wrote:
Here is the final patch to enable dynamic eu instruction store size:
increase the brw eu instruction store size dynamically instead of just
allocating it statically with a constant
On Thu, Dec 22, 2011 at 11:09:12AM -0800, Kenneth Graunke wrote:
On 12/21/2011 01:33 AM, Yuanhan Liu wrote:
[snip]
+ int emit_endif = 1;
Please use bool and true/false rather than int.
Yes, right. Will fix it.
/* In single program flow mode, we can express IF and ELSE
On Thu, Dec 22, 2011 at 07:51:46PM -0800, Kenneth Graunke wrote:
On 12/22/2011 07:04 PM, Yuanhan Liu wrote:
On Thu, Dec 22, 2011 at 02:33:03PM -0800, Kenneth Graunke wrote:
On 12/21/2011 01:33 AM, Yuanhan Liu wrote:
[snip]
-#define BRW_EU_MAX_INSN_STACK 5
-#define BRW_EU_MAX_INSN 1
introduce vbo_sizeof_ib_type() function to return the index data type
size. I see some place use switch(ib-type) to get the index data type,
which is sort of duplicate.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/state_tracker/st_draw.c | 15 +
src/mesa
-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_draw.c | 18 --
1 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 621195d..3d0cc7c 100644
--- a/src
On Tue, Dec 27, 2011 at 11:15:42AM -0800, Eric Anholt wrote:
On Sun, 25 Dec 2011 12:26:25 +0800, Liu Aleaxander aleaxan...@gmail.com
wrote:
On Sun, Dec 25, 2011 at 8:03 AM, Eric Anholt e...@anholt.net wrote:
On Thu, 22 Dec 2011 18:55:50 +0800, Yuanhan Liu
yuanhan@linux.intel.com
On Wed, Dec 28, 2011 at 12:07:08PM -0800, Eric Anholt wrote:
On Wed, 28 Dec 2011 13:54:43 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
The current code would just calculate min/max_index for the first prim
unconditionally, which is wrong if nr_prims 1.
This would some cases
On Thu, Dec 29, 2011 at 09:10:03AM +0100, Michel Dänzer wrote:
On Don, 2011-12-29 at 10:03 +0800, Yuanhan Liu wrote:
On Wed, Dec 28, 2011 at 12:07:08PM -0800, Eric Anholt wrote:
On Wed, 28 Dec 2011 13:54:43 +0800, Yuanhan Liu
yuanhan@linux.intel.com wrote:
The current code would
.
As when nr_prims = 1, we can pass 1 to paramter nr_prims, thus I made
vbo_get_minmax_index() static.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_draw.c |2 +-
src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c |3 +-
src/mesa/main/api_validate.c
to reduce some
map/unmap.
actually map the ib, you lose anyway). Hopefully won't hit that
performance hog often...
A comment inline.
Am 31.12.2011 07:32, schrieb Yuanhan Liu:
[snip]...
+ for (i = 0; i nr_prims; i++) {
+ tmp_ib.ptr = ib-ptr + prims[i].start * vbo_sizeof_ib_type
On Wed, Jan 04, 2012 at 11:20:07AM +0800, Yuanhan Liu wrote:
On Tue, Jan 03, 2012 at 08:25:31PM +0100, Roland Scheidegger wrote:
Ah index scanning...
I don't like that this will map/unmap the ib once for each prim,
Me either :)
though
I don't really see a nice way to avoid that (I
On Wed, Jan 04, 2012 at 02:55:44PM -0700, Brian Paul wrote:
We were wastefully mapping the whole source/dest buffers before.
---
src/mesa/main/bufferobj.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
Looks good to me.
Reviewed-by: Yuanhan Liu yuanhan
On Wed, Jan 04, 2012 at 07:23:24PM +0100, Roland Scheidegger wrote:
Am 04.01.2012 04:59, schrieb Yuanhan Liu:
On Wed, Jan 04, 2012 at 11:20:07AM +0800, Yuanhan Liu wrote:
On Tue, Jan 03, 2012 at 08:25:31PM +0100, Roland Scheidegger wrote:
Ah index scanning...
I don't like
On Tue, Jan 10, 2012 at 08:43:18PM -0700, Brian Paul wrote:
On Tue, Jan 3, 2012 at 8:59 PM, Yuanhan Liu yuanhan@linux.intel.com
wrote:
On Wed, Jan 04, 2012 at 11:20:07AM +0800, Yuanhan Liu wrote:
On Tue, Jan 03, 2012 at 08:25:31PM +0100, Roland Scheidegger wrote:
Ah index scanning
Fix the constant interpolation enable bit mask for flat light mode.
FRAG_BIT_COL0 attribute bit might be 0, in which case we need to
shift one more bit right.
This would fix the oglc specularColor test fail on both Sandybridge and
Ivybridge.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
into for(; attr
FRAG_ATTRIB_MAX; attr++) loop suggested by Eric.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
Signed-off-by: Xiang, Haihao haihao.xi...@intel.com
---
src/mesa/drivers/dri/i965/gen6_sf_state.c | 19 +--
src/mesa/drivers/dri/i965/gen7_sf_state.c | 19
format.
This patch did 1, 2, but didn't do 3, 4. As it simply seems wrong to me
just change the last vetex element's component setting and source
element format.
Thoughts?
BTW, this patch fix the oglc pntrast fail on SNB(haven't tested it on
IVB yet).
Signed-off-by: Yuanhan Liu yuanhan
.
This would fix the oglc divzero(basic.texQOrWEqualsZero) and
divzero(basic.texTrivialPrim) test case fail.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_tex_layout.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git
On Thu, Sep 08, 2011 at 01:16:23PM -0700, Ian Romanick wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 09/08/2011 03:16 AM, Yuanhan Liu wrote:
If user call glTexImage1D with width = 0 and height = 0(the last
level) like this: glTexImage1D(GL_TEXTURE_1D, level, interfomart,
0, 0
There is already comments show how to detect a null texture. Fix the
code to match the comments.
This would fix the oglc divzero(basic.texQOrWEqualsZero) and
divzero(basic.texTrivialPrim) test case fail.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/intel
On Fri, Sep 09, 2011 at 10:56:36AM +0800, Yuanhan Liu wrote:
There is already comments show how to detect a null texture. Fix the
code to match the comments.
This would fix the oglc divzero(basic.texQOrWEqualsZero) and
divzero(basic.texTrivialPrim) test case fail.
Signed-off-by: Yuanhan
On Thu, Sep 08, 2011 at 09:12:44PM -0700, Kenneth Graunke wrote:
On 09/08/2011 07:56 PM, Yuanhan Liu wrote:
There is already comments show how to detect a null texture. Fix the
code to match the comments.
This would fix the oglc divzero(basic.texQOrWEqualsZero) and
divzero
On Thu, Sep 08, 2011 at 09:25:30PM -0700, Kenneth Graunke wrote:
On 09/08/2011 06:59 PM, Yuanhan Liu wrote:
On Thu, Sep 08, 2011 at 08:39:46AM -0700, Eric Anholt wrote:
On Thu, 8 Sep 2011 11:00:52 +0800, Yuanhan Liu
yuanhan@linux.intel.com wrote:
BTW, this patch fix the oglc pntrast
On Fri, Sep 09, 2011 at 10:08:38AM -0700, Eric Anholt wrote:
On Fri, 9 Sep 2011 13:21:57 +0800, Yuanhan Liu yuanhan@linux.intel.com
wrote:
On Thu, Sep 08, 2011 at 09:25:30PM -0700, Kenneth Graunke wrote:
On 09/08/2011 06:59 PM, Yuanhan Liu wrote:
On Thu, Sep 08, 2011 at 08:39:46AM
.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/dlist.c |9 +
src/mesa/main/pack.c | 27 ++-
2 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
index 6e075b4..21840e6 100644
intel_image-mt might be NULL, say with border width set. It then would
trigger a segfault at intel_map/unmap_texture_image function.
This would fix the oglc misctest(basic.textureBorderIgnore) fail.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/drivers/dri/intel
The following patchs fixed some error handling for some gl functions.
Yuanhan Liu (8):
mesa: fix error handling for glBegin
mesa: fix error handling for glEvalMesh1/2D
mesa: fix error handling for some glGet* functions
mesa: fix error handling for glTexEnv
mesa: fix error handling
According to opengl spec, trigger GL_INVALID_ENUM error if mode is not
one of those valid primitive mode while calling glBegin.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/vbo/vbo_exec_api.c | 24
1 files changed, 24 insertions(+), 0 deletions
According man page, trigger error when calling glEvalMesh1/2D inside
glBegin/glEnd.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/api_noop.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/api_noop.c b/src/mesa/main/api_noop.c
According to the man page, it should trigger a GL_INVALID_OPERATION
while calling some glGet* functions inside glBegin and glEnd.
This patch dose handle the following functions:
glGetBooleanv
glGetFloatv
glGetIntegerv
glGetInteger64v
glGetDoublev
Signed-off-by: Yuanhan Liu yuanhan
Fix error handling while calling glTexEnv with invalid texture
environment parameters.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/texenv.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/mesa/main/texenv.c b/src/mesa/main/texenv.c
According the man page, GL_INVALID_OPERATION should be generated if
glIsEnabled is executed betwwen the execution of glBegin and the
correspoding execution of glEnd.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/enable.c |2 ++
1 files changed, 2 insertions(+), 0
Trigger GL_INVALID_ENUM error if the face paramter is not a valid value.
Trigger GL_INVALID_VALUE error if the GL_SHININESS value is out side
[0,128].
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/vbo/vbo_attrib_tmp.h | 10 +-
1 files changed, 9 insertions(+), 1
According the man page, GL_INVALID_OPERATION should generated if
glPixelZoom is executed between the execution of glBegin and the
corresponding execution of glEnd.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/pixel.c |2 ++
1 files changed, 2 insertions(+), 0
According the man page, trigger a GL_INVALID_VALUE if size 0.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/feedback.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/feedback.c b/src/mesa/main/feedback.c
index 597ec1e
If I understand correctly, the new GL3 buffer object queries parameters,
like BUFFER_MAP_ACCESS_FLAGS, depends on ARB_map_buffer_range
extension.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/bufferobj.c | 12 ++--
1 files changed, 6 insertions(+), 6
Accroding the man page, GL_INVALID_VALUE would generated if access has any
bits set other than those valid defined bits.
Signed-off-by: Yuanhan Liu yuanhan@linux.intel.com
---
src/mesa/main/bufferobj.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/src
On Mon, Sep 19, 2011 at 09:17:42AM -0700, Ian Romanick wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 09/19/2011 07:20 AM, Brian Paul wrote:
On 09/19/2011 04:25 AM, Yuanhan Liu wrote:
If I understand correctly, the new GL3 buffer object queries
parameters, like
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