a-b now.
On Mon, Apr 8, 2019 at 9:31 AM Samuel Pitoiset
wrote:
>
>
> On 3/21/19 11:09 AM, Bas Nieuwenhuizen wrote:
> > Honestly the zero tests is worrying me. This is a pretty big extension
> > and I have questions like:
> >
> > to 16-bit loads + 16-bit ALU actually work together or have we been
On 3/21/19 11:09 AM, Bas Nieuwenhuizen wrote:
Honestly the zero tests is worrying me. This is a pretty big extension
and I have questions like:
to 16-bit loads + 16-bit ALU actually work together or have we been
silently relying on the fact there is always a ZExt cast after and
that did not
On 3/21/19 11:09 AM, Bas Nieuwenhuizen wrote:
Honestly the zero tests is worrying me. This is a pretty big extension
and I have questions like:
to 16-bit loads + 16-bit ALU actually work together or have we been
silently relying on the fact there is always a ZExt cast after and
that did not
Honestly the zero tests is worrying me. This is a pretty big extension
and I have questions like:
to 16-bit loads + 16-bit ALU actually work together or have we been
silently relying on the fact there is always a ZExt cast after and
that did not care about input size?
On Thu, Mar 21, 2019 at
Should be safe to enable as all instructions seem to support 16-bit.
Unfortunately, there is no CTS test.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_extensions.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/amd/vulkan/radv_extensions.py
