Re: [Mesa-dev] [PATCH] util: fix missing swizzle components in the SINT <-> UINT conversion string

Am 22.11.2016 um 22:33 schrieb Charmaine Lee: > Fixes tgsi error introduced in commit 3817a7a. The error complains missing > swizzle component in the conversion string "UMIN TEMP[0], TEMP[0], IMM[0].x". > --- > src/gallium/auxiliary/util/u_simple_shaders.c | 4 ++-- > 1 file changed, 2

[Mesa-dev] [PATCH 1/6] intel/blorp_blit: Create structure for src & dst coordinates

This will be useful for splitting blits into smaller sizes. Signed-off-by: Jordan Justen --- src/intel/blorp/blorp_blit.c | 75 +--- 1 file changed, 56 insertions(+), 19 deletions(-) diff --git a/src/intel/blorp/blorp_blit.c

[Mesa-dev] [PATCH 6/6] i965: Increase max texture to 16k for gen7+

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98297 Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_context.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c

[Mesa-dev] [PATCH 2/6] intel/blorp_blit: Split blorp blits if they are too large

We rename do_blorp_blit() to try_blorp_blit(), and add a return error if the surface size for the blit is too large. Now, do_blorp_blit() is rewritten to try to split the blit into smaller operations if try_blorp_blit() fails. Note: In this commit, try_blorp_blit() will always attempt to blit and

[Mesa-dev] [PATCH] anv: expose depthBiasClamp, it is already set

The gen7/8_cmd_buffer logic already sets the clamp, and it's piped through via the dynamic state. Signed-off-by: Ilia Mirkin --- Untested. I don't think there are any VK-CTS tests about this. But reading the code, it all seems to have been piped through already.

Re: [Mesa-dev] [PATCH] anv: fix segfault in anv_BindImageMemory

It's not a problem on sky lake :-) For a very convoluted reason but yeah, we should fix this. Thanks! Reviewed-by: Jason Ekstrand On Tue, Nov 22, 2016 at 10:06 PM, Dave Airlie wrote: > From: Dave Airlie > > Since bind image

[Mesa-dev] [PATCH 4/6] intel/blorp_blit: Enable splitting large blorp blits

Detect when the surface sizes are too large for a blorp blit. When it is too large, the blorp blit will be split into a smaller operation and attempted again. For gen7, this fixes the cts test:

[Mesa-dev] [PATCH 0/6] Split blorp blits; Enable 16k render target on gen7+

git://people.freedesktop.org/~jljusten/mesa split-blorp-blit-v1 (These patches have been applied on top of my ISL surface dumping patch series, which is included in the branch above.) This series allows large blorp blits to be split into multiple smaller blits. For Haswell, this fixes some

[Mesa-dev] [PATCH 5/6] intel/blorp_blit: Add split_blorp_blit_debug switch

Enabling this debug switch causes surface shrinking to happen by default, and lowers the surface size limit which causes blorp blits to be split. Signed-off-by: Jordan Justen --- src/intel/blorp/blorp_blit.c | 11 --- 1 file changed, 8 insertions(+), 3

[Mesa-dev] [PATCH 3/6] intel/blorp_blit: Adjust blorp surface parameters for split blits

If try_blorp_blit() previously returned that a blit was too large, shrink_surface_params() will be used to update the surface parameters for the smaller blit so the blit operation can proceed. Signed-off-by: Jordan Justen --- src/intel/blorp/blorp_blit.c | 124

Re: [Mesa-dev] [PATCH] anv: fix enumeration of properties

Hey Emil, On Thu, 2016-10-06 at 14:12 +0100, Emil Velikov wrote: > From: Emil Velikov > > Driver should enumerate only up-to min2(num_available, num_requested) > properties and return VK_INCOMPLETE if the # of requested props is > smaller than the ones available. >

[Mesa-dev] [PATCH] swr: [rasterizer core] fix cast for stencil clear value

Bad type cast for stencil clear value was picking up structure padding bytes. --- src/gallium/drivers/swr/rasterizer/core/backend.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/core/backend.cpp

Re: [Mesa-dev] [PATCH 4/3] i965/hiz: Add debug dump for depth/hiz buffers around hiz ops

On Tue, Nov 22, 2016 at 4:02 PM, Jordan Justen wrote: > On 2016-11-22 15:16:45, Jason Ekstrand wrote: > >On Thu, Nov 17, 2016 at 3:27 PM, Jordan Justen < > jordan.l.jus...@intel.com> > >wrote: > > > > Signed-off-by: Jordan Justen

[Mesa-dev] [PATCH] swr: [rasterizer common] add SwrTrace() and macros

--- .../drivers/swr/rasterizer/common/swr_assert.cpp | 96 ++ .../drivers/swr/rasterizer/common/swr_assert.h | 14 2 files changed, 95 insertions(+), 15 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/common/swr_assert.cpp

Re: [Mesa-dev] [PATCH 3/3] glsl/cache/tests: Cast cache_get result to avoid compiler warning

On Tue, Nov 22, 2016 at 2:48 PM, Matt Turner wrote: > On 11/22, Aaron Watry wrote: > >> disk_cache_get returns void*, but we were storing/comparing a char*. >> >> Signed-off-by: Aaron Watry >> --- >> Note that this did, and still, segfaults for me when I

Re: [Mesa-dev] [PATCH] anv: expose depthBiasClamp, it is already set

On Tue, Nov 22, 2016 at 11:03 PM, Ilia Mirkin wrote: > The gen7/8_cmd_buffer logic already sets the clamp, and it's piped > through via the dynamic state. > > Signed-off-by: Ilia Mirkin > --- > > Untested. I don't think there are any VK-CTS tests about

[Mesa-dev] [PATCH] anv: fix segfault in anv_BindImageMemory

From: Dave Airlie Since bind image memory started memsetting surfaces, the device node can't be NULL, since we lookup device->info.has_llc. Not sure why it ever was NULL before. Fixes some things on my Ivybridge. Signed-off-by: Dave Airlie ---

Re: [Mesa-dev] [PATCH] swr: [rasterizer core] fix cast for stencil clear value

Reviewed-by: Ilia Mirkin On Tue, Nov 22, 2016 at 8:56 PM, Tim Rowley wrote: > Bad type cast for stencil clear value was picking up structure > padding bytes. > --- > src/gallium/drivers/swr/rasterizer/core/backend.cpp | 5 ++--- > 1 file

[Mesa-dev] [PATCH] anv: enable drawIndirectFirstInstance

This was already piped through in the CmdDraw(Indexed)Indirect handling. Signed-off-by: Ilia Mirkin --- Passes the 2 vk-cts tests dedicated to it as well. src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH] [rfc] radv: add initial prime support.

From: Dave Airlie This is kind of a gross hacks, but vulkan doesn't specify anything but it would be nice to let people with prime systems at least see some stuff rendering for now. This creates a linear shadow image in GART that gets blitted to at the image transition. Now

[Mesa-dev] [PATCH] scons: Recognize LLVM_CONFIG environment variable.

Signed-off-by: Vinson Lee --- scons/llvm.py | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/scons/llvm.py b/scons/llvm.py index 977e47a..a27bf00 100644 --- a/scons/llvm.py +++ b/scons/llvm.py @@ -194,11 +194,16 @@ def generate(env):

[Mesa-dev] [PATCH 2/6] swr: rearrange caps into limits/supported/unsupported groups

I find this a lot more readable and compact - much easier to scan through the list and see what's on and what's off. No functional change intended. Signed-off-by: Ilia Mirkin --- src/gallium/drivers/swr/swr_screen.cpp | 213 + 1 file

[Mesa-dev] [PATCH 4/6] swr: use util_copy_framebuffer_state helper

Signed-off-by: Ilia Mirkin --- src/gallium/drivers/swr/swr_state.cpp | 13 + 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/src/gallium/drivers/swr/swr_state.cpp b/src/gallium/drivers/swr/swr_state.cpp index 4119379..8541aca 100644 ---

[Mesa-dev] [PATCH 6/6] swr: add missing rgbx8_srgb variant

Signed-off-by: Ilia Mirkin --- src/gallium/drivers/swr/swr_screen.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/swr/swr_screen.cpp b/src/gallium/drivers/swr/swr_screen.cpp index 642f9be..19bb102 100644 ---

[Mesa-dev] [PATCH 5/6] swr: reorder renderable formats, add grouping comments

Signed-off-by: Ilia Mirkin --- src/gallium/drivers/swr/swr_screen.cpp | 152 +++-- 1 file changed, 87 insertions(+), 65 deletions(-) diff --git a/src/gallium/drivers/swr/swr_screen.cpp b/src/gallium/drivers/swr/swr_screen.cpp index

[Mesa-dev] [PATCH 1/6] swr: only store up to the LOD size

Signed-off-by: Ilia Mirkin --- src/gallium/drivers/swr/swr_draw.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/swr/swr_draw.cpp b/src/gallium/drivers/swr/swr_draw.cpp index e8c5b23..c4d5e5c 100644 ---

[Mesa-dev] [PATCH 3/6] swr: enable cubemap arrays

Everything is in place for these. Signed-off-by: Ilia Mirkin --- src/gallium/drivers/swr/swr_screen.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/swr/swr_screen.cpp b/src/gallium/drivers/swr/swr_screen.cpp index

Re: [Mesa-dev] [PATCH 2/4] anv/cmd_buffer: Handle running out of binding tables in compute shaders

On 22/11/16 04:26, Jason Ekstrand wrote: If we try to allocate a binding table and fail, we have to get a new binding table block, re-emit STATE_BASE_ADDRESS, and then try again. We already handle this correctly for 3D and blorp but it never got handled for CS. This fixes the new

[Mesa-dev] [PATCH] gbm: request correct version of the DRI2_FENCE extension

There is no version 2 of the DRI2_FENCE extension. So only a request for version 1 has a chance to succeed. Fixes: 74b1969d717f (gbm: wire up fence extension) Cc: "13.0" Signed-off-by: Lucas Stach --- src/gbm/backends/dri/gbm_dri.c | 2

Re: [Mesa-dev] [PATCH v2] nir/spirv: implement ordered / unordered floating point comparisons properly

On Tue, 2016-11-22 at 12:15 +, Lionel Landwerlin wrote: > > > Sounds good to me, thanks! > > Reviewed-by: Lionel Landwerlin >  On 17/11/16 08:36, Iago Toral Quiroga wrote: > > > > Besides the logical operation involved, these also require that we > > test if

Re: [Mesa-dev] [PATCH 2/3] radv: Use library mtime for cache UUID.

On 22 November 2016 at 01:19, Bas Nieuwenhuizen wrote: > We want to also invalidate the cache when LLVM gets changed. As the > specific LLVM revision is not fixed at build time, we will need to > check at runtime. Computing a checksum for LLVM is going to be very >

Re: [Mesa-dev] [PATCH v2] nir/spirv: implement ordered / unordered floating point comparisons properly

Sounds good to me, thanks! Reviewed-by: Lionel Landwerlin On 17/11/16 08:36, Iago Toral Quiroga wrote: Besides the logical operation involved, these also require that we test if the operands are ordered / unordered. For ordered operations, both operands must be

[Mesa-dev] [PATCH 07/13] glsl: assert on incoherent point mode layout-id-qualifier validation

The point mode value in an ast_type_qualifier can only be true if the flag is already set since this layout-id-qualifier can only be or not be present in a shader. Hence, it is useless to check for its value if the flag is already set. Just replaced with an assert. V2: assert instead of checking

Re: [Mesa-dev] [PATCH] i965/gen7: Only advertise 4 samples for RGBA32F on GLES

Reviewed-by: Samuel Iglesias Gonsálvez On Tue, 2016-11-22 at 00:17 -0800, Jordan Justen wrote: > We can't render to 8x MSAA if the width is greater than 64 bits. (see > brw_render_target_supported) > > Fixes ES31-CTS.sample_variables.mask.rgba32f.samples_8.mask_* > >

Re: [Mesa-dev] [PATCH 3/4] anv/cmd_buffer: Re-emit MEDIA_CURBE_LOAD when CS push constants are dirty

Reviewed-by: Lionel Landwerlin On 22/11/16 04:26, Jason Ekstrand wrote: This can happen even if the binding table isn't changed. For instance, you could have dynamic offsets with your descriptor set. This fixes the new stress.lots-of-surface-state.cs.dynamic

Re: [Mesa-dev] [PATCH 04/13] glsl: Split default in layout qualifier merge

On Mon, 2016-11-21 at 18:08 +0200, Andres Gomez wrote: > On Thu, 2016-11-17 at 16:56 +1100, Timothy Arceri wrote: > > > > On Mon, 2016-11-14 at 19:15 +0200, Andres Gomez wrote: > ...  > > > > > > > > diff --git a/src/compiler/glsl/glsl_parser.yy > > > b/src/compiler/glsl/glsl_parser.yy > > >

Re: [Mesa-dev] [PATCH] intel/aubinator: Use the correct length for MEDIA commands

On 22/11/16 02:58, Jason Ekstrand wrote: --- src/intel/tools/decoder.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/tools/decoder.c b/src/intel/tools/decoder.c index 6bd02bf..55488eb 100644 --- a/src/intel/tools/decoder.c +++ b/src/intel/tools/decoder.c @@

Re: [Mesa-dev] [PATCH 05/13] glsl: simplifies the merge of the default in layout qualifier

On Mon, 2016-11-21 at 18:08 +0200, Andres Gomez wrote: > On Thu, 2016-11-17 at 16:17 +1100, Timothy Arceri wrote: > > > > On Mon, 2016-11-14 at 19:15 +0200, Andres Gomez wrote: > ... > > > > > > > > diff --git a/src/compiler/glsl/ast_type.cpp > > > b/src/compiler/glsl/ast_type.cpp > > > index

Re: [Mesa-dev] [PATCH 3/3] radv: Incorporate GPU family into cache UUID.

Would it be possible to have a cache for each family? I imagine this might cause issues when someone has multiple cards in their system On Tue, 22 Nov 2016 at 01:20 Bas Nieuwenhuizen wrote: > Invalidates the cache when someone switches cards. > > Signed-off-by: Bas

Re: [Mesa-dev] [PATCH 4/4] anv/cmd_buffer: Emit a CS stall before setting a CS pipeline

Reviewed-by: Lionel Landwerlin On 22/11/16 04:26, Jason Ekstrand wrote: Cc: "13.0" Cc: Jordan Justen --- src/intel/vulkan/genX_cmd_buffer.c | 14 +- 1 file changed, 13 insertions(+), 1

Re: [Mesa-dev] [PATCH] mesa/glsl: remove unused uses_builtin_functions field

Reviewed-by: Samuel Iglesias Gonsálvez On Tue, 2016-11-22 at 18:01 +1100, Timothy Arceri wrote: > This has been unused since 943b69cddd > --- >  src/compiler/glsl/glsl_parser_extras.cpp | 1 - >  src/mesa/main/ff_fragment_shader.cpp | 1 - >  src/mesa/main/mtypes.h

Re: [Mesa-dev] [PATCH 3/3] radv: Incorporate GPU family into cache UUID.

The cache is actually stored by the application, and the UUID of the cache is application visible, so it should be able to store multiple caches. We might want to use different files for the driver cache of builtin shaders though. And as I'm writing this, I realized that PCI vendor and device are

[Mesa-dev] [PATCH] docs: get rid of duplicated description from sourcetree.html

Signed-off-by: Mun Gwan-gyeong --- docs/sourcetree.html | 1 - 1 file changed, 1 deletion(-) diff --git a/docs/sourcetree.html b/docs/sourcetree.html index aee3321..7013f65 100644 --- a/docs/sourcetree.html +++ b/docs/sourcetree.html @@ -140,7 +140,6 @@ each directory.

Re: [Mesa-dev] [PATCH 3/3] glsl/cache/tests: Cast cache_get result to avoid compiler warning

On 11/22, Aaron Watry wrote: disk_cache_get returns void*, but we were storing/comparing a char*. Signed-off-by: Aaron Watry --- Note that this did, and still, segfaults for me when I actually run it... Strange. It passes for me. But at least the compiler is no longer

Re: [Mesa-dev] [PATCH v5] clover: restore support for LLVM <= 3.9

On Tue, Nov 22, 2016 at 11:25 AM, Vedran Miletić wrote: > The commit 8e430ff8b060b4e8e922bae24b3c57837da6ea77 support for LLVM > 3.9 and older versionsin Clover. This patch restores it and refactors > the support using Clover compatibility layer for LLVM. > > v2: merged

Re: [Mesa-dev] [PATCH v2] main/getteximage: Use the height argument to calculate copy size

Reviewed-by: Jason Ekstrand On Tue, Nov 22, 2016 at 10:57 AM, Eduardo Lima Mitev wrote: > In get_tex_memcpy, when copying texture data directly from source > to destination (when row strides match for both src and dst), the > copy size is currently

Re: [Mesa-dev] [PATCH] i965: Use 3DSTATE_CLIP's User Clip Distance Enable bitmask on Gen8+.

On 11/15, Kenneth Graunke wrote: Gen6-7.5 specify the user clip distance enable bitmask in 3DSTATE_CLIP. Gen8+ normally uses the new internal signalling mechanism to select the one specified in the last enabled shader stage (3DSTATE_VS, DS, or GS). This is a pretty good fit for Vulkan, or even

Re: [Mesa-dev] [PATCH] i965/vec4: skip registers already marked as no_spill

On 11/11, Juan A. Suarez Romero wrote: Do not evaluate spill costs for registers that were already marked as no_spill. --- Reviewed-by: Matt Turner signature.asc Description: Digital signature ___ mesa-dev mailing list

Re: [Mesa-dev] [PATCH 05/13] glsl: simplifies the merge of the default in layout qualifier

On Tue, 2016-11-22 at 16:07 +0200, Andres Gomez wrote: > On Tue, 2016-11-22 at 22:22 +1100, Timothy Arceri wrote: > ... > > > > > > Can I ask that you write a follow up patch for this series that > > creates > > a helper function for each of these validations. For example: > > > > static bool >

[Mesa-dev] [PATCH 1/2] mesa: Add GL and GLSL plumbing for ARB_post_depth_coverage for i965 (gen9+).

This extension allows the fragment shader to control whether values in gl_SampleMaskIn[] reflect the coverage after application of the early depth and stencil tests. Signed-off-by: Plamena Manolova --- src/compiler/glsl/ast.h | 5 +

[Mesa-dev] [PATCH] util: fix missing swizzle components in the SINT <-> UINT conversion string

Fixes tgsi error introduced in commit 3817a7a. The error complains missing swizzle component in the conversion string "UMIN TEMP[0], TEMP[0], IMM[0].x". --- src/gallium/auxiliary/util/u_simple_shaders.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

Re: [Mesa-dev] [PATCH 2/5] swr: flatshading makes color outputs flat, it doesn't affect others

Reviewed-by: Tim Rowley > On Nov 21, 2016, at 11:52 AM, Ilia Mirkin > wrote: We were previously not marking the "regular" flat outputs as flat when flatshading was enabled.

[Mesa-dev] [PATCH 16/18] i965: Validate "General Restrictions Based on Operand Types"

--- src/mesa/drivers/dri/i965/brw_eu_validate.c| 215 + src/mesa/drivers/dri/i965/test_eu_validate.cpp | 58 +++ 2 files changed, 273 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c b/src/mesa/drivers/dri/i965/brw_eu_validate.c index

[Mesa-dev] [PATCH 07/18] i965: Add a test for the EU assembly validator.

--- src/mesa/drivers/dri/i965/Makefile.am | 7 + src/mesa/drivers/dri/i965/test_eu_validate.cpp | 169 + 2 files changed, 176 insertions(+) create mode 100644 src/mesa/drivers/dri/i965/test_eu_validate.cpp diff --git a/src/mesa/drivers/dri/i965/Makefile.am

[Mesa-dev] [PATCH 11/18] i965: Factor out send_restrictions() function.

--- src/mesa/drivers/dri/i965/brw_eu_validate.c | 34 +++-- 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c b/src/mesa/drivers/dri/i965/brw_eu_validate.c index d03ed71..8c2eb99 100644 ---

[Mesa-dev] [PATCH 15/18] i965: Validate "General Restrictions on Regioning Parameters"

--- src/mesa/drivers/dri/i965/brw_eu_validate.c| 139 src/mesa/drivers/dri/i965/test_eu_validate.cpp | 220 + 2 files changed, 359 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c b/src/mesa/drivers/dri/i965/brw_eu_validate.c

[Mesa-dev] [PATCH 18/18] i965: Validate "Special Cases for Byte Operations"

Do this in general_restrictions_based_on_operand_types() because the two rules that "Special Cases for Byte Operations" relax are checked there. --- src/mesa/drivers/dri/i965/brw_eu_validate.c| 70 +--- src/mesa/drivers/dri/i965/test_eu_validate.cpp | 89

[Mesa-dev] [PATCH 14/18] i965: Replace reg_type_size[] with a function.

A function is necessary to handle immediate types. --- src/mesa/drivers/dri/i965/brw_disasm.c | 35 src/mesa/drivers/dri/i965/brw_eu_emit.c | 58 +++-- src/mesa/drivers/dri/i965/brw_reg.h | 8 + 3 files changed, 77 insertions(+), 24

[Mesa-dev] [PATCH 13/18] i965: Validate math instruction sources.

--- src/mesa/drivers/dri/i965/brw_eu_emit.c| 9 - src/mesa/drivers/dri/i965/test_eu_validate.cpp | 23 +++ 2 files changed, 23 insertions(+), 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index

[Mesa-dev] [PATCH 12/18] i965: Claim that SEND/math has two sources.

src1 must be a descriptor (including the information to determine that the SEND is doing an extended math operation), but src0 can actually be null since it serves as the source of the implicit GRF -> MRF move. --- src/mesa/drivers/dri/i965/brw_eu_validate.c | 9 - 1 file changed, 8

[Mesa-dev] [PATCH 2/2] i965: Add i965 plumbing for ARB_post_depth_coverage for i965 (gen9+).

This extension allows the fragment shader to control whether values in gl_SampleMaskIn[] reflect the coverage after application of the early depth and stencil tests. Signed-off-by: Plamena Manolova --- src/mesa/drivers/dri/i965/brw_compiler.h | 1 +

Re: [Mesa-dev] [PATCH 1/3] compiler/glsl/tests: Fix print format when building 32-bit on 64-bit host

Patches 1 and 2 are Reviewed-by: Matt Turner signature.asc Description: Digital signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 3/5] swr: rework vert <-> frag shader linkage logic

Reviewed-by: Tim Rowley > On Nov 21, 2016, at 11:52 AM, Ilia Mirkin > wrote: Fixes a few things: - sprite coords only apply to generic varyings, and are a bitmask - back color only

Re: [Mesa-dev] [PATCH 5/5] swr: color interpolation is also supposed to get perspective division

Reviewed-by: Tim Rowley > On Nov 21, 2016, at 11:52 AM, Ilia Mirkin > wrote: Signed-off-by: Ilia Mirkin > ---

[Mesa-dev] [PATCH 17/18] i965: Validate "Region Alignment Rules"

--- src/mesa/drivers/dri/i965/brw_eu_validate.c| 410 - src/mesa/drivers/dri/i965/test_eu_validate.cpp | 288 + 2 files changed, 697 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c

Re: [Mesa-dev] [PATCH 4/5] swr: add sprite coord enable mask to fs key

Reviewed-by: Tim Rowley > On Nov 21, 2016, at 11:52 AM, Ilia Mirkin > wrote: This fixes gl-coord-replace-doesnt-eliminate-frag-tex-coords Signed-off-by: Ilia Mirkin

[Mesa-dev] [PATCH 05/18] i965: Make ERROR_IF usable from other functions.

--- src/mesa/drivers/dri/i965/brw_eu_validate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c b/src/mesa/drivers/dri/i965/brw_eu_validate.c index fa1d67c..e23f1ec 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_validate.c +++

[Mesa-dev] [PATCH 09/18] i965: Simplify num_sources_from_inst().

desc will always be non-NULL, because brw_validate_instructions() does not attempt to validate any instructions that fail the is_unsupported_inst() check. --- src/mesa/drivers/dri/i965/brw_eu_validate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git

[Mesa-dev] [PATCH 03/18] i965/vec4: Use UW-typed operands when dest is UW.

Using a UD-typed operand makes the execution size D, and if the size of the execution type is greater than the size of the destination type, the destination must be appropriately strided. We actually just want UW-types all around. --- src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 10

[Mesa-dev] [PATCH 10/18] i965: Factor out sources_not_null() validation function.

--- src/mesa/drivers/dri/i965/brw_eu_validate.c | 40 + 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c b/src/mesa/drivers/dri/i965/brw_eu_validate.c index efb1f1c..d03ed71 100644 ---

[Mesa-dev] [PATCH 04/18] i965: Mark error annotation on correct SIMD16 inst.

inst, whose assignment can be seen in the last line of context pointed to the correct instruction in the SIMD16 program, but src_offset was the offset from the beginning of the SIMD16 program. So if an instruction at offset 0x100 in the SIMD16 program was illegal, we would mark an error on the

[Mesa-dev] [PATCH 06/18] i965: Add a CHECK macro to call more complicated validation funcs.

--- src/mesa/drivers/dri/i965/brw_eu_validate.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c b/src/mesa/drivers/dri/i965/brw_eu_validate.c index e23f1ec..3225386 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_validate.c +++

[Mesa-dev] [PATCH 02/18] i965: Use W-typed immediate in brw_F32TO16().

--- src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index cfb3fa0..3146271 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++

[Mesa-dev] [PATCH 00/18] i965: More shader validation

This series adds the core "Register Region Restrictions" to the shader validator. I've added a make check test to verify that the validation checks are correct. There is still quite a bit more to do, but the next section in the PRM is "Special Requirements for Handling Double Precision Data

[Mesa-dev] [PATCH 08/18] i965: Structure code so unsupported inst will not generate more errors.

We want to rely on brw_opcode_desc() always returning non-NULL in other validation functions. Other validation functions will be in the else case of the block added in this patch. --- src/mesa/drivers/dri/i965/brw_eu_validate.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff

Re: [Mesa-dev] [PATCH] main/getteximage: Take y-offset into account for memcpy size

On Nov 22, 2016 11:03, "Eduardo Lima Mitev" wrote: > > On 11/22/2016 06:43 PM, Jason Ekstrand wrote: > > On Tue, Nov 22, 2016 at 9:11 AM, Eduardo Lima Mitev > > wrote: > > > > In get_tex_memcpy, when copying texture data directly

[Mesa-dev] [PATCH v5] clover: restore support for LLVM <= 3.9

The commit 8e430ff8b060b4e8e922bae24b3c57837da6ea77 support for LLVM 3.9 and older versionsin Clover. This patch restores it and refactors the support using Clover compatibility layer for LLVM. v2: merged #ifdef blocks v3: added support for LLVM 3.6-3.8 v4: add missing #ifdef around v5:

Re: [Mesa-dev] [PATCH 00/13] anv: Implement input attachments

Series Reviewed-by: Jordan Justen On 2016-11-16 11:31:32, Jason Ekstrand wrote: > This series adds input attachment support to the Intel Vulkan driver. It > applies on top of my series to implement CCS. It can be found here: > >

Re: [Mesa-dev] [PATCH 1/5] swr: only broadcast color0 value, not all color values

Reviewed-by: Tim Rowley > On Nov 21, 2016, at 11:52 AM, Ilia Mirkin > wrote: The way that dual-source blending is described for GLES2 is very odd, and we end up with a shader that

Re: [Mesa-dev] [PATCH] anv: Add missing error-checking to anv_block_pool_init

Hi Mun, On 20 November 2016 at 11:11, Mun Gwan-gyeong wrote: > When the allocation fails on u_vector_init(), it returns 0 > This fixes u_vector_init failure path on anv_block_pool_init > > CID 1394319 > > Signed-off-by: Mun Gwan-gyeong > --- >

Re: [Mesa-dev] [PATCH 05/13] glsl: simplifies the merge of the default in layout qualifier

On Tue, 2016-11-22 at 22:22 +1100, Timothy Arceri wrote: ... > > Can I ask that you write a follow up patch for this series that creates > a helper function for each of these validations. For example: > > static bool > validate_ordering(loc, state, qualifier, new_qualifier) > { >    if

Re: [Mesa-dev] [PATCH] i965/gen7: Only advertise 4 samples for RGBA32F on GLES

Reviewed-by: Iago Toral Quiroga On Tue, 2016-11-22 at 00:17 -0800, Jordan Justen wrote: > We can't render to 8x MSAA if the width is greater than 64 bits. (see > brw_render_target_supported) > > Fixes ES31-CTS.sample_variables.mask.rgba32f.samples_8.mask_* > > Signed-off-by:

Re: [Mesa-dev] [PATCH] anv: Fix unintentional integer overflow in anv_CreateDmaBufImageINTEL

On 20 November 2016 at 11:44, Mun Gwan-gyeong wrote: > pCreateInfo->strideInBytes * pCreateInfo->extent.height with type > "unsigned int" is evaluated using 32-bit arithmetic. > This fixes unintentional integer overflow by casting to uint64_t before > multifying. > > CID

Re: [Mesa-dev] [PATCH 2/4] anv/cmd_buffer: Handle running out of binding tables in compute shaders

On Tue, Nov 22, 2016 at 2:08 AM, Lionel Landwerlin < lionel.g.landwer...@intel.com> wrote: > On 22/11/16 04:26, Jason Ekstrand wrote: > >> If we try to allocate a binding table and fail, we have to get a new >> binding table block, re-emit STATE_BASE_ADDRESS, and then try again. We >> already

Re: [Mesa-dev] [PATCH v2 0/6] texture layout improvements

Great, thanks! I'll push these out tonight. On Tue, Nov 22, 2016 at 11:44 AM, Cherniak, Bruce wrote: > The entire set has now been r-v-b. > Reviewed-by: Bruce Cherniak > >> On Nov 17, 2016, at 10:56 PM, Ilia Mirkin

Re: [Mesa-dev] [PATCH v2 4/6] swr: remove unnecessary -1 entries in format mapping table

Reviewed-by: Bruce Cherniak > On Nov 17, 2016, at 10:56 PM, Ilia Mirkin wrote: > > Signed-off-by: Ilia Mirkin > --- > src/gallium/drivers/swr/swr_screen.cpp | 126 - > 1 file changed, 126

Re: [Mesa-dev] [PATCH v2 3/6] swr: rework resource layout and surface setup

Reviewed-by: Bruce Cherniak > On Nov 17, 2016, at 10:56 PM, Ilia Mirkin wrote: > > This is a bit of a mega-commit, but unfortunately there's no great way > to break this up since a lot of different pieces have to match up. Here > we do the

Re: [Mesa-dev] [PATCH v2 6/6] swr: avoid using exceptions for expected condition handling

Reviewed-by: Bruce Cherniak > On Nov 17, 2016, at 10:56 PM, Ilia Mirkin wrote: > > I was getting a weird segfault from GCC 4.9.3: > > 0x754f27aa in strlen () from /lib64/libc.so.6 > (gdb) bt > #0 0x754f27aa in strlen () from

Re: [Mesa-dev] [PATCH v2 5/6] swr: remove formats from mapping table that don't have StoreTile impls

Reviewed-by: Bruce Cherniak > On Nov 17, 2016, at 10:56 PM, Ilia Mirkin wrote: > > This table exists for the purpose of determining renderable formats. > Without a StoreTile implementation, that can't happen. > > This basically removes rendering

Re: [Mesa-dev] [PATCH 1/2] intel/common: Add an is_kabylake field to gen_device_info

On Mon, Nov 21, 2016 at 2:49 PM, Matt Turner wrote: > On Tue, Nov 8, 2016 at 1:21 PM, Jason Ekstrand > wrote: > > Most of the 3-D engine Kaby Lake is identical to Sky Lake. However, > there > > are a few small differences that we need to be able to

Re: [Mesa-dev] [PATCH] gbm: request correct version of the DRI2_FENCE extension

On 22 November 2016 at 10:12, Lucas Stach wrote: > There is no version 2 of the DRI2_FENCE extension. So only a request > for version 1 has a chance to succeed. > > Fixes: 74b1969d717f (gbm: wire up fence extension) > Cc: "13.0" >

Re: [Mesa-dev] [PATCH v2 0/6] texture layout improvements

The entire set has now been r-v-b. Reviewed-by: Bruce Cherniak > On Nov 17, 2016, at 10:56 PM, Ilia Mirkin wrote: > > Some of these are new, others have had some changes done to them. Most > notably, > I've fixed the 1D layout in both the

[Mesa-dev] [AppVeyor] mesa master #2774 completed

Build mesa 2774 completed Commit a3f6bea69a by Marek Olšák on 11/22/2016 5:28 PM: gallium: fix more occurences of u_hash.h\n\nthis fixes compile failures since 86514d84e0beec47c82da4888db12bf07f33cb83 Configure your notification preferences

Re: [Mesa-dev] [PATCH] main/getteximage: Take y-offset into account for memcpy size

On Tue, Nov 22, 2016 at 9:11 AM, Eduardo Lima Mitev wrote: > In get_tex_memcpy, when copying texture data directly from source > to destination (when row strides match for both src and dst), the > block size is currently calculated as 'bytes-per-row * image-height', > ignoring

Re: [Mesa-dev] [PATCH 4/3] i965/hiz: Add debug dump for depth/hiz buffers around hiz ops

Acked-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/2] intel/blorp: Fix rectangle size for level-not-zero resolves

Needed to prevent gpu hangs when mip-mapped compression gets enabled. Signed-off-by: Topi Pohjolainen CC: Jason Ekstrand --- src/intel/blorp/blorp_clear.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 1/2] i965/miptree: Don't shrink textures when augmenting for more levels

This was detected when examining CCS_E failures with piglit test: "fbo-generatemipmap-formats". Test creates a 2D texture with dimensions 293x277. It manually loops over all levels and calls glTexImage2D(). Level one triggers creation of full miptree: intel_alloc_texture_image_buffer() realizes

[Mesa-dev] [PATCH] main/getteximage: Take y-offset into account for memcpy size

In get_tex_memcpy, when copying texture data directly from source to destination (when row strides match for both src and dst), the block size is currently calculated as 'bytes-per-row * image-height', ignoring the given y-offset argument. This can cause a read past the end of the mapped buffer,

Re: [Mesa-dev] [PATCH 1/2] i965/miptree: Don't shrink textures when augmenting for more levels

On Tue, Nov 22, 2016 at 9:09 AM, Topi Pohjolainen < topi.pohjolai...@gmail.com> wrote: > This was detected when examining CCS_E failures with piglit test: > "fbo-generatemipmap-formats". Test creates a 2D texture with > dimensions 293x277. It manually loops over all levels and calls >

[Mesa-dev] [AppVeyor] mesa master #2773 failed

Build mesa 2773 failed Commit d219720d19 by Marek Olšák on 11/18/2016 8:00 PM: mesa: use special checksums for unset checksums and fixed-func shaders\n\nfor debugging\n\nReviewed-by: Timothy Arceri Configure your

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