Re: [Mesa-dev] [RFC] NIR serialization

On Monday, September 11, 2017 9:23:05 PM PDT Ian Romanick wrote: > On 09/08/2017 01:59 AM, Kenneth Graunke wrote: > > On Thursday, September 7, 2017 4:26:04 PM PDT Jordan Justen wrote: > >> On 2017-09-06 14:12:41, Daniel Schürmann wrote: > >>> Hello together! > >>> Recently, we had a small

[Mesa-dev] [Bug 102564] swr: GPU Caps Viewer crashes with any 3D demo

https://bugs.freedesktop.org/show_bug.cgi?id=102564 --- Comment #4 from Alex Granni --- Sorry, I didn't mention that GPU Caps Viewer is 32-bit even if running on 64-bit Windows so it goes in \windows\syswow64 on a 64-bit Windows. The way I get it to use Mesa is by copying

Re: [Mesa-dev] [PATCH] i965 : optimized bucket index calculation

Hi Jason, On the asserts you’ve mentioned below, I assume we need to add them after ‘bufmgr->num_buckets++’ in add_bucket() as num_buckets could be 0 initially. Another clarification on ~1%, we meant approx. 1% there, that’s an improvement we saw in 3Dmark total not a degradation, we’ll

Re: [Mesa-dev] [PATCH] glsl: Disallow unsized array of atomic_uint

On Monday, September 11, 2017 11:15:05 PM PDT Iago Toral Quiroga wrote: > This was a bugfix to the spec addressed in OpenGL 4.5 and there is > a CTS test to check this. > > Fixes: > KHR-GL45.shader_atomic_counters.negative-unsized-array > --- > src/compiler/glsl/ast_to_hir.cpp | 11 +++ >

Re: [Mesa-dev] [RFC] NIR serialization

On 12/09/17 16:55, Jordan Justen wrote: On 2017-09-11 21:44:32, Timothy Arceri wrote: On 12/09/17 14:23, Ian Romanick wrote: On 09/08/2017 01:59 AM, Kenneth Graunke wrote: We shouldn't use SPIR-V for the shader cache. The compilation process for GLSL is: GLSL -> GLSL IR -> NIR -> i965 IRs.

Re: [Mesa-dev] [PATCH] r600/sb: remove superfluos assert

On 09/11/2017 07:09 PM, Emil Velikov wrote: On 11 September 2017 at 15:39, Gert Wollny wrote: The assert checks whether pshader->num_arrays != 0, but the code after the assert actually branches based on the same check. Removing this assert fixes: piglit

Re: [Mesa-dev] [RFC] NIR serialization

On 2017-09-11 21:44:32, Timothy Arceri wrote: > On 12/09/17 14:23, Ian Romanick wrote: > > On 09/08/2017 01:59 AM, Kenneth Graunke wrote: > >> > >> We shouldn't use SPIR-V for the shader cache. > >> > >> The compilation process for GLSL is: GLSL -> GLSL IR -> NIR -> i965 IRs. > >> Storing the

Re: [Mesa-dev] [PATCH] glsl: Disallow unsized array of atomic_uint

On Tue, 2017-09-12 at 00:03 -0700, Kenneth Graunke wrote: > On Monday, September 11, 2017 11:15:05 PM PDT Iago Toral Quiroga > wrote: > > This was a bugfix to the spec addressed in OpenGL 4.5 and there is > > a CTS test to check this. > > > > Fixes: > >

Re: [Mesa-dev] [PATCH] gallium/{r600, radeonsi}: Fix segfault with color format (v2)

On Wed, Sep 13, 2017 at 12:31 AM, Marek Olšák wrote: > I think we shouldn't be getting PIPE_FORMAT_COUNT in > is_format_supported in the first place, and therefore drivers don't > have to work around it. Or any other invalid formats, for that matter. Marek > > Marek > > On

[Mesa-dev] [PATCH 6/8] i965: call brw_shader_gather_info() from the callers of brw_create_nir()

This will allow us to insert a nir linking step in brw_link_shader(). --- src/mesa/drivers/dri/i965/brw_link.cpp | 14 ++ src/mesa/drivers/dri/i965/brw_program.c | 11 --- 2 files changed, 18 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp

[Mesa-dev] [PATCH 2/8] glsl: mark xfb varyings as always active

This will be used by the nir linking pass so that we don't remove otherwise unused varyings. --- src/compiler/glsl/link_varyings.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/compiler/glsl/link_varyings.cpp b/src/compiler/glsl/link_varyings.cpp index 528506fd0eb..656bf79ca9d

[Mesa-dev] [PATCH 1/8] nir: add is_xfb_only to nir variable

Will be used in nir link pass to decided if we can remove a varying or not. --- src/compiler/glsl/glsl_to_nir.cpp | 1 + src/compiler/nir/nir.h| 10 ++ 2 files changed, 11 insertions(+) diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index

[Mesa-dev] [PATCH 5/8] i965: create a brw_shader_gather_info() helper

This will help us call gather info at a later point and allow us to do some linking in nir. --- src/mesa/drivers/dri/i965/brw_program.c | 20 +--- src/mesa/drivers/dri/i965/brw_program.h | 3 +++ 2 files changed, 16 insertions(+), 7 deletions(-) diff --git

[Mesa-dev] [PATCH 7/8] i965/nir: export nir_optimize

--- src/intel/compiler/brw_nir.c | 14 +++--- src/intel/compiler/brw_nir.h | 4 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index ce21c016699..a04f4af7b08 100644 --- a/src/intel/compiler/brw_nir.c +++

Re: [Mesa-dev] [PATCH 4/4] i965: Use prepare_external instead of make_shareable in setTexBuffer2

Adding people who may have some shot at understanding this stuff On Tue, Sep 12, 2017 at 4:23 PM, Jason Ekstrand wrote: > The setTexBuffer2 hook from GLX is used to implement glxBindTexImageEXT > which has tighter restrictions than just "it's shared". In particular, > it

[Mesa-dev] [PATCH] virgl: drop const dimensions on first block.

From: Dave Airlie The virgl protocol version of tgsi doesn't handle this yet, transform it back to the old ways. Fixes: 41e342d5 tgsi/ureg: always emit constants (and their decls) as 2D Signed-off-by: Dave Airlie ---

[Mesa-dev] [PATCH] util: Query build-id by symbol address, not library name

This patch renames build_id_find_nhdr() to build_id_find_nhdr_for_addr(), and changes it to never examine the library name. Tested on Fedora by confirming that build_id_get_data() returns the same build-id as the file(1) tool. For BSD, I confirmed that the API used (dladdr() and struct Dl_info)

Re: [Mesa-dev] [RFC] NIR serialization

On 13/09/17 03:00, Ian Romanick wrote: On 09/11/2017 09:44 PM, Timothy Arceri wrote: On 12/09/17 14:23, Ian Romanick wrote: On 09/08/2017 01:59 AM, Kenneth Graunke wrote: On Thursday, September 7, 2017 4:26:04 PM PDT Jordan Justen wrote: On 2017-09-06 14:12:41, Daniel Schürmann wrote:

Re: [Mesa-dev] [PATCH 1/2] radv/nir: call opt_remove_phis after trivial continues.

On 13/09/17 12:57, Dave Airlie wrote: From: Dave Airlie With the shaders in the ssao demo, the nir_opt_if wasn't working properly without this, after this the if gets optimised so that loop unrolling gets called. (loop unrolling fails due to instruction count, but at

Re: [Mesa-dev] [PATCH 1/2] radv/nir: call opt_remove_phis after trivial continues.

On 13/09/17 13:48, Dave Airlie wrote: On 13 September 2017 at 13:42, Timothy Arceri wrote: On 13/09/17 12:57, Dave Airlie wrote: From: Dave Airlie With the shaders in the ssao demo, the nir_opt_if wasn't working properly without this, after

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/2] radeonsi: hard-code pixel center for interpolateAtSample without multisample buffers

For the series: Reviewed-by: Marek Olšák Marek On Mon, Sep 11, 2017 at 5:11 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > The GLSL rules for interpolateAtSample are unfortunate: > >"Returns the value of the input

Re: [Mesa-dev] [PATCH] util: Query build-id by symbol address, not library name

On Tue, Sep 12, 2017 at 5:05 PM, Chad Versace wrote: > This patch renames build_id_find_nhdr() to > build_id_find_nhdr_for_addr(), and changes it to never examine the > library name. > > Tested on Fedora by confirming that build_id_get_data() returns the same > build-id as the

Re: [Mesa-dev] [PATCH 1/2] radv/nir: call opt_remove_phis after trivial continues.

On 13/09/17 13:52, Timothy Arceri wrote: On 13/09/17 13:48, Dave Airlie wrote: On 13 September 2017 at 13:42, Timothy Arceri wrote: On 13/09/17 12:57, Dave Airlie wrote: From: Dave Airlie With the shaders in the ssao demo, the nir_opt_if

[Mesa-dev] [PATCH 4/4] i965: Use prepare_external instead of make_shareable in setTexBuffer2

The setTexBuffer2 hook from GLX is used to implement glxBindTexImageEXT which has tighter restrictions than just "it's shared". In particular, it says that any rendering to the image while it is bound causes the contents to become undefined. This means that we can do whatever aux tracking we

Re: [Mesa-dev] [PATCH] radeonsi/uvd: fix interlaced video buffer height alignment

On 2017-09-12 02:39 PM, Christian König wrote: The problem is: In si_uvd.c struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe, const struct pipe_video_buffer *tmpl) { struct pipe_video_buffer template; template.height =

Re: [Mesa-dev] [PATCH 1/2] radv/nir: call opt_remove_phis after trivial continues.

On 13 September 2017 at 13:42, Timothy Arceri wrote: > > On 13/09/17 12:57, Dave Airlie wrote: >> >> From: Dave Airlie >> >> With the shaders in the ssao demo, the nir_opt_if wasn't >> working properly without this, after this the if gets optimised >>

Re: [Mesa-dev] [PATCH 1.5/4] [RFC] ac/addrlib: relax an assertion

Reviewed-by: Marek Olšák Marek On Mon, Sep 11, 2017 at 3:26 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > --- > We hit this assertion with 3D textures on gfx9. > > I'm not aware of any 3D-texture-specific failures, but

Re: [Mesa-dev] [PATCH 4/4] radeonsi: rename variable to clarify its meaning

For the series: Reviewed-by: Marek Olšák Marek On Mon, Sep 11, 2017 at 5:06 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > --- > src/gallium/drivers/radeonsi/si_state.c | 20 ++-- > 1 file changed, 10

Re: [Mesa-dev] [Intel-gfx] [PATCH 1/2] drm/i915/kbl: Remove unused Kabylake pci ids

On Tue, Sep 12, 2017 at 08:30:47PM +, Paulo Zanoni wrote: > Em Seg, 2017-09-11 às 10:10 -0700, Rodrigo Vivi escreveu: > > On Mon, Sep 11, 2017 at 04:11:33PM +, Anuj Phogat wrote: > > > See Mesa commits: ebc5ccf and b2dae9f > > > > I believe we need to be in sync between multiple gfx stack

Re: [Mesa-dev] [PATCH 2/2] [rfc] nir: bump unroll instruction count to 96.

On 13/09/17 12:57, Dave Airlie wrote: From: Dave Airlie This gets the ssao demo from 400->440 fps on radv with the previous patch. Now the demo does a 0->32 loop across a ubo with 32 members, I don't know if we still have that sort of information available about the UBO in

Re: [Mesa-dev] [RFC] NIR serialization

I think the arguments for doing NIR serialization and deseriallization are pretty persuasive. I've started a skeleton of a NIR serialization implementation at https://cgit.freedesktop.org/~cwabbott0/mesa/log/?h=nir-serialize. Note that filling this in by following nir_clone should be mostly

[Mesa-dev] [PATCH] radv/gfx9: fix image resource handling.

From: Dave Airlie GFX9 changes how images are layed out, so this needs updating. Fixes: dEQP-VK.query_pool.statistics_query.* CC: "17.2" --- src/amd/vulkan/radv_image.c | 27

Re: [Mesa-dev] [PATCH 3/4] i965/tex_image: Reference the renderbuffer miptree in setTexBuffer2

On Tue, Sep 12, 2017 at 04:23:04PM -0700, Jason Ekstrand wrote: > The old code made a new miptree that referenced the same BO as the > renderbuffer and just trusted in the memory aliasing to work. There are > only two ways in which the new miptree is liable to differ from the one > in the

[Mesa-dev] [PATCH] radv/gfx9: set mip0-depth correctly for 2d arrays/3d images

From: Dave Airlie This field covers the whole resource. Fixes: dEQP-VK.pipeline.image.suballocation.sampling_type.combined.view_type.3d.format.* dEQP-VK.texture.filtering.3d.combinations.* Cc: "17.2" Signed-off-by: Dave Airlie

Re: [Mesa-dev] [PATCH] gallium/{r600, radeonsi}: Fix segfault with color format (v2)

Do you mean delete check in u_format.c:: util_format_is_supported? Could you please explain more? On Wed, Sep 13, 2017 at 1:32 AM, Marek Olšák wrote: > On Wed, Sep 13, 2017 at 12:31 AM, Marek Olšák wrote: > > I think we shouldn't be getting PIPE_FORMAT_COUNT

[Mesa-dev] [PATCH] radv/ac: bump params array for image atomic comp swap

From: Dave Airlie For the comp_swap case this was overflowing and crashing sometimes. Fixes: dEQP-VK.image.atomic_operations.compare_exchange.* Cc: "17.2" Signed-off-by: Dave Airlie ---

[Mesa-dev] [PATCH 2/2] radv: handle GFX9 1D textures

From: Dave Airlie As GFX9 can't handle 1D depth textures, radeonsi and apparantly pro just update all 1D textures to 2D, and work around it. This ports the workarounds from radeonsi. Cc: "17.2" Signed-off-by: Dave Airlie

[Mesa-dev] [PATCH 1/2] radv: don't use iview for meta image width/height.

From: Dave Airlie Work out the width/height from the level manually, as on GFX9 we won't minify the iview width/height. This fixes: dEQP-VK.api.image_clearing.core.clear_color_image* on gfx9 Cc: "17.2" Signed-off-by: Dave Airlie

Re: [Mesa-dev] [RFC] NIR serialization

On Tue, Sep 12, 2017 at 4:39 PM, Jason Ekstrand wrote: > On Tue, Sep 12, 2017 at 11:09 AM, Jason Ekstrand > wrote: >> >> On Tue, Sep 12, 2017 at 10:12 AM, Ian Romanick >> wrote: >>> >>> On 09/11/2017 11:17 PM, Kenneth Graunke

[Mesa-dev] [Bug 102639] BadLength (poly request too large or internal Xlib length erro

https://bugs.freedesktop.org/show_bug.cgi?id=102639 thomas changed: What|Removed |Added Status|NEW |RESOLVED

Re: [Mesa-dev] [PATCH 00/10] swr: update rasterizer

Reviewed-by: Bruce Cherniak > On Sep 11, 2017, at 2:28 PM, Tim Rowley wrote: > > Mostly some api changes, plus making the cpu topology code a bit more > robust in the face of some odd configurations seen in virtualized > environments. > >

[Mesa-dev] [PATCH 1/2] radv/nir: call opt_remove_phis after trivial continues.

From: Dave Airlie With the shaders in the ssao demo, the nir_opt_if wasn't working properly without this, after this the if gets optimised so that loop unrolling gets called. (loop unrolling fails due to instruction count, but at least it gets to do that.) Signed-off-by:

[Mesa-dev] [PATCH 2/2] [rfc] nir: bump unroll instruction count to 96.

From: Dave Airlie This gets the ssao demo from 400->440 fps on radv with the previous patch. Now the demo does a 0->32 loop across a ubo with 32 members, I don't know if we still have that sort of information available about the UBO in question at this stage. Maybe someone

Re: [Mesa-dev] [PATCH] gallium/{r600, radeonsi}: Fix segfault with color format (v2)

I think we shouldn't be getting PIPE_FORMAT_COUNT in is_format_supported in the first place, and therefore drivers don't have to work around it. Marek On Tue, Sep 12, 2017 at 10:38 PM, Denis Pauk wrote: > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102552 > >

Re: [Mesa-dev] [PATCH 1/8] nir: add is_xfb_only to nir variable

Whoop subject should be: nir: add always_active_io to nir variable On 13/09/17 09:37, Timothy Arceri wrote: Will be used in nir link pass to decided if we can remove a varying or not. --- src/compiler/glsl/glsl_to_nir.cpp | 1 + src/compiler/nir/nir.h| 10 ++ 2 files

Re: [Mesa-dev] [PATCH 2/2] radeonsi: remove SET_PREDICATION workaround on newer firmware

For the series: Reviewed-by: Marek Olšák Marek On Mon, Sep 11, 2017 at 5:01 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > We need to keep the workaround for older firmware, though. > --- >

Re: [Mesa-dev] [PATCH] (UNTESTED) virgl: filter out 2D constant file accesses and declarations

On 13 September 2017 at 06:34, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > Sorry for the mess. > > I suspect something like this patch is needed. Is this sufficient to > fix the problem? Oops I missed this, I just posted almost identical patch,

Re: [Mesa-dev] [PATCH] i965 : optimized bucket index calculation

>-Original Message- >From: Matt Turner [mailto:matts...@gmail.com] > >On Tue, Sep 12, 2017 at 10:19 AM, Ian Romanick wrote: >> On 09/12/2017 02:40 AM, Marathe, Yogesh wrote: >>> Hi Jason, >>> >>> >>> >>> On the asserts you’ve mentioned below, I assume we need to add

[Mesa-dev] [PATCH 2/4] i965: Reset miptree aux state on update_image_buffer

When we get a miptree in through glxBindImageEXT, we don't know the current aux state so we have to assume the worst-case. If the image gets recreated, everything is fine because miptreecreate_for_dri_image sets it to the default. However, if our miptree is recycled, then we may have stale

[Mesa-dev] [PATCH 3/4] i965/tex_image: Reference the renderbuffer miptree in setTexBuffer2

The old code made a new miptree that referenced the same BO as the renderbuffer and just trusted in the memory aliasing to work. There are only two ways in which the new miptree is liable to differ from the one in the renderbuffer and neither of them matter: 1) It may have a different target.

[Mesa-dev] [PATCH 1/4] intel/isl: Add a drm_modifier_get_default_aux_state helper

--- src/intel/isl/isl.h | 20 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index e77d7ee..d30b2de 100644 --- a/src/intel/isl/isl.h

[Mesa-dev] [PATCH 0/4] i965: Properly handle CCS in glxBindTexImageEXT

This little series fixes (I think!) a bug in glxBindTexImageEXT when using modifiers. Before, we were using make_shareable which resolves everything and then permanently throws away any aux information. In the world of modifiers, that aux information is suddenly important. This was causing

[Mesa-dev] [PATCH 3/8] nir: add a helper for getting the bitmask for a variable's location

--- src/compiler/nir/nir.h | 31 +++ 1 file changed, 31 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index fab2110f619..e52a1006896 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -351,6 +351,37 @@ typedef struct

[Mesa-dev] [PATCH 4/8] nir: add some helpers for doing linking

The initial helpers as support for removing unused varyings between stages. --- src/compiler/Makefile.sources | 1 + src/compiler/nir/nir.h | 6 ++ src/compiler/nir/nir_linking_helpers.c | 136 + 3 files changed, 143 insertions(+)

[Mesa-dev] i965 NIR linking

This started out based off the work Jason did back in 2015 to add NIR linking to the Intel VK driver. It needed a reasonable amount of updates to work with the GL driver, tess, xfb, etc. As per the results in patch 8, it can provide some nice improvements despite the GLSL IR linker already doing

[Mesa-dev] [PATCH 8/8] i965: make use of nir linking

For now linking is just removing unused varyings between stages. shader-db results BDW: total instructions in shared programs: 13198288 -> 13191693 (-0.05%) instructions in affected programs: 48325 -> 41730 (-13.65%) helped: 473 HURT: 0 total cycles in shared programs: 541184926 -> 541159260

[Mesa-dev] [PATCH mesa] glsl: compile unused function out

The function is only called from one place, which is hidden behind the same `#ifdef DEBUG`. Fixes: ca73c3358c91434e68ab "glsl: Mark functions static" Signed-off-by: Eric Engestrom --- src/compiler/glsl/ir_validate.cpp | 2 ++ 1 file changed, 2 insertions(+) diff

Re: [Mesa-dev] [PATCH mesa] glx: remove dead code

On Wednesday, 2017-09-06 17:25:29 +0100, Emil Velikov wrote: > On 6 September 2017 at 17:17, Adam Jackson wrote: > > On Fri, 2017-09-01 at 15:04 +0100, Eric Engestrom wrote: > >> These fields were added in 2d94601582 but never used; hasPresent was > >> never set, while the other

Re: [Mesa-dev] [PATCH mesa] docs/egl: remove reference to EGL_DRIVERS_PATH

On 12 September 2017 at 15:38, Eric Engestrom wrote: > Support for external egl drivers was dropped a few years ago. > > Fixes: 209360bbb91bb10346eb "egl/main: drop support for external egl drivers" > Signed-off-by: Eric Engestrom Thanks!

[Mesa-dev] [PATCH mesa] radv: compile out unused code

Signed-off-by: Eric Engestrom --- src/amd/vulkan/radv_wsi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c index aa44b7d78a..8a551c48bb 100644 --- a/src/amd/vulkan/radv_wsi.c +++ b/src/amd/vulkan/radv_wsi.c

Re: [Mesa-dev] [PATCH mesa] glx: remove dead code

On Tue, 2017-09-12 at 16:08 +0100, Eric Engestrom wrote: > On Wednesday, 2017-09-06 17:25:29 +0100, Emil Velikov wrote: > > I'm not that much of an expert on things XCB, so perhaps a silly question. > > Isn't the presence checked with the code just above the removed hunk? > > Namely: > > > >

[Mesa-dev] [PATCH] i965: add BRW_NEW_BLORP to the list of dirty state for render targets

Commit b96313c0e1289b removed BRW_NEW_BLORP for a bunch of SURFACE_STATE setup code, including render targets, on the basis that blorp invalidates binding tables but not surface states, however, at least on Broadwell, this seems to be causing a regression in a CTS test that seems related to render

Re: [Mesa-dev] [PATCH] r600/sb: remove superfluos assert

Am Dienstag, den 12.09.2017, 09:56 +0300 schrieb Vadim Girlin: > On 09/11/2017 07:09 PM, Emil Velikov wrote: > Anyway, if num_arrays is 0 there, I suspect it can be a result of > some other issue. At the very least it looks like a potential > performance problem, because in that case we assume

[Mesa-dev] [PATCH 10/15] radeonsi: move si_get_wave_info() to AMD common code

This will allow us to use it from radv. Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_debug.c | 76 ++ src/amd/common/ac_debug.h | 18 +++ src/gallium/drivers/radeonsi/si_debug.c | 96

[Mesa-dev] [PATCH 02/15] radv: save the bound pipeline pointers into the trace BO

When a GPU hang is detected in radv_gpu_hang_occured() we know which command buffer is faulty but the bound pipelines might have been updated during the execution. The pointers to the radv_pipeline objects are emitted just after the second trace ID, that way it would be easy to dump the active

[Mesa-dev] [PATCH 07/15] radv: dump shader stats when a hang occured

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_debug.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c index fe9d9cfdba..4abdb6489e 100644 --- a/src/amd/vulkan/radv_debug.c +++

[Mesa-dev] [PATCH 12/15] radv: save all descriptor pointers into the trace BO

To dump them when a hang is detected. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 32 src/amd/vulkan/radv_debug.c | 3 +++ 2 files changed, 35 insertions(+) diff --git a/src/amd/vulkan/radv_cmd_buffer.c

[Mesa-dev] [PATCH 08/15] radv/winsys: add a read_registers() callback

To dump some status MMIO registers when a hang is detected. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_radeon_winsys.h | 3 +++ src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c | 11 +++ 2 files changed, 14 insertions(+) diff --git

[Mesa-dev] [PATCH 09/15] radv: dump some status MMIO registers when a hang occured

Might report some useful information to help figuring out where does the hang happened. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_debug.c | 57 + 1 file changed, 57 insertions(+) diff --git

[Mesa-dev] [PATCH 05/15] radv: dump the active shaders when a hang occured

Only the disassembly is currently dumped. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_debug.c | 78 ++--- 1 file changed, 73 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/radv_debug.c

[Mesa-dev] [PATCH 11/15] radv: dump annotated shaders using UMR

This might be very useful in order to figure out where a shader is stucked. This uses UMR to detect which instruction is executing bad things. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_debug.c | 166 1 file

Re: [Mesa-dev] [PATCH] anv: fix build issues on release build

On 12 September 2017 at 11:11, Tapani Pälli wrote: > Fixes: d083bc1c4b ("anv: wire up vk_errorf macro to do debug reporting") > Signed-off-by: Tapani Pälli FWIW Reviewed-by: Emil Velikov -Emil

[Mesa-dev] [PATCH mesa] r600: extend use of HAS_SIZE() macro

The macro was only used a few times; let's use it everywhere, simplifying the code. I also uniformised the use of curly brackets by adding them around all uses of the macro, removed a few unnecessary `else` after `return`, and turned a ternary op into an `if`. Signed-off-by: Eric Engestrom

Re: [Mesa-dev] Is there a mesa Docker image available like on travis-ci? (was Re: [PATCH 1/2] gallium/targets/dri: Add libunwind to linker flags)

On 12 September 2017 at 11:17, Gert Wollny wrote: > >> > This doesn't seem right. GALLIUM_COMMON_LIB_DEPS already has >> > $(LIBUNWIND_LIBS) so this change should not be needed. >> >> I already started looking at this, but haven't been able to figure >> out why in this

[Mesa-dev] [PATCH] anv: fix build issues on release build

Fixes: d083bc1c4b ("anv: wire up vk_errorf macro to do debug reporting") Signed-off-by: Tapani Pälli --- src/intel/vulkan/anv_private.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h

[Mesa-dev] [PATCH 13/15] radv: dump descriptors when a hang occured

Might be useful for checking if all descriptors are sets by the application. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_debug.c | 181 1 file changed, 181 insertions(+) diff --git a/src/amd/vulkan/radv_debug.c

[Mesa-dev] [PATCH 15/15] radv: dump the list of enabled options when a hang occured

Useful to know which debug/perftest options were enabled when a hang report is generated. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_debug.c | 25 + src/amd/vulkan/radv_device.c | 14 ++ src/amd/vulkan/radv_private.h

[Mesa-dev] [PATCH 14/15] radv: dump last 60 lines of dmesg when a hang occured

Copied from dd_dump_dmesg(). Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_debug.c | 20 1 file changed, 20 insertions(+) diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c index 741bf76f15..106c6e4f64 100644 ---

Re: [Mesa-dev] [PATCH] glsl: remove assert in lower_packed_varyings

Reviewed-by: Marek Olšák Marek On Mon, Sep 11, 2017 at 3:37 PM, Ilia Mirkin wrote: > It's obviously misformed, and it's triggering on > > dEQP-GLES31.functional.program_interface_query.program_input.type.separable_geometry.int > > and a few related

[Mesa-dev] [PATCH 00/15] radv: GPU hangs should now be easier to detect

Hi, Currently, it's not easy to debug a GPU hang with radv because only a trace file is generated (cf. RADV_TRACE_FILE). That file contains all packets and commands emitted into the IB, that's useful but definitely not enough. For example, the active shaders at the moment of the hang are not

[Mesa-dev] [PATCH 04/15] radv: add debug flags for syncing shaders after every draw call

To improve GPU hangs detection when shaders are stucked. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 15 +++ src/amd/vulkan/radv_debug.h | 1 + src/amd/vulkan/radv_device.c | 1 + 3 files changed, 17 insertions(+) diff

[Mesa-dev] [PATCH 01/15] radv: add a comment that describes the trace BO layout

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_debug.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c index d52ba5d86d..052daaef2f 100644 --- a/src/amd/vulkan/radv_debug.c +++

[Mesa-dev] [PATCH 06/15] radv: add radv_shader_dump_stats() helper

To dump the shader stats when a hang is detected. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_pipeline.c | 64 +- src/amd/vulkan/radv_shader.c | 70 ++

[Mesa-dev] [PATCH 03/15] radv: add radv_cmd_buffer_after_draw() helper function

To share common code after every draw/compute calls. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c

[Mesa-dev] [Bug 102665] test_glsl_to_tgsi_lifetime.cpp:53:67: error: ‘?=>>=?UTF-8?Q?’ should be ‘?=> >=?UTF-8?Q?’ within a nested template argument list

https://bugs.freedesktop.org/show_bug.cgi?id=102665 --- Comment #2 from Emil Velikov --- One option is to add space between the two >> - it's compatible with older C++ standards and part of Mesa already uses it. Alternatively, move '&' one character to the right (again

[Mesa-dev] Is there a mesa Docker image available like on travis-ci? (was Re: [PATCH 1/2] gallium/targets/dri: Add libunwind to linker flags)

> > This doesn't seem right. GALLIUM_COMMON_LIB_DEPS already has > > $(LIBUNWIND_LIBS) so this change should not be needed. > > I already started looking at this, but haven't been able to figure > out why in this specific configuration GALLIUM_COMMON_LIB_DEPS seems > to be empty, or at least it

Re: [Mesa-dev] [PATCH] anv: fix build issues on release build

On 12 September 2017 at 11:11, Tapani Pälli wrote: > Fixes: d083bc1c4b ("anv: wire up vk_errorf macro to do debug reporting") > Signed-off-by: Tapani Pälli Reviewed-by: Daniel Stone

Re: [Mesa-dev] [PATCH 10/15] radeonsi: move si_get_wave_info() to AMD common code

Reviewed-by: Marek Olšák Marek On Tue, Sep 12, 2017 at 12:35 PM, Samuel Pitoiset wrote: > This will allow us to use it from radv. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/common/ac_debug.c | 76

[Mesa-dev] [PATCH] glsl: Disallow unsized array of atomic_uint

This was a bugfix to the spec addressed in OpenGL 4.5 and there is a CTS test to check this. Fixes: KHR-GL45.shader_atomic_counters.negative-unsized-array --- src/compiler/glsl/ast_to_hir.cpp | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/compiler/glsl/ast_to_hir.cpp

Re: [Mesa-dev] [RFC] NIR serialization

On 2017-09-10 17:15:48, Timothy Arceri wrote: > Ccing list. > > On 11/09/17 09:50, Timothy Arceri wrote: > > Hi Daniel, > > > > Here is the code that does the caching of tgsi in Gallium. > > > > https://cgit.freedesktop.org/mesa/mesa/tree/src/mesa/state_tracker/st_shader_cache.c > > > > > >

[Mesa-dev] [PATCH mesa] swr: use ARRAY_SIZE macro

Signed-off-by: Eric Engestrom --- src/gallium/drivers/swr/rasterizer/memory/StoreTile.h | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/memory/StoreTile.h

Re: [Mesa-dev] [PATCH 01/15] radv: add a comment that describes the trace BO layout

add something that the offsets are in multiple of 4 bytes? On Tue, Sep 12, 2017 at 12:35 PM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_debug.c | 6 ++ > 1 file changed, 6 insertions(+) > > diff

Re: [Mesa-dev] [PATCH 01/15] radv: add a comment that describes the trace BO layout

On 09/12/2017 08:05 PM, Bas Nieuwenhuizen wrote: add something that the offsets are in multiple of 4 bytes? Okay. On Tue, Sep 12, 2017 at 12:35 PM, Samuel Pitoiset wrote: Signed-off-by: Samuel Pitoiset ---

Re: [Mesa-dev] [PATCH 05/15] radv: dump the active shaders when a hang occured

On 09/12/2017 09:07 PM, Bas Nieuwenhuizen wrote: On Tue, Sep 12, 2017 at 8:57 PM, Samuel Pitoiset wrote: On 09/12/2017 08:12 PM, Bas Nieuwenhuizen wrote: On Tue, Sep 12, 2017 at 12:35 PM, Samuel Pitoiset wrote: Only the disassembly

Re: [Mesa-dev] [PATCH 05/15] radv: dump the active shaders when a hang occured

On 09/12/2017 09:16 PM, Bas Nieuwenhuizen wrote: On Tue, Sep 12, 2017 at 9:13 PM, Samuel Pitoiset wrote: On 09/12/2017 09:07 PM, Bas Nieuwenhuizen wrote: On Tue, Sep 12, 2017 at 8:57 PM, Samuel Pitoiset wrote: On 09/12/2017 08:12

Re: [Mesa-dev] [PATCH] i965 : optimized bucket index calculation

On Tue, Sep 12, 2017 at 10:19 AM, Ian Romanick wrote: > On 09/12/2017 02:40 AM, Marathe, Yogesh wrote: >> Hi Jason, >> >> >> >> On the asserts you’ve mentioned below, I assume we need to add them >> after ‘bufmgr->num_buckets++’ in add_bucket() as num_buckets could be 0 >>

Re: [Mesa-dev] [PATCH] radeonsi/uvd: fix interlaced video buffer height alignment

Am 12.09.2017 um 18:10 schrieb Leo Liu: On 09/12/2017 11:37 AM, Christian König wrote: Am 12.09.2017 um 17:32 schrieb Leo Liu: On 09/12/2017 11:23 AM, Christian König wrote: I don't think this is correct. A long long time ago I've came up with this because the firmware didn't liked what

Re: [Mesa-dev] [PATCH 05/15] radv: dump the active shaders when a hang occured

On 09/12/2017 08:12 PM, Bas Nieuwenhuizen wrote: On Tue, Sep 12, 2017 at 12:35 PM, Samuel Pitoiset wrote: Only the disassembly is currently dumped. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_debug.c | 78

Re: [Mesa-dev] [PATCH 05/15] radv: dump the active shaders when a hang occured

On Tue, Sep 12, 2017 at 8:57 PM, Samuel Pitoiset wrote: > > > On 09/12/2017 08:12 PM, Bas Nieuwenhuizen wrote: >> >> On Tue, Sep 12, 2017 at 12:35 PM, Samuel Pitoiset >> wrote: >>> >>> Only the disassembly is currently dumped. >>> >>>

Re: [Mesa-dev] [PATCH 05/15] radv: dump the active shaders when a hang occured

On Tue, Sep 12, 2017 at 12:35 PM, Samuel Pitoiset wrote: > Only the disassembly is currently dumped. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_debug.c | 78 > ++--- > 1 file

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