Re: [Mesa-dev] [PATCH 1/3] amd/common: scan which components of gl_WorkGroupID are used

On 12/14/2017 08:32 PM, Bas Nieuwenhuizen wrote: On Thu, Dec 14, 2017 at 4:48 PM, Samuel Pitoiset wrote: Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_shader_info.c | 8 src/amd/common/ac_shader_info.h | 1 + 2 files

[Mesa-dev] [ANNOUNCE] mesa 17.2.7

Mesa 17.2.7 is now available. In this release we have: The current queue consists of a variety of fixes, with a sizeable hunk in the shared GLSL codebase. Whereas for individual drivers - i965 has a crash fix for when playing various Valve games, r600 and nouveau have tweaks in their compiler

[Mesa-dev] [PATCH 3/3] radv: set FORCE_SIMD_DIST(1) for compute when profitable

Ported from RadeonSI. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index d6aaff707b..4a048485c8 100644 ---

[Mesa-dev] [PATCH 2/3] radv: calculate best compute resource limits

Ported from RadeonSI. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index

[Mesa-dev] [PATCH 1/3] radv: store the dispatch initiator into the device

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 12 +--- src/amd/vulkan/radv_device.c | 10 ++ src/amd/vulkan/radv_private.h| 1 + 3 files changed, 12 insertions(+), 11 deletions(-) diff --git

[Mesa-dev] [PATCH 3/3] radv: export SampleMask from pixel shaders at full rate

Use 16_ABGR instead of 32_ABGR if Z isn't written. Ported from RadeonSI. No CTS regressions on Polaris. v2: - make use of ac_get_spi_shader_z_format() Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 46 +++--

[Mesa-dev] [PATCH 2/3] radeonsi: make use of ac_get_spi_shader_z_format()

Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/radeonsi/si_shader.c| 22 ++ src/gallium/drivers/radeonsi/si_shader.h| 2 -- src/gallium/drivers/radeonsi/si_state_shaders.c | 3 ++- 3 files changed, 4 insertions(+), 23

[Mesa-dev] [PATCH 1/3] amd/common: add ac_get_spi_shader_z_format()

ac_shader_util.c will contain shader helpers for RadeonSI and RADV. Signed-off-by: Samuel Pitoiset --- src/amd/Makefile.sources| 5 - src/amd/common/ac_shader_util.c | 45 + src/amd/common/ac_shader_util.h | 33

Re: [Mesa-dev] [PATCH 2/4] radeon/vce: determine idr by pic type

On 12/13/2017 01:59 PM, boyuan.zh...@amd.com wrote: From: Boyuan Zhang Signed-off-by: Boyuan Zhang Reviewed-by: Leo Liu --- src/gallium/drivers/radeon/radeon_vce_52.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

Re: [Mesa-dev] [PATCH] radeonsi: don't use fast color clear for small images even on APUs

On 12/13/2017 12:53 AM, Marek Olšák wrote: From: Marek Olšák Increase the limit and handle non-square images better. This makes glxgears 20% faster on APUs, and a little more on dGPUs. We all use and love glxgears. We love it. :) Reviewed-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH 3/3] Revert "i965: Disable regular fast-clears (CCS_D) on gen9+"

Hi, As expected, this series fixes the perf regression in GfxBench when fast clears were disabled. On SKL GT2: * 2-5% Manhattan 3.1 * 1% AztecRuins & CarChase (on top of Francisco's large improvement between the perf regression and this fix) On 14.12.2017 03:54, Jason Ekstrand wrote:

[Mesa-dev] [PATCH 3/3] radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID components

We should also not load the input SGPRs and VGPRS, but let's start with this for now. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_shader.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_shader.c

[Mesa-dev] [PATCH 2/3] amd/common: scan which components of gl_LocalInvocationID are used

Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_shader_info.c | 7 ++- src/amd/common/ac_shader_info.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_shader_info.c b/src/amd/common/ac_shader_info.c index

[Mesa-dev] [PATCH 1/3] amd/common: scan which components of gl_WorkGroupID are used

Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_shader_info.c | 8 src/amd/common/ac_shader_info.h | 1 + 2 files changed, 9 insertions(+) diff --git a/src/amd/common/ac_shader_info.c b/src/amd/common/ac_shader_info.c index 09dd4bbd55..01949770d6 100644

Re: [Mesa-dev] AMD WX7100 screen display problem on AArch64 architecture server.

On 12/13/2017 07:46 AM, Lvzhihong (ReJohn) wrote: > Hi, > >    We met a problem on ubuntu17.10 for arm server with amdgpu(AMD > RADEON PRO WX7100),  we use open source driver which are integrated in > ubuntu17.10. And the architecture is AArch64-linux-gnu. > > we install : > >  

[Mesa-dev] [PATCH] radv: do not load the local invocation index when it's unused

Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 3 ++- src/amd/common/ac_shader_info.c | 3 +++ src/amd/common/ac_shader_info.h | 1 + src/amd/vulkan/radv_shader.c| 2 +- 4 files changed, 7 insertions(+), 2 deletions(-) diff --git

Re: [Mesa-dev] [PATCH 0/4] GL_EXT_disjoint_timer_query series

Since you remembered to modify dispatch_sanity.cpp in patch 2, I'm going to assume that 'make check' still passes. If that's the case, the series is Reviewed-by: Ian Romanick On 12/14/2017 04:03 AM, Tapani Pälli wrote: > Hi; > > Here's a revisited

Re: [Mesa-dev] [PATCH 3/3] radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID components

Reviewed-by: Bas Nieuwenhuizen for the series. On Thu, Dec 14, 2017 at 4:48 PM, Samuel Pitoiset wrote: > We should also not load the input SGPRs and VGPRS, but > let's start with this for now. > > Signed-off-by: Samuel Pitoiset

[Mesa-dev] [PATCH] util: scons: wire up the sha1 test

From: Emil Velikov Cc: Fixes: 513d7ffa23d ("util: Add a SHA1 unit test program") Signed-off-by: Emil Velikov --- We want this and the original commit for stable, to catch any breakage that may happen.

Re: [Mesa-dev] [PATCH v2 3/4] meson: build clover

On Wed, 2017-12-13 at 14:56 -0800, Dylan Baker wrote: > Quoting Jan Vesely (2017-12-13 14:23:21) > > On Wed, 2017-12-13 at 13:54 -0800, Dylan Baker wrote: > > > Quoting Jan Vesely (2017-12-13 12:53:25) > > > > On Wed, 2017-12-13 at 09:47 -0800, Dylan Baker wrote: > > > > > +if (with_gallium_va or

Re: [Mesa-dev] [PATCH] radv: do not load the local invocation index when it's unused

Reviewed-by: Bas Nieuwenhuizen On Thu, Dec 14, 2017 at 5:32 PM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/amd/common/ac_nir_to_llvm.c | 3 ++- > src/amd/common/ac_shader_info.c | 3 +++ >

Re: [Mesa-dev] [PATCH 3/3] radv: set FORCE_SIMD_DIST(1) for compute when profitable

Reviewed-by: Bas Nieuwenhuizen Would it make sense to move the compute_resource_limits calculation to pipeline creation time? On Thu, Dec 14, 2017 at 3:51 PM, Samuel Pitoiset wrote: > Ported from RadeonSI. > > Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH 1/3] amd/common: scan which components of gl_WorkGroupID are used

On Thu, Dec 14, 2017 at 4:48 PM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/amd/common/ac_shader_info.c | 8 > src/amd/common/ac_shader_info.h | 1 + > 2 files changed, 9 insertions(+) > > diff --git

Re: [Mesa-dev] [PATCH 1/3] amd/common: add ac_get_spi_shader_z_format()

Reviewed-by: Bas Nieuwenhuizen for the series. On Thu, Dec 14, 2017 at 1:51 PM, Samuel Pitoiset wrote: > ac_shader_util.c will contain shader helpers for RadeonSI > and RADV. > > Signed-off-by: Samuel Pitoiset >

[Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround

From: Kevin Rogovin This patch series implements a needed workaround for Gen9 for ASTC5x5 sampler reads. The crux of the work around is to make sure that the sampler does not read an ASTC5x5 texture and a surface with an auxilary buffer without having a texture cache

[Mesa-dev] [PATCH v2 2/5] i965: set ASTC5x5 workaround texture type tracking on texture validate

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/intel_tex_validate.c | 13 + 1 file changed, 13 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c

[Mesa-dev] [PATCH v2 1/5] i965: define astx5x5 workaround infrastructure

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/Makefile.sources| 1 + src/mesa/drivers/dri/i965/brw_context.c | 6 + src/mesa/drivers/dri/i965/brw_context.h | 24 ++

[Mesa-dev] [PATCH v2 4/5] i965: use ASTC5x5 workaround in brw_compute

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_compute.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_compute.c b/src/mesa/drivers/dri/i965/brw_compute.c index

[Mesa-dev] [PATCH v2 3/5] i965: use ASTC5x5 workaround in brw_draw

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/brw_draw.c | 16 ++-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 + 2 files changed, 19 insertions(+), 2 deletions(-) diff

[Mesa-dev] [PATCH v2 5/5] i965: ASTC5x5 workaround logic for blorp

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/mesa/drivers/dri/i965/genX_blorp_exec.c | 5 + src/mesa/drivers/dri/i965/intel_tex_image.c | 16 2 files changed, 17 insertions(+), 4 deletions(-) diff --git

[Mesa-dev] [PATCH 11/20] swr/rast: SIMD16 Fetch - Fully widen 16-bit float vertex components

--- .../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 55 +++--- 1 file changed, 48 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp b/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp index 2065db3475..c960dc77fb 100644

[Mesa-dev] [PATCH 03/20] swr/rast: Corrections to multi-scissor handling

binner's GatherScissors() will be turned into a real gather in the not too distant future. --- src/gallium/drivers/swr/rasterizer/core/binner.cpp | 176 ++--- 1 file changed, 88 insertions(+), 88 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/core/binner.cpp

[Mesa-dev] [PATCH 01/20] swr/rast: Remove unneeded copy of gather mask

--- .../drivers/swr/rasterizer/jitter/builder_misc.cpp | 22 +- .../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 80 ++ 2 files changed, 23 insertions(+), 79 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.cpp

[Mesa-dev] [PATCH 08/20] swr/rast: Pull most of the VPAI manipulation out of the binner/clipper

Move out of binner/clipper; hand them down from the frontend code instead. --- src/gallium/drivers/swr/rasterizer/core/binner.cpp | 124 ++--- src/gallium/drivers/swr/rasterizer/core/clip.cpp | 25 ++--- src/gallium/drivers/swr/rasterizer/core/clip.h | 58 +++---

[Mesa-dev] [PATCH 02/20] swr/rast: Binner fixes for viewport index offset handling

--- src/gallium/drivers/swr/rasterizer/core/binner.cpp | 9 - src/gallium/drivers/swr/rasterizer/core/clip.h | 5 - 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/core/binner.cpp

[Mesa-dev] [PATCH 00/20] swr: update rasterizer

Highlights include simd16 work, thread pool initialization rework, and code cleanup. Tim Rowley (20): swr/rast: Remove unneeded copy of gather mask swr/rast: Binner fixes for viewport index offset handling swr/rast: Corrections to multi-scissor handling swr/rast: WIP - Widen fetch shader

[Mesa-dev] [PATCH 04/20] swr/rast: WIP - Widen fetch shader to SIMD16

Widen vertex gather/storage to SIMD16 for all component types. --- .../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 716 - 1 file changed, 689 insertions(+), 27 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp

[Mesa-dev] [PATCH 10/20] swr/rast: SIMD16 Fetch - Fully widen 32-bit float vertex components

--- .../swr/rasterizer/codegen/gen_llvm_ir_macros.py | 3 +- .../drivers/swr/rasterizer/jitter/builder_misc.cpp | 41 - .../drivers/swr/rasterizer/jitter/builder_misc.h | 7 +- .../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 175 ++--- 4 files changed, 194

[Mesa-dev] [PATCH 05/20] swr/rast: Convert gather masks to Nx1bit

Simplifies calling code, gets gather function interface closer to llvm's masked_gather. --- .../drivers/swr/rasterizer/jitter/builder_misc.cpp | 20 + .../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 34 +- 2 files changed, 14 insertions(+), 40 deletions(-)

[Mesa-dev] [PATCH 06/20] swr/rast: Rewrite Shuffle8bpcGatherd using shuffle

Ease future code maintenance, prepare for folding simd8 and simd16 versions. --- .../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 244 ++--- 1 file changed, 62 insertions(+), 182 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp

[Mesa-dev] [PATCH 07/20] swr/rast: Move GatherScissors to header

--- src/gallium/drivers/swr/rasterizer/core/binner.cpp | 127 - src/gallium/drivers/swr/rasterizer/core/binner.h | 127 + 2 files changed, 127 insertions(+), 127 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/core/binner.cpp

[Mesa-dev] [PATCH 09/20] swr/rast: Pass prim to ClipSimd

--- src/gallium/drivers/swr/rasterizer/core/clip.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/core/clip.h b/src/gallium/drivers/swr/rasterizer/core/clip.h index 148f661ab4..8b947668d3 100644 ---

Re: [Mesa-dev] [PATCH 1/2] radv: always emit all compute block components

Reviewed-by: Bas Nieuwenhuizen On Thu, Dec 14, 2017 at 12:51 PM, Samuel Pitoiset wrote: > The number of grid components is always 3 when gl_NumWorkGroups > is declared, because it relies on the number of components of >

Re: [Mesa-dev] [PATCH 3/3] radv: set FORCE_SIMD_DIST(1) for compute when profitable

On 12/14/2017 08:35 PM, Bas Nieuwenhuizen wrote: Reviewed-by: Bas Nieuwenhuizen Would it make sense to move the compute_resource_limits calculation to pipeline creation time? Yeah, possibly. On Thu, Dec 14, 2017 at 3:51 PM, Samuel Pitoiset

[Mesa-dev] [PATCH 15/20] swr/rast: Pull of RTAI gather & offset out of clip/bin code

--- src/gallium/drivers/swr/rasterizer/core/binner.cpp | 118 +++- src/gallium/drivers/swr/rasterizer/core/clip.cpp | 30 ++-- src/gallium/drivers/swr/rasterizer/core/clip.h | 35 +++-- src/gallium/drivers/swr/rasterizer/core/context.h | 4 +-

[Mesa-dev] [PATCH 16/20] swr/rast: Rework thread binding parameters for machine partitioning

Add BASE_NUMA_NODE, BASE_CORE, BASE_THREAD parameters to SwrCreateContext. Add optional SWR_API_THREADING_INFO parameter to SwrCreateContext to control reservation of API threads. Add SwrBindApiThread() function to allow binding of API threads to reserved HW threads. ---

[Mesa-dev] [PATCH 14/20] swr/rast: Remove no-op VBROADCAST of vID

--- src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp b/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp index ec3b5eafcc..1312ac0009 100644 ---

[Mesa-dev] [PATCH 12/20] swr/rast: Replace INSERT2 vextract/vinsert with JOIN2 vshuffle

--- .../drivers/swr/rasterizer/jitter/builder_misc.cpp | 38 ++--- .../drivers/swr/rasterizer/jitter/builder_misc.h | 5 +- .../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 92 ++ 3 files changed, 30 insertions(+), 105 deletions(-) diff --git

[Mesa-dev] [PATCH 20/20] swr/rast: Move more RTAI handling out of binner

--- src/gallium/drivers/swr/rasterizer/core/binner.cpp | 13 + src/gallium/drivers/swr/rasterizer/core/clip.h | 1 + 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/core/binner.cpp

[Mesa-dev] [PATCH 13/20] swr/rast: SIMD16 Fetch - Fully widen 32-bit integer vertex components

Also widen the 16-bit a 8-bit integer vertex component gathers to SIMD16. --- .../swr/rasterizer/codegen/gen_llvm_ir_macros.py | 1 + .../drivers/swr/rasterizer/jitter/builder_misc.cpp | 36 + .../drivers/swr/rasterizer/jitter/builder_misc.h | 3 +

[Mesa-dev] [PATCH 18/20] swr/rast: Fix cache of API thread event manager

--- src/gallium/drivers/swr/rasterizer/core/api.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/swr/rasterizer/core/api.cpp b/src/gallium/drivers/swr/rasterizer/core/api.cpp index 25a3f34841..09b482dcc0 100644 ---

[Mesa-dev] [PATCH 19/20] swr/rast: EXTRACT2 changed from vextract/vinsert to vshuffle

--- .../drivers/swr/rasterizer/jitter/builder_misc.cpp | 60 ++ .../drivers/swr/rasterizer/jitter/builder_misc.h | 3 +- .../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 30 +-- 3 files changed, 32 insertions(+), 61 deletions(-) diff --git

[Mesa-dev] [PATCH 17/20] swr/rast: Replace VPSRL with LSHR

Replace use of x86 intrinsic with general llvm IR instruction. Generates the same final assembly. --- .../swr/rasterizer/codegen/gen_llvm_ir_macros.py | 2 -- .../drivers/swr/rasterizer/jitter/builder_misc.cpp | 30 -- .../drivers/swr/rasterizer/jitter/builder_misc.h |

Re: [Mesa-dev] [PATCH] drirc: add option to disable ARB_draw_indirect

On Wed, Dec 6, 2017 at 3:31 PM, Ian Romanick wrote: > On 12/05/2017 08:25 AM, Ilia Mirkin wrote: >> On Tue, Dec 5, 2017 at 8:18 AM, Emil Velikov >> wrote: >>> Hi Rob, >>> >>> On 5 December 2017 at 12:54, Rob Clark wrote:

Re: [Mesa-dev] [PATCH v2 00/25] Initial gl_spirv and spirv_extensions support in Mesa and i965

Any chance to wrap up this review? Thanks! Eduardo On 11/30/2017 06:28 PM, Eduardo Lima Mitev wrote: > Hello, > > This is the second version of the series providing initial support for > ARB_gl_spirv and ARB_spirv_extensions in Mesa and i965. > > First version of the series can be found at >

Re: [Mesa-dev] [PATCH] isl: Don't require VALIGN_2 for R32G32B32_FLOAT on Haswell.

Fine with me Reviewed-by: Jason Ekstrand On Thu, Dec 14, 2017 at 4:56 PM, Kenneth Graunke wrote: > According to the RENDER_SURFACE_STATE internal documentation, the > R32G32B32_FLOAT restriction is marked "IVB" only. We choose to apply > it to

Re: [Mesa-dev] [PATCH v3 00/10] Initial gl_spirv support in Mesa and i965

Any chance to wrap up this review? Thanks! Eduardo On 12/13/2017 08:32 PM, Eduardo Lima Mitev wrote: > Hi, > > This is the 3rd version of the series adding initial support for ARB_gl_spirv. > > Previous versions of this series included also support for > ARB_spirv_extensions, but we have

Re: [Mesa-dev] [PATCH] st/st_glsl_to_nir: call nir_lower_64bit_pack

Tested-by: Dieter Nützel Dieter Am 14.12.2017 06:02, schrieb Timothy Arceri: Fixes 56 crashes in radeonsi. --- src/mesa/state_tracker/st_glsl_to_nir.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp

Re: [Mesa-dev] [PATCH] st/glsl_to_nir: add patch support to st_nir_assign_var_locations()

Tested-by: Dieter Nützel Dieter Am 14.12.2017 00:14, schrieb Timothy Arceri: --- src/mesa/state_tracker/st_glsl_to_nir.cpp | 22 +- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp

Re: [Mesa-dev] [PATCH] st/glsl_to_nir: call post opt functions after opts have finished

Tested-by: Dieter Nützel Dieter Am 14.12.2017 04:48, schrieb Timothy Arceri: We need to move this to a separate loop because nir_compact_varyings() can alter the IR of a previous stage. Fixes: 6648bd68fd27 "st/glsl_to_nir: enable NIR link time opts" ---

Re: [Mesa-dev] [PATCH] spirv: Relax the validation conditions of OpSelect

It turns out there's already a glslang bug for this and it was closed in March: https://github.com/KhronosGroup/glslang/issues/809 Unfortunately, there are applications shipping with these shaders so failure isn't really an option. --Jason On Thu, Dec 14, 2017 at 7:56 PM, Jason Ekstrand

Re: [Mesa-dev] [PATCH 0/4] GL_EXT_disjoint_timer_query series

On 14.12.2017 21:20, Ian Romanick wrote: Since you remembered to modify dispatch_sanity.cpp in patch 2, I'm going to assume that 'make check' still passes. If that's the case, the series is Reviewed-by: Ian Romanick Yes, 'make check' passes; Thanks for the

Re: [Mesa-dev] [PATCH v2 00/25] Initial gl_spirv and spirv_extensions support in Mesa and i965

Oops, sorry, wrong thread. This is version 2 of the series and there is a version 3 which is the one that needs review. Eduardo On 12/15/2017 08:13 AM, Eduardo Lima Mitev wrote: > Any chance to wrap up this review? > > Thanks! > > Eduardo > > On 11/30/2017 06:28 PM, Eduardo Lima Mitev wrote:

[Mesa-dev] [PATCH] spirv: Relax the validation conditions of OpSelect

The Talos Principle contains shaders with an OpSelect between two vectors where the condition is a scalar boolean. This is technically against the spec bout nir_builder gracefully handles it by splatting out the condition to all the channels. So long as the condition is a boolean, just emit a

Re: [Mesa-dev] [PATCH v2 07/20] ac: move some helpers to ac_llvm_build.c

This one do not apply anylonger after Samuel's commit amd/common: add ac_build_waitcnt() #225b19880204024a805cc54b1001d09ef3b58054 For your motivation: I've tested V1 and V2 of the whole series (before the latest master commits) and could ran _all_ my 'normal' stuff. Even UH run with GREAT

[Mesa-dev] [PATCH] isl: Don't require VALIGN_2 for R32G32B32_FLOAT on Haswell.

According to the RENDER_SURFACE_STATE internal documentation, the R32G32B32_FLOAT restriction is marked "IVB" only. We choose to apply it to Ivybridge and Baytrail, but not Haswell. Fixes KHR-GL46.texture_size_promotion.functional on Haswell. Changes these tests from crashing to skipping on

[Mesa-dev] [PATCH] gallium: Deallocate screens and buffers on exit.

This allows dclose()'ing this code in dynamically-linked library without leaking memory. --- src/gallium/state_trackers/osmesa/osmesa.c | 77 +- 1 file changed, 55 insertions(+), 22 deletions(-) diff --git a/src/gallium/state_trackers/osmesa/osmesa.c

Re: [Mesa-dev] [PATCH 00/11] intel/tools: Unify batch decoding between aubinators

This looks really good :) I can't find anything to nitpick : Reviewed-by: Lionel Landwerlin On 13/12/17 20:05, Jason Ekstrand wrote: Both aubinator and aubinator_error_decode try and do the same task of decoding batches. They both have code to try and decode

[Mesa-dev] [PATCH 1/2] radv: always emit all compute block components

The number of grid components is always 3 when gl_NumWorkGroups is declared, because it relies on the number of components of nir_instrinsic_load_num_work_groups. Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 9 ++---

[Mesa-dev] [PATCH 2/2] radv: replace grid_components_used by uses_grid_size

Use a boolean instead because the number of needed SGPRs is always 3. Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 7 --- src/amd/common/ac_shader_info.c | 2 +- src/amd/common/ac_shader_info.h | 2 +- 3 files changed, 6 insertions(+), 5

Re: [Mesa-dev] [PATCH] radv: export SampleMask from pixel shaders at full rate

On 12/13/2017 09:21 PM, Bas Nieuwenhuizen wrote: On Tue, Dec 12, 2017 at 6:08 PM, Samuel Pitoiset wrote: Use 16_ABGR instead of 32_ABGR if Z isn't written. Ported from RadeonSI. No CTS regressions on Polaris. Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH v2 02/20] ac: add load_tes_inputs() to the abi

On 13/12/17 18:52, Timothy Arceri wrote: V2: drop type param and just use ctx->i32 I forgot to add that this drops the ctx->nctx check. Both driver now just follow the same path, the strangeness I had been seeing is no longer present it was probably just a bug during development. ---

[Mesa-dev] [PATCH 0/4] GL_EXT_disjoint_timer_query series

Hi; Here's a revisited GL_EXT_disjoint_timer_query series. One patch got dropped (as discussed with Lionel) and enabling is now via EXT_disjoint_timer_query boolean as was intended (Ian). Thanks; Tapani Pälli (4): mesa: add DisjointOperation to gl_shared_state glapi: add

[Mesa-dev] [PATCH 2/4] glapi: add GL_EXT_disjoint_timer_query

Most entrypoints already available via other extensions like GL_EXT_occlusion_query_boolean, GL_EXT_timer_query. Signed-off-by: Tapani Pälli Reviewed-by: Lionel Landwerlin --- src/mapi/glapi/gen/es_EXT.xml | 16

[Mesa-dev] [PATCH 4/4] i965: enable EXT_disjoint_timer_query extension

Following dEQP cases pass: dEQP-EGL.functional.get_proc_address.extension.gl_ext_disjoint_timer_query dEQP-EGL.functional.client_extensions.disjoint Piglit test 'ext_disjoint_timer_query-simple' passes with these changes. No changes/regression observed in Intel CI. Signed-off-by: Tapani

[Mesa-dev] [PATCH 1/4] mesa: add DisjointOperation to gl_shared_state

This state will be used by EXT_disjoint_timer_query. As first usage, patch sets DisjointOperation true when gpu reset happens. Signed-off-by: Tapani Pälli Reviewed-by: Lionel Landwerlin --- src/mesa/main/mtypes.h | 8

[Mesa-dev] [PATCH 3/4] mesa: GL_EXT_disjoint_timer_query extension API bits

Patch adds GL_GPU_DISJOINT_EXT and enables to use timer queries when EXT_disjoint_timer_query is enabled. v2: enable extension only when EXT_disjoint_timer_query set Signed-off-by: Tapani Pälli Reviewed-by: Lionel Landwerlin (v1) ---