[Mesa-dev] [Bug 105296] Account request for Chema Casanova

https://bugs.freedesktop.org/show_bug.cgi?id=105296 Bug ID: 105296 Summary: Account request for Chema Casanova Product: Mesa Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal

[Mesa-dev] [Bug 105296] Account request for Chema Casanova

https://bugs.freedesktop.org/show_bug.cgi?id=105296 --- Comment #1 from Chema Casanova --- Created attachment 137698 --> https://bugs.freedesktop.org/attachment.cgi?id=137698=edit SSH Publick Key - Chema Casanova -- You are receiving this mail because: You are the QA

[Mesa-dev] [RFC PATCH] get_reviewer.pl: Delete

I find this script *really* annoying. Getting Cc'd on a random sample of a series is doing it wrong. Cc lists of 14 people is doing it wrong. Let's start the negotiation with "delete this script" and see if anyone can come up with a way of making this not so stupid. --- scripts/get_reviewer.pl |

Re: [Mesa-dev] [PATCH 1/4] intel: Split gen_device_info out into libintel_dev

Jordan Justen writes: > On 2018-02-28 01:58:24, Samuel Iglesias Gonsálvez wrote: >> What is the idea for src/intel/dev/ ? >> >> I'm not against this patch, just asking. > > Ken noticed a lot of duplicate lines in the xml for surface formats. > (Patch 4). But, then we

Re: [Mesa-dev] [PATCH 3/3] radv: only emit cache flushes when the pool size is large enough

On 02/28/2018 09:06 PM, Bas Nieuwenhuizen wrote: On Wed, Feb 28, 2018 at 8:31 PM, Samuel Pitoiset wrote: This is an optimization which reduces the number of flushes for small pool buffers. Signed-off-by: Samuel Pitoiset ---

Re: [Mesa-dev] [RFC PATCH] get_reviewer.pl: Delete

Quoting Rob Clark (2018-02-28 12:54:28) > On Wed, Feb 28, 2018 at 3:25 PM, Matt Turner wrote: > > I find this script *really* annoying. Getting Cc'd on a random sample of > > a series is doing it wrong. Cc lists of 14 people is doing it wrong. > > > > Let's start the

Re: [Mesa-dev] [PATCH 2/2] travis: make Meson find the proper llvm-config

On Wed, 2018-02-28 at 18:53 +0100, Gert Wollny wrote: > Am Mittwoch, den 28.02.2018, 17:52 +0200 schrieb Andres Gomez: [...] > > + test -f /usr/bin/llvm-config && ln -s /usr/bin/llvm-config > > $HOME/prefix/bin > > I'm not sure how the toolchain packages on travis are created and maybe >

Re: [Mesa-dev] [RFC PATCH] get_reviewer.pl: Delete

On Wed, Feb 28, 2018 at 3:25 PM, Matt Turner wrote: > I find this script *really* annoying. Getting Cc'd on a random sample of > a series is doing it wrong. Cc lists of 14 people is doing it wrong. > > Let's start the negotiation with "delete this script" and see if anyone >

Re: [Mesa-dev] [PATCH 18.0] swr/rast: Fix index buffer overfetch issue for non-indexed draws

Reviewed-by: Bruce Cherniak > On Feb 28, 2018, at 1:16 PM, George Kyriazis > wrote: > > Populate pLastIndex, even for the non-indexed case. An zero pLastIndex > can cause the index offsets inside the fetcher to have non-sensical values >

Re: [Mesa-dev] [RFC PATCH] get_reviewer.pl: Delete

Matt Turner writes: > I find this script *really* annoying. Getting Cc'd on a random sample of > a series is doing it wrong. Cc lists of 14 people is doing it wrong. > > Let's start the negotiation with "delete this script" and see if anyone > can come up with a way of making

Re: [Mesa-dev] [RFC PATCH] get_reviewer.pl: Delete

Quoting Dylan Baker (2018-02-28 13:02:02) > Quoting Rob Clark (2018-02-28 12:54:28) > > On Wed, Feb 28, 2018 at 3:25 PM, Matt Turner wrote: > > > I find this script *really* annoying. Getting Cc'd on a random sample of > > > a series is doing it wrong. Cc lists of 14 people is

Re: [Mesa-dev] [PATCH 15/21] intel/blorp: Use isl_surf_get_uncompressed_surf

On Wed, Feb 28, 2018 at 10:11:56AM -0800, Jason Ekstrand wrote: > On February 28, 2018 09:23:59 "Pohjolainen, Topi" > wrote: > > >On Thu, Feb 22, 2018 at 11:06:55PM -0800, Jason Ekstrand wrote: > >>--- > >> src/intel/blorp/blorp_blit.c | 58 > >>

[Mesa-dev] [PATCH 18.0] swr/rast: Fix index buffer overfetch issue for non-indexed draws

Populate pLastIndex, even for the non-indexed case. An zero pLastIndex can cause the index offsets inside the fetcher to have non-sensical values that can be either very large positive or very large negative numbers. Cherry-pick of 539de78633 for 18.0. Surrounding context is different for 18.0

[Mesa-dev] [PATCH 3/3] radv: only emit cache flushes when the pool size is large enough

This is an optimization which reduces the number of flushes for small pool buffers. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_buffer.c | 6 -- src/amd/vulkan/radv_private.h | 6 ++ src/amd/vulkan/radv_query.c | 12 3

[Mesa-dev] [PATCH 1/3] radv: make sure to emit cache flushes before starting a query

If the query pool has been previously resetted using the compute shader path. v2: handle multiple commands buffers with same pool Fixes: a41e2e9cf5 ("radv: allow to use a compute shader for resetting the query pool") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105292 Cc: "18.0"

[Mesa-dev] [PATCH 2/3] radv: keep track of the query pool size

Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_private.h | 1 + src/amd/vulkan/radv_query.c | 9 - 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index

[Mesa-dev] [PATCH 12/13] compiler: int8/uint8 support

From: Karol Herbst OpenCL kernels also have int8/uint8. Signed-off-by: Rob Clark --- src/compiler/builtin_type_macros.h | 10 src/compiler/glsl/ast_to_hir.cpp| 2 ++ src/compiler/glsl/ir_clone.cpp

[Mesa-dev] [PATCH 13/13] RFC: nir/vtn: "raw" pointer support

An attempt to add physical pointer support to vtn. I'm not totally happy about the handling of logical pointers vs physical pointers. So this is really more of an RFS (request for suggestions) --- src/compiler/spirv/spirv_to_nir.c | 47 +++-- src/compiler/spirv/vtn_private.h | 19 +++-

Re: [Mesa-dev] [PATCH 3/3] radv: only emit cache flushes when the pool size is large enough

On Wed, Feb 28, 2018 at 8:31 PM, Samuel Pitoiset wrote: > This is an optimization which reduces the number of flushes for > small pool buffers. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_meta_buffer.c | 6 -- >

[Mesa-dev] [PATCH 11/22 v2] nir: Recognize some more open-coded fmin / fmax

From: Ian Romanick This transformation is inexact because section 4.7.1 (Range and Precision) says: Operations and built-in functions that operate on a NaN are not required to return a NaN as the result. The fmin or fmax might not return NaN in cases where the

[Mesa-dev] [PATCH 11.1/22] nir: Mark bcsel-to-fmin (or fmax) transformations as inexact

From: Ian Romanick These transformations are inexact because section 4.7.1 (Range and Precision) says: Operations and built-in functions that operate on a NaN are not required to return a NaN as the result. The fmin or fmax might not return NaN in cases where

Re: [Mesa-dev] [PATCH v2 0/8] anv: VK_KHR_16bit_storage enabling SSBO/UBO/PushConstant

On 28/02/18 18:02, Jason Ekstrand wrote: > I think all the interesting patches are reviewed now.  All the boring > "turn stuff on" patches are > > Reviewed-by: Jason Ekstrand > Thanks a lot for the quick review of the series. One step less to

[Mesa-dev] [PATCH 04/13] nir: add load/store_global intrinsics

From: Karol Herbst OpenCL kernels have raw pointers to global memory, so we need instructions to load/store in order to dereference these pointers. In some ways similar to other load/store intrinsics, but rather than taking an offset as a src argument, they take a raw pointer

[Mesa-dev] [PATCH 08/13] nir/vtn: add OpLifetime*

These are just hints so we can ignore them. Signed-off-by: Rob Clark --- src/compiler/spirv/spirv_to_nir.c | 4 1 file changed, 4 insertions(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index e539d944302..3e7ac46c639 100644

[Mesa-dev] [PATCH 07/13] nir/vtn: handle WorkGroupSize for kernels

Unlike glsl/vk compute shaders, this isn't a builtin constant. Signed-off-by: Rob Clark --- src/compiler/spirv/spirv_to_nir.c | 3 +++ src/compiler/spirv/vtn_private.h | 2 ++ src/compiler/spirv/vtn_variables.c | 6 +++--- 3 files changed, 8 insertions(+), 3 deletions(-)

[Mesa-dev] [PATCH 09/13] nir/vtn: add OpConvertPtrToU

Signed-off-by: Rob Clark --- src/compiler/spirv/vtn_alu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index d0c9e316935..9397240912b 100644 --- a/src/compiler/spirv/vtn_alu.c +++

[Mesa-dev] [PATCH 10/13] nir/vtn: print extension name in fail msg

Signed-off-by: Rob Clark --- src/compiler/spirv/spirv_to_nir.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 3e7ac46c639..b9e5198e7bc 100644 ---

[Mesa-dev] [PATCH 01/13] nir: allow 64 bit shifts

From: Karol Herbst This is a thing for OpenCL kernels. Signed-off-by: Rob Clark --- src/compiler/nir/nir_opcodes.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/compiler/nir/nir_opcodes.py

[Mesa-dev] [PATCH 06/13] nir/vtn: implement SpvOpCopyMemorySized

I think a new intrinsic is the easiest way to do this. We can lower this to a sequence of load/stores after vtn. Signed-off-by: Rob Clark --- src/compiler/nir/nir_intrinsics.h | 2 ++ src/compiler/spirv/vtn_variables.c | 17 - 2 files changed, 18

[Mesa-dev] [PATCH 11/13] nir/vtn: implement BuiltInGlobalSize

From: Karol Herbst Signed-off-by: Rob Clark --- src/compiler/nir/nir_lower_system_values.c | 8 src/compiler/shader_enums.c| 1 + src/compiler/shader_enums.h| 2 ++ src/compiler/spirv/vtn_variables.c | 4

[Mesa-dev] [PATCH 02/13] nir: add load_param

From: Karol Herbst OpenCL kernels have parameters (see pipe_grid_info::input), and so we need a way to access them. Signed-off-by: Rob Clark --- src/compiler/nir/nir_intrinsics.h | 2 ++ src/compiler/nir/nir_lower_io.c | 13 ++--- 2 files

[Mesa-dev] [PATCH 03/13] nir: kernel entrypoints can have arguments

This assert is not valid for OpenCL kernels. TODO can we somehow conditionally assert based on glsl vs cl?? Signed-off-by: Rob Clark --- src/compiler/nir/nir.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index

[Mesa-dev] [PATCH 05/13] nir: expose 'C' wrappers for std430 size/alignment

Signed-off-by: Rob Clark --- src/compiler/nir_types.cpp | 12 src/compiler/nir_types.h | 4 2 files changed, 16 insertions(+) diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp index cbdd452dc81..0085a19248a 100644 ---

Re: [Mesa-dev] [PATCH 15/21] intel/blorp: Use isl_surf_get_uncompressed_surf

On February 28, 2018 09:23:59 "Pohjolainen, Topi" wrote: On Thu, Feb 22, 2018 at 11:06:55PM -0800, Jason Ekstrand wrote: --- src/intel/blorp/blorp_blit.c | 58 +--- 1 file changed, 17 insertions(+), 41 deletions(-) diff

Re: [Mesa-dev] [PATCH] swr/rast: Fix macOS macro.

Yes, a typo on our end. Thank you! Reviewed-By: George Kyriazis > On Feb 24, 2018, at 5:55 PM, Vinson Lee > wrote: Fixes: a25093de7188 ("swr/rast: Implement JIT shader caching to

[Mesa-dev] [PATCH 19/22 v3] i965/fs: Merge CMP and SEL into CSEL on Gen8+

From: Ian Romanick v2: Fix several problems handling inverted predicates. Add a much bigger comment around the BRW_CONDITIONAL_NZ case. v3: Allow uniforms and shader inputs as sources for the original SEL and CMP instructions. This enables a LOT more shaders to

Re: [Mesa-dev] [PATCH v2 1/2] meson: Add default DRI drivers for ARM/AArch64

Quoting Daniel Stone (2018-02-28 01:36:51) > Hi, > > On 28 February 2018 at 09:33, Eric Engestrom > wrote: > > On Tuesday, 2018-02-27 18:01:11 +, Daniel Stone wrote: > >> On all Arm architectures (ARMv7 and below as 'arm', ARMv8 and above as > >> 'aarch64'), only

[Mesa-dev] [PATCH 00/13] nir/vtn/compiler: first batch of compute support

This is by no means everything needed for clover/OpenCL.. but I took a bit of time this morning to extract some parts of our growing stack of patches which where plausibly mergable (or at least not complete hacks), with the idea that review could start in parallel with further clover/compute

Re: [Mesa-dev] [PATCH 3/3] radv: only emit cache flushes when the pool size is large enough

On Wed, Feb 28, 2018 at 9:41 PM, Samuel Pitoiset wrote: > > > On 02/28/2018 09:06 PM, Bas Nieuwenhuizen wrote: >> >> On Wed, Feb 28, 2018 at 8:31 PM, Samuel Pitoiset >> wrote: >>> >>> This is an optimization which reduces the number of

[Mesa-dev] [PATCH v3] radv: make sure to emit cache flushes before starting a query

If the query pool has been previously resetted using the compute shader path. v3: set pending_reset_query only for the compute shader path v2: handle multiple commands buffers with same pool Fixes: a41e2e9cf5 ("radv: allow to use a compute shader for resetting the query pool") Bugzilla:

Re: [Mesa-dev] [PATCH 11/22 v2] nir: Recognize some more open-coded fmin / fmax

Rb On Wed, Feb 28, 2018 at 12:18 PM, Ian Romanick wrote: > From: Ian Romanick > > This transformation is inexact because section 4.7.1 (Range and > Precision) says: > > Operations and built-in functions that operate on a NaN are not >

Re: [Mesa-dev] [PATCH 01/13] nir: allow 64 bit shifts

I do not think this patch does what you think it does. The old opcode allowed you to shift any bit size integer by a 32-bit integer. The new version allows you to shift N bits by N bits. In particular, you can't shift a 16-bit by a 32-bit value. I'm not sure what the best thing is to do here.

Re: [Mesa-dev] [PATCH 1/2] meson: fix LLVM version detection when <= 3.4

On Wed, 2018-02-28 at 17:12 +, Eric Engestrom wrote: > On Wednesday, 2018-02-28 17:08:41 +, Eric Engestrom wrote: > > On Wednesday, 2018-02-28 17:02:50 +, Eric Engestrom wrote: > > > On Wednesday, 2018-02-28 17:52:05 +0200, Andres Gomez wrote: > > > > 3 digits versions in LLVM only

[Mesa-dev] [PATCH v2] travis: make Meson find the proper llvm-config

Travis CI has moved to LLVM 5.0, and meson is detecting automatically the available version in /usr/local/bin based on the PATH env variable order preference. As for 0.44.x, Meson cannot receive the path to the llvm-config binary as a configuration parameter. See

Re: [Mesa-dev] [PATCH 05/13] nir: expose 'C' wrappers for std430 size/alignment

it isn't yet. But you would use it in your driver when calculating your memory offsets for kernel arguments. In OpenCL things are aligned in memory by the size of the type and we would use those functions to calculate those. On Wed, Feb 28, 2018 at 10:39 PM, Jason Ekstrand

Re: [Mesa-dev] [PATCH 1/4] intel: Split gen_device_info out into libintel_dev

On 2018-02-28 12:53:01, Francisco Jerez wrote: > Jordan Justen writes: > > > On 2018-02-28 01:58:24, Samuel Iglesias Gonsálvez wrote: > >> What is the idea for src/intel/dev/ ? > >> > >> I'm not against this patch, just asking. > > > > Ken noticed a lot of duplicate

Re: [Mesa-dev] [PATCH 05/13] nir: expose 'C' wrappers for std430 size/alignment

I needed it in ir3, since nir->ir3 is .c code, and I need it to map load_param offset to offset in constant registers. Sorry, I didn't think the ir3 patches were interesting to others so I didn't include them in the patchset. Tbh if we used uniforms to pass params, I might not need these in ir3

Re: [Mesa-dev] [PATCH 1/1] radv/gfx9: fix texture buffer objects and image buffers with IDXEN==0

On 02/28/2018 10:39 PM, Emil Velikov wrote: Hi Samuel, On 20 February 2018 at 11:33, Samuel Pitoiset wrote: Ported from RadeonSI. Signed-off-by: Samuel Pitoiset Cc: --- src/amd/vulkan/radv_image.c

Re: [Mesa-dev] [PATCH] nir/serialize: handle var->name being NULL

Reviewed-by: Timothy Arceri On 01/03/18 04:13, Alejandro Piñeiro wrote: var->name could be true under ARB_gl_spirv for example. And in any case, the code is already handing var name being NULL when reading a variable, so it is consistent to do it writing a variable too.

[Mesa-dev] [PATCH] anv: Always set has_context_priority

We don't zalloc the physical device so we need to unconditionally set everything. Crucible helpfully initializes all allocations to 139 so it was getting true regardless of whether or not the kernel actually supports context priorities. Fixes: 6d8ab53303331 "anv: implement VK_EXT_global_priority

Re: [Mesa-dev] [PATCH] ac/nir: don't apply slice rounding on txf_ms

Reviewed-by: Bas Nieuwenhuizen On Thu, Mar 1, 2018 at 12:33 AM, Timothy Arceri wrote: > Thanks! > > Reviewed-by: Timothy Arceri > > On 01/03/18 10:26, Dave Airlie wrote: >> >> From: Dave Airlie >> >>

Re: [Mesa-dev] [PATCH] ac/nir: fix shared atomic operations.

On 01/03/18 10:39, Dave Airlie wrote: From: Dave Airlie The nir->llvm conversion was using the wrong srcs. Well that's embarrassing. Reviewed-by: Timothy Arceri Fixes: tests/spec/arb_compute_shader/execution/shared-atomics.shader_test

Re: [Mesa-dev] [PATCH v2] travis: make Meson find the proper llvm-config

On 28 February 2018 at 21:18, Andres Gomez wrote: > Travis CI has moved to LLVM 5.0, and meson is detecting automatically > the available version in /usr/local/bin based on the PATH env variable > order preference. > > As for 0.44.x, Meson cannot receive the path to the

Re: [Mesa-dev] [PATCH v2] meson: fix LLVM version detection when <= 3.4

Quoting Emil Velikov (2018-02-28 15:49:37) > On 28 February 2018 at 21:15, Andres Gomez wrote: > > 3 digits versions in LLVM only started from 3.4.1 on. Hence, if you > > have installed 3.4 or below, meson will fail even when we may not make > > use of LLVM. > > > > v2:

[Mesa-dev] [PATCH] radeonsi/nir: increase values to 8 for gs fetch.

From: Dave Airlie This stops a crash when running (still fails): tests/spec/arb_gpu_shader_fp64/execution/explicit-location-gs-fs-vs.shader_test Signed-off-by: Dave Airlie --- src/gallium/drivers/radeonsi/si_shader_nir.c | 2 +- 1 file changed, 1

[Mesa-dev] [PATCH 1/2] meson: Allow building dri based EGL without GLX

It should be possible to build EGL without GLX, but the meson build currently doesn't allow that because it too tightly couples glx and dri. This patch eases dri and glx apart, so that EGL without GLX can be built. CC: Daniel Stone Signed-off-by: Dylan Baker

Re: [Mesa-dev] [PATCH 1/1] radv/gfx9: fix texture buffer objects and image buffers with IDXEN==0

Hi Samuel, On 20 February 2018 at 11:33, Samuel Pitoiset wrote: > Ported from RadeonSI. > > Signed-off-by: Samuel Pitoiset > Cc: > --- > src/amd/vulkan/radv_image.c | 35

Re: [Mesa-dev] [PATCH 05/13] nir: expose 'C' wrappers for std430 size/alignment

Looking through commit titles, I don't see any obvious place where this would get used. On Wed, Feb 28, 2018 at 11:51 AM, Rob Clark wrote: > Signed-off-by: Rob Clark > --- > src/compiler/nir_types.cpp | 12 > src/compiler/nir_types.h |

Re: [Mesa-dev] [PATCH 01/13] nir: allow 64 bit shifts

On Wed, Feb 28, 2018 at 1:35 PM, Rob Clark wrote: > On Wed, Feb 28, 2018 at 4:18 PM, Karol Herbst wrote: > > On Wed, Feb 28, 2018 at 9:46 PM, Jason Ekstrand > wrote: > >> I do not think this patch does what you think it does. The

Re: [Mesa-dev] [PATCH 12/13] compiler: int8/uint8 support

On Wed, Feb 28, 2018 at 11:51 AM, Rob Clark wrote: > From: Karol Herbst > > OpenCL kernels also have int8/uint8. > > Signed-off-by: Rob Clark > --- > src/compiler/builtin_type_macros.h | 10 >

Re: [Mesa-dev] [PATCH 05/13] nir: expose 'C' wrappers for std430 size/alignment

hmm, I haven't tried passing a struct (rather than a pointer to a struct) as a parameter, but if there were 8/16 bit fields in the struct it would calculate the size incorrectly. (otoh the more important question is whether this agrees with how clover lays out the input buffer, as far as where

Re: [Mesa-dev] [PATCH] i965: Allow 48-bit addressing on Gen8+.

On 27 February 2018 at 00:05, Kenneth Graunke wrote: > --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c > +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c > @@ -203,12 +203,23 @@ brw_emit_surface_state(struct brw_context *brw, > * FIXME: move to the

Re: [Mesa-dev] [PATCH] ac/nir: fix shared atomic operations.

Reviewed-by: Bas Nieuwenhuizen On Thu, Mar 1, 2018 at 12:39 AM, Dave Airlie wrote: > From: Dave Airlie > > The nir->llvm conversion was using the wrong srcs. > > Fixes: >

[Mesa-dev] [PATCH] ac/nir: don't apply slice rounding on txf_ms

From: Dave Airlie This matches the tgsi code. Fixes arb_texture_multisample texelFetch piglit tests. Signed-off-by: Dave Airlie --- src/amd/common/ac_nir_to_llvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [Mesa-dev] [PATCH] anv: Always set has_context_priority

On Wednesday, February 28, 2018 3:29:00 PM PST Jason Ekstrand wrote: > We don't zalloc the physical device so we need to unconditionally set > everything. Crucible helpfully initializes all allocations to 139 so it > was getting true regardless of whether or not the kernel actually > supports

[Mesa-dev] [PATCH] gallium/tests/trivial: fix viewport depth transform

These were getting mapped off into outer space, which would cause nv50 and nvc0 to clip the primitives (as depth_clip was enabled). Oddly enough, it worked with nv30 and llvmpipe though. Perhaps their frustrum clipping rules are a bit different? Signed-off-by: Ilia Mirkin

[Mesa-dev] [PATCH] [rfc] st/nir: handle components on fs outputs.

From: Dave Airlie fs outputs don't start above VARYING_SLOT_VAR0, but I assume that is there for a reason, so make an exception for fragment outputs. This fixes with NIR: tests/spec/arb_enhanced_layouts/execution/component-layout/fs-output.shader_test Signed-off-by: Dave

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/6] i965/miptree: Loosen the format check in miptree_match_image

On Wed, Feb 28, 2018 at 1:41 PM, Emil Velikov wrote: > Hi Jason, > > On 24 January 2018 at 23:46, Jason Ekstrand wrote: > > This function is used to determine when we need to re-allocate a > > miptree. Since we do nothing different in miptree

[Mesa-dev] [Bug 105291] r600 [CEDAR]: GPU stalls when running shadertoy "ladybug"

https://bugs.freedesktop.org/show_bug.cgi?id=105291 mirh changed: What|Removed |Added CC||m...@protonmail.ch -- You

[Mesa-dev] [PATCH] intel: Drop program size pointer from vec4/fs assembly getters.

These days, we're just passing a pointer to a prog_data field, which we already have access to. We can just use it directly. (In the past, it was a pointer to a separate value.) --- src/intel/compiler/brw_fs.cpp | 4 ++-- src/intel/compiler/brw_fs.h| 2 +-

Re: [Mesa-dev] [PATCH] ac/nir: don't apply slice rounding on txf_ms

Thanks! Reviewed-by: Timothy Arceri On 01/03/18 10:26, Dave Airlie wrote: From: Dave Airlie This matches the tgsi code. Fixes arb_texture_multisample texelFetch piglit tests. Signed-off-by: Dave Airlie ---

[Mesa-dev] [PATCH v2] meson: fix LLVM version detection when <= 3.4

3 digits versions in LLVM only started from 3.4.1 on. Hence, if you have installed 3.4 or below, meson will fail even when we may not make use of LLVM. v2: Properly compare LLVM version and set patch version to 0 if < 3.4.1 (Eric). Cc: Dylan Baker Cc: Eric Engestrom

Re: [Mesa-dev] [PATCH 02/13] nir: add load_param

Rob Clark writes: > From: Karol Herbst > > OpenCL kernels have parameters (see pipe_grid_info::input), and so we > need a way to access them. > > Signed-off-by: Rob Clark > > --- > src/compiler/nir/nir_intrinsics.h | 2 ++ >

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/6] i965/miptree: Loosen the format check in miptree_match_image

Hi Jason, On 24 January 2018 at 23:46, Jason Ekstrand wrote: > This function is used to determine when we need to re-allocate a > miptree. Since we do nothing different in miptree allocation for > sRGB vs. linear, loosening this should be safe and may lead to less >

Re: [Mesa-dev] [PATCH v2] meson: fix LLVM version detection when <= 3.4

Quoting Andres Gomez (2018-02-28 13:15:07) > 3 digits versions in LLVM only started from 3.4.1 on. Hence, if you > have installed 3.4 or below, meson will fail even when we may not make > use of LLVM. > > v2: Properly compare LLVM version and set patch version to 0 > if < 3.4.1 (Eric). > >

Re: [Mesa-dev] [PATCH v2] i965/sbe: fix number of inputs for active components

On Monday, February 26, 2018 11:02:08 PM PST Iago Toral Quiroga wrote: > In 16631ca30ea6 we fixed gen9 active components to account for padded > inputs in the URB, which we can have with SSO programs. To do that, > instead of going through the bitfield of inputs (which doesn't include > padding

[Mesa-dev] [PATCH] ac/nir: fix shared atomic operations.

From: Dave Airlie The nir->llvm conversion was using the wrong srcs. Fixes: tests/spec/arb_compute_shader/execution/shared-atomics.shader_test Signed-off-by: Dave Airlie --- src/amd/common/ac_nir_to_llvm.c | 10 +- 1 file changed, 5

Re: [Mesa-dev] [PATCH v2] i965/sbe: fix number of inputs for active components

On Monday, February 26, 2018 11:02:08 PM PST Iago Toral Quiroga wrote: > In 16631ca30ea6 we fixed gen9 active components to account for padded > inputs in the URB, which we can have with SSO programs. To do that, > instead of going through the bitfield of inputs (which doesn't include > padding

Re: [Mesa-dev] [RFC PATCH] get_reviewer.pl: Delete

Rob Clark writes: > On Wed, Feb 28, 2018 at 4:09 PM, Eric Anholt wrote: >> Matt Turner writes: >> >>> I find this script *really* annoying. Getting Cc'd on a random sample of >>> a series is doing it wrong. Cc lists of 14 people is

Re: [Mesa-dev] [PATCH] radeonsi/nir: increase values to 8 for gs fetch.

Reviewed-by: Timothy Arceri On 01/03/18 11:02, Dave Airlie wrote: From: Dave Airlie This stops a crash when running (still fails): tests/spec/arb_gpu_shader_fp64/execution/explicit-location-gs-fs-vs.shader_test Signed-off-by: Dave Airlie

Re: [Mesa-dev] [RFC PATCH] get_reviewer.pl: Delete

On Wed, Feb 28, 2018 at 1:09 PM, Eric Anholt wrote: > Matt Turner writes: > >> I find this script *really* annoying. Getting Cc'd on a random sample of >> a series is doing it wrong. Cc lists of 14 people is doing it wrong. >> >> Let's start the negotiation

Re: [Mesa-dev] [PATCH 02/13] nir: add load_param

On Wed, Feb 28, 2018 at 4:16 PM, Eric Anholt wrote: > Rob Clark writes: > >> From: Karol Herbst >> >> OpenCL kernels have parameters (see pipe_grid_info::input), and so we >> need a way to access them. >> >> Signed-off-by: Rob Clark

Re: [Mesa-dev] [PATCH 18.0] swr/rast: Fix index buffer overfetch issue for non-indexed draws

On 28 February 2018 at 19:16, George Kyriazis wrote: > Populate pLastIndex, even for the non-indexed case. An zero pLastIndex > can cause the index offsets inside the fetcher to have non-sensical values > that can be either very large positive or very large negative

Re: [Mesa-dev] [Mesa-stable] [PATCH 1/2] intel/compiler: Memory fence commit must always be enabled for gen10+

On 22 February 2018 at 19:23, Emil Velikov wrote: > Hi Anuj, > > On 7 February 2018 at 01:09, Anuj Phogat wrote: >> Commit bit in the message descriptor (Bit 13) must be always set >> to true in CNL+ for memory fence messages. It also fixes a

Re: [Mesa-dev] [PATCH v2] travis: make Meson find the proper llvm-config

Looks fine to me, Reviewed-By: Gert Wollny Am Mittwoch, den 28.02.2018, 23:18 +0200 schrieb Andres Gomez: > Travis CI has moved to LLVM 5.0, and meson is detecting automatically > the available version in /usr/local/bin based on the PATH env > variable > order preference.

[Mesa-dev] [PATCH 2/2] meson: Fix building gallium media libs without egl

Signed-off-by: Dylan Baker --- meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/meson.build b/meson.build index 7cfd7f2183a..c565a81fe95 100644 --- a/meson.build +++ b/meson.build @@ -1188,7 +1188,8 @@ if with_platform_x11 endif

Re: [Mesa-dev] [RFC PATCH] get_reviewer.pl: Delete

On Wed, Feb 28, 2018 at 4:09 PM, Eric Anholt wrote: > Matt Turner writes: > >> I find this script *really* annoying. Getting Cc'd on a random sample of >> a series is doing it wrong. Cc lists of 14 people is doing it wrong. >> >> Let's start the negotiation

[Mesa-dev] [PATCH] nir/search: Support 8 and 16-bit constants

--- src/compiler/nir/nir_search.c | 20 1 file changed, 20 insertions(+) diff --git a/src/compiler/nir/nir_search.c b/src/compiler/nir/nir_search.c index dec56fe..c7c52ae 100644 --- a/src/compiler/nir/nir_search.c +++ b/src/compiler/nir/nir_search.c @@ -27,6 +27,7 @@

Re: [Mesa-dev] [PATCH 01/13] nir: allow 64 bit shifts

On Wed, Feb 28, 2018 at 9:46 PM, Jason Ekstrand wrote: > I do not think this patch does what you think it does. The old opcode > allowed you to shift any bit size integer by a 32-bit integer. The new > version allows you to shift N bits by N bits. In particular, you can't

Re: [Mesa-dev] [PATCH 01/13] nir: allow 64 bit shifts

On Wed, Feb 28, 2018 at 4:18 PM, Karol Herbst wrote: > On Wed, Feb 28, 2018 at 9:46 PM, Jason Ekstrand wrote: >> I do not think this patch does what you think it does. The old opcode >> allowed you to shift any bit size integer by a 32-bit integer. The

Re: [Mesa-dev] [PATCH 01/13] nir: allow 64 bit shifts

On Wed, Feb 28, 2018 at 1:18 PM, Karol Herbst wrote: > On Wed, Feb 28, 2018 at 9:46 PM, Jason Ekstrand > wrote: > > I do not think this patch does what you think it does. The old opcode > > allowed you to shift any bit size integer by a 32-bit integer.

Re: [Mesa-dev] [PATCH 05/13] nir: expose 'C' wrappers for std430 size/alignment

I thought OpenCL used a different set of alignment rules for structs, unions, etc. In particular, I thought it was very close to standard C. If that's true, then std430 is not what you want. On Wed, Feb 28, 2018 at 1:44 PM, Karol Herbst wrote: > it isn't yet. But you would

Re: [Mesa-dev] [PATCH v2] meson: fix LLVM version detection when <= 3.4

On 28 February 2018 at 21:15, Andres Gomez wrote: > 3 digits versions in LLVM only started from 3.4.1 on. Hence, if you > have installed 3.4 or below, meson will fail even when we may not make > use of LLVM. > > v2: Properly compare LLVM version and set patch version to 0 >

[Mesa-dev] [PATCH] r600/cayman: fix fragcood loading recip generation.

From: Dave Airlie This fixes some hangs seen where the recip_ieee opcodes would end up split across the wrong slots. Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/r600_shader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH 1/2] radeonsi: move si_nir_load_input_gs() to si_shader.c

All the tess shader and tgsi equivalents are here and it allows use to use llvm_type_is_64bit() in the following patch without exposing it externally. --- src/gallium/drivers/radeonsi/si_shader.c | 20 src/gallium/drivers/radeonsi/si_shader_internal.h | 9 -

Re: [Mesa-dev] [RFC PATCH] get_reviewer.pl: Delete

On Wed, Feb 28, 2018 at 7:20 PM, Eric Anholt wrote: > Rob Clark writes: > >> On Wed, Feb 28, 2018 at 4:09 PM, Eric Anholt wrote: >>> Matt Turner writes: >>> I find this script *really* annoying. Getting Cc'd on a

[Mesa-dev] [PATCH] vbo: Try to reuse the same VAO more often for successive dlists.

From: Mathias Fröhlich Hi Brian, that's what I mentioned yesterday. You may want to test this change against your use cases of your recent draw primitive optimization. With one openscenegraph dlist based workload this change improves the framerates on radeonsi by about

Re: [Mesa-dev] [Mesa-users] GraphicsFuzz metamorphic testing of shader compilers

Hi; Some feedback below .. On 02/28/2018 02:21 PM, Hugues Evrard wrote: Hi Brian, all, Thanks for the follow-up, and congrats to the team for the prompt bug fix! We've just tweeted about it: https://twitter.com/GraphicsFuzz/status/968815766681333760 We'll be pleased to report further Mesa

Re: [Mesa-dev] [PATCH] i965: Allow 48-bit addressing on Gen8+.

On Wednesday, February 28, 2018 2:21:24 PM PST Emil Velikov wrote: > On 27 February 2018 at 00:05, Kenneth Graunke wrote: > > > --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c > > +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c > > @@ -203,12 +203,23 @@

Re: [Mesa-dev] [PATCH] gallium/tests/trivial: fix viewport depth transform

On Wed, Feb 28, 2018 at 8:42 PM, Roland Scheidegger wrote: > I suppose that's ok (and safer), albeit I'm not sure why it wouldn't > work with nv50. > Depth clip is enabled, yes, but I can't see why the produced values > wouldn't be inside the view volume (which is defined by

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