Re: [Mesa-dev] [PATCH 30/59] intel/compiler: document MAD algebraic optimization

On Tue, Dec 04, 2018 at 08:16:54AM +0100, Iago Toral Quiroga wrote: > This optimization depends on two other optimization passes: the > constant propagation pass, which allows immediate propagation > on MAD/LRP instructions even though the hardware can't do it, > and the combine constants pass to

Re: [Mesa-dev] [PATCH 1/2] nv50/ir: fix use-after-free in ConstantFolding::visit

On Fri, Dec 7, 2018 at 3:57 AM Karol Herbst wrote: > > opnd() might delete the passed in instruction, but it's used through > i->srcExists() later in visit > > Signed-off-by: Karol Herbst > --- > .../nouveau/codegen/nv50_ir_peephole.cpp | 71 +++ > 1 file changed, 43

[Mesa-dev] [Bug 108530] [Tracker] Mesa 18.3 Release Tracker

https://bugs.freedesktop.org/show_bug.cgi?id=108530 Emil Velikov changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

Re: [Mesa-dev] [PATCH 1/2] nv50/ir: fix use-after-free in ConstantFolding::visit

On Fri, Dec 7, 2018 at 1:58 PM Ilia Mirkin wrote: > > On Fri, Dec 7, 2018 at 3:57 AM Karol Herbst wrote: > > > > opnd() might delete the passed in instruction, but it's used through > > i->srcExists() later in visit > > > > Signed-off-by: Karol Herbst > > --- > >

Re: [Mesa-dev] [PATCH] nir: Fixup algebraic test for variable-sized conversions

Ack On December 7, 2018 03:54:21 Connor Abbott wrote: b2i can now take any size boolean in preparation for 1-bit booleans, so the error message printed is slightly different. Fixes: dca6cd9ce65 ("nir: Make boolean conversions sized just like the others") Bugzilla:

[Mesa-dev] [ANNOUNCE] mesa 18.3.0

Mesa 18.3.0 is now available. This release consists of approximately 1700 commits from 120 developers. Huge thanks to all the developers, testers and users for their ongoing work and support shaping up the 18.3.0 release. The top highlights include: - GL_AMD_depth_clamp_separate on r600,

[Mesa-dev] [Bug 108967] DRM : eglCreatePbufferSurface failed with error EGL_BAD_MATCH

https://bugs.freedesktop.org/show_bug.cgi?id=108967 Bug ID: 108967 Summary: DRM : eglCreatePbufferSurface failed with error EGL_BAD_MATCH Product: Mesa Version: 17.3 Hardware: ARM OS: Linux (All)

Re: [Mesa-dev] [PATCH] gallivm: remove unused float coord wrapping for aos sampling

On 07/12/2018 01:28, srol...@vmware.com wrote: From: Roland Scheidegger AoS sampling tries to use integers for coord wrapping when possible, as it should be faster. However, for AVX, this was suboptimal, because only floats can use 8x32bit vectors, whereas integers have to be split into

Re: [Mesa-dev] [PATCH 34/59] intel/compiler: fix ddy for half-float in gen8

On Tue, Dec 04, 2018 at 08:16:58AM +0100, Iago Toral Quiroga wrote: > We use ALign16 mode for this, since it is more convenient, but the PRM > for Broadwell states in Volume 3D Media GPGPU, Chapter 'Register region > restrictions', Section '1. Special Restrictions': > >"In Align16 mode, the

[Mesa-dev] [Bug 107524] Broken packDouble2x32 at llvmpipe

https://bugs.freedesktop.org/show_bug.cgi?id=107524 Emil Velikov changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

Re: [Mesa-dev] [PATCH 2/2] nv50/ir: initialize relDegree staticly

Reviewed-by: Ilia Mirkin On Fri, Dec 7, 2018 at 3:57 AM Karol Herbst wrote: > > this race condition is pretty harmless, but also pretty trivial to fix > > Signed-off-by: Karol Herbst > --- > .../drivers/nouveau/codegen/nv50_ir_ra.cpp| 23 +-- > 1 file changed, 16

[Mesa-dev] [Bug 107971] SPV_GOOGLE_hlsl_functionality1 / SPV_GOOGLE_decorate_string

https://bugs.freedesktop.org/show_bug.cgi?id=107971 Emil Velikov changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

Re: [Mesa-dev] [PATCH] gallium: add missing PIPE_CAP_SURFACE_SAMPLE_COUNT default value

On 2018-12-07 10:08 a.m., Samuel Pitoiset wrote: > Fixes: 2710c40e3c8 ("gallium: Add new PIPE_CAP_SURFACE_SAMPLE_COUNT") > Signed-off-by: Samuel Pitoiset > --- > src/gallium/auxiliary/util/u_screen.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git

Re: [Mesa-dev] [PATCH 41/59] intel/compiler: split is_partial_write() into two variants

On Tue, Dec 04, 2018 at 08:17:05AM +0100, Iago Toral Quiroga wrote: > This function is used in two different scenarios that for 32-bit > instructions are the same, but for 16-bit instructions are not. > > One scenario is that in which we are working at a SIMD8 register > level and we need to know

Re: [Mesa-dev] [PATCH 34/59] intel/compiler: fix ddy for half-float in gen8

On Fri, 2018-12-07 at 15:06 +0200, Pohjolainen, Topi wrote: > On Tue, Dec 04, 2018 at 08:16:58AM +0100, Iago Toral Quiroga wrote: > > We use ALign16 mode for this, since it is more convenient, but the > > PRM > > for Broadwell states in Volume 3D Media GPGPU, Chapter 'Register > > region > >

Re: [Mesa-dev] [PATCH 06/25] amd/common: scan/reduce across waves of a workgroup

On 06.12.18 15:20, Connor Abbott wrote: > Is this going to be used by an extension? If you don't have a use for > it yet, it would probably be better to wait. Well, I have been using it quite extensively in a branch I've been working on, but that's not quite ready yet. Cheers, Nicolai > On

[Mesa-dev] [PATCH] meson: Add nir_algebraic_parser_test to suites

Just to make it easier to run a nir tests together. Fixes: a0ae12ca91a45f81897e774019cde9bd081f03a0 ("nir/algebraic: Add unit tests for bitsize validation") --- src/compiler/nir/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/nir/meson.build

Re: [Mesa-dev] [PATCH 16/59] intel/compiler: implement 16-bit fsign

I think it's probably less code to just make a separate 16-bit case. On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > --- > src/intel/compiler/brw_fs_nir.cpp | 27 +-- > 1 file changed, 21 insertions(+), 6 deletions(-) > > diff --git

Re: [Mesa-dev] [PATCH 23/59] intel/compiler: Extended Math is limited to SIMD8 on half-float

On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > From the Skylake PRM, Extended Math Function: > > "The execution size must be no more than 8 when half-floats >are used in source or destination operand." > > Earlier generations do not support Extended Math with half-float. > ---

Re: [Mesa-dev] [PATCH] meson: Add nir_algebraic_parser_test to suites

On Friday, 2018-12-07 09:16:38 -0800, Dylan Baker wrote: > Just to make it easier to run a nir tests together. > > Fixes: a0ae12ca91a45f81897e774019cde9bd081f03a0 >("nir/algebraic: Add unit tests for bitsize validation") Reviewed-by: Eric Engestrom > --- > src/compiler/nir/meson.build

Re: [Mesa-dev] [PATCH 08/59] compiler/spirv: implement 16-bit frexp

Looks the same as what we do for the others. Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > --- > src/compiler/spirv/vtn_glsl450.c | 48 ++-- > 1 file changed, 46 insertions(+), 2 deletions(-) > > diff --git

Re: [Mesa-dev] [PATCH 13/59] intel/compiler: simplify f2*64 opcodes

On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > Now that this case only handles 64-bit destinations we can simplify > a bit the code. > "the code a bit". Sorry, English is hard > --- > src/intel/compiler/brw_fs_nir.cpp | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >

Re: [Mesa-dev] [PATCH 11/28] util: added float to float16 conversions with RTZ and RTNE

Am 07.12.18 um 05:22 schrieb Matt Turner: > On Thu, Dec 6, 2018 at 7:22 PM Roland Scheidegger wrote: >> >> Am 07.12.18 um 03:20 schrieb Matt Turner: >>> Since this is for an extension that will be BDW+ can we use the >>> _cvtss_sh() intrinsic instead? It corresponds to an IVB+ instruction >>> and

[Mesa-dev] [PATCH 19/38] ac/nir: implement 16-bit shifts

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 9 +++-- 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 517da7ba9b..aac3330c0d 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH 37/38] ac/nir: have nir_op_f2f16 round to zero

In the hope that one day LLVM will then be able to generate code with vectorized v_cvt_pkrtz_f16_f32 instructions. Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH 30/38] ac/nir: add 8-bit and 16-bit types to glsl_base_to_llvm_type

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 8 1 file changed, 8 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index d69135cc25..e4ae85a1ae 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH 20/38] compiler/nir: add lowering option for 16-bit ffma

The lowering needs to be disabled for sufficient precision to pass deqp-vk's 16-bit fma test on radv. Signed-off-by: Rhys Perry --- src/broadcom/compiler/nir_to_vir.c| 1 + src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 4 +++-

[Mesa-dev] [PATCH 35/38] ac,radv: run LLVM's SLP vectorizer

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_util.c | 9 ++--- src/amd/common/ac_llvm_util.h | 1 + src/amd/vulkan/radv_shader.c | 3 +++ 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c index

[Mesa-dev] [PATCH 23/38] nir: make bitfield_reverse and ifind_msb work with all integers

Signed-off-by: Rhys Perry --- src/compiler/nir/nir_opcodes.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index 4ef4ecc6f2..962971c650 100644 --- a/src/compiler/nir/nir_opcodes.py +++

[Mesa-dev] [PATCH 33/38] radv: store all fragment shader inputs as f32

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_nir_to_llvm.c | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index e5e4637f0d..3d367c1378 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c

[Mesa-dev] [PATCH 26/38] ac/nir: implement 8 and 16 bit ac_build_imsb

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 4 1 file changed, 4 insertions(+) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 0123f3e31d..2172d81f8b 100644 --- a/src/amd/common/ac_llvm_build.c +++ b/src/amd/common/ac_llvm_build.c @@

[Mesa-dev] [PATCH 25/38] ac/nir: make ac_build_umsb work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 38 +++--- 1 file changed, 7 insertions(+), 31 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 754ceda89b..0123f3e31d 100644 ---

[Mesa-dev] [PATCH 22/38] ac/nir: implement 8 and 16 bit ac_build_readlane

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index f394d16bc9..6266058b77 100644 --- a/src/amd/common/ac_llvm_build.c +++

[Mesa-dev] [PATCH 27/38] ac/nir: make ac_build_bit_count work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 33 +++-- 1 file changed, 7 insertions(+), 26 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 2172d81f8b..3990a1f56d 100644 ---

[Mesa-dev] [PATCH 32/38] ac/nir: store all outputs as f32

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 13 - src/amd/vulkan/radv_nir_to_llvm.c | 22 +- 2 files changed, 17 insertions(+), 18 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index

[Mesa-dev] [PATCH 34/38] radv: handle all fragment output types

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_nir_to_llvm.c | 55 --- 1 file changed, 35 insertions(+), 20 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 3d367c1378..342b79274a 100644 ---

[Mesa-dev] [PATCH 28/38] ac/nir: make ac_build_bitfield_reverse work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 3990a1f56d..68ea6078d3 100644 --- a/src/amd/common/ac_llvm_build.c

[Mesa-dev] [PATCH 29/38] ac/nir: implement 16-bit pack/unpack opcodes

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 24 1 file changed, 24 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index aac3330c0d..d69135cc25 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH 24/38] ac/nir: make ac_find_lsb work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 31 +-- 1 file changed, 5 insertions(+), 26 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 6266058b77..754ceda89b 100644 ---

[Mesa-dev] [PATCH 38/38] radv: expose float16, int16 and int8 features and extensions

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_device.c | 17 + src/amd/vulkan/radv_extensions.py | 4 src/amd/vulkan/radv_shader.c | 3 +++ 3 files changed, 24 insertions(+) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index

[Mesa-dev] [PATCH 31/38] ac/nir, radv: create an array of varying output types

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 68 +++ src/amd/common/ac_shader_abi.h| 1 + src/amd/vulkan/radv_nir_to_llvm.c | 3 ++ 3 files changed, 72 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH 21/38] ac/nir: implement 16-bit ac_build_ddxy

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 17 ++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index e85c178f78..f394d16bc9 100644 --- a/src/amd/common/ac_llvm_build.c +++

[Mesa-dev] [PATCH 36/38] ac/nir: generate better code for nir_op_f2f16_rtz

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index b4418af50a..92b773981b 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

Re: [Mesa-dev] [PATCH 10/59] intel/compiler: implement conversions from 16-bit float to 64-bit

Would it be easier to split it into two instructions in NIR and just implement the two conversions in the back-end? I suppose structuring things this way, it's probably fairly easy to just do it in the back-end. I guess that's ok. On Tue, Dec 4, 2018 at 1:17 AM Iago Toral Quiroga wrote: >

[Mesa-dev] [PATCH] radv: implement VK_EXT_sample_locations

Basically, this extension allows applications to use custom sample locations. This only implements the barely minimum. It doesn't support variable sample locations during subpass. Most of the dEQP-VK.pipeline.multisample.sample_locations_ext.* CTS now pass. Only enabled on VI+ because it's

[Mesa-dev] [Bug 107565] TypeError: __init__() got an unexpected keyword argument 'future_imports'

https://bugs.freedesktop.org/show_bug.cgi?id=107565 Emil Velikov changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

Re: [Mesa-dev] [PATCH 14/59] intel/compiler: lower some 16-bit float operations to 32-bit

Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > The hardware doesn't support half-float for these. > --- > src/intel/compiler/brw_nir.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/src/intel/compiler/brw_nir.c

Re: [Mesa-dev] [PATCH 12/59] intel/compiler: handle b2i/b2f with other integer conversion opcodes

This'll have to be rebased on dca6cd9ce6510 but otherwise looks fine. I've been a bit annoyed by this myself. Reviewed-by: Jason Ekstrand Incidentally, this could also be lowered in NIR Not sure if we want to but there it is. On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: >

[Mesa-dev] [Bug 102597] [Regression] mpv, high rendering times (two to three times higher)

https://bugs.freedesktop.org/show_bug.cgi?id=102597 Emil Velikov changed: What|Removed |Added Status|NEEDINFO|RESOLVED Resolution|---

[Mesa-dev] [PATCH 08/38] ac/nir: make ac_build_clamp work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index cc7c6da5a4..1ef28323d1 100644 --- a/src/amd/common/ac_llvm_build.c +++

[Mesa-dev] [PATCH 15/38] ac/nir: implement half-float nir_op_ldexp

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index b447da092f..bb7c421606 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH 10/38] ac/nir: make ac_build_isign work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 27 --- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 0a1987c65b..fa5c68d1b6 100644 --- a/src/amd/common/ac_llvm_build.c

[Mesa-dev] [PATCH 11/38] ac/nir: make ac_build_fsign work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 16 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index fa5c68d1b6..c85f9a214e 100644 --- a/src/amd/common/ac_llvm_build.c +++

[Mesa-dev] [PATCH 01/38] ac: add various helpers for float16/int16/int8

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 123 ++-- src/amd/common/ac_llvm_build.h | 22 +- src/amd/common/ac_nir_to_llvm.c | 30 3 files changed, 154 insertions(+), 21 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c

[Mesa-dev] [PATCH 13/38] ac/nir: implement half-float nir_op_frcp

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index ef850d6d22..7084b390d2 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH 05/38] ac/nir: implement 8-bit nir_load_const_instr

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 4 1 file changed, 4 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 535a47d790..6d0d2cbd55 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH 07/38] ac/nir: fix 64-bit nir_op_f2f16_rtz

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 7c827b443b..ef850d6d22 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@

[Mesa-dev] [PATCH 09/38] ac/nir: make ac_build_fract work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 13 +++-- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 1ef28323d1..0a1987c65b 100644 --- a/src/amd/common/ac_llvm_build.c +++

[Mesa-dev] [PATCH 16/38] radv: lower 16-bit flrp

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_shader.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 456c462a23..9ba20ac72e 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -53,6 +53,7 @@

[Mesa-dev] [PATCH 00/38] radv, ac: 16-bit and 8-bit arithmetic and 8-bit storage

This series add support for: - VK_KHR_shader_float16_int8 - VK_AMD_gpu_shader_half_float - VK_AMD_gpu_shader_int16 - VK_KHR_8bit_storage on VI+. Half floats are currently disabled on LLVM 7 because of a bug causing large memory usage and long (or unbounded) compilation times with some tests. It

[Mesa-dev] [PATCH 03/38] ac/nir: implement 8-bit ssbo stores

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 8910dabb3d..31fb77290c 100644 --- a/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH 02/38] ac/nir: implement 8-bit push constant, ssbo and ubo loads

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 37 +++-- 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 2e9fd7b689..8910dabb3d 100644 ---

[Mesa-dev] [PATCH 06/38] ac/nir: implement 8-bit conversions

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 6d0d2cbd55..7c827b443b 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH 12/38] ac/nir: make ac_build_fdiv support 16-bit floats

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index c85f9a214e..e85c178f78 100644 --- a/src/amd/common/ac_llvm_build.c +++

[Mesa-dev] [PATCH 18/38] ac/nir: make emit_b2i work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 459d9c119c..517da7ba9b 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH 17/38] ac/nir: support half floats in emit_b2f

This seems to generate fine code, even though the IR is a bit ugly. Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index

[Mesa-dev] [PATCH 04/38] ac/nir: fix 16-bit ssbo stores

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 31fb77290c..535a47d790 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@

[Mesa-dev] [PATCH 14/38] ac/nir: implement half-float nir_op_frsq

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 7084b390d2..b447da092f 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

Re: [Mesa-dev] [PATCH 09/59] compiler/spirv: use 32-bit polynomial approximation for 16-bit asin()

On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > The 16-bit polynomial execution doesn't meet Khronos precision > requirements. > Also, the half-float denorm range starts at 2^(-14) and with asin taking > input > values in the range [0, 1], polynomial approximations can lead to

[Mesa-dev] [Bug 94957] dEQP failures on llvmpipe

https://bugs.freedesktop.org/show_bug.cgi?id=94957 --- Comment #12 from Emil Velikov --- The below commit allows us to disable the perf. optimisations (for release builds), and thus fixing the functional.texture tests. Should we close this bug, or keep it open as all the failing tests have a

Re: [Mesa-dev] [PATCH v2] docs: Document GitLab merge request process (email alternative)

On Wednesday, 2018-12-05 15:32:05 -0800, Jordan Justen wrote: > This documents a process for using GitLab Merge Requests as an second > way to submit code changes for Mesa. Only one of the two methods is > allowed for each patch series. > > We will *not* require all patches to be emailed. Some

Re: [Mesa-dev] [PATCH 22/59] compiler/nir: add lowering for 16-bit ldexp

On Wed, Dec 5, 2018 at 5:32 AM Pohjolainen, Topi wrote: > On Wed, Dec 05, 2018 at 12:26:06PM +0100, Iago Toral wrote: > > On Wed, 2018-12-05 at 13:20 +0200, Pohjolainen, Topi wrote: > > > On Wed, Dec 05, 2018 at 11:53:44AM +0100, Iago Toral wrote: > > > > On Wed, 2018-12-05 at 11:39 +0200,

Re: [Mesa-dev] [PATCH 07/59] compiler/spirv: implement 16-bit hyperbolic trigonometric functions

My comment earlier, I think, applies to all of the first 7. Let's just add nir_fadd_imm and nir_fmul_imm and rewrite them to use those. That'll make them handle doubles as well if we ever need it. On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > --- >

Re: [Mesa-dev] [PATCH 15/59] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9

I haven't checked the HW docs but Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > Extended math desn't support half-float on these generations. > --- > src/intel/compiler/brw_nir.c | 13 - > 1 file changed, 12 insertions(+), 1 deletion(-) >

Re: [Mesa-dev] [PATCH 28/59] intel/compiler: set correct precision fields for 3-source float instructions

On Wed, Dec 5, 2018 at 7:14 AM Pohjolainen, Topi wrote: > On Wed, Dec 05, 2018 at 02:04:16PM +0100, Iago Toral wrote: > > On Wed, 2018-12-05 at 14:58 +0200, Pohjolainen, Topi wrote: > > > On Tue, Dec 04, 2018 at 08:16:52AM +0100, Iago Toral Quiroga wrote: > > > > Source0 and Destination extract

Re: [Mesa-dev] [PATCH 36/59] compiler/spirv: add implementation to check for SpvCapabilityFloat16 support

Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > --- > src/compiler/shader_info.h| 1 + > src/compiler/spirv/spirv_to_nir.c | 4 +++- > 2 files changed, 4 insertions(+), 1 deletion(-) > > diff --git a/src/compiler/shader_info.h

Re: [Mesa-dev] [PATCH 42/59] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit

Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:19 AM Iago Toral Quiroga wrote: > Particularly, we need the same lowewrings we use for 16-bit > integers. > --- > src/intel/compiler/brw_nir.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git

Re: [Mesa-dev] [PATCH v2] docs: Document GitLab merge request process (email alternative)

Hi, On Sat, 8 Dec 2018 at 05:15, Eric Engestrom wrote: > On Friday, 2018-12-07 10:19:23 +0100, Erik Faye-Lund wrote: > > Automated emails (and perhaps IRC bot) would be really nice. > > Agreed. Email would be great to help with the transition. > There's work currently being done on GitLab to

Re: [Mesa-dev] [PATCH 29/59] intel/compiler: don't propagate HF immediates to 3-src instructions

Seems reasonable though I thought you had patches to the constant combining to fix this. Maybe they'll be ready in time that we won't need this? On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > 3-src instructions don't support immediates, but since 36bc5f06dd22, > we allow them on

Re: [Mesa-dev] [PATCH 33/59] intel/compiler: do not copy-propagate strided regions to ddx/ddy arguments

On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > The implementation of these opcodes in the generator assumes that their > arguments are packed, and it generates register regions based on that > assumption. While this expectation is reasonable for 32-bit, Expectation, sure, but if

Re: [Mesa-dev] [PATCH 46/59] intel/compiler: fix integer to/from half-float in atom platforms

We are starting to get a *lot* of special cases in the conversion code. I'm not sure what the best thing to do is. Maybe some master conversion function that just does it all? Maybe some NIR lowering? In any case, I think we can do better than the pile of special cases we are starting to

Re: [Mesa-dev] [PATCH 48/59] intel/compiler: implement isign for int8

Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:19 AM Iago Toral Quiroga wrote: > --- > src/intel/compiler/brw_fs_nir.cpp | 25 + > 1 file changed, 21 insertions(+), 4 deletions(-) > > diff --git a/src/intel/compiler/brw_fs_nir.cpp >

Re: [Mesa-dev] [PATCH 53/59] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit

On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > There are no 8-bit immediates, so assert in that case. > 16-bit immediates are replicated in each word of a 32-bit immediate, so > we only need to check the lower 16-bits. > --- > src/intel/compiler/brw_shader.cpp | 20

Re: [Mesa-dev] [PATCH 54/59] intel/compiler: add a brw_reg_type_is_integer helper

Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:19 AM Iago Toral Quiroga wrote: > --- > src/intel/compiler/brw_reg_type.h | 18 ++ > 1 file changed, 18 insertions(+) > > diff --git a/src/intel/compiler/brw_reg_type.h > b/src/intel/compiler/brw_reg_type.h > index

[Mesa-dev] [PATCH 1/2] pci_ids: add new vega10 pci ids

Signed-off-by: Alex Deucher Cc: mesa-sta...@lists.freedesktop.org --- include/pci_ids/radeonsi_pci_ids.h | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 35ea3559b02..f7defc4197a 100644 ---

[Mesa-dev] [PATCH 2/2] pci_ids: add new vega20 pci id

Signed-off-by: Alex Deucher Cc: mesa-sta...@lists.freedesktop.org --- include/pci_ids/radeonsi_pci_ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index f7defc4197a..a2bc9213207 100644 ---

Re: [Mesa-dev] [PATCH 31/59] intel/compiler: fix ddx and ddy for 16-bit float

On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > We were assuming 32-bit elements. > --- > src/intel/compiler/brw_fs_generator.cpp | 34 + > 1 file changed, 18 insertions(+), 16 deletions(-) > > diff --git a/src/intel/compiler/brw_fs_generator.cpp >

Re: [Mesa-dev] [PATCH 32/59] intel/compiler: fix 16-bit float ddx and ddy for SIMD8

And here we are I think I'd still like byte_offset better but, either way patches 31 and 32 are Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > In SIMD8 we pack 2 vector components in a single SIMD register, so > for example, component Y of a 16-bit

Re: [Mesa-dev] [PATCH 39/59] anv/device: expose support for shaderFloat16 in gen8+

Pending review on previous patches. 37 and 39 are Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > --- > src/intel/vulkan/anv_device.c | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/src/intel/vulkan/anv_device.c

Re: [Mesa-dev] [PATCH 40/59] anv/extensions: expose VK_KHR_shader_float16_int8 on gen8+

rb On Tue, Dec 4, 2018 at 1:19 AM Iago Toral Quiroga wrote: > --- > src/intel/vulkan/anv_extensions.py | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/intel/vulkan/anv_extensions.py > b/src/intel/vulkan/anv_extensions.py > index 7c81228f705..9ca42d998ef 100644 > ---

Re: [Mesa-dev] [PATCH 00/11] i965 shader debug through KHR_debug

Ilia Mirkin writes: > On Thu, Dec 6, 2018 at 7:36 PM Mark Janes wrote: >> >> This series provides Intel shader compilation debug information via >> KHR_debug. Previously, shader assembly and related compilation >> artifacts were dumped to stderr. Tools associating compilation >> artifacts

Re: [Mesa-dev] [PATCH v2] docs: Document GitLab merge request process (email alternative)

On Friday, 2018-12-07 10:19:23 +0100, Erik Faye-Lund wrote: > On Wed, 2018-12-05 at 21:46 -0600, Jason Ekstrand wrote: > > On Wed, Dec 5, 2018 at 7:05 PM Jordan Justen < > > jordan.l.jus...@intel.com> wrote: > > > On 2018-12-05 15:44:18, Jason Ekstrand wrote: > > > > On Wed, Dec 5, 2018 at 5:32 PM

Re: [Mesa-dev] [PATCH 49/59] intel/eu: force stride of 2 on NULL register for Byte instructions

Reviewed-by: Jason Ekstrand On Tue, Dec 4, 2018 at 1:18 AM Iago Toral Quiroga wrote: > The hardware only allows a stride of 1 on a Byte destination for raw > byte MOV instructions. This is required even when the destination > is the NULL register. > > Rather than making sure that we emit a

Re: [Mesa-dev] [PATCH 34/59] intel/compiler: fix ddy for half-float in gen8

On Tue, Dec 4, 2018 at 1:19 AM Iago Toral Quiroga wrote: > We use ALign16 mode for this, since it is more convenient, but the PRM > for Broadwell states in Volume 3D Media GPGPU, Chapter 'Register region > restrictions', Section '1. Special Restrictions': > >"In Align16 mode, the channel

Re: [Mesa-dev] [PATCH 52/59] anv/device: expose shaderInt8 feature

51 and 52 should probably be rolled together. For that matter, I don't think we need 6 patches just to add two SPIR-V capabilities and advertise one extension. Maybe roll the two SPIR-V patches together, add one or two for the extension and the enables? On Tue, Dec 4, 2018 at 1:18 AM Iago Toral

Re: [Mesa-dev] [PATCH 2/3] intel/blorp: Make KSP a blorp_address instead of an offset.

I somewhat recant my statements below. Even in a driver that puts the full address in the offset field, having the BO pointer may still be useful for the purpose of adding it to a residency list somewhere. On Fri, Dec 7, 2018 at 4:13 PM Jason Ekstrand wrote: > I kind-of wonder if we want to

[Mesa-dev] [RFC PATCH 06/14] anv/allocator: Add getters for anv_block_pool.

We will need specially the anv_block_pool_map, to find the map relative to some BO that is not at the start of the block pool. --- src/intel/vulkan/anv_allocator.c | 23 --- src/intel/vulkan/anv_batch_chain.c | 5 +++-- src/intel/vulkan/anv_private.h | 7 +++

[Mesa-dev] [RFC PATCH 13/14] anv/allocator: Add padding information.

It's possible that we still have some space left in the block pool, but we try to allocate a state larger than that state. This means such state would start somewhere within the range of the old block_pool, and end after that range, within the range of the new size. That's fine when we use

[Mesa-dev] [RFC PATCH 11/14] anv: Remove some asserts.

They won't be true anymore once we add support for multiple BOs with non-userptr. --- src/intel/vulkan/genX_gpu_memcpy.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/intel/vulkan/genX_gpu_memcpy.c b/src/intel/vulkan/genX_gpu_memcpy.c index 1bee1c6dc17..e20179fa675 100644 ---

[Mesa-dev] [RFC PATCH 05/14] anv/allocator: Remove usage of anv_free_list.

Maybe we should already rename anv_free_list2 -> anv_free_list since the old one is gone. --- src/intel/vulkan/anv_allocator.c | 55 src/intel/vulkan/anv_private.h | 11 --- 2 files changed, 66 deletions(-) diff --git a/src/intel/vulkan/anv_allocator.c

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