On Tue, 18 Dec 2018 18:59:10 +0100
Lucas Stach wrote:
> Am Dienstag, den 18.12.2018, 17:43 + schrieb Emil Velikov:
> > > On Tue, 18 Dec 2018 at 11:16, Lucas Stach wrote:
> > >
> > > Currently we dispose any unneeded color buffers immediately if we detect
> > > that
> > > there are more
On Tue, 18 Dec 2018 at 17:59, Lucas Stach wrote:
>
> Am Dienstag, den 18.12.2018, 17:43 + schrieb Emil Velikov:
> > > On Tue, 18 Dec 2018 at 11:16, Lucas Stach wrote:
> > >
> > > Currently we dispose any unneeded color buffers immediately if we detect
> > > that
> > > there are more
Hi,
On Tue, 18 Dec 2018 at 17:59, Lucas Stach wrote:
> Am Dienstag, den 18.12.2018, 17:43 + schrieb Emil Velikov:
> > > On Tue, 18 Dec 2018 at 11:16, Lucas Stach wrote:
> > > if (dri2_surf->back == NULL)
> > > dri2_surf->back = _surf->color_buffers[i];
> > > -
On Tue, Jan 15, 2019 at 1:02 AM Tapani Pälli wrote:
>
>
>
> On 1/14/19 2:36 PM, Daniel Stone wrote:
> > Hi,
> >
> > On Fri, 11 Jan 2019 at 17:05, Jason Ekstrand wrote:
> >> 5. There's no way with gitlab for Reviewed-by tags to get automatically
> >> applied as part of the merging process.
Hi,
On Tue, 15 Jan 2019 at 12:21, Rob Clark wrote:
> On Tue, Jan 15, 2019 at 1:02 AM Tapani Pälli wrote:
> > On 1/14/19 2:36 PM, Daniel Stone wrote:
> > > On Fri, 11 Jan 2019 at 17:05, Jason Ekstrand wrote:
> > > In other projects, we looked for ways to apply the tags and ended up
> > >
On 15/1/19 7:01, Tapani Pälli wrote:
>
>
> On 1/14/19 2:36 PM, Daniel Stone wrote:
>> Hi,
>>
>> On Fri, 11 Jan 2019 at 17:05, Jason Ekstrand
>> wrote:
>>> 5. There's no way with gitlab for Reviewed-by tags to get
>>> automatically applied as part of the merging process. This makes
>>> merging
https://bugs.freedesktop.org/show_bug.cgi?id=109339
Ahmed Elsayed changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
We are now using these bits, so don't assert that they are not set, just
avoid compaction in that case.
Reviewed-by: Topi Pohjolainen
---
src/intel/compiler/brw_eu_compact.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_eu_compact.c
There is a hardware restriction where <0,1,0>:HF in Align16 doesn't replicate
a single 16-bit channel, but instead it replicates a full 32-bit channel.
---
.../compiler/brw_fs_combine_constants.cpp | 24 +--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git
v2:
- Do not propagate if the bit-size changes
---
src/intel/compiler/brw_fs_cmod_propagation.cpp | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/intel/compiler/brw_fs_cmod_propagation.cpp
b/src/intel/compiler/brw_fs_cmod_propagation.cpp
index
Reviewed-by: Topi Pohjolainen
---
src/intel/compiler/brw_eu_emit.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index e21df4624b3..a785f96b650 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++
This function is used in two different scenarios that for 32-bit
instructions are the same, but for 16-bit instructions are not.
One scenario is that in which we are working at a SIMD8 register
level and we need to know if a register is fully defined or written.
This is useful, for example, in
Reviewed-by: Jason Ekstrand
---
src/compiler/nir/nir.h| 1 +
src/compiler/nir/nir_opt_algebraic.py | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 19056e79206..adcc8e36cc9 100644
--- a/src/compiler/nir/nir.h
+++
Extended math doesn't support half-float on these generations.
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_nir.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index
Reviewed-by: Jason Ekstrand
---
src/compiler/nir/nir.h| 1 +
src/compiler/nir/nir_opt_algebraic.py | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 3cb2d166cb3..19056e79206 100644
--- a/src/compiler/nir/nir.h
+++
v2:
- Merge Float16 and Int8 in a single patch (Jason)
Reviewed-by: Jason Ekstrand (v1)
---
src/intel/vulkan/anv_pipeline.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 899160746d4..663d1c77fa5 100644
---
These are not directly supported in hardware and brw_nir_lower_conversions
should have taken care of that before we get here. Also, while we are
at it, make sure 64-bit integer to 8-bit are also properly split by
the same lowering pass, since they have the same hardware restrictions.
---
The original SrcType is a 3-bit field that takes a subset of the types
supported for the hardware for 3-source instructions. Since gen8,
when the half-float type was added, 3-source floating point operations
can use use mixed precision mode, where not all the operands have the
same floating-point
v2 (Jason):
- Merge Float16 and Int8 into a single patch.
- Merge extension enable.
Reviewed-by: Jason Ekstrand (v1)
---
src/intel/vulkan/anv_device.c | 9 +
src/intel/vulkan/anv_extensions.py | 1 +
2 files changed, 10 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c
Reviewed-by: Topi Pohjolainen
---
.../compiler/brw_fs_combine_constants.cpp | 60 +++
1 file changed, 49 insertions(+), 11 deletions(-)
diff --git a/src/intel/compiler/brw_fs_combine_constants.cpp
b/src/intel/compiler/brw_fs_combine_constants.cpp
index
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_compiler.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/compiler/brw_compiler.c
b/src/intel/compiler/brw_compiler.c
index f885e79c3e6..04a1a7cac4e 100644
--- a/src/intel/compiler/brw_compiler.c
+++
Reviewed-by: Topi Pohjolainen
---
src/intel/compiler/brw_fs_nir.cpp | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index e454578d99b..a739562c3ab 100644
---
Source0 and Destination extract the floating-point precision automatically
from the SrcType and DstType instruction fields respectively when they are
set to types :F or :HF. For Source1 and Source2 operands, we use the new
1-bit fields Src1Type and Src2Type, where 0 means normal precision and 1
---
src/intel/compiler/brw_fs_nir.cpp | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index a3d193b8a44..ccf1891b925 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++
The hardware doesn't support half-float for these.
Reviewed-by: Topi Pohjolainen
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_nir.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 572ab824a94..f0fe7f870c2
We were assuming 32-bit elements. Also, In SIMD8 we pack 2 vector components
in a single SIMD register, so for example, component Y of a 16-bit vec2
starts is at byte offset 16B. This means that when we compute the offset of
the elements to be differentiated we should not stomp whatever base
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_reg_type.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/src/intel/compiler/brw_reg_type.h
b/src/intel/compiler/brw_reg_type.h
index ffbec90d3fe..a3365b7e34c 100644
--- a/src/intel/compiler/brw_reg_type.h
+++
Broadwell hardware has a bug that manifests in SIMD8 executions of
16-bit MAD instructions when any of the sources is a Y or W component.
We pack these components in the same SIMD register as components X and
Z respectively, but starting at offset 16B (so they live in the second
half of the
v2:
- Merge Float16 and Int8 capabilities into a single patch (Jason)
Reviewed-by: Jason Ekstrand (v1)
---
src/compiler/shader_info.h| 2 ++
src/compiler/spirv/spirv_to_nir.c | 8 ++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/compiler/shader_info.h
v2 (Topi):
- Make bit-size handling order be 16-bit, 32-bit, 64-bit
- Clamp lower exponent range at -28 instead of -30.
Reviewed-by: Topi Pohjolainen
Reviewed-by: Jason Ekstrand
---
src/compiler/nir/nir_opt_algebraic.py | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff
Even if we don't do 3-src algebraic optimizations for MAD and LRP in
the backend any more, the combine constants pass can still do a fine
job putting grouping these constants into single registers for better
register pressure.
v2:
- updated comment to reference register pressure benefits rather
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_nir.cpp | 25 +
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index a739562c3ab..a3d193b8a44 100644
---
There are no 8-bit immediates, so assert in that case.
16-bit immediates are replicated in each word of a 32-bit immediate, so
we only need to check the lower 16-bits.
v2:
- Fix is_zero with half-float to consider -0 as well (Jason).
- Fix is_negative_one for word type.
---
Going forward having these split is a bit more convenient since these two
groups have different restrictions.
v2:
- Rebased on top of new regioning lowering pass.
Reviewed-by: Topi Pohjolainen (v1)
---
src/intel/compiler/brw_fs_nir.cpp | 7 +++
1 file changed, 7 insertions(+)
diff --git
Particularly, we need the same lowewrings we use for 16-bit
integers.
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_nir.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 3b2909da33e..2dfbf8824dc
The hardware only allows a stride of 1 on a Byte destination for raw
byte MOV instructions. This is required even when the destination
is the NULL register.
Rather than making sure that we emit a proper NULL:B destination
every time we need one, just fix it at emission time.
Reviewed-by: Jason
NIR already has these so they are redundant. A run of shader-db confirms
that the only cases where these backend optimizations are activated
are some Tomb Raider shaders where the affected variables are qualified
as "precise", which is why NIR won't apply them and why the backend
shouldn't either
This is available since gen8.
v2: restore previously existing assertion.
Reviewed-by: Topi Pohjolainen (v1)
---
src/intel/compiler/brw_reg_type.c | 36 +++
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/src/intel/compiler/brw_reg_type.c
We open coded this in a couple of places, so a helper function is probably
sensible. Plus it makes it more consistent with the 3src hardware type case.
Suggested-by: Topi Pohjolainen
---
src/intel/compiler/brw_reg_type.c | 34 ---
1 file changed, 18 insertions(+), 16
Just tested it with the ARB_gl_spirv tests where I found this:
Tested-by: Alejandro Piñeiro
On 15/1/19 12:08, Sergii Romantsov wrote:
During conversion type-length was lost due to math.
CC: Jason Ekstrand
Fixes: 44227453ec03 (nir: Switch to using 1-bit Booleans for almost everything)
v2:
- make 16-bit be its own separate case (Jason)
Reviewed-by: Topi Pohjolainen
---
src/intel/compiler/brw_fs_nir.cpp | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index
3-src instructions don't support immediates, but since 36bc5f06dd22,
we allow them on MAD and LRP relying on the combine constants pass to
fix it up later. However, that pass is specialized for 32-bit float
immediates and can't handle HF constants at present, so this patch
ensures that
There are some hardware restrictions that brw_nir_lower_conversions should
have taken care of before we get here.
v2:
- rebased on top of regioning lowering pass
Reviewed-by: Topi Pohjolainen (v1)
---
src/intel/compiler/brw_fs_nir.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_compiler.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/compiler/brw_compiler.c
b/src/intel/compiler/brw_compiler.c
index fe632c5badc..f885e79c3e6 100644
--- a/src/intel/compiler/brw_compiler.c
+++
Since we handle booleans as integers this makes more sense.
v2:
- rebased to incorporate new boolean conversion opcodes
v3:
- rebased on top regioning lowering pass
Reviewed-by: Jason Ekstrand (v1)
Reviewed-by: Topi Pohjolainen (v2)
---
src/intel/compiler/brw_fs_nir.cpp | 16
From the Skylake PRM, Extended Math Function:
"The execution size must be no more than 8 when half-floats
are used in source or destination operand."
Earlier generations do not support Extended Math with half-float.
v2:
- Rewrite the code to make it more readable (Jason).
v3:
- Use
We use ALign16 mode for this, since it is more convenient, but the PRM
for Broadwell states in Volume 3D Media GPGPU, Chapter 'Register region
restrictions', Section '1. Special Restrictions':
"In Align16 mode, the channel selects and channel enables apply to a
pair of half-floats, because
v2: adapted to work with the new regioning lowering pass
Reviewed-by: Topi Pohjolainen (v1)
---
src/intel/compiler/brw_ir_fs.h | 33 ++---
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h
The PRM states that half-float operands are supported since gen9.
Reviewed-by: Topi Pohjolainen
---
src/intel/compiler/brw_eu_emit.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index
Some conversions are not directly supported in hardware and need to be
split in two conversion instructions going through an intermediary type.
Doing this at the NIR level simplifies a bit the complexity in the backend.
v2:
- Consider fp16 rounding conversion opcodes
- Properly handle swizzles
The changes in this version address review feedback to v2 and, most importantly,
rebase on top of relevant changes in master, specifically Curro's regioning
lowering pass. This new regioning pass simplifies some of the NIR translation
code (specifically the code for translating regioning
Hello list,
The candidate for the Mesa 18.3.2 is now available. Currently we have:
- 78 queued
- 3 nominated (outstanding)
- and 0 rejected patches
With this release candidate we have added more PCI IDs for AMD Vega devices and
a number of fixes for the RADV Vulkan drivers.
On the Intel
During conversion type-length was lost due to math.
CC: Jason Ekstrand
Fixes: 44227453ec03 (nir: Switch to using 1-bit Booleans for almost everything)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109353
Signed-off-by: Sergii Romantsov
---
src/compiler/spirv/spirv_to_nir.c | 9
On 1/15/19 8:02 AM, Daniel Stone wrote:
> Hi,
>
> On Tue, 18 Dec 2018 at 17:59, Lucas Stach wrote:
>> Am Dienstag, den 18.12.2018, 17:43 + schrieb Emil Velikov:
On Tue, 18 Dec 2018 at 11:16, Lucas Stach wrote:
if (dri2_surf->back == NULL)
Previously, we only applied the fix to shaders with a dispatch mode of
SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16
instructions. If you have a SIMD8 instruction in a SIMD16 shader,
neither would trigger and the restriction could still be hit.
Cc: Jose Maria Casanova
From: Marek Olšák
---
src/gallium/auxiliary/util/u_format.c | 40 ++
src/gallium/auxiliary/util/u_format.h | 3 ++
src/gallium/drivers/radeonsi/si_blit.c | 32 ++---
3 files changed, 45 insertions(+), 30 deletions(-)
diff --git
Quoting Chuck Atkins (2019-01-15 11:17:43)
> I'm jumping into Meson land now and I'm trying to configure the most recent
> release, 18.3.1, to build a minimal OSMesa containing only softpipe. So I'm
> trying to make sure everything is explicitly disabled and only turning on the
> few pieces I
Quoting Jason Ekstrand (2019-01-15 11:57:01)
> On Tue, Jan 15, 2019 at 12:52 PM Eric Anholt wrote:
>
> Daniel Stone writes:
>
> > Hi,
> >
> > On Tue, 15 Jan 2019 at 12:21, Rob Clark wrote:
> >> On Tue, Jan 15, 2019 at 1:02 AM Tapani Pälli
> wrote:
> >> > On
From: Sonny Jiang
v2: marek: fix snorm8 blits
Signed-off-by: Sonny Jiang
Signed-off-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_blit.c| 12 ++
.../drivers/radeonsi/si_compute_blit.c| 108 ++
src/gallium/drivers/radeonsi/si_pipe.c| 4 +
On Tue, Jan 15, 2019 at 7:40 AM Daniel Stone wrote:
>
> Hi,
>
> On Tue, 15 Jan 2019 at 12:21, Rob Clark wrote:
> > On Tue, Jan 15, 2019 at 1:02 AM Tapani Pälli wrote:
> > > On 1/14/19 2:36 PM, Daniel Stone wrote:
> > > > On Fri, 11 Jan 2019 at 17:05, Jason Ekstrand
> > > > wrote:
> > > > In
Reviewed-by: Bruce Cherniak
> On Dec 17, 2018, at 8:36 AM, Alok Hota wrote:
>
> Use gfxptr_t type value for stream pointer uses in gather and similar
> calls
> ---
> .../swr/rasterizer/jitter/fetch_jit.cpp | 34 +--
> 1 file changed, 16 insertions(+), 18 deletions(-)
>
>
Reviewed-by: Bruce Cherniak
> On Dec 17, 2018, at 8:36 AM, Alok Hota wrote:
>
> - added graphics address translation in odd gathers
> - added support for unaligned gathers in fetch shader
> - changed how 2+ GB offsets are handled to make them compatible with
> unaligned offsets
> ---
>
Reviewed-by: Bruce Cherniak
> On Dec 17, 2018, at 8:36 AM, Alok Hota wrote:
>
> Avoids confusion with other defaulted integer parameters
>
> - fixed some unspecified usages
> - removed unnecessary includes
> - removed unecessary protected access specifier in buckets framework
> ---
>
Reviewed-by: Bruce Cherniak
> On Dec 17, 2018, at 8:36 AM, Alok Hota wrote:
>
> Fixes relocation errors with LLVM 7.0.0
> ---
> .../swr/rasterizer/jitter/JitManager.cpp | 79 +++
> .../swr/rasterizer/jitter/JitManager.h| 28 +--
> 2 files changed, 65
Reviewed-by: Bruce Cherniak
> On Dec 17, 2018, at 8:36 AM, Alok Hota wrote:
>
> - updated sample from TRTT surfaces correctly
> - implemented mapped status return for TRTT surfaces
> - implemented per-sample instruction minLod clamp
> - updated bilinear filter weight calculation to be closer
Reviewed-by: Bruce Cherniak
> On Dec 17, 2018, at 8:36 AM, Alok Hota wrote:
>
> This improves cache filesystem performance, especially during CI tests
> Also updated jitcache magic number due to codegen parameter changes
> Removed 2 `if constexpr` to prevent C++17 requirement
> ---
>
Reviewed-by: Alok Hota
-Alok
-Original Message-
From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On Behalf Of
Bruce Cherniak
Sent: Friday, January 4, 2019 2:54 PM
To: mesa-dev@lists.freedesktop.org
Cc: mesa-sta...@lists.freedesktop.org
Subject: [Mesa-dev] [PATCH]
From: Marek Olšák
for radeonsi
---
src/gallium/auxiliary/util/u_format.csv | 4
src/gallium/include/pipe/p_format.h | 5 +
2 files changed, 9 insertions(+)
diff --git a/src/gallium/auxiliary/util/u_format.csv
b/src/gallium/auxiliary/util/u_format.csv
index
From: Marek Olšák
same as AMDVLK.
GL_NV_alpha_to_coverage_dither_control allows controlling this behavior.
The default is implementation-dependent.
---
src/gallium/drivers/radeonsi/si_state.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git
I'm jumping into Meson land now and I'm trying to configure the most recent
release, 18.3.1, to build a minimal OSMesa containing only softpipe. So
I'm trying to make sure everything is explicitly disabled and only turning
on the few pieces I need:
meson -Ddebug=false -Degl=false -Dgbm=false
Quoting Chuck Atkins (2019-01-15 11:17:43)
> I'm jumping into Meson land now and I'm trying to configure the most recent
> release, 18.3.1, to build a minimal OSMesa containing only softpipe. So I'm
> trying to make sure everything is explicitly disabled and only turning on the
> few pieces I
On Tue, Jan 15, 2019 at 12:52 PM Eric Anholt wrote:
> Daniel Stone writes:
>
> > Hi,
> >
> > On Tue, 15 Jan 2019 at 12:21, Rob Clark wrote:
> >> On Tue, Jan 15, 2019 at 1:02 AM Tapani Pälli
> wrote:
> >> > On 1/14/19 2:36 PM, Daniel Stone wrote:
> >> > > On Fri, 11 Jan 2019 at 17:05, Jason
Reviewed-by: Bruce Cherniak
> On Dec 17, 2018, at 8:36 AM, Alok Hota wrote:
>
> To make debugging simpler
> ---
> .../swr/rasterizer/jitter/JitManager.cpp | 27 +--
> .../swr/rasterizer/jitter/JitManager.h| 12 -
> 2 files changed, 36 insertions(+), 3
https://bugs.freedesktop.org/show_bug.cgi?id=109258
--- Comment #2 from Eric Engestrom ---
I can reproduce, I'll take a look. Thanks for the report :)
As for your bisect, I had messed up a rebase and accidentally dropped a line in
8cb84c8477a57ed05d70, which lead to Marek reverting my commit a
Daniel Stone writes:
> Hi,
>
> On Tue, 15 Jan 2019 at 12:21, Rob Clark wrote:
>> On Tue, Jan 15, 2019 at 1:02 AM Tapani Pälli wrote:
>> > On 1/14/19 2:36 PM, Daniel Stone wrote:
>> > > On Fri, 11 Jan 2019 at 17:05, Jason Ekstrand
>> > > wrote:
>> > > In other projects, we looked for ways to
I noticed that gitlab breaks formatting of . It
removes < and >, and converts the address to a hyperlink. I can preserve
the formatting by enclosing the comment in ` ... `.
Marek
On Tue, Jan 15, 2019 at 1:52 PM Eric Anholt wrote:
> Daniel Stone writes:
>
> > Hi,
> >
> > On Tue, 15 Jan 2019 at
Quoting Chuck Atkins (2019-01-15 11:17:43)
> I'm jumping into Meson land now and I'm trying to configure the most recent
> release, 18.3.1, to build a minimal OSMesa containing only softpipe. So I'm
> trying to make sure everything is explicitly disabled and only turning on the
> few pieces I
Currently something like:
meson -Dgallium-drivers= -Dvulkan-drivers= -Ddri-drivers=swrast -Dosmesa=classic
-Degl=false -Dglx=disabled
will error, which is wrong.
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/115
Dylan
signature.asc
Description: signature
On Tue, Jan 15, 2019 at 3:54 PM Axel Davy wrote:
> On 15/01/2019 18:50, Marek Olšák wrote:
> >
> > +void si_compute_copy_image(struct si_context *sctx,
> > +struct pipe_resource *dst,
> > +unsigned dst_level,
> > +struct
On Tue, 15 Jan 2019 02:34:08 +
Lionel Landwerlin wrote:
> When writing this I used this page to figure the bytes' ordering :
> https://docs.microsoft.com/en-us/windows/desktop/medfound/recommended-8-bit-yuv-formats-for-video-rendering#ayuv
> Of course endianess confuses everything :(
>
>
Hey,
On Tue, 15 Jan 2019 at 20:22, Rob Clark wrote:
> On Tue, Jan 15, 2019 at 7:40 AM Daniel Stone wrote:
> > My question would again be what value that brings you. Do you just
> > like seeing the name there, or do you go poke the people on IRC, or
> > follow up via email, or ... ? Again I
On 15/01/2019 18:50, Marek Olšák wrote:
+void si_compute_copy_image(struct si_context *sctx,
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ struct pipe_resource *src,
+ unsigned
Reviewed-by: Marek Olšák
Marek
On Sun, Jan 13, 2019 at 1:57 PM Ilia Mirkin wrote:
> Currently we were only returning it for BGRA8. But it makes sense to
> return it for all the BGR[AX] variants. This was discovered when
> figuring out why wlroots was sending a RGBX instead of BGRX image when
On Tue, 15 Jan 2019 09:45:52 +0200
Tapani Pälli wrote:
> On 1/15/19 4:34 AM, Lionel Landwerlin wrote:
> > When writing this I used this page to figure the bytes' ordering :
> > https://docs.microsoft.com/en-us/windows/desktop/medfound/recommended-8-bit-yuv-formats-for-video-rendering#ayuv
> >
DXVK often sets dynamic state without actually changing it.
Signed-off-by: Rhys Perry
---
src/amd/vulkan/radv_cmd_buffer.c | 92 ++--
1 file changed, 76 insertions(+), 16 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
Iago Toral Quiroga writes:
> v2: adapted to work with the new regioning lowering pass
>
> Reviewed-by: Topi Pohjolainen (v1)
> ---
> src/intel/compiler/brw_ir_fs.h | 33 ++---
> 1 file changed, 26 insertions(+), 7 deletions(-)
>
> diff --git
On Mon, Jan 14, 2019 at 4:36 AM Daniel Stone wrote:
>
> Hi,
>
> On Fri, 11 Jan 2019 at 17:05, Jason Ekstrand wrote:
> > 5. There's no way with gitlab for Reviewed-by tags to get automatically
> > applied as part of the merging process. This makes merging a bit more
> > manual than it needs
On Tue, Jan 15, 2019 at 8:58 AM Jason Ekstrand wrote:
>
> Previously, we only applied the fix to shaders with a dispatch mode of
> SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16
> instructions. If you have a SIMD8 instruction in a SIMD16 shader,
> neither would trigger
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_texture.c | 117 ++
1 file changed, 53 insertions(+), 64 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_texture.c
b/src/gallium/drivers/radeonsi/si_texture.c
index c169d4e443d..a56674b6000 100644
---
On Tue, Jan 15, 2019 at 10:59 PM Rhys Perry wrote:
>
> DXVK often sets dynamic state without actually changing it.
>
> Signed-off-by: Rhys Perry
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 92 ++--
> 1 file changed, 76 insertions(+), 16 deletions(-)
>
> diff --git
I misread some code and forgot to remove it.
It was always unrelated to this patch.
On Wed, 16 Jan 2019 at 00:22, Bas Nieuwenhuizen
wrote:
>
> On Tue, Jan 15, 2019 at 10:59 PM Rhys Perry wrote:
> >
> > DXVK often sets dynamic state without actually changing it.
> >
> > Signed-off-by: Rhys
On Sat, Jan 12, 2019 at 7:56 PM Jason Ekstrand wrote:
>
> For a long time, we based exec sizes on destination register widths.
> We've not been doing that since 1ca3a9442760b6f7 but a few remnants
> accidentally remained.
> ---
> src/intel/compiler/brw_eu_emit.c | 3 ---
> 1 file changed, 3
On Mon, Oct 29, 2018 at 11:16 AM Lionel Landwerlin
wrote:
>
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tools/intel_sanitize_gpu.in | 55 ++-
> 1 file changed, 54 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/tools/intel_sanitize_gpu.in
>
On Mon, Jan 14, 2019 at 5:12 PM Rhys Perry wrote:
>
> I did and found small improvements in Rise of the Tomb Raider. I
> measured framerates ~104.3% that of without the changes for the
> Geothermal Valley scene, ~101.2% for Spine of the Mountain and ~102.3%
> for Prophets Tomb.
My main question
On January 15, 2019 17:55:31 Matt Turner wrote:
On Tue, Jan 15, 2019 at 8:58 AM Jason Ekstrand wrote:
Previously, we only applied the fix to shaders with a dispatch mode of
SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16
instructions. If you have a SIMD8 instruction
I did a before/after comparison during development with multiple runs
but only 1 before and after run to produce the numbers I sent. They
seemed to match up well enough to the runs during development, so I
wasn't too concerned.
IIRC, the two runs were with a Vega 64 at 1080p with "High" settings.
https://bugs.freedesktop.org/show_bug.cgi?id=109258
--- Comment #3 from n3rdopolis ---
Haha. after all that manual bisecting too :) However, I feel something was
still broken, because I found a built Mesa I had from a January 2018 commit in
master, that didn't work...
To verify, I tried to see
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_texture.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_texture.c
b/src/gallium/drivers/radeonsi/si_texture.c
index a56674b6000..585f58c1e38 100644
---
Adam Jackson wrote:
> > On Fri, 2019-01-11 at 15:01 +, Emil Velikov wrote:
> >
> > > > @@ -460,6 +464,14 @@ driGetConfigAttribIndex(const __DRIconfig
> > *config,
> > > > else
> > > > *value = 0;
> > > > break;
> > > > +case __DRI_ATTRIB_RED_MASK_HI:
> > > > +
Emil Velikov wrote:
> Hi Kevin,
>
> Thanks for that massive undertaking in addressing this.
Sure thing!
> On 2019/01/04, Kevin Strasser wrote:
> > The dri core api was written with the assumption that all attribute
> > values would fit into 32 bits. This limitation means the config
> > handlers
1 - 100 of 109 matches
Mail list logo
