Re: Emulation problems with status register#1
At 05:15 PM 9/2/99 +0200, you wrote: To reset a interrupt from a horizontal line interrupt (reg #19), I used to set the interupt enable bit to zero and then back on again. Turning the bit off also dropped the interrupt. This was better because I could now make the interupt line drop in lesser time, I just had two write twice to a register. With the official read methode I had to write a register, wait, read a status register and then put #15 back to zero (as assumed by the standard interrupt handler) Nice trick! I didn't know it. The fact that this trick works also tells something about the internal workings of the VDP. I expect Frits can use this info for perfecting NLMSX. Bye, Maarten MSX Mailinglist. To unsubscribe, send an email to [EMAIL PROTECTED] and put in the body (not subject) "unsubscribe msx [EMAIL PROTECTED]" (without the quotes :-) Problems? contact [EMAIL PROTECTED] (www.stack.nl/~wiebe/mailinglist/)
Re: Emulation problems with status register#1
Laurens Holst wrote: This still doesn't answer the question whether interrupt cancelling is possible. Scenario: 1. DI 2. enable interrupts at VDP level 3. wait for some time, long enough for an interrupt to occur 4. disable interrupts at VDP level 5. EI 6. test: does an interrupt occur? The interrupt does not occur. The VDP simply copies the value of the FH bit to the interrupt-pin of the slot. This pin remains set (and thus generating an interrupt, unless they are disabled using DI) until the corresponding statusregister is read. Since both are different statusregisters, they can overlap eachother. ~Grauw Hello, Just working my way trough all the mail I got during my vacation. Interesting to know and never told in this entire discussion is the following trick (One I used a lot in the beginning) To reset a interrupt from a horizontal line interrupt (reg #19), I used to set the interupt enable bit to zero and then back on again. Turning the bit off also dropped the interrupt. This was better because I could now make the interupt line drop in lesser time, I just had two write twice to a register. With the official read methode I had to write a register, wait, read a status register and then put #15 back to zero (as assumed by the standard interrupt handler) David Heremans -- "One difference between SuSE and Red Hat is that the former operates in a country where people don't sue each other over coffee being too hot." Linus Torvalds MSX Mailinglist. To unsubscribe, send an email to [EMAIL PROTECTED] and put in the body (not subject) "unsubscribe msx [EMAIL PROTECTED]" (without the quotes :-) Problems? contact [EMAIL PROTECTED] (www.stack.nl/~wiebe/mailinglist/)
Re: Emulation problems with status register#1
This still doesn't answer the question whether interrupt cancelling is possible. Scenario: 1. DI 2. enable interrupts at VDP level 3. wait for some time, long enough for an interrupt to occur 4. disable interrupts at VDP level 5. EI 6. test: does an interrupt occur? The interrupt does not occur. The VDP simply copies the value of the FH bit to the interrupt-pin of the slot. This pin remains set (and thus generating an interrupt, unless they are disabled using DI) until the corresponding statusregister is read. Since both are different statusregisters, they can overlap eachother. ~Grauw -- email me: [EMAIL PROTECTED] or ICQ: 10196372 visit the Datax homepage at http://datax.cjb.net/ MSX fair Bussum / MSX Marathon homepage: http://msxfair.cjb.net/ MSX Mailinglist. To unsubscribe, send an email to [EMAIL PROTECTED] and put in the body (not subject) "unsubscribe msx [EMAIL PROTECTED]" (without the quotes :-) Problems? contact [EMAIL PROTECTED] (www.stack.nl/~wiebe/mailinglist/)
