Thanks again. So with two level shifters available and two open pins on the
1284P, which two of three lines, CLK, DATA, and LE, would be best to
separate? From your description, are you saying that CLK and DATA are the
two best separated?
On Sunday, October 18, 2015 at 12:30:45 PM UTC-4,
There's no need to separate *both* CLK and DATA. If you have separate data
lines and CLK everything at the same time, you've basically shortened the
length of the serial data chain, and you're loading them in parallel. This
will give you the fastest load-time.
On the other hand, if you split
So to be clear, if you split the CLK lines into CLKA and CLKB, the serial
data will go into the first HV5530. The first, third, fifth, etc HV5530's
would use CLKA. The second, fourth, etc HV5530's would use CLKB. The
DATA_OUT of the first HV5530 goes to the DATA_IN of the second HV5530, etc.
Thank you. I'll do it that way.
On Saturday, October 17, 2015 at 9:26:23 AM UTC-4, Mitch wrote:
>
> Hi All,
>
> The seven digit, IN-18 board is on order so I'm on to the next project, a
> fifteen digit Union Square Metronome type clock similar to Jarek's clock
> here:
>
If you are going to use FPGA, then why not let it design itself?
http://www.damninteresting.com/on-the-origin-of-circuits/
John K.
[there are more learned refs]
- Original Message -
From: gregebert
To: neonixie-l
Sent: Monday, October 19, 2015 3:00 AM
Subject: [neonixie-l] Re
David - Four are connected serially, updating 120 bits of 128 available.
That group is updated every second. The fifth chip stands alone and only 30
of 32 bits needs to be updated every 10ms.
Greg - This is a much simpler application. From what I understand, which is
not too much, it appears
Separating CLK or DATA for individual HV5530's will, as you said,
accomplish the same result. Separating LE is another option but you have to
be careful to keep-track of what has been shifted. It's not obvious from
the diagrams I posted, but I actually have 4 serial data signals on the
