Re: [neonixie-l] Re: Loop compensation and Bode plots?

2017-08-16 Thread Paul Andrews
No I hadn't seen that. It looks very useful. Thanks. 

> On Aug 16, 2017, at 11:24 AM, Nick  wrote:
> 
>> On Wednesday, 16 August 2017 01:48:18 UTC+4, Paul Andrews wrote:
>> BTW the zipped model works fne.
> 
> That's good - have you seen this article: 
> http://www.linear.com/solutions/5788 ?
> 
> Nick
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Re: [neonixie-l] Re: Loop compensation and Bode plots?

2017-08-12 Thread Paul Andrews
Hi Nick,

I will check when I get back to my computer.

> On Aug 12, 2017, at 11:15 PM, Nick  wrote:
> 
> In LTspice, if you go to Tools -> Control Panel, the select the Netlist 
> Options tab, in the Style/Convention area click the Convert ... tickbox - 
> that will make your capacitor values look ok - modern versions of LTspice 
> convert "u" in component values to the Greek letter mu (i.e., "micro")
> 
> Where did your Wurth transformer model come from? The only ones I could find 
> are from http://katalog.we-online.de/de/pbs/WE-FLEX#vs_ct:1 and don't include 
> the model you are using - which specific transformer is this?
> 
> Nick
> 
>> On Saturday, 12 August 2017 20:16:53 UTC+4, Paul Andrews wrote:
>> I tried running this version, but the simulation window doesn't open and I 
>> can't place probes on the circuit. I looked in the .asc file and fixed up 
>> the path to the wurth model, but it made no difference. I have no idea how 
>> to get that window back.
>> 
>> Also, the values of caps that were uF became odd characters. What version of 
>> LTSpice are you using on what OS?
>> 
>>> On Saturday, August 12, 2017 at 10:50:23 AM UTC-4, Nick wrote:
>>> Hi - Your LM3478 symbol pinout was wrong - you've got pins 5 - 8 flipped...
>>> 
>>> Its a slow deck for sure - I'll have a play with in in the next couple of 
>>> days.
>>> 
>>> Also attached slightly reformatted schematic to compensate for change in 
>>> the ASY file.
>>> 
>>> Annoying that the PSPICE model from TI has a different pin order to the IC 
>>> itself...
>>> 
>>> Nick
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Re: [neonixie-l] Re: Loop compensation and Bode plots?

2017-08-12 Thread Nick
That doesn't sound right - If you post your stack I'm sure one of us with 
more LTspice experience may be able to help. The LTspice Yahoo! group is 
also an excellent resource for advice - the LTspice developers hang out 
there and that's where the real knowledge is.

Nick

On Friday, 11 August 2017 16:14:47 UTC+4, Paul Andrews wrote:
>
> Thanks. I will check.
>
> I wish I had a faster computer. It is taking about 15 mins to do a 8ms 
> simulation ATM. I wonder if there are any online versions? Hmm. I wonder if 
> I could use my own online servers or Amazon cloud? I've never used my own 
> servers for anything other web hosting/svn etc. 
>

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Re: [neonixie-l] Re: Loop compensation and Bode plots?

2017-08-11 Thread gregebert
You really only need to run until the transients have settled-out.  The 
design I'm doing now runs at about 50kHz, and it takes 1-2 minutes to reach 
15msec. Most of the transient activity ends around 3-4msec, but the runtime 
isn't a nuisance yet.

Is the simulation running really slow in 1 particular spot ? I see that 
happen a lot during the initial design, and it's usually caused by 
increased computations to handle discontinuities. Changing pulses from 
near-zero rise/fall times to a realistic value, and adding some parasitic 
series resistance can help. Also, having additional DC-paths around caps 
and inductors helps; 100Meg resistors in a few spots can work wonders. 
There is a gmindc parameter that effectively puts resistors to ground 
everywhere to help with convergence, but I dont use it.


I believe this converter runs up to 1Mhz so if you are running that fast 
you may not need 8msec. If you do run that fast,  be careful with component 
selection, as many power inductors undergo self-resonance in the Mhz region 
(see datasheet), and skin-effect will increase the resistance. And then 
there's capacitors; aluminum electrolytics are too inductive at that 
frequency so ceramic is a better option.

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Re: [neonixie-l] Re: Loop compensation and Bode plots?

2017-08-11 Thread Paul Andrews
Thanks. I will check.

I wish I had a faster computer. It is taking about 15 mins to do a 8ms 
simulation ATM. I wonder if there are any online versions? Hmm. I wonder if I 
could use my own online servers or Amazon cloud? I've never used my own servers 
for anything other web hosting/svn etc. 

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Re: [neonixie-l] Re: Loop compensation and Bode plots?

2017-08-10 Thread gregebert
Make sure to look carefully at corner cases, like max-load at 
min-input-voltage (typically causes max inductor current).

>From the app-note, I see there is a discrete NMOS transistor, and 
thankfully a single inductor (not transformer), so your modeling is easier. 
Be very careful about the voltage spikes across the NMOS device; you must 
never allow Vds to exceed the  max-spec value, which often derates at 
higher temperature.

There are a lot of devices with low Rds(on); when I say low, I'm talking 
below 50milliohms, but they often have higher gate-source capacitance and 
require higher gate-drive voltage. This will put some constraints on the 
gate-driver. So, tradeoffs need to be made. I'd suggest picking a device 
with a low-enough Rds(on) such that it's power-dissipation does not cause 
significant heat-rise with a small heat-sink.

Using the tiny PCB-mounted devices is tricky for thermal reasons; I prefer 
TO-220 packages or similar.

There's a lot of really good info in the TI datasheet, appnote, and the 
IRF7807 datasheet. Once you read thru all of that you will have a good 
understanding. Just be aware the IRF7807 wont give you nixie-level voltages 
as t's rated for 30V max.

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Re: [neonixie-l] Re: Loop compensation and Bode plots?

2017-08-10 Thread Nick
Varying load is easy - parameterise the load and use the .step param [name] 
list val1,val2... command.

Nick

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Re: [neonixie-l] Re: Loop compensation and Bode plots?

2017-08-10 Thread Paul Andrews
Yes. I've got 3 different linear tech devices on my list. The LM3478 actually 
has an LTSpice model and the Wurth flex transformer I'm using does too (from TI 
and Wurth respectively). The circuit I put together simulates just fine, so I'm 
just trying to increase my level of confidence in it at this point (plus I 
don't like not being able to do something!). What I haven't done is simulate it 
with a varying load, yet (although, lets face it, the load isn't going to vary 
much over a short timescale). I also need to check the current going through 
the transformer against the specs.

> On Aug 10, 2017, at 7:01 PM, gregebert  wrote:
> 
> Have you considered using devices from Linear Technology (now Analog Devices) 
> ? You can run extensive simulations with LTSpice, using accurate models for 
> their ICs (I assume they are encrypted spice models).
> 
> I dont do bode plots for any of my designs; instead I rely heavily on spice 
> simulations and run a lot of corner cases, varying component values, etc.  As 
> your design improves, you will see that overall behavior is not sensitive to 
> component values. For example, I'm working on a DCDC converter and I had 
> horrible ringing; changing a capacitor value 2X had a major impact on the 
> ringing. After some other fiddling, even a 10X change in capacitance no 
> longer increases the ringing appreciably.
> 
> One thing to really watch-out for is inductor current; make sure you stay 
> well-clear of the saturation current (Isat) spec for the device. If you are 
> using a transformer (coupled inductors) , make sure your circuit works nicely 
> with non-ideal conditions such as finite DC resistance (usually in the 
> datasheet), and non-ideal coupling (K < 1). All kinds of bugs come crawling 
> out of the woods; much easier to deal with them with a simulator than a real 
> circuit on your workbench.
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