This series adds support for Socionext AVE ethernet controller implemented
on UniPhier SoCs. This driver supports RGMII/RMII modes.
v4: https://www.spinics.net/lists/netdev/msg469294.html
The PHY patch included in v1 has already separated in:
http://www.spinics.net/lists/netdev/msg454595.html
The UniPhier platform from Socionext provides the AVE ethernet
controller that includes MAC and MDIO bus supporting RGMII/RMII
modes. The controller is named AVE.
Signed-off-by: Kunihiko Hayashi
Signed-off-by: Jassi Brar
Reviewed-by:
DT bindings for the AVE ethernet controller found on Socionext's
UniPhier platforms.
Signed-off-by: Kunihiko Hayashi
Signed-off-by: Jassi Brar
Acked-by: Rob Herring
---
.../bindings/net/socionext,uniphier-ave4.txt
e1000e_check_for_copper_link() and e1000_check_for_copper_link_ich8lan()
are the two functions that may be assigned to mac.ops.check_for_link when
phy.media_type == e1000_media_type_copper. Commit 19110cfbb34d ("e1000e:
Separate signaling for link check/link up") changed the meaning of the
return
On Mon, Dec 04, 2017 at 11:34:48AM +0100, Geert Uytterhoeven wrote:
> Hi David, Andrew, Florian, Simon, Magnus,
>
> This patch series adds optional PHY reset support to phylib.
>
> The first two patches are destined for David's net-next tree. They add
> core PHY reset code, and update a
On 2017/12/11 13:38, Al Viro wrote:
> On Mon, Dec 11, 2017 at 05:05:20AM +, Al Viro wrote:
>
>> What for? Sure, this variant will work, but why bother with
>> a = le32_to_cpu(b);
>> (cpu_to_le32(a) & ) |
>> and how is that better than
>> (b & ...) | ...
>>
>> IDGI...
On Sun, Dec 10, 2017 at 9:02 AM, Alexander Duyck
wrote:
> On Sat, Dec 9, 2017 at 10:40 PM, Michael Chan
> wrote:
>> It is possible that if you have incoming packets 1, 2, 3, 4, 5 for a
>> TCP connection, HW_GRO can aggregate packets 1, 2, 3,
On 2017/12/11 13:05, Al Viro wrote:
> On Mon, Dec 11, 2017 at 12:33:42PM +0800, Jie Deng wrote:
>> Hi AI Viro,
>>> @@ -125,8 +125,8 @@
>>> typeof(len) _len = (len); \
>>> typeof(val) _val = (val); \
>>> _val =
On Mon, Dec 11, 2017 at 05:05:20AM +, Al Viro wrote:
> What for? Sure, this variant will work, but why bother with
> a = le32_to_cpu(b);
> (cpu_to_le32(a) & ) |
> and how is that better than
> (b & ...) | ...
>
> IDGI... Mind you, I'm not sure if there is any
On Mon, Dec 11, 2017 at 12:33:42PM +0800, Jie Deng wrote:
> Hi AI Viro,
> > @@ -125,8 +125,8 @@
> > typeof(len) _len = (len); \
> > typeof(val) _val = (val); \
> > _val = (_val << _pos) & GENMASK(_pos + _len -
> From: David Miller [mailto:da...@davemloft.net]
>
> From: Prashant Bhole
> Date: Fri, 8 Dec 2017 09:52:50 +0900
>
> > Return value is now checked with IS_ERROR_OR_NULL because
> > debugfs_create_dir doesn't return error value. It either returns NULL
> > or a
Hi AI Viro,
On 2017/12/10 12:53, Al Viro wrote:
> In xlgmac_dev_xmit():
>
> /* Mark it as a CONTEXT descriptor */
> dma_desc->desc3 = XLGMAC_SET_REG_BITS_LE(
> dma_desc->desc3,
>
From: Pravin Shedge
Date: Sun, 10 Dec 2017 23:30:21 +0530
> On Thu, Dec 7, 2017 at 2:28 AM, David Miller wrote:
>> From: Pravin Shedge
>> Date: Wed, 6 Dec 2017 23:02:58 +0530
>>
>>> These duplicate includes
On Sat, Dec 09, 2017 at 04:07:15PM +0100, Vincent Legoll wrote:
> No need to get into the submenu to disable all PTP-related
> config entries.
>
> This makes it easier to disable all PTP config options
> without entering the submenu. It will also enable one
> to see that en/dis-abled state from
On Sat, Dec 9, 2017 at 10:49 PM, Michael Chan wrote:
> On Sat, Dec 9, 2017 at 2:37 PM, Alexander Duyck
> wrote:
>> On Sat, Dec 9, 2017 at 1:40 PM, Michael Chan
>> wrote:
>>> On Sat, Dec 9, 2017 at 10:56 AM,
On 12/10/2017 06:08 PM, Linus Torvalds wrote:
> Another week, another rc.
>
um (uml) won't build on i386 or x86_64:
CC init/main.o
In file included from ../include/linux/perf_event.h:18:0,
from ../include/linux/trace_events.h:10,
from
On 12/10/2017 03:20 PM, Sergei Shtylyov wrote:
[...]
The reset looks good...
Sorry, I meant to type "rest". :-)
MBR, Sergei
On 12/04/2017 05:17 PM, Thomas Petazzoni wrote:
This commit adds the sh_eth_cpu_data structure that describes the
SH7786 variant of the IP.
Signed-off-by: Thomas Petazzoni
---
drivers/net/ethernet/renesas/sh_eth.c | 25 +
1 file
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_main.o
In file included from ./include/net/vxlan.h:6:0,
from drivers/net/ethernet/intel/ixgbe/ixgbe_main.c:60:
./include/net/dst_metadata.h: In function ‘skb_vpls_info’:
./include/net/dst_metadata.h:36:9: error: implicit declaration
Hello!
On 12/08/2017 06:40 PM, Thomas Petazzoni wrote:
This commit adds the sh_eth_cpu_data structure that describes the
SH7786 variant of the IP.
The manual seems to be unavailable, so I have to trust you. :-)
Yes, sadly. However, if you tell me what to double check, I'd be happy
to
guehdr struct is used to build or parse gue packets, which
are always in big endian. It's better to define all guehdr
members as __beXX types.
Also, in validate_gue_flags it's not good to use a __be32
variable for both Standard flags(__be16) and Private flags
(__be32), and pass it to other
Hi!
In v4.15-rc2+, network manager can not see my ethernet card, and
manual attempts to ifconfig it up did not really help, either.
Card is:
02:00.0 Ethernet controller: Intel Corporation 82573L Gigabit Ethernet
Controller
Dmesg says:
dmesg | grep eth
[0.648931] e1000e :02:00.0
22 matches
Mail list logo