On 07/05/2018 11:22, Jiong Wang wrote:
execution time
===
test_l4lb_noinline:
existing check_subprog/check_cfg: ~55000 ns
new infrastructure: ~135000 ns
test_xdp_noinline:
existing check_subprog/check_cfg: ~52000 ns
new infrastructure: ~12 ns
Intel(R) Xeon(R) CPU E5-2630 v4
As we have detected loop and unreachable insns based on domination
information and call graph, there is no need of check_cfg.
This patch removes check_cfg and it's associated push_insn.
state prune heuristic marking as moved to check_subprog.
Signed-off-by: Jiong Wang <jiong.w...@netronome.
is built but not tested.
Signed-off-by: Jiong Wang <jiong.w...@netronome.com>
---
include/linux/bpf_verifier.h | 3 +
kernel/bpf/cfg.c | 386 ++-
kernel/bpf/cfg.h | 3 +-
kernel/bpf/verifier.c| 5 +-
4 files change
This patch add edges between basic blocks. Both edges for predecessors and
successors are added.
Signed-off-by: Jiong Wang <jiong.w...@netronome.com>
---
kernel/bpf/cfg.c | 129 +-
kernel/bpf/cfg.h | 1 +
kernel/bpf/verifier.c
t;From benchmarks like test_xdp_noinline, this patch reduce peek memory usage
of new cfg infrastructure by more than 50%.
Signed-off-by: Jiong Wang <jiong.w...@netronome.com>
---
include/linux/bpf_verifier.h | 7 +-
kernel/bpf/cfg.c | 503 -
Do unreachable basic blocks detection as a side-product of the dfs walk
when building domination information.
Signed-off-by: Jiong Wang <jiong.w...@netronome.com>
---
kernel/bpf/cfg.c | 31 ++-
kernel/bpf/cfg.h | 3 ++-
kernel/bpf/verifier.c | 3
If one bb is dominating its predecessor, then there is loop.
Signed-off-by: Jiong Wang <jiong.w...@netronome.com>
---
kernel/bpf/cfg.c | 22 ++
kernel/bpf/cfg.h | 1 +
kernel/bpf/verifier.c | 8
3 files changed, 31 insertions(+)
diff --git a/kern
of estimated size (aligned to 2K). The pool
will grow later if space are not enough.
- There is no support on returning memory back to the pool.
Signed-off-by: Jiong Wang <jiong.w...@netronome.com>
---
kernel/bpf/cfg.c | 164 +-
kern
lay the ground for further
static analysis inside eBPF verifier, for example bounded loop detection,
path-sensitive data-flow analysis etc.
Jiong Wang (10):
bpf: cfg: partition basic blocks for each subprog
bpf: cfg: add edges between basic blocks to form CFG
bpf: cfg: build domination tree
mmediately follows branch insn start a BB.
Insn immediately follows exit and within subprog start a BB.
BBs for each subprog are organized as a list in ascending head.
Two special BBs, entry and exit are added as well.
Signed-off-by: Jiong Wang <jiong.w...@netronome.com>
---
include/linux/bpf
This patch centre find_subprog and add_subprog to cfg.c.
Signed-off-by: Jiong Wang <jiong.w...@netronome.com>
---
kernel/bpf/cfg.c | 41 +
kernel/bpf/cfg.h | 2 ++
kernel/bpf/verifier.c | 42 --
3
On 10/05/2018 19:17, John Fastabend wrote:
On 05/07/2018 03:22 AM, Jiong Wang wrote:
If one bb is dominating its predecessor, then there is loop.
Signed-off-by: Jiong Wang <jiong.w...@netronome.com>
---
kernel/bpf/cfg.c | 22 ++
kernel/bpf/cfg.h | 1 +
It is better to centre all subprog information fields into one structure.
This structure could later serve as function node in call graph.
Signed-off-by: Jiong Wang <jiong.w...@netronome.com>
---
include/linux/bpf_verifier.h | 9 ---
kernel/bpf/verifier.c
ter
to unify them, and register all progs detected into env->subprog_starts.
This could also help simplifying some code logic.
Signed-off-by: Jiong Wang <jiong.w...@netronome.com>
---
include/linux/bpf_verifier.h | 2 +-
kernel/bpf/verifier.c| 57 ---
marker in subprog_info array to tell the end of
it.
We could resolve this issue by introducing a faked "ending" subprog.
The special "ending" subprog is with "insn_cnt" as start offset, so it is
serving as the end mark whenever we iterate over all subprogs.
- fixed adjust_subprog_starts to also update fake "exit" subprog start.
- for John's suggestion on renaming subprog to prog, I could work on
a follow-up patch if it is recognized as worth the change.
Jiong Wang (3):
bpf: unify main prog and subprog
bpf: centre subprog informatio
It is better to centre all subprog information fields into one structure.
This structure could later serve as function node in call graph.
Signed-off-by: Jiong Wang <jiong.w...@netronome.com>
---
include/linux/bpf_verifier.h | 9 ---
kernel/bpf/verifier.c
On 02/05/2018 18:24, John Fastabend wrote:
On 05/02/2018 09:59 AM, Jiong Wang wrote:
On 01/05/2018 23:22, Alexei Starovoitov wrote:
...
[ 27.784931] ? bpf_int_jit_compile+0x7ac/0xab0
[ 27.785475] bpf_int_jit_compile+0x2b6/0xab0
[ 27.786001] ? do_jit+0x6020/0x6020
[ 27.786428
On 01/05/2018 23:22, Alexei Starovoitov wrote:
...
[ 27.784931] ? bpf_int_jit_compile+0x7ac/0xab0
[ 27.785475] bpf_int_jit_compile+0x2b6/0xab0
[ 27.786001] ? do_jit+0x6020/0x6020
[ 27.786428] ? kasan_kmalloc+0xa0/0xd0
[ 27.786885] bpf_check+0x2c05/0x4c40
[ 27.787346] ?
ter
to unify them, and register all progs detected into env->subprog_starts.
This could also help simplifying some code logic.
Signed-off-by: Jiong Wang <jiong.w...@netronome.com>
---
include/linux/bpf_verifier.h | 2 +-
kernel/bpf/verifier.c| 57 ---
nd = insn_cnt;
else
subprog_end = env->subprog_info[cur_subprog + 1].start;
into:
subprog_end = env->subprog_info[cur_subprog + 1].start;
There is no functional change by this patch set.
No bpf selftest regression found after this patch set.
Jiong Wang (3):
marker in subprog_info array to tell the end of
it.
We could resolve this issue by introducing a faked "ending" subprog.
The special "ending" subprog is with "insn_cnt" as start offset, so it is
serving as the end mark whenever we iterate over all subprogs.
On Fri, 12 Jan 2018 12:31:15 +0100, Daniel Borkmann wrote:
What kind of string would sit in jited_arch_name for nfp?
The name is purely to let libfd know which bfd backend to choose for the
disassembler.
Given you know
the {ifindex, netns_dev, netns_ino} 3‑tuple, isn't it possible to infer
On 13/02/2018 05:09, John Fastabend wrote:
To find these we do the following
1.a: Build the CFG of all the instructions so we can walk around the
program easily.
1.b: Find the basic blocks and build the basic block CFG. After this
with a few helper calls we can move
On 26/06/2018 21:59, Jakub Kicinski wrote:
On Sun, 24 Jun 2018 20:54:21 -0700, Jakub Kicinski wrote:
+* NOTE: because we are using "reciprocal_value_adv" which doesn't
+* support dividend with MSB set, so we need to JIT separate NFP
+* sequence to handle such case. It
On 06/04/2018 18:14, Edward Cree wrote:
Since that algorithm selects
+ * nodes in the order of the sorted output, we can do our processing in the
loop
+ * that does the tsort, rather than storing the sorted list and then having a
+ * second loop to iterate over it and compute the
On 06/04/2018 18:11, Edward Cree wrote:
By storing subprog boundaries as a subprogno mark on each insn, rather than
a start (and implicit end) for each subprog, the code handling subprogs can
in various places be made simpler, more explicit, and more efficient (i.e.
better asymptotic
On 03/04/2018 02:08, Alexei Starovoitov wrote:
Combining subprog pass with do_check is going into opposite direction
of this long term work. Divide and conquer. Combining more things into
do_check is the opposite of this programming principle.
Agree. And for the redundant insn traversal issue
On Tue, Jun 26, 2018 at 7:21 AM, Song Liu wrote:
> On Sun, Jun 24, 2018 at 8:54 PM, Jakub Kicinski
> wrote:
>> From: Jiong Wang
>> +
>> +struct reciprocal_value_adv reciprocal_value_adv(u32 d, u8 prec)
>> +{
>> + struct reciprocal_value
"max_pkt_offset".
Jiong Wang (2):
bpf: let verifier to calculate and record max_pkt_offset
nfp: bpf: relax prog rejection through max_pkt_offset
drivers/net/ethernet/netronome/nfp/bpf/offload.c | 9 +
include/linux/bpf.h | 1 +
kernel/bpf/
) offset,
and kept it in max_pkt_offset inside prog auxiliar information. This patch
relax prog rejection based on max_pkt_offset.
Reviewed-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
drivers/net/ethernet/netronome/nfp/bpf/offload.c | 9 +
1 file changed, 5 insertions(+), 4 deletions
to MAX_PACKET_OFF for such
case.
Reviewed-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
include/linux/bpf.h | 1 +
kernel/bpf/verifier.c | 12
2 files changed, 13 insertions(+)
diff --git a/include/linux/bpf.h b/include/linux/bpf.h
index 33014ae..b6a296e 100644
--- a/include
On 03/10/2018 16:59, Alexei Starovoitov wrote:
On Wed, Oct 03, 2018 at 04:36:31PM +0100, Jiong Wang wrote:
Now this hasn't happened. I am still debugging the root cause, but kind of
feel
"64-bit" attribute propagation is the issue, it seems to me it can't be
nicely
On 28/09/2018 14:36, Edward Cree wrote:
> On 26/09/18 23:16, Jiong Wang wrote:
>> On 22/08/2018 20:00, Edward Cree wrote:
>>> In the future this idea may be extended to form use-def chains.
>>
>> 1. instruction level use->def chain
>>
>> - new u
On 03/10/2018 17:53, Jiong Wang wrote:
On 03/10/2018 16:59, Alexei Starovoitov wrote:
On Wed, Oct 03, 2018 at 04:36:31PM +0100, Jiong Wang wrote:
Now this hasn't happened. I am still debugging the root cause, but kind of
feel
"64-bit" attribute propagation is the issue, it s
On 22/08/2018 20:00, Edward Cree wrote:
The first patch is a simplification of register liveness tracking by using
a separate parentage chain for each register and stack slot, thus avoiding
the need for logic to handle callee-saved registers when applying read
marks. In the future this idea
.
Fixes: f31318fdf324 ("MIPS: uasm: Add srlv uasm instruction")
CC: Markos Chandras
CC: Paul Burton
Acked-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
arch/mips/include/uapi/asm/inst.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/uapi/asm/inst
This patch implements code-gen for BPF_ALU | BPF_ARSH | BPF_*.
Cc: Naveen N. Rao
Cc: Sandipan Das
Signed-off-by: Jiong Wang
---
arch/powerpc/include/asm/ppc-opcode.h | 2 ++
arch/powerpc/net/bpf_jit.h| 4
arch/powerpc/net/bpf_jit_comp64.c | 6 ++
3 files changed, 12
Jitting of BPF_K is supported already, but not BPF_X. This patch complete
the support for the latter on both MIPS and microMIPS.
Cc: Paul Burton
Cc: linux-m...@vger.kernel.org
Signed-off-by: Jiong Wang
---
arch/mips/include/asm/uasm.h | 1 +
arch/mips/include/uapi/asm/inst.h | 1 +
arch
BPF_X support needs indirect shift mode, please see code comments for
details.
Reviewed-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
drivers/net/ethernet/netronome/nfp/bpf/jit.c | 45
1 file changed, 45 insertions(+)
diff --git a/drivers/net/ethernet/netronome
This patch implements interpreting BPF_ALU | BPF_ARSH. Do arithmetic right
shift on low 32-bit sub-register, and zero the high 32 bits.
Reviewed-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
kernel/bpf/core.c | 52 ++--
1 file changed, 30
d-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
tools/testing/selftests/bpf/test_verifier.c | 29 +
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/tools/testing/selftests/bpf/test_verifier.c
b/tools/testing/selftests/bpf/test_verifier.c
index 18d
This patch implements code-gen for BPF_ALU | BPF_ARSH | BPF_*.
Cc: Martin Schwidefsky
Cc: Heiko Carstens
Signed-off-by: Jiong Wang
---
arch/s390/net/bpf_jit_comp.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/s390/net/bpf_jit_comp.c b/arch/s390/net/bpf_jit_comp.c
on mips-fixes branch at the moment.
Thanks.
Jiong Wang (7):
bpf: interpreter support BPF_ALU | BPF_ARSH
mips: bpf: implement jitting of BPF_ALU | BPF_ARSH | BPF_X
ppc: bpf: implement jitting of BPF_ALU | BPF_ARSH | BPF_*
s390: bpf: implement jitting of BPF_ALU | BPF_ARSH | BPF_*
nfp: bpf: implemen
This patch remove the rejection on BPF_ALU | BPF_ARSH as we have supported
them on interpreter and all JIT back-ends
Reviewed-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
kernel/bpf/verifier.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/kernel/bpf/verifier.c b/kernel/bpf
On 05/12/2018 00:02, Paul Burton wrote:
Hi Jiong,
On Tue, Dec 04, 2018 at 03:55:16PM -0500, Jiong Wang wrote:
Jitting of BPF_K is supported already, but not BPF_X. This patch complete
the support for the latter on both MIPS and microMIPS.
Cc: Paul Burton
Cc: linux-m...@vger.kernel.org
Signed
ould generate several processed insn info, above
number is sum of them.
Reviewed-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
kernel/bpf/verifier.c | 32 ++---
tools/testing/selftests/bpf/test_verifier.c | 13
2 files changed, 29 insert
Sandipan Das writes:
> Hi Jiong,
>
> On 05/12/18 2:25 AM, Jiong Wang wrote:
>> This patch implements code-gen for BPF_ALU | BPF_ARSH | BPF_*.
>>
>> Cc: Naveen N. Rao
>> Cc: Sandipan Das
>> Signed-off-by: Jiong Wang
>> ---
> [...]
>> dif
On 05/12/2018 14:52, Edward Cree wrote:
On 05/12/18 09:46, Jiong Wang wrote:
There is NO processed instruction number regression, either with or without
-mattr=+alu32.
Cilium bpf
===
bpf_lb-DLB_L3.o 2110/21101730/1733
That looks like a regression of 3 insns in the 32-bit case
32_op"),
which is on mips-fixes branch at the moment.
Thanks.
Jiong Wang (7):
mips: bpf: implement jitting of BPF_ALU | BPF_ARSH | BPF_X
ppc: bpf: implement jitting of BPF_ALU | BPF_ARSH | BPF_*
s390: bpf: implement jitting of BPF_ALU | BPF_ARSH | BPF_*
nfp: bpf: implement jitting o
This patch implements code-gen for BPF_ALU | BPF_ARSH | BPF_*.
Cc: Naveen N. Rao
Cc: Sandipan Das
Signed-off-by: Jiong Wang
---
arch/powerpc/include/asm/ppc-opcode.h | 2 ++
arch/powerpc/net/bpf_jit.h| 4
arch/powerpc/net/bpf_jit_comp64.c | 6 ++
3 files changed, 12
This patch implements interpreting BPF_ALU | BPF_ARSH. Do arithmetic right
shift on low 32-bit sub-register, and zero the high 32 bits.
Reviewed-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
kernel/bpf/core.c | 52 ++--
1 file changed, 30
Jitting of BPF_K is supported already, but not BPF_X. This patch complete
the support for the latter on both MIPS and microMIPS.
Cc: Paul Burton
Cc: linux-m...@vger.kernel.org
Signed-off-by: Jiong Wang
---
arch/mips/include/asm/uasm.h | 1 +
arch/mips/include/uapi/asm/inst.h | 1 +
arch
d-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
tools/testing/selftests/bpf/test_verifier.c | 29 +
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/tools/testing/selftests/bpf/test_verifier.c
b/tools/testing/selftests/bpf/test_verifier.c
index 18d
This patch remove the rejection on BPF_ALU | BPF_ARSH as we have supported
them on interpreter and all JIT back-ends
Reviewed-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
kernel/bpf/verifier.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/kernel/bpf/verifier.c b/kernel/bpf
This patch implements code-gen for BPF_ALU | BPF_ARSH | BPF_*.
Cc: Martin Schwidefsky
Cc: Heiko Carstens
Signed-off-by: Jiong Wang
---
arch/s390/net/bpf_jit_comp.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/s390/net/bpf_jit_comp.c b/arch/s390/net/bpf_jit_comp.c
BPF_X support needs indirect shift mode, please see code comments for
details.
Reviewed-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
drivers/net/ethernet/netronome/nfp/bpf/jit.c | 45
1 file changed, 45 insertions(+)
diff --git a/drivers/net/ethernet/netronome
On 04/12/2018 20:10, David Miller wrote:
From: Alexei Starovoitov
Date: Tue, 4 Dec 2018 11:29:55 -0800
I guess sparc doesn't really have 32 subregisters. All registers
are considered 64-bit. It has 32-bit alu ops on 64-bit registers
instead.
Right.
Anyways, sparc will require two
due to another issue inside verifier on supporting alu32
binary.
- Each cilium bpf program could generate several processed insn number,
above number is sum of them.
v1->v2:
- Restrict the change on SCALAR_VALUE.
- Update benchmark numbers on Cilium bpf tests.
Signed-off
On 06/12/2018 03:13, Alexei Starovoitov wrote:
On Wed, Dec 05, 2018 at 03:32:50PM +, Jiong Wang wrote:
On 05/12/2018 14:52, Edward Cree wrote:
On 05/12/18 09:46, Jiong Wang wrote:
There is NO processed instruction number regression, either with or without
-mattr=+alu32.
Cilium bpf
->v2:
- Keep mm_srlv32_op sorted by value.
Fixes: f31318fdf324 ("MIPS: uasm: Add srlv uasm instruction")
Cc: Markos Chandras
Cc: Paul Burton
Cc: linux-m...@vger.kernel.org
Acked-by: Jakub Kicinski
Acked-by: Song Liu
Signed-off-by: Jiong Wang
---
arch/mips/include/uapi/asm/ins
On 03/12/2018 22:04, Paul Burton wrote:
Hi Jiong,
On Sat, Dec 01, 2018 at 04:10:01AM -0500, Jiong Wang wrote:
For micro-mips, srlv inside POOL32A encoding space should use 0x50
sub-opcode, NOT 0x90.
Some early version ISA doc describes the encoding as 0x90 for both srlv and
srav, this looks
BPF_X support needs indirect shift mode, please see code comments for
details.
Reviewed-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
drivers/net/ethernet/netronome/nfp/bpf/jit.c | 45
1 file changed, 45 insertions(+)
diff --git a/drivers/net/ethernet/netronome
d-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
tools/testing/selftests/bpf/test_verifier.c | 29 +
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/tools/testing/selftests/bpf/test_verifier.c
b/tools/testing/selftests/bpf/test_verifier.c
index 18d
32_op"),
which is on mips-fixes branch at the moment.
Thanks.
v1->v2:
- Fix ppc implementation bug. Should zero high bits explicitly.
Cc: Paul Burton
Cc: Naveen N. Rao
Cc: Sandipan Das
Cc: Martin Schwidefsky
Cc: Heiko Carstens
Jiong Wang (7):
mips: bpf: implement jitting of BPF_ALU |
This patch remove the rejection on BPF_ALU | BPF_ARSH as we have supported
them on interpreter and all JIT back-ends
Reviewed-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
kernel/bpf/verifier.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/kernel/bpf/verifier.c b/kernel/bpf
This patch implements code-gen for BPF_ALU | BPF_ARSH | BPF_*.
Cc: Martin Schwidefsky
Cc: Heiko Carstens
Signed-off-by: Jiong Wang
---
arch/s390/net/bpf_jit_comp.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/s390/net/bpf_jit_comp.c b/arch/s390/net/bpf_jit_comp.c
This patch implements interpreting BPF_ALU | BPF_ARSH. Do arithmetic right
shift on low 32-bit sub-register, and zero the high 32 bits.
Reviewed-by: Jakub Kicinski
Signed-off-by: Jiong Wang
---
kernel/bpf/core.c | 52 ++--
1 file changed, 30
This patch implements code-gen for BPF_ALU | BPF_ARSH | BPF_*.
Cc: Naveen N. Rao
Cc: Sandipan Das
Signed-off-by: Jiong Wang
---
arch/powerpc/include/asm/ppc-opcode.h | 2 ++
arch/powerpc/net/bpf_jit.h| 4
arch/powerpc/net/bpf_jit_comp64.c | 6 ++
3 files changed, 12
Jitting of BPF_K is supported already, but not BPF_X. This patch complete
the support for the latter on both MIPS and microMIPS.
Cc: Paul Burton
Cc: linux-m...@vger.kernel.org
Acked-by: Paul Burton
Signed-off-by: Jiong Wang
---
arch/mips/include/asm/uasm.h | 1 +
arch/mips/include/uapi
On 05/12/2018 15:32, Jiong Wang wrote:
On 05/12/2018 14:52, Edward Cree wrote:
On 05/12/18 09:46, Jiong Wang wrote:
There is NO processed instruction number regression, either with or
without
-mattr=+alu32.
Cilium bpf
===
bpf_lb-DLB_L3.o 2110/2110 1730/1733
That looks like
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