Re: [PATCH v2 net 6/6] net: mvneta: Fix race condition during stopping

On Mon, 1 Feb 2016 14:07:47 +0100 Gregory CLEMENT wrote: > When stopping the port, the CPU notifier are still there whereas the > mvneta_stop_dev function calls mvneta_percpu_disable() on each CPUs. > It was possible to have a new CPU coming at this point which could be > racy. > > This patch

Re: [PATCH net 1/3] net: mvneta: Fix spinlock usage

Dear Gregory, On Tue, 8 Mar 2016 13:57:04 +0100 Gregory CLEMENT wrote: > In the previous patch, the spinlock was not initialized. While it didn't > cause any trouble yet it could be a problem to use it uninitialized. > > The most annoying part was the critical section protected by the spinlock

[PATCH] net: mvneta: remove useless RX descriptor prefetch

The rx descriptors are allocated using dma_alloc_coherent, so prefetch doesn't really happen at all. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- drivers/net/ethernet/marvell/mvneta.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/d

Re: [PATCH] net: mvneta: remove useless RX descriptor prefetch

Hi, + linux arm kernel On Thu, 31 Mar 2016 14:36:30 +0800 Jisheng Zhang wrote: > The rx descriptors are allocated using dma_alloc_coherent, so prefetch > doesn't really happen at all. This is for RFC, I'm sorry to send it without changing its title -- s/PATCH/RFC. I'm not sure whether t

Re: [PATCH] net: mvneta: remove useless RX descriptor prefetch

Hi all, On Thu, 31 Mar 2016 14:45:37 +0800 Jisheng Zhang wrote: > Hi, > > + linux arm kernel > > On Thu, 31 Mar 2016 14:36:30 +0800 Jisheng Zhang wrote: > > > The rx descriptors are allocated using dma_alloc_coherent, so prefetch > > doesn't really happen at al

Re: [PATCH] net: mvneta: explicitly disable BM on 64bit platform

Hi Gregory, On Wed, 30 Mar 2016 17:11:41 +0200 Gregory CLEMENT wrote: > Hi Jisheng, > > On mer., mars 30 2016, Jisheng Zhang <jszh...@marvell.com> wrote: > > > The mvneta BM can't work on 64bit platform, as the BM hardware expects > > buf virtual address to be

[PATCH v2] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with cache_line_size

The mvneta is also used in some Marvell berlin family SoCs which may have different cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE usage with cache_line_size(). And since dma_alloc_coherent() is always cacheline size aligned, so remove the align checks. Signed-off-by: Jisheng Zhang

[PATCH] net: mvpp2: fix maybe-uninitialized warning

This is to fix the following maybe-uninitialized warning: drivers/net/ethernet/marvell/mvpp2.c:6007:18: warning: 'err' may be used uninitialized in this function [-Wmaybe-uninitialized] Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- drivers/net/ethernet/marvell/mvpp2.c | 4 +++-

[PATCH v2] net: mvpp2: replace MVPP2_CPU_D_CACHE_LINE_SIZE with cache_line_size

The mvpp2 ip maybe used in SoCs which may have have different cacheline size. Replace the MVPP2_CPU_D_CACHE_LINE_SIZE with cache_line_size. And since dma_alloc_coherent() is always cacheline size aligned, so remove the align checks. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- Si

Re: [PATCH] net: mvneta: explicitly disable BM on 64bit platform

Hi Marcin, On Thu, 31 Mar 2016 08:49:19 +0200 Marcin Wojtas wrote: > Hi Jisheng, > > 2016-03-31 7:53 GMT+02:00 Jisheng Zhang <jszh...@marvell.com>: > > Hi Gregory, > > > > On Wed, 30 Mar 2016 17:11:41 +0200 Gregory CLEMENT wrote: > > > >> Hi Ji

Re: [PATCH net 1/3] net: mvneta: Fix spinlock usage

Dear Gregory, On Wed, 9 Mar 2016 08:49:40 +0100 Gregory CLEMENT wrote: > Hi Jisheng, > > On mer., mars 09 2016, Jisheng Zhang <jszh...@marvell.com> wrote: > > > Dear Gregory, > > > > On Tue, 8 Mar 2016 13:57:04 +0100 Gregory CLEMENT wrote: > >

[PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES

The mvneta is also used in some Marvell berlin family SoCs which may have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE usage with L1_CACHE_BYTES. And since dma_alloc_coherent() is always cacheline size aligned, so remove the align checks. Signed-off-by: Jisheng Zhang <j

[PATCH] net: mvpp2: replace MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES

The mvpp2 ip maybe used in SoCs which may have have 64bytes cacheline size. Replace the MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES. And since dma_alloc_coherent() is always cacheline size aligned, so remove the align checks. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- d

[PATCH] net: mvneta: explicitly disable BM on 64bit platform

-by: Jisheng Zhang <jszh...@marvell.com> --- drivers/net/ethernet/marvell/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig index b5c6d42..53d6572 100644 --- a/drivers/net/ethernet/marvell/Kconfig

[RFC] net: mvneta: 64bit platform support

Hi all, Obviously, current mvneta driver can't work on 64bit platforms. For one thing the BM feature should be explicitly disabled, I just sent out one patch for this purpose. What's more, the buf_cookie in mvneta_rx_desc need to be carefully considered. The driver use the buf_cookie(u32 type)

Re: [RFC] net: mvneta: 64bit platform support

On Wed, 30 Mar 2016 21:37:00 +0800 Jisheng Zhang wrote: > Hi all, > > Obviously, current mvneta driver can't work on 64bit platforms. For one thing > the BM feature should be explicitly disabled, I just sent out one patch for > this purpose. > > What's more, the buf_coo

[PATCH] net: mvpp2: use cache_line_size() to get cacheline size

L1_CACHE_BYTES may not be the real cacheline size, use cache_line_size to determine the cacheline size in runtime. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> Suggested-by: Marcin Wojtas <m...@semihalf.com> --- drivers/net/ethernet/marvell/mvpp2.c | 2 +- 1 file changed, 1 ins

[PATCH] net: mvneta: use cache_line_size() to get cacheline size

L1_CACHE_BYTES may not be the real cacheline size, use cache_line_size to determine the cacheline size in runtime. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> Suggested-by: Marcin Wojtas <m...@semihalf.com> --- drivers/net/ethernet/marvell/mvneta.c | 2 +- 1 file changed,

Re: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES

Hi David, Thomas, On Thu, 31 Mar 2016 16:47:10 -0400 David Miller wrote: > From: Thomas Petazzoni <thomas.petazz...@free-electrons.com> > Date: Thu, 31 Mar 2016 22:37:35 +0200 > > > Hello, > > > > On Thu, 31 Mar 2016 15:15:47 -0400 (EDT), David Miller wrote:

[PATCH 0/2] net: pxa168_eth: improve performance

This series is to improve the pxa168_eth driver performance by using {readl|writel}_relaxed or appropriate memory barriers. Jisheng Zhang (2): net: pxa168_eth: use {readl|writel}_relaxed instead of readl/writel net: pxa168_eth: Use dma_wmb/rmb where appropriate drivers/net/ethernet/marvell

[PATCH 1/2] net: pxa168_eth: use {readl|writel}_relaxed instead of readl/writel

Since appropriate memory barriers are already there, use the relaxed version to improve performance a bit. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- drivers/net/ethernet/marvell/pxa168_eth.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/et

Re: [PATCH 1/2] net: mv643xx_eth: use {readl|writel}_relaxed instead of readl/writel

Dear Arnd, On Fri, 13 May 2016 14:09:43 +0200 Arnd Bergmann wrote: > On Friday 13 May 2016 19:59:19 Jisheng Zhang wrote: > > /* port register accessors > > **/ > > static inline u32 rdl(struct mv643xx_eth_pr

[PATCH 2/2] net: pxa168_eth: Use dma_wmb/rmb where appropriate

Update the pxa168_eth driver to use the dma_rmb/wmb calls instead of the full barriers in order to improve performance: reduced 97ns/39ns on average in tx/rx path on Marvell BG4CT platform. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- drivers/net/ethernet/marvell/pxa168_eth

[PATCH 2/2] net: mv643xx_eth: use dma_wmb/rmb where appropriate

Update the mv643xx_eth driver to use the dma_rmb/wmb calls instead of the full barriers in order to improve performance. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- drivers/net/ethernet/marvell/mv643xx_eth.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff

[PATCH 0/2] net: mv643xx_eth: improve performance

This series is to improve the mv643xx_eth driver performance by using {readl|writel}_relaxed or appropriate memory barriers. Since I have no mv643xx_eth platforms, tests are appreciated! Jisheng Zhang (2): net: mv643xx_eth: use {readl|writel}_relaxed instead of readl/writel net: mv643xx_eth

[PATCH 1/2] net: mv643xx_eth: use {readl|writel}_relaxed instead of readl/writel

Since appropriate memory barriers are already there, use the relaxed version to improve performance a bit. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- drivers/net/ethernet/marvell/mv643xx_eth.c | 33 +++--- 1 file changed, 17 insertions(+), 16 del

[PATCH v5 net-next] net: mvneta: implement .set_wol and .get_wol

From: Jingju Hou <houji...@marvell.com> The mvneta itself does not support WOL, but the PHY might. So pass the calls to the PHY Signed-off-by: Jingju Hou <houji...@marvell.com> Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- since v4: - address Andrew Lunn's comment s

Re: [PATCH v4 net-next] net: mvneta: implement .set_wol and .get_wol

Hi Andrew, On Mon, 23 Jan 2017 19:10:34 +0100 Andrew Lunn wrote: > > On Mon, Jan 23, 2017 at 02:55:07PM +0800, Jisheng Zhang wrote: > > From: Jingju Hou <houji...@marvell.com> > > > > From: Jingju Hou <houji...@marvell.com> > > > > The mvnet

Re: [PATCH v4 net-next] net: mvneta: implement .set_wol and .get_wol

On Mon, 6 Feb 2017 15:08:48 +0800 Jisheng Zhang wrote: > Hi Andrew, > > On Mon, 23 Jan 2017 19:10:34 +0100 Andrew Lunn wrote: > > > > > On Mon, Jan 23, 2017 at 02:55:07PM +0800, Jisheng Zhang wrote: > > > From: Jingju Hou <houji...@marvell.com&g

Re: [PATCHv2 net-next] net: mvneta: implement .set_wol and .get_wol

On Mon, 23 Jan 2017 10:44:07 +0800 Jingju Hou <houji...@marvell.com> wrote: > The mvneta itself does not support WOL, but the PHY might. > So pass the calls to the PHY > > Signed-off-by: Jingju Hou <houji...@marvell.com> Reviewed-by: Jisheng Zhang <jszh...@mar

Re: [PATCH] net: mvneta: implement .set_wol and .get_wol

Hi Jingju, On Mon, 23 Jan 2017 10:43:08 +0800 wrote: > The mvneta itself does not support WOL, but the PHY might. > So pass the calls to the PHY > > Signed-off-by: Jingju Hou > --- > Since v1: > - using phy_dev member in struct net_device I noticed that you send a new v2

Re: [PATCH v2 net-next] net: phy: marvell: Add Wake from LAN support for 88E1510 PHY

On Mon, 23 Jan 2017 10:58:15 +0800 wrote: > This is test on BG4CT platform with 88E1518 marvell PHY. > > Signed-off-by: Jingju Hou <houji...@marvell.com> Reviewed-by: Jisheng Zhang <jszh...@marvell.com> > --- > Since v1: > - add some commit messages > > d

[PATCH v4 net-next] net: mvneta: implement .set_wol and .get_wol

From: Jingju Hou <houji...@marvell.com> From: Jingju Hou <houji...@marvell.com> The mvneta itself does not support WOL, but the PHY might. So pass the calls to the PHY Signed-off-by: Jingju Hou <houji...@marvell.com> Signed-off-by: Jisheng Zhang <jszh...@marvell.com> ---

[PATCH net-next v3 1/4] net: mvneta: avoid getting status from rx_desc as much as possible

ory. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> Suggested-by: Arnd Bergmann <a...@arndb.de> Tested-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- drivers/net/ethernet/marvell/mvneta.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a

[PATCH net-next v3 3/4] net: mvneta: avoid reading from tx_desc as much as possible

. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- drivers/net/ethernet/marvell/mvneta.c | 50 ++- 1 file changed, 26 insertions(+), 24 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index a25042

[PATCH net-next v3 2/4] net: mvneta: avoid getting buf_phys_addr from rx_desc again

ing from uncached memory. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> Suggested-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- drivers/net/ethernet/marvell/mvneta.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/marv

[PATCH net-next v3 4/4] net: mvneta: Use cacheable memory to store the rx buffer DMA address

address. We get the following performance data on Marvell BG4CT Platforms (tested with iperf): before the patch: recving 1GB in mvneta_rx_swbm() costs 1492659600 ns after the patch: recving 1GB in mvneta_rx_swbm() costs 1421565640 ns We saved 4.76% time. Signed-off-by: Jisheng Zhang <j

[PATCH net-next v3 0/4] net: mvneta: improve rx/tx performance

wbm() - add patch 3 to avoid reading from tx_desc as much as possible Since v1: - correct the performance data typo Jisheng Zhang (4): net: mvneta: avoid getting status from rx_desc as much as possible net: mvneta: avoid getting buf_phys_addr from rx_desc again net: mvneta: avoid reading

Re: [PATCH net-next v3 0/4] net: mvneta: improve rx/tx performance

Hi Gregory, On Mon, 20 Feb 2017 15:21:35 +0100 Gregory CLEMENT wrote: > Hi Jisheng, > > On lun., févr. 20 2017, Jisheng Zhang <jszh...@marvell.com> wrote: > > > In hot code path such as mvneta_rx_swbm(), we access fields of rx_desc > > and tx_desc.

Re: [PATCH net-next v3 0/4] net: mvneta: improve rx/tx performance

Hi David, Marcin, On Tue, 21 Feb 2017 11:16:02 -0500 David Miller wrote: > From: Jisheng Zhang <jszh...@marvell.com> > Date: Tue, 21 Feb 2017 12:37:40 +0800 > > > Thanks for your review. > > > > The measurement is simple: record how much time we spent in mvnet

[PATCH] net: mvneta: make mvneta_eth_tool_ops static

The mvneta_eth_tool_ops is only used internally in mvneta driver, so make it static. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- drivers/net/ethernet/marvell/mvneta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/d

[PATCH net-next 1/2] net: mvneta: avoid getting status from rx_desc as much as possible

ory. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> Suggested-by: Arnd Bergmann <a...@arndb.de> --- drivers/net/ethernet/marvell/mvneta.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell

[PATCH net-next 0/2] net: mvneta: improve rx performance

/msg405889.html Jisheng Zhang (2): net: mvneta: avoid getting status from rx_desc as much as possible net: mvneta: Use cacheable memory to store the rx buffer DMA address drivers/net/ethernet/marvell/mvneta.c | 36 --- 1 file changed, 21 insertions(+), 15

[PATCH net-next 2/2] net: mvneta: Use cacheable memory to store the rx buffer DMA address

the rx buffer DMA address. We get the following performance data on Marvell BG4CT Platforms (tested with iperf): before the patch: recving 1GB in mvneta_rx_swbm() costs 149265960 ns after the patch: recving 1GB in mvneta_rx_swbm() costs 1421565640 ns We saved 4.76% time. Signed-off-by: Jisheng

[PATCH net-next v2 0/2] net: mvneta: improve rx performance

/msg405889.html Since v1: - correct the performance data typo Jisheng Zhang (2): net: mvneta: avoid getting status from rx_desc as much as possible net: mvneta: Use cacheable memory to store the rx buffer DMA address drivers/net/ethernet/marvell/mvneta.c | 36

[PATCH net-next v2 1/2] net: mvneta: avoid getting status from rx_desc as much as possible

ory. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> Suggested-by: Arnd Bergmann <a...@arndb.de> --- drivers/net/ethernet/marvell/mvneta.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell

[PATCH net-next v2 2/2] net: mvneta: Use cacheable memory to store the rx buffer DMA address

the rx buffer DMA address. We get the following performance data on Marvell BG4CT Platforms (tested with iperf): before the patch: recving 1GB in mvneta_rx_swbm() costs 1492659600 ns after the patch: recving 1GB in mvneta_rx_swbm() costs 1421565640 ns We saved 4.76% time. Signed-off-by: Jisheng

Re: [PATCH net-next v2 0/2] net: mvneta: improve rx performance

On Fri, 17 Feb 2017 18:02:31 +0800 Jisheng Zhang <jszh...@marvell.com> wrote: > In hot code path such as mvneta_rx_hwbm() and mvneta_rx_swbm(), we may > access fields of rx_desc. The rx_desc is allocated by > dma_alloc_coherent, it's uncacheable if the device isn't cache > cohe

Re: [PATCH net-next v2 0/2] net: mvneta: improve rx performance

On Fri, 17 Feb 2017 11:37:21 +0100 Gregory CLEMENT wrote: > Hi Jisheng, > > On ven., févr. 17 2017, Jisheng Zhang <jszh...@marvell.com> wrote: > > > In hot code path such as mvneta_rx_hwbm() and mvneta_rx_swbm(), we may > > access fields of rx_

Re: [PATCH net-next 1/4] net: mvneta: Convert to be 64 bits compatible

On Tue, 22 Nov 2016 22:04:12 +0100 Arnd Bergmann wrote: > On Tuesday, November 22, 2016 5:48:41 PM CET Gregory CLEMENT wrote: > > +#ifdef CONFIG_64BIT > > + void *data_tmp; > > + > > + /* In Neta HW only 32 bits data is supported, so in order to > > +* obtain whole 64 bits

Re: [PATCH net-next 1/4] net: mvneta: Convert to be 64 bits compatible

Hi Arnd, On Wed, 23 Nov 2016 11:15:32 +0100 Arnd Bergmann wrote: > On Wednesday, November 23, 2016 5:53:41 PM CET Jisheng Zhang wrote: > > On Tue, 22 Nov 2016 22:04:12 +0100 Arnd Bergmann wrote: > > > > > On Tuesday, November 22, 2016 5:48:41 PM CET Gregory CLEMENT

Re: [PATCH net-next 1/4] net: mvneta: Convert to be 64 bits compatible

On Thu, 24 Nov 2016 10:00:36 +0100 Arnd Bergmann <a...@arndb.de> wrote: > On Thursday, November 24, 2016 4:37:36 PM CET Jisheng Zhang wrote: > > solB (a SW shadow cookie) perhaps gives a better performance: in hot path, > > such as mvneta_rx(), the driver accesses buf_coo

Re: [PATCH net-next 1/4] net: mvneta: Convert to be 64 bits compatible

d Bergmann wrote: > > > >> On Wednesday, November 23, 2016 5:53:41 PM CET Jisheng Zhang wrote: > >>> On Tue, 22 Nov 2016 22:04:12 +0100 Arnd Bergmann wrote: > >>> > >>> > On Tuesday, November 22, 201

Re: [PATCH net-next 1/5] net: mvneta: Use cacheable memory to store the rx buffer virtual address

Hi Gregory, On Fri, 25 Nov 2016 16:30:14 +0100 Gregory CLEMENT wrote: > Until now the virtual address of the received buffer were stored in the > cookie field of the rx descriptor. However, this field is 32-bits only > which prevents to use the driver on a 64-bits architecture. > > With this

Re: [PATCH net-next 0/5] Support Armada 37xx SoC (ARMv8 64-bits) in mvneta driver

Hi Gregory, On Fri, 25 Nov 2016 16:30:13 +0100 Gregory CLEMENT wrote: > Hi, > > The Armada 37xx is a new ARMv8 SoC from Marvell using same network > controller as the older Armada 370/38x/XP SoCs. This series adapts the > driver in order to be able to use it on this new SoC. The main changes >

Re: [PATCH v5 net-next 4/7] net: mvneta: Convert to be 64 bits compatible

arm64. If that's implemented and merged, then we can revert this patch later. Thanks, Jisheng > > Best regards, > Marcin > > > > 2016-12-01 12:26 GMT+01:00 Jisheng Zhang <jszh...@marvell.com>: > > Hi Gregory, Marcin, > > > > On Wed, 30 Nov 2016 22

Re: [PATCH v5 net-next 4/7] net: mvneta: Convert to be 64 bits compatible

On Thu, 1 Dec 2016 20:02:05 +0800 Jisheng Zhang wrote: > Hi Marcin, > > On Thu, 1 Dec 2016 12:48:39 +0100 Marcin Wojtas wrote: > > > Hi Jisheng, > > > > Which baseline do you use? > > > > It took me really lot of time to catch why RX broke after rebas

Re: [PATCH v5 net-next 4/7] net: mvneta: Convert to be 64 bits compatible

Hi Gregory, Marcin, On Wed, 30 Nov 2016 22:42:49 +0100 Gregory CLEMENT wrote: > From: Marcin Wojtas > > Prepare the mvneta driver in order to be usable on the 64 bits platform > such as the Armada 3700. > > [gregory.clem...@free-electrons.com]: this patch was extract from a

Re: [PATCH v5 net-next 3/7] net: mvneta: Use cacheable memory to store the rx buffer virtual address

ie > field, this also means that currently the hwbm is not usable in 64-bits. > > Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> Reviewed-by: Jisheng Zhang <jszh...@marvell.com> Thanks, Jisheng > --- > drivers/net/ethernet/marvell/mvneta.c |

Re: [PATCH v5 net-next 4/7] net: mvneta: Convert to be 64 bits compatible

On Thu, 1 Dec 2016 19:26:04 +0800 Jisheng Zhang <jszh...@marvell.com> wrote: > Hi Gregory, Marcin, > > On Wed, 30 Nov 2016 22:42:49 +0100 Gregory CLEMENT wrote: > > > From: Marcin Wojtas <m...@semihalf.com> > > > > Prepare the mvneta driver in

[PATCH] net: mvneta: set rx mode during resume if interface is running

n't. It turns out the rx mode isn't resumed correctly. This patch fixes it by adding mvneta_set_rx_mode(dev) in the resume hook if interface is running. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- drivers/net/ethernet/marvell/mvneta.c | 5 - 1 file changed, 4 insertions(+), 1

[PATCH net-next] net: mvneta: add RGMII_RXID and RGMII_TXID support

RGMII_RXID and RGMII_TX_ID share the same GMAC CTRL setting as RGMII or RGMII_ID. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- drivers/net/ethernet/marvell/mvneta.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/et

[PATCH net-next v2] net: mvneta: set rx mode during resume if interface is running

n't. It turns out the rx mode isn't resumed correctly. This patch fixes it by adding mvneta_set_rx_mode(dev) in the resume hook if interface is running. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- Since v1: - rebased to the latest net-next tree and explictly mention it dr

Re: [PATCH] net: mvneta: set rx mode during resume if interface is running

Dear David, On Mon, 27 Mar 2017 16:15:34 -0700 David Miller wrote: > From: Jisheng Zhang <jszh...@marvell.com> > Date: Mon, 27 Mar 2017 18:59:05 +0800 > > > I found a bug by: > > > > 0. boot and start dhcp client > > 1. echo mem > /sys/power/state &

Re: [PATCH v2] net: mvneta: support suspend and resume

On Thu, 16 Mar 2017 11:19:10 +0800 Jane Li wrote: > Add basic support for handling suspend and resume. > > Signed-off-by: Jane Li > --- > Since v1: > - add mvneta_conf_mbus_windows() and mvneta_bm_port_init() in mvneta_resume() > > drivers/net/ethernet/marvell/mvneta.c | 62

Re: [PATCH v3] net: mvneta: support suspend and resume

device); > + struct net_device *dev = dev_get_drvdata(device); > + struct mvneta_port *pp = netdev_priv(dev); > + int err; > + > + clk_prepare_enable(pp->clk); > + clk_prepare_enable(pp->clk_bus); hmm, since clk_bus is optional, it's better to add chec

Re: [PATCH] net: mvneta: support suspend and resume

Hi Jane, On Wed, 15 Mar 2017 15:08:34 +0800 Jane Li wrote: > Add basic support for handling suspend and resume. > > Signed-off-by: Jane Li > --- > drivers/net/ethernet/marvell/mvneta.c | 44 > +++ > 1 file changed, 44 insertions(+) > > diff

[PATCH net-next] net: mvneta: fix failed to suspend if WOL is enabled

support WOL. 2. in mvneta_ethtool_set_wol(), call device_set_wakeup_enable() to set power.wakeup if WOL has been successfully enabled in phy. Signed-off-by: Jisheng Zhang <jszh...@marvell.com> --- drivers/net/ethernet/marvell/mvneta.c | 12 +++- 1 file changed, 11 insertions(+), 1 de

Re: [PATCH] net: phy: marvell: clear wol event before setting it

On Fri, 27 Apr 2018 09:22:34 +0530 Bhadram Varka wrote: > Hi Andrew/Jisheng, > > On 4/26/2018 6:10 PM, Andrew Lunn wrote: > >> hmm, so you want a "stick" WOL feature, I dunno whether Linux kernel > >> requires WOL should be "stick". > > I see two different cases: > > > > Suspend/resume: The

Re: [PATCH] net: phy: marvell: clear wol event before setting it

On Thu, 26 Apr 2018 12:39:59 +0530 Bhadram Varka wrote: > > > > diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c > > index c22e8e383247..b6abe1cbc84b 100644 > > --- a/drivers/net/phy/marvell.c > > +++ b/drivers/net/phy/marvell.c > > @@ -115,6 +115,9 @@ >

[PATCH] drivers: net: replace UINT64_MAX with U64_MAX

. Replace the UINT64_MAX with U64_MAX to clean up the source code. Signed-off-by: Jisheng Zhang <jisheng.zh...@synaptics.com> --- drivers/net/dsa/mv88e6xxx/chip.c | 6 +++--- drivers/net/dsa/mv88e6xxx/chip.h | 4 drivers/net/phy/bcm-phy-lib.c| 6 +- drivers/net/phy/marvell.c

Re: [PATCH] net: phy: marvell: clear wol event before setting it

On Thu, 26 Apr 2018 11:56:33 +0530 Bhadram Varka wrote: > Hi, > On 4/26/2018 11:45 AM, Jisheng Zhang wrote: > > Hi, > > > > On Thu, 26 Apr 2018 11:10:21 +0530 Bhadram Varka wrote: > > > >> Hi, > >> > >> On 4/19/2018 5:48 PM, Andrew Lun

Re: [PATCH] net: phy: marvell: clear wol event before setting it

Hi, On Thu, 26 Apr 2018 11:10:21 +0530 Bhadram Varka wrote: > Hi, > > On 4/19/2018 5:48 PM, Andrew Lunn wrote: > > On Thu, Apr 19, 2018 at 04:02:32PM +0800, Jisheng Zhang wrote: > >> From: Jingju Hou <jingju@synaptics.com> > >> > >> If W

Re: [PATCH v1 6/7] net: mvneta: Don't use GRO on Armada 3720

+ more people On Wed, 8 Aug 2018 17:27:05 +0200 Marek Behún wrote: > For some reason on Armada 3720 boards (EspressoBin and Turris Mox) the > networking driver behaves weirdly when using napi_gro_receive. > > For example downloading a big file from a local network (low ping) is > fast, but

Re: [PATCH v1 6/7] net: mvneta: Don't use GRO on Armada 3720

On Thu, 9 Aug 2018 19:27:55 +0800 Jisheng Zhang wrote: > Hi, > > On Thu, 9 Aug 2018 12:40:41 +0800 Jisheng Zhang wrote: > > > + more people > > > > On Wed, 8 Aug 2018 17:27:05 +0200 Marek Behún wrote: > > > > > For some reason on A

Re: [PATCH v1 6/7] net: mvneta: Don't use GRO on Armada 3720

Hi, On Thu, 9 Aug 2018 12:40:41 +0800 Jisheng Zhang wrote: > + more people > > On Wed, 8 Aug 2018 17:27:05 +0200 Marek Behún wrote: > > > For some reason on Armada 3720 boards (EspressoBin and Turris Mox) the > > networking driver behaves weirdly whe

[query] about recent mvneta patches

Hi, Today I have a look at recent mvneta patches in net-next, I worried two patches: 1. commit 562e2f467e71 ("net: mvneta: Improve the buffer allocation method for SWBM") sets rx_offset_correction as 0 for SW BM, but IIRC, the offset is introduced to support 64bit platforms. So in theory the

Re: [PATCH] net: phy: marvell: clear wol event before setting it

Hi, On Thu, 19 Apr 2018 08:38:45 + Bhadram Varka wrote: > Hi, > > > -Original Message- > > From: netdev-ow...@vger.kernel.org <netdev-ow...@vger.kernel.org> On > > Behalf Of Jisheng Zhang > > Sent: Thursday, April 19, 2018 1:33 PM > >

Re: [PATCH] net: phy: marvell: clear wol event before setting it

On Thu, 19 Apr 2018 09:00:40 + Bhadram Varka wrote: > Hi, > > > -Original Message- > > From: Jisheng Zhang <jisheng.zh...@synaptics.com> > > Sent: Thursday, April 19, 2018 2:24 PM > > To: Bhadram Varka <vbhad...@nvidia.com> > > Cc

[PATCH] net: phy: marvell: clear wol event before setting it

From: Jingju Hou <jingju@synaptics.com> If WOL event happened once, the LED[2] interrupt pin will not be cleared unless reading the CSISR register. So clear the WOL event before enabling it. Signed-off-by: Jingju Hou <jingju@synaptics.com> Signed-off-by: Jisheng Zhang

[PATCH v2] net: phy: marvell: clear wol event before setting it

abling it if !phy_interrupt_is_valid(). Signed-off-by: Jingju Hou <jingju@synaptics.com> Signed-off-by: Jisheng Zhang <jisheng.zh...@synaptics.com> --- Since v1: - reuse MII_M1011_IEVENT, suggested by Bhadram Varka - make read conditional on !phy_interrupt_is_valid(), suggested by Andrew drivers

[PATCH v2 1/2] net: mvneta: split rxq/txq init and txq deinit into SW and HW parts

-by: Jisheng Zhang <jisheng.zh...@synaptics.com> --- drivers/net/ethernet/marvell/mvneta.c | 85 +++ 1 file changed, 66 insertions(+), 19 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 30aab9bf77cc..f96815

[PATCH v2 2/2] net: mvneta: improve suspend/resume

to fragmented dma coherent memory. After this patch, the non-necessary memory alloc/free is optimized out. Signed-off-by: Jisheng Zhang <jisheng.zh...@synaptics.com> --- drivers/net/ethernet/marvell/mvneta.c | 71 ++- 1 file changed, 61 insertions(+), 10 del

Re: [PATCH 1/2] net: mvneta: split rxq/txq init into SW and HW parts

Hi, On Thu, 29 Mar 2018 13:42:59 +0200 Thomas Petazzoni wrote: > Hello, > > On Thu, 29 Mar 2018 18:13:56 +0800, Jisheng Zhang wrote: > > This is to prepare the suspend/resume improvement in next patch. The > > SW parts can be optimized out during resume. > > >

[PATCH v2 0/2] net: mvneta: improve suspend/resume

to patch1, because in v2, I added new code to split the txq deinit into two parts. Jisheng Zhang (2): net: mvneta: split rxq/txq init and txq deinit into SW and HW parts net: mvneta: improve suspend/resume drivers/net/ethernet/marvell/mvneta.c | 156 +++--- 1 file

Re: [PATCH 2/2] net: mvneta: improve suspend/resume

On Thu, 29 Mar 2018 13:54:32 +0200 Thomas Petazzoni wrote: > Hello Jisheng, Hi Thomas, > > On Thu, 29 Mar 2018 18:15:36 +0800, Jisheng Zhang wrote: > > Current suspend/resume implementation reuses the mvneta_open() and > > mvneta_close(), but it could be optimized t

[PATCH 0/2] net: mvneta: improve suspend/resume

This series tries to optimize the mvneta's suspend/resume implementation by only taking necessary actions. Jisheng Zhang (2): net: mvneta: split rxq/txq init into SW and HW parts net: mvneta: improve suspend/resume drivers/net/ethernet/marvell/mvneta.c | 146

[PATCH 2/2] net: mvneta: improve suspend/resume

to fragmented dma coherent memory. After this patch, the non-necessary memory alloc/free is optimized out. Signed-off-by: Jisheng Zhang <jisheng.zh...@synaptics.com> --- drivers/net/ethernet/marvell/mvneta.c | 76 ++- 1 file changed, 66 insertions(+), 10 del

[PATCH] net: mvneta: remove duplicate *_coal assignment

off-by: Jisheng Zhang <jisheng.zh...@synaptics.com> --- drivers/net/ethernet/marvell/mvneta.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index eaa4bb80f1c9..30aab9bf77cc 100644 --- a/drivers/net/etherne

[PATCH 1/2] net: mvneta: split rxq/txq init into SW and HW parts

This is to prepare the suspend/resume improvement in next patch. The SW parts can be optimized out during resume. Signed-off-by: Jisheng Zhang <jisheng.zh...@synaptics.com> --- drivers/net/ethernet/marvell/mvneta.c | 70 ++- 1 file changed, 53 insertions(

[PATCH v3 0/2] net: mvneta: improve suspend/resume

behavior - split txq deinit into sw/hw parts as well - adjust mvneta_stop_dev() location I didn't add Thomas's Ack tag to patch1, because in v2, I add new code to split the txq deinit into two parts. Jisheng Zhang (2): net: mvneta: split rxq/txq init and txq deinit into SW and HW parts net

[PATCH v3 1/2] net: mvneta: split rxq/txq init and txq deinit into SW and HW parts

-by: Jisheng Zhang <jisheng.zh...@synaptics.com> --- drivers/net/ethernet/marvell/mvneta.c | 85 +++ 1 file changed, 66 insertions(+), 19 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 30aab9bf77cc..f96815

[PATCH v3 2/2] net: mvneta: improve suspend/resume

to fragmented dma coherent memory. After this patch, the non-necessary memory alloc/free is optimized out. Signed-off-by: Jisheng Zhang <jisheng.zh...@synaptics.com> --- drivers/net/ethernet/marvell/mvneta.c | 69 +++ 1 file changed, 62 insertions(+), 7 del