Add three files. ralink,rt2880-net.txt descibes the actual frame engine
and the other two describe the switch forntend bindings.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <igv...@gmail.c
Signed-off-by: John Crispin <blo...@openwrt.org>
---
MAINTAINERS |7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ea17512..767f108 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6897,6 +6897,13 @@ F: include/uapi/linux/meye.h
F: includ
This driver is very basic and only provides basic init and irq support.
The SoC and switch core both have support for a special tag making DSA
support possible.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
drivers/net/ethernet/mediatek/esw_rt3050.c
Add support for SoCs from the rt3050 family. This include rt3050, rt3052,
rt3352 and rt5350. These all have a builtin 5 port 100mbit switch.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <igv...@gmail.co
silicon issues. Due to these issues we need to
PDMA for RX and QDMA for TX. All SoCs newer than the MT7621 can can run on
QDMA exclusively.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <igv...@gmail.com>
Add support for rt3883 and its smaller version rt3662. They both have a
single gBit port that will normally be attached to an external phy or
switch.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <i
This driver is very basic and only provides basic init and irq support.
The SoC and switch core both have support for a special tag making DSA
support possible.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
drivers/net/ethernet/mediatek/gsw_mt7620.c
rt2880 is the oldest SoC with this core. It has a single gBit port that
will normally be attached to an external phy or switch. The patch also
adds the code required to drive the mdio bus.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
This driver is very basic and only provides basic init and irq support.
The SoC and switch core both have support for a special tag making DSA
support possible.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
drivers/net/ethernet/mediatek/gsw_mt7621.c | 283 +
Add support for SoCs from the mt7621 family. These all have 2 GMAC ports,
both of which are attached to the same internal 1000MBit switch. Currently
we only support GMAC1 as the sole CPU port.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.or
This patch adds the Makefile and Kconfig required to make the driver build.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <igv...@gmail.com>
---
drivers/net/ethernet/Kconfig |1 +
dr
Add support for SoCs from the mt7620 family. These all have one dedicated
external gbit port and a builtin 5 port 100mbit switch. Additionally one
of the 5 switch ports can be changed to become an additional gbit port
that we can attach a phy to.
Signed-off-by: John Crispin <blo...@openwrt.
On 23/11/2015 00:16, Andrew Lunn wrote:
>> Hi Andrew,
>>
>> we have had a switch layer inside openwrt called swconfig for several
>> years. at the moment i have an add-on patch in openwrt to provide an
>> userland interface via that layer.
>
> Hi John
>
> I know of swconfig. However, it has
. These values
come straight from the SDK driver and we do not know the meaning of most of
them.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <igv...@gmail.com>
---
drivers/net/ethernet/ralink/e
rt2880 is the oldest SoC with this core. It has a single gBit port that will
normally be attached to an external phy of switch. The patch also adds the
code required to drive the mdio bus.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
on which SoC
we are on. The code to bring up the switches and external ports has also been
split into separate files.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <igv...@gmail.com>
---
drivers/net/ethe
. Instead the driver can manually handle the carrier
state.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <igv...@gmail.com>
Cc: Florian Fainelli <f.faine...@gmail.com>
---
drivers/net/phy/phy.c |9
Add three files. ralink,rt2880-net.txt descibes the actual frame engine
and the other two describe the switch forntend bindings.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <igv...@gmail.c
This patch adds the Makefile and Kconfig required to make the driver build.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <igv...@gmail.com>
---
drivers/net/ethernet/Kconfig |1 +
dr
Add support for rt3883 and its smaller version rt3662. They both have a single
gBit port that will normally be attached to an external phy of switch.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <i
rudimentary code to power up the switch. There are a lot of magic values
that get written to the switch and the internal phys. These values come
straight from the SDK driver.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by:
On 22/11/2015 17:36, Andrew Lunn wrote:
> On Sun, Nov 22, 2015 at 09:40:55AM +0100, John Crispin wrote:
>> Add support for SoCs from the rt3050 family. This include rt3050, rt3052,
>> rt3352 and rt5350. These all have a builtin 5 port 100mbit switch. This patch
>> incl
The current code only disables those IRQs that we will later use. To
ensure that we have a predefined state, we really want to disable all IRQs.
Change the code to disable all IRQs to achieve this.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth
The QDMA engine can fail to update the register pointing to the next TX
descriptor if this bit does not get set in the QDMA configuration register.
Not setting this bit can result in invalid values inside the TX rings
registers which will causes TX stalls.
Signed-off-by: John Crispin &l
During stress testing, after reducing the threshold value, we have seen
TX timeouts that were caused by the watchdog_timeo value being too low.
Increase the value to 5 * HZ which is a value commonly used by many other
drivers.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drive
Scratch memory gets allocated in mtk_init_fq_dma() but the corresponding
code to free it is missing inside mtk_dma_free() causing a memory leak.
With this patch applied, we can run ifconfig up/down several thousand
times without any problems.
Signed-off-by: John Crispin <j...@phrozen.
.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 93af4e3..8b289e1 100644
--- a/d
This series contains various small fixes that we stumbled across while
doing thorough testing and code level reviewing of the driver. The only
patch that sticks out is the first one, which addresses a DQL related
issue. The rest are just minor fixes.
John Crispin (12):
net: mediatek: fix DQL
The lookup of the tx_buffer in the error path inside mtk_tx_map() uses the
wrong descriptor pointer. This looks like a copy & paste error. Change the
code to use the correct pointer.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |2
There are two places inside mtk_poll_rx where rx_dropped is not being
incremented properly. Fix this by adding the missing code to increment
the counter.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |2 ++
1 file changed, 2 inse
housekeeping again. There is no rush in enqueuing the next packet, it
needs to wait for all the others in the queue to be dispatched first
anyway.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |7 ++-
1 file changed, 2 insertions
The TX ring setup has an off by one error causing it to not utilise all
descriptors. This has the side effect that we need to reset the next
pointer at runtime to make it work. Fix the off by one and remove the
code fixing the ring at runtime.
Signed-off-by: John Crispin <j...@phrozen.
The current code unconditionally wakes up the queue at the end of each
tx_poll action. Change the code to only wake up the queues if any of
them have actually been stopped before.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c
On 06/06/2016 14:21, Andrew Lunn wrote:
>> Hi Andrew,
>>
>> it is waiting for the watchdog to trigger :-) TBH the 1s seems to be too
>> short to for the dma ring length to be flushed and i had to pick some
>> value and 5 is used most places.
>>
>> it really depends on the amount of packets in
housekeeping again. There is no rush in enqueuing the next packet, it
needs to wait for all the others in the queue to be dispatched first
anyway.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |7 ++-
1 file changed, 2 insertions
The TX ring setup has an off by one error causing it to not utilise all
descriptors. This has the side effect that we need to reset the next
pointer at runtime to make it work. Fix the off by one and remove the
code fixing the ring at runtime.
Signed-off-by: John Crispin <j...@phrozen.
During stress testing, after reducing the threshold value, we have seen
TX timeouts that were caused by the watchdog_timeo value being too low.
Increase the value to 5 * HZ which is a value commonly used by many other
drivers.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drive
.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 93af4e3..8b289e1 100644
--- a/d
Scratch memory gets allocated in mtk_init_fq_dma() but the corresponding
code to free it is missing inside mtk_dma_free() causing a memory leak.
With this patch applied, we can run ifconfig up/down several thousand
times without any problems.
Signed-off-by: John Crispin <j...@phrozen.
The QDMA engine can fail to update the register pointing to the next TX
descriptor if this bit does not get set in the QDMA configuration register.
Not setting this bit can result in invalid values inside the TX rings
registers which will causes TX stalls.
Signed-off-by: John Crispin &l
The current code only disables those IRQs that we will later use. To
ensure that we have a predefined state, we really want to disable all IRQs.
Change the code to disable all IRQs to achieve this.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth
The code fails to check if the scratch memory was properly allocated. Add
this check and return with an error if the allocation failed.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/d
On 10/06/2016 13:27, John Crispin wrote:
> This series contains various small fixes that we stumbled across while
> doing thorough testing and code level reviewing of the driver. The only
> patch that sticks out is the first one, which addresses a DQL related
> issue. The rest ar
the list until a better solution is found
John Crispin (11):
net: mediatek: add missing return code check
net: mediatek: fix missing free of scratch memory
net: mediatek: invalid buffer lookup in mtk_tx_map()
net: mediatek: dropped rx packets are not being counted properly
net: mediatek: add
The lookup of the tx_buffer in the error path inside mtk_tx_map() uses the
wrong descriptor pointer. This looks like a copy & paste error. Change the
code to use the correct pointer.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |2
The current code unconditionally wakes up the queue at the end of each
tx_poll action. Change the code to only wake up the queues if any of
them have actually been stopped before.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c
On 10/06/2016 19:46, David Miller wrote:
> From: John Crispin <j...@phrozen.org>
> Date: Fri, 10 Jun 2016 13:30:15 +0200
>
>>
>>
>> On 10/06/2016 13:27, John Crispin wrote:
>>> This series contains various small fixes that we stumbled across while
The driver currently uses kfree() to clear the mii_bus. This is not the
correct way to clear the memory and mdiobus_free() should be used instead.
This patch fixes the two instances where this happens in the driver.
Reviewed-by: Andrew Lunn <and...@lunn.ch>
Signed-off-by: John Cris
driver needs to be adapted to handle all 3 rgmii-*id modes
in the same way as normal rgmii when setting up the MAC.
Reviewed-by: Andrew Lunn <and...@lunn.ch>
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |3 +++
1 file changed,
Lunn <and...@lunn.ch>
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index b0652f6..23
The current code will not setup the PHYs advertisement features correctly.
Fix this and properly advertise Gigabit features and properly handle
asymmetric pause frames.
Signed-off-by: Sean Wang <keyha...@gmail.com>
Signed-off-by: John Crispin <j...@phrozen.org>
---
Changes
The current driver did not handle the RGMII delay modes and asymmetric flow
control properly. The mii_bus is not freed properly. Also add support for
fixed-phy allowing the driver to work on SoCs that have an internal gigabit
switch.
John Crispin (4):
net-next: mediatek: use mdiobus_free
Hi Thomas
Hi Hauke
On 04/06/2016 16:43, Langer, Thomas wrote:
>> + /* there is an errata regarding irqs in this rev */
> And then this is comment is also now valid.
> What about a system with a single external phy connected,
> on a non-Lantiq/Intel SoC?
>
> I think the feasibility of
There are two places inside mtk_poll_rx where rx_dropped is not being
incremented properly. Fix this by adding the missing code to increment
the counter.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |2 ++
1 file changed, 2 inse
handler.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 156 +--
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 15 ++-
2 files changed, 111 insertions(+), 60 deletions(-)
diff --git a/drivers/net/ethernet/me
remove the intermediate variables.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
b/drivers/net/et
-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |4
1 file changed, 4 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index ebfca7d..b3032f4 100644
--- a/drivers/net/ethernet/me
The code that enables and disables IRQs is missing proper locking. After
adding the IRQ grouping patch and routing the RX and TX IRQs to different
cores we experienced IRQ stalls. Fix this by adding proper locking.
We use a dedicated lock to reduce the latency if the IRQ code.
Signed-off-by: John
allows us to use different IRQs for TX and RX. By doing so we can
use affinity to let the SoC handle the IRQs on different cores.
John Crispin (4):
net-next: mediatek: remove superfluous register reads
net-next: mediatek: don't use intermediate variables to store IRQ
masks
net-next
The code fails to check if the scratch memory was properly allocated. Add
this check and return with an error if the allocation failed.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/d
as the traffic of the other device.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 33 ---
1 file changed, 20 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
b/drivers/net/et
On 05/06/2016 16:56, Andrew Lunn wrote:
> On Sun, Jun 05, 2016 at 08:33:02AM +0200, John Crispin wrote:
>> During stress testing, after reducing the threshold value, we have seen
>> TX timeouts that were caused by the watchdog_timeo value being too low.
>> Increase the
On 05/06/2016 09:32, David Miller wrote:
> From: John Crispin <j...@phrozen.org>
> Date: Sun, 5 Jun 2016 08:32:54 +0200
>
>> @@ -625,7 +625,16 @@ static int mtk_tx_map(struct sk_buff *skb, struct
>> net_device *dev,
>> WRITE_ONCE(itxd->txd3, (TX_DM
On 09/06/2016 08:06, Alexander Stein wrote:
> On Wednesday 08 June 2016 14:30:08, Rob Herring wrote:
>>> diff --git a/Documentation/devicetree/bindings/phy/phy-leds.txt
>>> b/Documentation/devicetree/bindings/phy/phy-leds.txt new file mode 100644
>>> index 000..1a35e3d
>>> --- /dev/null
>>>
On 16/06/2016 07:20, David Miller wrote:
> From: John Crispin <j...@phrozen.org>
> Date: Wed, 15 Jun 2016 16:58:46 +0200
>
>> This series contains 2 small code cleanups that are leftovers from the
>> MIPS support. There is also a small fix that adds proper locki
and only provides basic init and irq support.
The SoC and switch core both have support for a special tag making DSA
support possible.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
drivers/net/ethernet/mediatek/gsw_mt7620.c | 256 +
drivers/net/ethernet/mediatek/gsw_mt
internally. I have not had time yet to look at these new features in
detail.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <igv...@gmail.com>
---
drivers/net/ethernet/mediatek/s
.
On device testing has however shown that this does not work reliably so we
do not enable it.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <igv...@gmail.com>
---
drivers/net/ethernet/mediatek/md
SoC to have the new QDMA engine builtin. The older PDMA engine is
also present. unfortunatley, to get the best performance we need to run RX
on PDMA and TX on QDMA. This SoC is also the first to have TX vlan
offloading and TSO6 support.
Signed-off-by: John Crispin <blo...@openwrt.org>
Sign
and will be part of a later series once we evaluated if we want to
use DSA or switchdev.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <igv...@gmail.com>
---
drivers/net/ethernet/mediatek/md
Add three files. One describes the actual frame engine, the other two
describe fast ethernet and gigabit switches bindings.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <igv...@gmail.com>
Cc: devicet.
mplied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blo...@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <n...@openwrt.org>
+ * Copyright (C)
Changes in V2
* change the namespace of the functions from fe_* to mtk_*
* add support for the latest generation of ARM SoCs
* add dual MAC support
* remove the swconfig specific bits
* remove most of the magic values and replace them with defines
* add verbose descriptions to the patches
John Crispin
there is a MDIO bus that can be used to talk to PHYs. In these
cases one switch port get changed into a normal MAC port.
Some SoCs have a dual MAC, we currently only support this on MT7623.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
added support. RT3883 is somewhat unique as it is the only SoC made
by Ralink that uses the mips74 core.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <igv...@gmail.com>
---
drivers/net/ethernet/med
cost device, that had seen some changes in the
reset bits and register layout. However as the difference are rather minor
support for all of these is in the same driver. OpenWrt builds generic
images where the kernel works on all of the SoCs listed above.
Signed-off-by: John Crispin <
Add myself and Felix as the Maintainers for the driver.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
---
MAINTAINERS |7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 156e1d3..4a
On 26/02/2016 16:18, Andrew Lunn wrote:
> On Fri, Feb 26, 2016 at 03:21:35PM +0100, John Crispin wrote:
>> The ESW is found in many of the old 100mbit MIPS based SoCs. it has 5
>> external ports, 1 cpu port and 1 further port that the internal HW
>> offlo
This patch adds the Makefile and Kconfig required to make the driver build.
Signed-off-by: John Crispin <blo...@openwrt.org>
Signed-off-by: Felix Fietkau <n...@openwrt.org>
Signed-off-by: Michael Lee <igv...@gmail.com>
---
drivers/net/ethernet/Kconfig |1 +
dr
Hi,
Dave merged the V6 of the MediaTek ethernet driver. However in
linux-next I can see the correct devicetree binding aswell as the
obseleted version of the binding docs from the V1 series. The following
files should not be there.
On 15/03/2016 08:19, Dan Carpenter wrote:
> There was a missing unlock on the error path.
>
> Fixes: 656e705243fd ('net-next: mediatek: add support for MT7623 ethernet')
> Signed-off-by: Dan Carpenter <dan.carpen...@oracle.com>
>
Acked-by: John Crispin <blo...@openwr
On 15/03/2016 08:18, Dan Carpenter wrote:
> of_phy_connect() returns NULL on error, it never returns error pointers.
>
> Fixes: 656e705243fd ('net-next: mediatek: add support for MT7623 ethernet')
> Signed-off-by: Dan Carpenter <dan.carpen...@oracle.com>
>
Acked-
On 14/03/2016 15:07, Arnd Bergmann wrote:
> dma_alloc_coherent() expects a dma_addr_t pointer as its argument,
> not an 'unsigned int', and gcc correctly warns about broken
> code in the mtk_init_fq_dma function:
>
> drivers/net/ethernet/mediatek/mtk_eth_soc.c: In function 'mtk_init_fq_dma':
>
. This happens as there are 2 netdevs running on the
same physical DMA ring.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/me
The current binding document only describes a single interrupt. Update the
document by adding the 2 other interrupts.
The driver currently only uses a single interrupt. The HW is however able
to using IRQ grouping to split TX and RX onto separate GIC irqs.
Signed-off-by: John Crispin <
The code used to also support the PDMA engine, which had 2 packet pointers
per descriptor. Because of this we had to divide the result by 2 and round
it up. This is no longer needed as the code only supports QDMA.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
drivers/net/ethernet/me
The original commit failed to set watchdog_timeo. This patch sets
watchdog_timeo to HZ.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
b/d
The driver supports 2 MACs. Both run on the same DMA ring. If we hit a TX
timeout we need to stop both netdevs before restarting them again. If we
don't do this, mtk_stop() wont shutdown DMA and the consecutive call to
mtk_open() wont restart DMA and enable IRQs.
Signed-off-by: John Crispin <
HW reset is triggered in the mtk_hw_init() function. There is no need to
also reset the core during probe.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |4
1 file changed, 4 deletions(-)
diff --git a/drivers/net/ethernet/me
The worker always touches both netdevs. It is ethernet core and not MAC
specific. We only need one worker, which belongs into the ethernets core
struct.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 10 --
drivers/net/et
The driver supports 2 MACs. Both run on the same DMA ring. If we go
above/below the TX rings threshold value, we always need to wake/stop
the queue of both devices. Not doing to can cause TX stalls and packet
drops on one of the devices.
Signed-off-by: John Crispin <blo...@openwrt.
of
the upstream driver yet.
This patch removes the code setting the QID field, resulting in all
traffic ending up in queue 0 which works without any special setup.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |3 +--
1 file changed, 1 ins
. Instead we use a tasklet to handle housekeeping.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 115 +--
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 12 ++-
2 files changed, 86 insertions(+), 41 deletions(-)
. This happens as there are 2 netdevs running on the
same physical DMA ring.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/me
The current binding document only describes a single interrupt. Update the
document by adding the 2 other interrupts.
The driver currently only uses a single interrupt. The HW is however able
to using IRQ grouping to split TX and RX onto separate GIC irqs.
Signed-off-by: John Crispin <
The driver supports 2 MACs. Both run on the same DMA ring. If we go
above/below the TX rings threshold value, we always need to wake/stop
the queue of both devices. Not doing to can cause TX stalls and packet
drops on one of the devices.
Signed-off-by: John Crispin <blo...@openwrt.
The code used to also support the PDMA engine, which had 2 packet pointers
per descriptor. Because of this we had to divide the result by 2 and round
it up. This is no longer needed as the code only supports QDMA.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
drivers/net/ethernet/me
The original commit failed to set watchdog_timeo. This patch sets
watchdog_timeo to HZ.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
b/d
The driver supports 2 MACs. Both run on the same DMA ring. If we hit a TX
timeout we need to stop both netdevs before restarting them again. If we
don't do this, mtk_stop() wont shutdown DMA and the consecutive call to
mtk_open() wont restart DMA and enable IRQs.
Signed-off-by: John Crispin <
patch applied to randomly stop
irqs and/or one of the queues and successfully manages to recover from these
simulated tx stalls.
John Crispin (8):
net: mediatek: watchdog_timeo was not set
net: mediatek: mtk_cal_txd_req() returns bad value
net: mediatek: remove superfluous reset call
net
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