Hi Florian,
Sorry for reply late.
在 2017/6/24 0:22, Florian Fainelli 写道:
On 06/22/2017 09:59 PM, David Wu wrote:
To make internal phy worked, need to configure the phy_clock,
phy cru_reset and related registers.
Change-Id: I6971c0a769754b824b1b908b56080cbaf7867d13
Signed-off-by: David Wu
---
Hi Heiko,
在 2017/6/24 1:19, Heiko Stuebner 写道:
Hi David,
Am Freitag, 23. Juni 2017, 12:59:07 CEST schrieb David Wu:
To make internal phy worked, need to configure the phy_clock,
phy cru_reset and related registers.
Change-Id: I6971c0a769754b824b1b908b56080cbaf7867d13
please remove all Chang
Hi Andrew,
在 2017/6/24 10:19, Andrew Lunn 写道:
On Fri, Jun 23, 2017 at 12:41:59PM +0800, David Wu wrote:
Support internal ephy currently.
Signed-off-by: David Wu
---
drivers/net/phy/Kconfig| 4 ++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/rockchip.c | 94 +
Hi Andrew,
在 2017/6/27 22:46, Andrew Lunn 写道:
it has been licensed from somebody.
And does that somebody already have a driver for it? There is no point
adding a driver, if all you need to do is add the ID to another
driver.
I didn't find it.
Maybe use the same, but the configuration is dif
Hi Andrew,
在 2017/6/24 10:29, Andrew Lunn 写道:
If this is the PHY clock, should it actually be specified in the PHY
binding? Can you read the PHY ID registers with this clock off?
If the phy clock is closed, we can not read the PHYID.
Hi Andrew,
在 2017/7/27 21:48, Andrew Lunn 写道:
I think we need to discuss this. This PHY appears to be on an MDIO
bus, it uses a standard PHY driver, and it appears to be using an RMII
interface. So it is just an ordinary PHY.
Internal is supposed to be something which is not ordinary, does not
Hi Florian,
在 2017/7/28 0:54, Florian Fainelli 写道:
- if you need knowledge about this PHY connection type prior to binding
the PHY device and its driver (that is, before of_phy_connect()) we
could add a boolean property e.g: "phy-is-internal" that allows us to
know that, or we can have a new phy
Hi Andrew,
在 2017/7/27 21:38, Andrew Lunn 写道:
+ /*
+* If mode switch happens from 10BT to 100BT, all DSP/AFE
+* registers are set to default values. So any AFE/DSP
+* registers have to be re-initialized in this case.
+*/
Hi David
Are they also lost on sus
Hi Florian,
在 2017/7/28 0:51, Florian Fainelli 写道:
+}
+
+static int rockchip_internal_phy_config_init(struct phy_device *phydev)
+{
+ int val;
+
+ /*
+* The auto MIDX has linked problem on some board,
+* workround to disable auto MDIX.
+*/
If this a board-spe
Hi Florian & ChenYu
在 2017/8/3 1:38, Florian Fainelli 写道:
This is incorrect in two ways:
- this is a property of the PHY, so it should be documented as such in
Documentation/devicetree/bindings/net/phy.txt so other bindings can
re-use it
- if it was specific to your MAC you would expect a vend
Hi Andrew,
在 2017/8/2 21:21, Andrew Lunn 写道:
+static struct phy_driver rockchip_phy_driver[] = {
+{
+ .phy_id = 0x1234d400,
+ .phy_id_mask= 0xfff0,
+ .name = "Rockchip internal EPHY",
+ .features = (PHY_BASIC
Hello Corentin, Chen-Yu
在 2017/8/9 16:45, Corentin Labbe 写道:
On Thu, Aug 03, 2017 at 07:06:33PM +0800, Chen-Yu Tsai wrote:
On Thu, Aug 3, 2017 at 1:38 AM, Florian Fainelli wrote:
On 08/01/2017 11:21 PM, David Wu wrote:
To make internal phy work, need to configure the phy_clock,
phy cru_reset
Hi Chen-Yu,
在 2017/8/10 10:40, Chen-Yu Tsai 写道:
Hi David,
On Wed, Aug 9, 2017 at 5:38 PM, David.Wu wrote:
Hello Corentin, Chen-Yu
在 2017/8/9 16:45, Corentin Labbe 写道:
On Thu, Aug 03, 2017 at 07:06:33PM +0800, Chen-Yu Tsai wrote:
On Thu, Aug 3, 2017 at 1:38 AM, Florian Fainelli
wrote
Hi Andrew, Florian
在 2017/8/10 8:20, Andrew Lunn 写道:
Hi Florian, David.
I'm happy with the property name. But i think the text needs more
description. We deal with Ethernet switches with integrated PHYs. Yet
for us, this property is unneeded.
Seeing this property means some bit of software nee
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