Re: [PATCH] net: ethernet: mediatek: Add MT7628/88 SoC support
Hi Rene, On 14.08.19 15:08, René van Dorst wrote: Quoting Stefan Roese : Hi Rene, On 14.08.19 11:26, René van Dorst wrote: Great, Thanks for addressing this issue. I hope we can collaborate to also support mt76x8 in my PHYLINK patches [0][1]. I am close to posting V2 of the patches but I am currently waiting on some fiber modules to test the changes better. I do have a "hackish" DSA driver for the integrated switch (ESW) in my tree. If time permits, I'll work on upstreaming this one as well. And yes, hopefully we can collaborate on your PHYLINK work too. It is not only the switch driver but also the Mediatek ethernet driver that is converted to PHYLINK. So we have a conflict in each others work. Yes, I am aware of this. I don't no what the right way is to go but I was thinking about 2 options 1. Lets say your work goes in first. I rebase my patches on your changes. We collaborate to create an extra PHYLINK patch ontop of my work for your SOC. 2. My patches goes in first and you adapt your patches to that. What do you think? It really depends on the timing, when the patches arrive in the kernel (net-next). If yours makes it first, I'll rebase my patch on top of your work. Otherwise you will need to rebase yours. I have latest changes here [0]. Also my modules did arrive so I can test my changes. Thanks, Stefan
Re: [PATCH] net: ethernet: mediatek: Add MT7628/88 SoC support
Hi Stefan, Quoting Stefan Roese : Hi Rene, On 14.08.19 11:26, René van Dorst wrote: Great, Thanks for addressing this issue. I hope we can collaborate to also support mt76x8 in my PHYLINK patches [0][1]. I am close to posting V2 of the patches but I am currently waiting on some fiber modules to test the changes better. I do have a "hackish" DSA driver for the integrated switch (ESW) in my tree. If time permits, I'll work on upstreaming this one as well. And yes, hopefully we can collaborate on your PHYLINK work too. It is not only the switch driver but also the Mediatek ethernet driver that is converted to PHYLINK. So we have a conflict in each others work. I don't no what the right way is to go but I was thinking about 2 options 1. Lets say your work goes in first. I rebase my patches on your changes. We collaborate to create an extra PHYLINK patch ontop of my work for your SOC. 2. My patches goes in first and you adapt your patches to that. What do you think? I have latest changes here [0]. Also my modules did arrive so I can test my changes. Thanks, Stefan Greats, René [0] https://github.com/vDorst/linux-1/commits/net-next-phylink-upstream-mediatek
Re: [PATCH] net: ethernet: mediatek: Add MT7628/88 SoC support
Hi Rene,
On 14.08.19 11:26, René van Dorst wrote:
Hi Stefan,
Quoting Stefan Roese :
Hi Rene,
On 17.07.19 14:53, René van Dorst wrote:
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -39,7 +39,8 @@
NETIF_F_SG | NETIF_F_TSO | \
NETIF_F_TSO6 | \
NETIF_F_IPV6_CSUM)
-#define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
+#define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM)
+#define NEXT_DESP_IDX(X, Y)(((X) + 1) & ((Y) - 1))
#define MTK_MAX_RX_RING_NUM 4
#define MTK_HW_LRO_DMA_SIZE 8
@@ -118,6 +119,7 @@
/* PDMA Global Configuration Register */
#define MTK_PDMA_GLO_CFG 0xa04
#define MTK_MULTI_EN BIT(10)
+#define MTK_PDMA_SIZE_8DWORDS (1 << 4)
/* PDMA Reset Index Register */
#define MTK_PDMA_RST_IDX 0xa08
@@ -276,11 +278,18 @@
#define TX_DMA_OWNER_CPU BIT(31)
#define TX_DMA_LS0BIT(30)
#define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16)
+#define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN)
#define TX_DMA_SWCBIT(14)
#define TX_DMA_SDL(_x)(((_x) & 0x3fff) << 16)
+/* PDMA on MT7628 */
+#define TX_DMA_DONEBIT(31)
+#define TX_DMA_LS1 BIT(14)
+#define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
+
/* QDMA descriptor rxd2 */
#define RX_DMA_DONE BIT(31)
+#define RX_DMA_LSO BIT(30)
#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
@@ -289,6 +298,7 @@
/* QDMA descriptor rxd4 */
#define RX_DMA_L4_VALID BIT(24)
+#define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
#define RX_DMA_FPORT_SHIFT19
#define RX_DMA_FPORT_MASK 0x7
@@ -412,6 +422,19 @@
#define CO_QPHY_SELBIT(0)
#define GEPHY_MAC_SEL BIT(1)
+/* MT7628/88 specific stuff */
+#define MT7628_PDMA_OFFSET 0x0800
+#define MT7628_SDM_OFFSET 0x0c00
+
+#define MT7628_TX_BASE_PTR0(MT7628_PDMA_OFFSET + 0x00)
+#define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04)
+#define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08)
+#define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c)
+#define MT7628_PST_DTX_IDX0BIT(0)
+
+#define MT7628_SDM_MAC_ADRL(MT7628_SDM_OFFSET + 0x0c)
+#define MT7628_SDM_MAC_ADRH(MT7628_SDM_OFFSET + 0x10)
+
struct mtk_rx_dma {
unsigned int rxd1;
unsigned int rxd2;
@@ -509,6 +532,7 @@ enum mtk_clks_map {
BIT(MTK_CLK_SGMII_CK) | \
BIT(MTK_CLK_ETH2PLL))
#define MT7621_CLKS_BITMAP(0)
+#define MT7628_CLKS_BITMAP (0)
#define MT7629_CLKS_BITMAP(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
@@ -563,6 +587,10 @@ struct mtk_tx_ring {
struct mtk_tx_dma *last_free;
u16 thresh;
atomic_t free_count;
+ int dma_size;
+ struct mtk_tx_dma *dma_pdma;/* For MT7628/88 PDMA handling */
+ dma_addr_t phys_pdma;
+ int cpu_idx;
};
/* PDMA rx ring mode */
@@ -604,6 +632,7 @@ enum mkt_eth_capabilities {
MTK_HWLRO_BIT,
MTK_SHARED_INT_BIT,
MTK_TRGMII_MT7621_CLK_BIT,
+ MTK_SOC_MT7628,
This should be MTK_SOC_MT7628_BIT, this only defines the bit number!
and futher on #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
Okay, thanks.
Based on this commit [0], MT7621 also needs the PDMA for the RX path.
I know that is not your issue but I think it is better to add a extra
capability bit for the PDMA bits so it can also be used on other socs.
Yes, MT7621 also uses PDMA for RX. The code for RX is pretty much
shared (re-used), with slight changes for the MT7628/88 to work
correctly on this SoC.
I'll work on a capability bit for PDMA vs QDMA on TX though. This
might make things a little more transparent.
Great, Thanks for addressing this issue.
I hope we can collaborate to also support mt76x8 in my PHYLINK patches [0][1].
I am close to posting V2 of the patches but I am currently waiting on some
fiber modules to test the changes better.
I do have a "hackish" DSA driver for the integrated switch (ESW) in my
tree. If time permits, I'll work on upstreaming this one as well. And
yes, hopefully we can collaborate on your PHYLINK work too.
Thanks,
Stefan
Re: [PATCH] net: ethernet: mediatek: Add MT7628/88 SoC support
Hi Stefan,
Quoting Stefan Roese :
Hi Rene,
On 17.07.19 14:53, René van Dorst wrote:
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -39,7 +39,8 @@
NETIF_F_SG | NETIF_F_TSO | \
NETIF_F_TSO6 | \
NETIF_F_IPV6_CSUM)
-#define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
+#define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM)
+#define NEXT_DESP_IDX(X, Y)(((X) + 1) & ((Y) - 1))
#define MTK_MAX_RX_RING_NUM4
#define MTK_HW_LRO_DMA_SIZE8
@@ -118,6 +119,7 @@
/* PDMA Global Configuration Register */
#define MTK_PDMA_GLO_CFG 0xa04
#define MTK_MULTI_EN BIT(10)
+#define MTK_PDMA_SIZE_8DWORDS (1 << 4)
/* PDMA Reset Index Register */
#define MTK_PDMA_RST_IDX 0xa08
@@ -276,11 +278,18 @@
#define TX_DMA_OWNER_CPU BIT(31)
#define TX_DMA_LS0 BIT(30)
#define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16)
+#define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN)
#define TX_DMA_SWC BIT(14)
#define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16)
+/* PDMA on MT7628 */
+#define TX_DMA_DONEBIT(31)
+#define TX_DMA_LS1 BIT(14)
+#define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
+
/* QDMA descriptor rxd2 */
#define RX_DMA_DONEBIT(31)
+#define RX_DMA_LSO BIT(30)
#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
@@ -289,6 +298,7 @@
/* QDMA descriptor rxd4 */
#define RX_DMA_L4_VALIDBIT(24)
+#define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
#define RX_DMA_FPORT_SHIFT 19
#define RX_DMA_FPORT_MASK 0x7
@@ -412,6 +422,19 @@
#define CO_QPHY_SELBIT(0)
#define GEPHY_MAC_SEL BIT(1)
+/* MT7628/88 specific stuff */
+#define MT7628_PDMA_OFFSET 0x0800
+#define MT7628_SDM_OFFSET 0x0c00
+
+#define MT7628_TX_BASE_PTR0(MT7628_PDMA_OFFSET + 0x00)
+#define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04)
+#define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08)
+#define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c)
+#define MT7628_PST_DTX_IDX0BIT(0)
+
+#define MT7628_SDM_MAC_ADRL(MT7628_SDM_OFFSET + 0x0c)
+#define MT7628_SDM_MAC_ADRH(MT7628_SDM_OFFSET + 0x10)
+
struct mtk_rx_dma {
unsigned int rxd1;
unsigned int rxd2;
@@ -509,6 +532,7 @@ enum mtk_clks_map {
BIT(MTK_CLK_SGMII_CK) | \
BIT(MTK_CLK_ETH2PLL))
#define MT7621_CLKS_BITMAP (0)
+#define MT7628_CLKS_BITMAP (0)
#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
@@ -563,6 +587,10 @@ struct mtk_tx_ring {
struct mtk_tx_dma *last_free;
u16 thresh;
atomic_t free_count;
+ int dma_size;
+ struct mtk_tx_dma *dma_pdma;/* For MT7628/88 PDMA handling */
+ dma_addr_t phys_pdma;
+ int cpu_idx;
};
/* PDMA rx ring mode */
@@ -604,6 +632,7 @@ enum mkt_eth_capabilities {
MTK_HWLRO_BIT,
MTK_SHARED_INT_BIT,
MTK_TRGMII_MT7621_CLK_BIT,
+ MTK_SOC_MT7628,
This should be MTK_SOC_MT7628_BIT, this only defines the bit number!
and futher on #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
Okay, thanks.
Based on this commit [0], MT7621 also needs the PDMA for the RX path.
I know that is not your issue but I think it is better to add a extra
capability bit for the PDMA bits so it can also be used on other socs.
Yes, MT7621 also uses PDMA for RX. The code for RX is pretty much
shared (re-used), with slight changes for the MT7628/88 to work
correctly on this SoC.
I'll work on a capability bit for PDMA vs QDMA on TX though. This
might make things a little more transparent.
Great, Thanks for addressing this issue.
I hope we can collaborate to also support mt76x8 in my PHYLINK patches [0][1].
I am close to posting V2 of the patches but I am currently waiting on some
fiber modules to test the changes better.
Greats,
René
[0] https://patchwork.ozlabs.org/patch/1136551/
[1] https://patchwork.ozlabs.org/patch/1136519/
Greats,
René
[0] https://lkml.org/lkml/2018/3/14/1038
Thanks,
Stefan
Re: [PATCH] net: ethernet: mediatek: Add MT7628/88 SoC support
Hi Rene,
On 17.07.19 14:53, René van Dorst wrote:
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -39,7 +39,8 @@
NETIF_F_SG | NETIF_F_TSO | \
NETIF_F_TSO6 | \
NETIF_F_IPV6_CSUM)
-#define NEXT_RX_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
+#define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM)
+#define NEXT_DESP_IDX(X, Y)(((X) + 1) & ((Y) - 1))
#define MTK_MAX_RX_RING_NUM 4
#define MTK_HW_LRO_DMA_SIZE 8
@@ -118,6 +119,7 @@
/* PDMA Global Configuration Register */
#define MTK_PDMA_GLO_CFG 0xa04
#define MTK_MULTI_EN BIT(10)
+#define MTK_PDMA_SIZE_8DWORDS (1 << 4)
/* PDMA Reset Index Register */
#define MTK_PDMA_RST_IDX 0xa08
@@ -276,11 +278,18 @@
#define TX_DMA_OWNER_CPU BIT(31)
#define TX_DMA_LS0BIT(30)
#define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16)
+#define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN)
#define TX_DMA_SWCBIT(14)
#define TX_DMA_SDL(_x)(((_x) & 0x3fff) << 16)
+/* PDMA on MT7628 */
+#define TX_DMA_DONEBIT(31)
+#define TX_DMA_LS1 BIT(14)
+#define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
+
/* QDMA descriptor rxd2 */
#define RX_DMA_DONE BIT(31)
+#define RX_DMA_LSO BIT(30)
#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
@@ -289,6 +298,7 @@
/* QDMA descriptor rxd4 */
#define RX_DMA_L4_VALID BIT(24)
+#define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
#define RX_DMA_FPORT_SHIFT19
#define RX_DMA_FPORT_MASK 0x7
@@ -412,6 +422,19 @@
#define CO_QPHY_SELBIT(0)
#define GEPHY_MAC_SEL BIT(1)
+/* MT7628/88 specific stuff */
+#define MT7628_PDMA_OFFSET 0x0800
+#define MT7628_SDM_OFFSET 0x0c00
+
+#define MT7628_TX_BASE_PTR0(MT7628_PDMA_OFFSET + 0x00)
+#define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04)
+#define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08)
+#define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c)
+#define MT7628_PST_DTX_IDX0BIT(0)
+
+#define MT7628_SDM_MAC_ADRL(MT7628_SDM_OFFSET + 0x0c)
+#define MT7628_SDM_MAC_ADRH(MT7628_SDM_OFFSET + 0x10)
+
struct mtk_rx_dma {
unsigned int rxd1;
unsigned int rxd2;
@@ -509,6 +532,7 @@ enum mtk_clks_map {
BIT(MTK_CLK_SGMII_CK) | \
BIT(MTK_CLK_ETH2PLL))
#define MT7621_CLKS_BITMAP(0)
+#define MT7628_CLKS_BITMAP (0)
#define MT7629_CLKS_BITMAP(BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
@@ -563,6 +587,10 @@ struct mtk_tx_ring {
struct mtk_tx_dma *last_free;
u16 thresh;
atomic_t free_count;
+ int dma_size;
+ struct mtk_tx_dma *dma_pdma;/* For MT7628/88 PDMA handling */
+ dma_addr_t phys_pdma;
+ int cpu_idx;
};
/* PDMA rx ring mode */
@@ -604,6 +632,7 @@ enum mkt_eth_capabilities {
MTK_HWLRO_BIT,
MTK_SHARED_INT_BIT,
MTK_TRGMII_MT7621_CLK_BIT,
+ MTK_SOC_MT7628,
This should be MTK_SOC_MT7628_BIT, this only defines the bit number!
and futher on #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
Okay, thanks.
Based on this commit [0], MT7621 also needs the PDMA for the RX path.
I know that is not your issue but I think it is better to add a extra
capability bit for the PDMA bits so it can also be used on other socs.
Yes, MT7621 also uses PDMA for RX. The code for RX is pretty much
shared (re-used), with slight changes for the MT7628/88 to work
correctly on this SoC.
I'll work on a capability bit for PDMA vs QDMA on TX though. This
might make things a little more transparent.
Greats,
René
[0] https://lkml.org/lkml/2018/3/14/1038
Thanks,
Stefan
Re: [PATCH] net: ethernet: mediatek: Add MT7628/88 SoC support
On 17.07.19 14:15, Daniel Golle wrote: On Wed, Jul 17, 2019 at 01:02:43PM +0200, Stefan Roese wrote: This patch adds support for the MediaTek MT7628/88 SoCs to the common MediaTek ethernet driver. Some minor changes are needed for this and a bigger change, as the MT7628 does not support QDMA (only PDMA). The Ethernet core found in MT7628/88 is identical to that found in Ralink Rt5350F SoC. Wouldn't it hence make sense to indicate that in the compatible string of this driver as well? In OpenWrt we are using "ralink,rt5350-eth". Okay. I'll use this ralink compatible instead in the next version. Thanks, Stefan
Re: [PATCH] net: ethernet: mediatek: Add MT7628/88 SoC support
Hi Stefan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on next-20190718]
[cannot apply to v5.2]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Stefan-Roese/net-ethernet-mediatek-Add-MT7628-88-SoC-support/20190719-020931
config: arm64-allmodconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 7.4.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
All warnings (new ones prefixed by >>):
vim +649 drivers/net//ethernet/mediatek/mtk_eth_soc.c
646
647 static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma)
648 {
> 649 return ((u32)dma - (u32)ring->dma) / sizeof(*dma);
650 }
651
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
Re: [PATCH] net: ethernet: mediatek: Add MT7628/88 SoC support
On 17.07.19 14:15, Daniel Golle wrote:
On Wed, Jul 17, 2019 at 01:02:43PM +0200, Stefan Roese wrote:
This patch adds support for the MediaTek MT7628/88 SoCs to the common
MediaTek ethernet driver. Some minor changes are needed for this and
a bigger change, as the MT7628 does not support QDMA (only PDMA).
The Ethernet core found in MT7628/88 is identical to that found in
Ralink Rt5350F SoC. Wouldn't it hence make sense to indicate that
in the compatible string of this driver as well? In OpenWrt we are
using "ralink,rt5350-eth".
Yes sure, I can switch back to the original compatible string.
I'm on vacation for a bit over 2 weeks now and will try to address
all review comments after that.
Thanks,
Stefan
Signed-off-by: Stefan Roese
Cc: René van Dorst
Cc: Sean Wang
Cc: Felix Fietkau
Cc: John Crispin
---
.../devicetree/bindings/net/mediatek-net.txt | 1 +
drivers/net/ethernet/mediatek/mtk_eth_path.c | 4 +
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 490 ++
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 39 +-
4 files changed, 424 insertions(+), 110 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt
b/Documentation/devicetree/bindings/net/mediatek-net.txt
index 770ff98d4524..ec6793562148 100644
--- a/Documentation/devicetree/bindings/net/mediatek-net.txt
+++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
@@ -11,6 +11,7 @@ Required properties:
"mediatek,mt2701-eth": for MT2701 SoC
"mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
"mediatek,mt7622-eth": for MT7622 SoC
+ "mediatek,mt7628-eth": for MT7628/88 SoC
"mediatek,mt7629-eth": for MT7629 SoC
- reg: Address and length of the register set for the device
- interrupts: Should contain the three frame engines interrupts in numeric
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_path.c
b/drivers/net/ethernet/mediatek/mtk_eth_path.c
index 7f05880cf9ef..28960e4c4e43 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
@@ -315,6 +315,10 @@ int mtk_setup_hw_path(struct mtk_eth *eth, int mac_id, int
phymode)
{
int err;
+ /* No mux'ing for MT7628/88 */
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
+ return 0;
+
switch (phymode) {
case PHY_INTERFACE_MODE_TRGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index b20b3a5a1ebb..1f248ef6ef88 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -323,11 +323,14 @@ static int mtk_phy_connect(struct net_device *dev)
goto err_phy;
}
- /* put the gmac into the right mode */
- regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
- val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
- val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
- regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
+ /* No MT7628/88 support for now */
+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
+ /* put the gmac into the right mode */
+ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
+ val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
+ val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
+ regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
+ }
/* couple phydev to net_device */
if (mtk_phy_connect_node(eth, mac, np))
@@ -395,8 +398,8 @@ static inline void mtk_tx_irq_disable(struct mtk_eth *eth,
u32 mask)
u32 val;
spin_lock_irqsave(ð->tx_irq_lock, flags);
- val = mtk_r32(eth, MTK_QDMA_INT_MASK);
- mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
+ val = mtk_r32(eth, eth->tx_int_mask_reg);
+ mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg);
spin_unlock_irqrestore(ð->tx_irq_lock, flags);
}
@@ -406,8 +409,8 @@ static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
u32 val;
spin_lock_irqsave(ð->tx_irq_lock, flags);
- val = mtk_r32(eth, MTK_QDMA_INT_MASK);
- mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
+ val = mtk_r32(eth, eth->tx_int_mask_reg);
+ mtk_w32(eth, val | mask, eth->tx_int_mask_reg);
spin_unlock_irqrestore(ð->tx_irq_lock, flags);
}
@@ -437,6 +440,7 @@ static int mtk_set_mac_address(struct net_device *dev, void *p)
{
int ret = eth_mac_addr(dev, p);
struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
const char *macaddr = dev->dev_addr;
if (ret)
@@ -446,11 +450,19 @@ static int mtk_set_mac_address(struct net_device *dev,
void *p)
return -EBUSY;
spin_lock_bh(&mac->hw->page_lock);
- mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
- MTK_GDMA_MAC
Re: [PATCH] net: ethernet: mediatek: Add MT7628/88 SoC support
From: Stefan Roese Date: Wed, 17 Jul 2019 13:02:43 +0200 > This patch adds support for the MediaTek MT7628/88 SoCs to the common > MediaTek ethernet driver. Some minor changes are needed for this and > a bigger change, as the MT7628 does not support QDMA (only PDMA). > > Signed-off-by: Stefan Roese Besides the feedback you've received, this kind of change is only appropriate for the net-next tree at this time. If you wish to keep sending versions for review until the net-next tree opens back up, clearly indicate in your Subject line by saying "[PATCH RFC ...]" or similar. Thank you.
Re: [PATCH] net: ethernet: mediatek: Add MT7628/88 SoC support
Quoting Stefan Roese :
Hi Stefan,
So comments below.
This patch adds support for the MediaTek MT7628/88 SoCs to the common
MediaTek ethernet driver. Some minor changes are needed for this and
a bigger change, as the MT7628 does not support QDMA (only PDMA).
Signed-off-by: Stefan Roese
Cc: René van Dorst
Cc: Sean Wang
Cc: Felix Fietkau
Cc: John Crispin
---
.../devicetree/bindings/net/mediatek-net.txt | 1 +
drivers/net/ethernet/mediatek/mtk_eth_path.c | 4 +
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 490 ++
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 39 +-
4 files changed, 424 insertions(+), 110 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt
b/Documentation/devicetree/bindings/net/mediatek-net.txt
index 770ff98d4524..ec6793562148 100644
--- a/Documentation/devicetree/bindings/net/mediatek-net.txt
+++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
@@ -11,6 +11,7 @@ Required properties:
"mediatek,mt2701-eth": for MT2701 SoC
"mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
"mediatek,mt7622-eth": for MT7622 SoC
+ "mediatek,mt7628-eth": for MT7628/88 SoC
"mediatek,mt7629-eth": for MT7629 SoC
- reg: Address and length of the register set for the device
- interrupts: Should contain the three frame engines interrupts in numeric
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_path.c
b/drivers/net/ethernet/mediatek/mtk_eth_path.c
index 7f05880cf9ef..28960e4c4e43 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
@@ -315,6 +315,10 @@ int mtk_setup_hw_path(struct mtk_eth *eth, int
mac_id, int phymode)
{
int err;
+ /* No mux'ing for MT7628/88 */
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
+ return 0;
+
switch (phymode) {
case PHY_INTERFACE_MODE_TRGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index b20b3a5a1ebb..1f248ef6ef88 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -323,11 +323,14 @@ static int mtk_phy_connect(struct net_device *dev)
goto err_phy;
}
- /* put the gmac into the right mode */
- regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
- val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
- val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
- regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
+ /* No MT7628/88 support for now */
+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
+ /* put the gmac into the right mode */
+ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
+ val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
+ val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
+ regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
+ }
/* couple phydev to net_device */
if (mtk_phy_connect_node(eth, mac, np))
@@ -395,8 +398,8 @@ static inline void mtk_tx_irq_disable(struct
mtk_eth *eth, u32 mask)
u32 val;
spin_lock_irqsave(ð->tx_irq_lock, flags);
- val = mtk_r32(eth, MTK_QDMA_INT_MASK);
- mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
+ val = mtk_r32(eth, eth->tx_int_mask_reg);
+ mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg);
spin_unlock_irqrestore(ð->tx_irq_lock, flags);
}
@@ -406,8 +409,8 @@ static inline void mtk_tx_irq_enable(struct
mtk_eth *eth, u32 mask)
u32 val;
spin_lock_irqsave(ð->tx_irq_lock, flags);
- val = mtk_r32(eth, MTK_QDMA_INT_MASK);
- mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
+ val = mtk_r32(eth, eth->tx_int_mask_reg);
+ mtk_w32(eth, val | mask, eth->tx_int_mask_reg);
spin_unlock_irqrestore(ð->tx_irq_lock, flags);
}
@@ -437,6 +440,7 @@ static int mtk_set_mac_address(struct net_device
*dev, void *p)
{
int ret = eth_mac_addr(dev, p);
struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
const char *macaddr = dev->dev_addr;
if (ret)
@@ -446,11 +450,19 @@ static int mtk_set_mac_address(struct
net_device *dev, void *p)
return -EBUSY;
spin_lock_bh(&mac->hw->page_lock);
- mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
- MTK_GDMA_MAC_ADRH(mac->id));
- mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
- (macaddr[4] << 8) | macaddr[5],
- MTK_GDMA_MAC_ADRL(mac->id));
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
+ mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
+ MT7628_SDM_MAC_ADRH);
+ mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
+
Re: [PATCH] net: ethernet: mediatek: Add MT7628/88 SoC support
On Wed, Jul 17, 2019 at 01:02:43PM +0200, Stefan Roese wrote:
> This patch adds support for the MediaTek MT7628/88 SoCs to the common
> MediaTek ethernet driver. Some minor changes are needed for this and
> a bigger change, as the MT7628 does not support QDMA (only PDMA).
The Ethernet core found in MT7628/88 is identical to that found in
Ralink Rt5350F SoC. Wouldn't it hence make sense to indicate that
in the compatible string of this driver as well? In OpenWrt we are
using "ralink,rt5350-eth".
>
> Signed-off-by: Stefan Roese
> Cc: René van Dorst
> Cc: Sean Wang
> Cc: Felix Fietkau
> Cc: John Crispin
> ---
> .../devicetree/bindings/net/mediatek-net.txt | 1 +
> drivers/net/ethernet/mediatek/mtk_eth_path.c | 4 +
> drivers/net/ethernet/mediatek/mtk_eth_soc.c | 490 ++
> drivers/net/ethernet/mediatek/mtk_eth_soc.h | 39 +-
> 4 files changed, 424 insertions(+), 110 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt
> b/Documentation/devicetree/bindings/net/mediatek-net.txt
> index 770ff98d4524..ec6793562148 100644
> --- a/Documentation/devicetree/bindings/net/mediatek-net.txt
> +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
> @@ -11,6 +11,7 @@ Required properties:
> "mediatek,mt2701-eth": for MT2701 SoC
> "mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
> "mediatek,mt7622-eth": for MT7622 SoC
> + "mediatek,mt7628-eth": for MT7628/88 SoC
> "mediatek,mt7629-eth": for MT7629 SoC
> - reg: Address and length of the register set for the device
> - interrupts: Should contain the three frame engines interrupts in numeric
> diff --git a/drivers/net/ethernet/mediatek/mtk_eth_path.c
> b/drivers/net/ethernet/mediatek/mtk_eth_path.c
> index 7f05880cf9ef..28960e4c4e43 100644
> --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
> +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
> @@ -315,6 +315,10 @@ int mtk_setup_hw_path(struct mtk_eth *eth, int mac_id,
> int phymode)
> {
> int err;
>
> + /* No mux'ing for MT7628/88 */
> + if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
> + return 0;
> +
> switch (phymode) {
> case PHY_INTERFACE_MODE_TRGMII:
> case PHY_INTERFACE_MODE_RGMII_TXID:
> diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> index b20b3a5a1ebb..1f248ef6ef88 100644
> --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> @@ -323,11 +323,14 @@ static int mtk_phy_connect(struct net_device *dev)
> goto err_phy;
> }
>
> - /* put the gmac into the right mode */
> - regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
> - val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
> - val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
> - regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
> + /* No MT7628/88 support for now */
> + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
> + /* put the gmac into the right mode */
> + regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
> + val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
> + val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
> + regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
> + }
>
> /* couple phydev to net_device */
> if (mtk_phy_connect_node(eth, mac, np))
> @@ -395,8 +398,8 @@ static inline void mtk_tx_irq_disable(struct mtk_eth
> *eth, u32 mask)
> u32 val;
>
> spin_lock_irqsave(ð->tx_irq_lock, flags);
> - val = mtk_r32(eth, MTK_QDMA_INT_MASK);
> - mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
> + val = mtk_r32(eth, eth->tx_int_mask_reg);
> + mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg);
> spin_unlock_irqrestore(ð->tx_irq_lock, flags);
> }
>
> @@ -406,8 +409,8 @@ static inline void mtk_tx_irq_enable(struct mtk_eth *eth,
> u32 mask)
> u32 val;
>
> spin_lock_irqsave(ð->tx_irq_lock, flags);
> - val = mtk_r32(eth, MTK_QDMA_INT_MASK);
> - mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
> + val = mtk_r32(eth, eth->tx_int_mask_reg);
> + mtk_w32(eth, val | mask, eth->tx_int_mask_reg);
> spin_unlock_irqrestore(ð->tx_irq_lock, flags);
> }
>
> @@ -437,6 +440,7 @@ static int mtk_set_mac_address(struct net_device *dev,
> void *p)
> {
> int ret = eth_mac_addr(dev, p);
> struct mtk_mac *mac = netdev_priv(dev);
> + struct mtk_eth *eth = mac->hw;
> const char *macaddr = dev->dev_addr;
>
> if (ret)
> @@ -446,11 +450,19 @@ static int mtk_set_mac_address(struct net_device *dev,
> void *p)
> return -EBUSY;
>
> spin_lock_bh(&mac->hw->page_lock);
> - mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
> - MTK_GDMA_MAC_ADRH(mac->id));
> - mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
> -
