Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-13 Thread Andre McCurdy
On Wed, Nov 6, 2019 at 12:37 PM Alistair Francis
 wrote:
>
> Signed-off-by: Alistair Francis 
> ---
>  meta/conf/machine/include/riscv/arch-riscv.inc |  3 ++-
>  meta/conf/machine/include/riscv/tune-riscv.inc | 17 +++--
>  2 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc 
> b/meta/conf/machine/include/riscv/arch-riscv.inc
> index f3edcc39f7..6737545e00 100644
> --- a/meta/conf/machine/include/riscv/arch-riscv.inc
> +++ b/meta/conf/machine/include/riscv/arch-riscv.inc
> @@ -4,7 +4,8 @@ DEFAULTTUNE ?= "riscv64"
>
>  TUNE_ARCH = "${TUNE_ARCH_tune-${DEFAULTTUNE}}"
>  TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}"
> -TUNE_CCARGS .= ""
> +TUNE_CCARGS_riscv64 .= "${@bb.utils.contains('TUNE_FEATURES', 'riscv64-f', ' 
> -mabi=lp64d', ' -mabi=lp64', d)}"
> +TUNE_CCARGS_riscv32 .= "${@bb.utils.contains('TUNE_FEATURES', 'riscv32-f', ' 
> -mabi=ilp32f', ' -mabi=ilp32', d)}"

Using an over-ride to set TUNE_CCARGS is probably going to cause
problems if/when you need to add something else to TUNE_CCARGS in the
future.

In general using += .= etc with an over-ride is discouraged as it
doesn't do what most people might expect...

>  # QEMU usermode fails with invalid instruction error (For riscv32)
>  MACHINE_FEATURES_BACKFILL_CONSIDERED_append = 
> "${@bb.utils.contains('TUNE_FEATURES', 'riscv32', ' qemu-usermode', '', d)}"
> diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc 
> b/meta/conf/machine/include/riscv/tune-riscv.inc
> index 25d0463492..631653f2a2 100644
> --- a/meta/conf/machine/include/riscv/tune-riscv.inc
> +++ b/meta/conf/machine/include/riscv/tune-riscv.inc
> @@ -1,12 +1,26 @@
>  require conf/machine/include/riscv/arch-riscv.inc
>
>  TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
> +TUNEVALID[riscv64-f] = "Enable 64-bit RISC-V optimizations with hard float"
>  TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
> +TUNEVALID[riscv32-f] = "Enable 32-bit RISC-V optimizations with hard float"
>
>  TUNEVALID[bigendian] = "Big endian mode"
>
> -AVAILTUNES += "riscv64 riscv32"
> +AVAILTUNES += "riscv64 riscv64-f riscv32 riscv32-f"
>
> +# Hard float
> +TUNE_FEATURES_tune-riscv64-f = "${TUNE_FEATURES_tune-riscv64} riscv64-f"
> +TUNE_ARCH_tune-riscv64-f = "riscv64"
> +TUNE_PKGARCH_tune-riscv64-f = "riscv64"
> +PACKAGE_EXTRA_ARCHS_tune-riscv64-f = "riscv64"
> +
> +TUNE_FEATURES_tune-riscv32-f = "${TUNE_FEATURES_tune-riscv32} riscv32-f"
> +TUNE_ARCH_tune-riscv32-f = "riscv32"
> +TUNE_PKGARCH_tune-riscv32-f = "riscv32"
> +PACKAGE_EXTRA_ARCHS_tune-riscv32-f = "riscv32"
> +
> +# Soft float
>  TUNE_FEATURES_tune-riscv64 = "riscv64"
>  TUNE_ARCH_tune-riscv64 = "riscv64"
>  TUNE_PKGARCH_tune-riscv64 = "riscv64"
> @@ -16,4 +30,3 @@ TUNE_FEATURES_tune-riscv32 = "riscv32"
>  TUNE_ARCH_tune-riscv32 = "riscv32"
>  TUNE_PKGARCH_tune-riscv32 = "riscv32"
>  PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32"
> -
> --
> 2.23.0
>
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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-11 Thread Alistair Francis
On Fri, Nov 8, 2019 at 3:14 PM Alistair Francis  wrote:
>
> On Fri, Nov 8, 2019 at 3:07 PM Richard Purdie
>  wrote:
> >
> > On Fri, 2019-11-08 at 22:24 +0200, Adrian Bunk wrote:
> > > Especially when looking at the arm64 situation I am wondering
> > > whether the best option might be to throw away the tunes mess and let
> > > the user write the compiler options directly.
> >
> > OE once did that. I think anyone who lived through it would say that
> > the current situation *is* an improvement over a free-for-all.
> >
> > This is mainly as at least we're now consistent whereas before the same
> > thing had different names in each BSP.
> >
> > I don't know what the answer is but I don't want to go back to that!
>
> Ha ok. I won't argue with that.
>
> I can just carry the patch locally, so I'm not in a rush to get this
> in. I have reached out to Rich (musl maintainer) to see if he has any
> ideas.

I just realised I got my wires crossed here, ignore this.

Alistair

>
> Alistair
>
> >
> > Cheers,
> >
> > Richard
> >
> >
> >
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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-10 Thread Adrian Bunk
On Sat, Nov 09, 2019 at 10:05:22PM +, Richard Purdie wrote:
> On Sat, 2019-11-09 at 22:30 +0200, Adrian Bunk wrote:
> > On Fri, Nov 08, 2019 at 11:07:04PM +, Richard Purdie wrote:
> > > On Fri, 2019-11-08 at 22:24 +0200, Adrian Bunk wrote:
> > > > Especially when looking at the arm64 situation I am wondering
> > > > whether the best option might be to throw away the tunes mess and
> > > > let
> > > > the user write the compiler options directly.
> > > 
> > > OE once did that. I think anyone who lived through it would say
> > > that
> > > the current situation *is* an improvement over a free-for-all.
> > > 
> > > This is mainly as at least we're now consistent whereas before the
> > > same
> > > thing had different names in each BSP.
> > 
> > The BSPs should not invent names for anything, all a BSP should do
> > would be to set some kind of
> >   TARGET_CFLAGS += "-mcpu=cortex-a53+crc+crypto+sm4+nosimd"
> 
> What is the name of the package feed these binaries would go into?

The name of whatever is passed to the compiler,
or an artificial name chosen by the distribution.

> > > I don't know what the answer is but I don't want to go back to
> > > that!
> > 
> > As of gcc 9 there are for arm64[1]:
> > 
> > 6 -march= architecture levels (8.0 to 8.5)
> > 35 -mtune= tune options
> > 22 modifiers for -march= and -mtune=
> > 3 different ABIs (aarch64, aarch64-ilp32, armv7)
> > 
> > Even ignoring the tunes you already have
> >   6 * 2^22
> > different architecture+modifier combinations.
> > 
> > Not all combinations are valid, but another can of worms are the
> > definitions what is valid and what is default amd what gets
> > indirectly
> > enabled, e.g.
> >   fp16fml
> > Enable FP16 fmla extension. This also enables FP16 extensions
> > and 
> > floating-point instructions. This option is enabled by default
> > for 
> > -march=armv8.4-a. Use of this option with architectures prior to 
> > Armv8.2-A is not supported.
> > 
> > It can be recursive:
> >   Feature crypto implies aes, sha2, and simd, which implies fp. 
> >   Conversely, nofp implies nosimd, which implies nocrypto, noaes and
> > nosha2. 
> 
> I'd advocate that we add the combinations which people need and use.
> The tune structure doesn't require every combination be there.

Does any person volunteer to be the "we"?

This is nothing that will just work, and for arm64 we are talking about 
30+ tune file each with a sizeable number of tune combintations.

The few tunes that currently exist do not even expose the fact that
there are already 6 architecture levels with one-way compatibility.

And how do you determine "combinations which people need and use"?

It is up to the SoC designer which features to buy from ARM,
and new combinations appear all the time.

Like how will it work in practice if a user asks today for a tune for
a Cortex A55 without sha3 but with sm4 enabled for warrior?

I understand what you want, but I am worried that in practice this might
just be a huge mess.

And it is a lot more complex than the few combinations currently
available on RISC-V.

> Cheers,
> 
> Richard

cu
Adrian

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   "Only a promise," Lao Er said.
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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-09 Thread Richard Purdie
On Sat, 2019-11-09 at 22:30 +0200, Adrian Bunk wrote:
> On Fri, Nov 08, 2019 at 11:07:04PM +, Richard Purdie wrote:
> > On Fri, 2019-11-08 at 22:24 +0200, Adrian Bunk wrote:
> > > Especially when looking at the arm64 situation I am wondering
> > > whether the best option might be to throw away the tunes mess and
> > > let
> > > the user write the compiler options directly.
> > 
> > OE once did that. I think anyone who lived through it would say
> > that
> > the current situation *is* an improvement over a free-for-all.
> > 
> > This is mainly as at least we're now consistent whereas before the
> > same
> > thing had different names in each BSP.
> 
> The BSPs should not invent names for anything, all a BSP should do
> would be to set some kind of
>   TARGET_CFLAGS += "-mcpu=cortex-a53+crc+crypto+sm4+nosimd"

What is the name of the package feed these binaries would go into?

> > I don't know what the answer is but I don't want to go back to
> > that!
> 
> As of gcc 9 there are for arm64[1]:
> 
> 6 -march= architecture levels (8.0 to 8.5)
> 35 -mtune= tune options
> 22 modifiers for -march= and -mtune=
> 3 different ABIs (aarch64, aarch64-ilp32, armv7)
> 
> Even ignoring the tunes you already have
>   6 * 2^22
> different architecture+modifier combinations.
> 
> Not all combinations are valid, but another can of worms are the
> definitions what is valid and what is default amd what gets
> indirectly
> enabled, e.g.
>   fp16fml
> Enable FP16 fmla extension. This also enables FP16 extensions
> and 
> floating-point instructions. This option is enabled by default
> for 
> -march=armv8.4-a. Use of this option with architectures prior to 
> Armv8.2-A is not supported.
> 
> It can be recursive:
>   Feature crypto implies aes, sha2, and simd, which implies fp. 
>   Conversely, nofp implies nosimd, which implies nocrypto, noaes and
> nosha2. 

I'd advocate that we add the combinations which people need and use.
The tune structure doesn't require every combination be there.

Cheers,

Richard



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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-09 Thread Adrian Bunk
On Fri, Nov 08, 2019 at 11:07:04PM +, Richard Purdie wrote:
> On Fri, 2019-11-08 at 22:24 +0200, Adrian Bunk wrote:
> > Especially when looking at the arm64 situation I am wondering
> > whether the best option might be to throw away the tunes mess and let
> > the user write the compiler options directly.
> 
> OE once did that. I think anyone who lived through it would say that
> the current situation *is* an improvement over a free-for-all.
> 
> This is mainly as at least we're now consistent whereas before the same
> thing had different names in each BSP.

The BSPs should not invent names for anything, all a BSP should do would 
be to set some kind of
  TARGET_CFLAGS += "-mcpu=cortex-a53+crc+crypto+sm4+nosimd"

> I don't know what the answer is but I don't want to go back to that!

As of gcc 9 there are for arm64[1]:

6 -march= architecture levels (8.0 to 8.5)
35 -mtune= tune options
22 modifiers for -march= and -mtune=
3 different ABIs (aarch64, aarch64-ilp32, armv7)

Even ignoring the tunes you already have
  6 * 2^22
different architecture+modifier combinations.

Not all combinations are valid, but another can of worms are the
definitions what is valid and what is default amd what gets indirectly
enabled, e.g.
  fp16fml
Enable FP16 fmla extension. This also enables FP16 extensions and 
floating-point instructions. This option is enabled by default for 
-march=armv8.4-a. Use of this option with architectures prior to 
Armv8.2-A is not supported.

It can be recursive:
  Feature crypto implies aes, sha2, and simd, which implies fp. 
  Conversely, nofp implies nosimd, which implies nocrypto, noaes and nosha2. 

> Cheers,
> 
> Richard

cu
Adrian

[1] https://gcc.gnu.org/onlinedocs/gcc-9.1.0/gcc/AArch64-Options.html

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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-08 Thread Alistair Francis
On Fri, Nov 8, 2019 at 3:07 PM Richard Purdie
 wrote:
>
> On Fri, 2019-11-08 at 22:24 +0200, Adrian Bunk wrote:
> > Especially when looking at the arm64 situation I am wondering
> > whether the best option might be to throw away the tunes mess and let
> > the user write the compiler options directly.
>
> OE once did that. I think anyone who lived through it would say that
> the current situation *is* an improvement over a free-for-all.
>
> This is mainly as at least we're now consistent whereas before the same
> thing had different names in each BSP.
>
> I don't know what the answer is but I don't want to go back to that!

Ha ok. I won't argue with that.

I can just carry the patch locally, so I'm not in a rush to get this
in. I have reached out to Rich (musl maintainer) to see if he has any
ideas.

Alistair

>
> Cheers,
>
> Richard
>
>
>
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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-08 Thread Richard Purdie
On Fri, 2019-11-08 at 22:24 +0200, Adrian Bunk wrote:
> Especially when looking at the arm64 situation I am wondering
> whether the best option might be to throw away the tunes mess and let
> the user write the compiler options directly.

OE once did that. I think anyone who lived through it would say that
the current situation *is* an improvement over a free-for-all.

This is mainly as at least we're now consistent whereas before the same
thing had different names in each BSP.

I don't know what the answer is but I don't want to go back to that!

Cheers,

Richard



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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-08 Thread Adrian Bunk
On Thu, Nov 07, 2019 at 04:39:22PM -0800, Alistair Francis wrote:
> On Wed, Nov 6, 2019 at 11:33 PM Nathan Rossi  wrote:
> >
> > On Thu, 7 Nov 2019 at 09:34, Adrian Bunk  wrote:
> > >
> > > On Wed, Nov 06, 2019 at 10:18:18AM -0800, Alistair Francis wrote:
> > > >...
> > > > +TUNE_CCARGS_riscv64 .= "${@bb.utils.contains('TUNE_FEATURES', 
> > > > 'riscv64-f', ' -mabi=lp64d', ' -mabi=lp64', d)}"
> > > > +TUNE_CCARGS_riscv32 .= "${@bb.utils.contains('TUNE_FEATURES', 
> > > > 'riscv32-f', ' -mabi=ilp32f', ' -mabi=ilp32', d)}"
> > > >...
> > >
> > > That looks wrong, what would you put in TUNE_FEATURES
> > > for -mabi=lp64f when -mabi=lp64d is called riscv64-f?
> > >
> > > Also note that this is only the floating point calling convention,
> > > whether the compiler emits floating point instructions is defined
> > > by -march.
> > >
> > > It would be good if this would start with a plan how to handle
> > > all possible combination of RISC-V ISA extensions, ideally better
> > > than the arm mess.
> >
> > I am keen to see this as well, since I am currently directly
> > hardcoding -march/-mabi in the machine conf.
> >
> > It would be nice to see the ISA tunes available in oe-core, even if
> > that is just the tune features and not predefined tunes (e.g. like
> > microblaze).
> 
> I think this idea as well. Some generic way of generating tunes from
> ISA stings would be great!
> 
> Does anyone have any ideas on the best way to do this?

Especially when looking at the arm64 situation I am wondering whether 
the best option might be to throw away the tunes mess and let the user 
write the compiler options directly.

If OE needs information about a specific feature, it would be easier to 
ask the compiler[1] than duplicating all the target knowledge.

> Alistair

cu
Adrian

[1] $CC -dM -E - < /dev/null

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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-07 Thread Alistair Francis
On Wed, Nov 6, 2019 at 11:33 PM Nathan Rossi  wrote:
>
> On Thu, 7 Nov 2019 at 09:34, Adrian Bunk  wrote:
> >
> > On Wed, Nov 06, 2019 at 10:18:18AM -0800, Alistair Francis wrote:
> > >...
> > > +TUNE_CCARGS_riscv64 .= "${@bb.utils.contains('TUNE_FEATURES', 
> > > 'riscv64-f', ' -mabi=lp64d', ' -mabi=lp64', d)}"
> > > +TUNE_CCARGS_riscv32 .= "${@bb.utils.contains('TUNE_FEATURES', 
> > > 'riscv32-f', ' -mabi=ilp32f', ' -mabi=ilp32', d)}"
> > >...
> >
> > That looks wrong, what would you put in TUNE_FEATURES
> > for -mabi=lp64f when -mabi=lp64d is called riscv64-f?
> >
> > Also note that this is only the floating point calling convention,
> > whether the compiler emits floating point instructions is defined
> > by -march.
> >
> > It would be good if this would start with a plan how to handle
> > all possible combination of RISC-V ISA extensions, ideally better
> > than the arm mess.
>
> I am keen to see this as well, since I am currently directly
> hardcoding -march/-mabi in the machine conf.
>
> It would be nice to see the ISA tunes available in oe-core, even if
> that is just the tune features and not predefined tunes (e.g. like
> microblaze).

I think this idea as well. Some generic way of generating tunes from
ISA stings would be great!

Does anyone have any ideas on the best way to do this?

Alistair

>
> Regards,
> Nathan
>
> >
> > cu
> > Adrian
> >
> > --
> >
> >"Is there not promise of rain?" Ling Tan asked suddenly out
> > of the darkness. There had been need of rain for many days.
> >"Only a promise," Lao Er said.
> >Pearl S. Buck - Dragon Seed
> >
> > --
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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-07 Thread Adrian Bunk
On Wed, Nov 06, 2019 at 04:55:05PM -0800, Khem Raj wrote:
> On Wed, Nov 6, 2019 at 4:48 PM Alistair Francis 
> wrote:
>...
> > -march is another can of worms that I was trying to avoid. I don't have
> > a good way of handling the ISA strings at the moment without some crazy
> > number of tune options.
> 
> We need to handle that but I think that should be in meta-riscv since I
> think for Linux we should just stick to rv64gc ABI and something cross
> distro agreed upon abi for riscv32 and bare metal is another story that’s
> where probably we need to address the ABIs

We have the same problem even worse on arm64,
with billions of combinations available.

A solution is needed in both cases.

cu
Adrian

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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-06 Thread Nathan Rossi
On Thu, 7 Nov 2019 at 09:34, Adrian Bunk  wrote:
>
> On Wed, Nov 06, 2019 at 10:18:18AM -0800, Alistair Francis wrote:
> >...
> > +TUNE_CCARGS_riscv64 .= "${@bb.utils.contains('TUNE_FEATURES', 'riscv64-f', 
> > ' -mabi=lp64d', ' -mabi=lp64', d)}"
> > +TUNE_CCARGS_riscv32 .= "${@bb.utils.contains('TUNE_FEATURES', 'riscv32-f', 
> > ' -mabi=ilp32f', ' -mabi=ilp32', d)}"
> >...
>
> That looks wrong, what would you put in TUNE_FEATURES
> for -mabi=lp64f when -mabi=lp64d is called riscv64-f?
>
> Also note that this is only the floating point calling convention,
> whether the compiler emits floating point instructions is defined
> by -march.
>
> It would be good if this would start with a plan how to handle
> all possible combination of RISC-V ISA extensions, ideally better
> than the arm mess.

I am keen to see this as well, since I am currently directly
hardcoding -march/-mabi in the machine conf.

It would be nice to see the ISA tunes available in oe-core, even if
that is just the tune features and not predefined tunes (e.g. like
microblaze).

Regards,
Nathan

>
> cu
> Adrian
>
> --
>
>"Is there not promise of rain?" Ling Tan asked suddenly out
> of the darkness. There had been need of rain for many days.
>"Only a promise," Lao Er said.
>Pearl S. Buck - Dragon Seed
>
> --
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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-06 Thread Khem Raj
On Wed, Nov 6, 2019 at 4:48 PM Alistair Francis 
wrote:

> On Thu, 2019-11-07 at 00:12 +0200, Adrian Bunk wrote:
> > On Wed, Nov 06, 2019 at 10:18:18AM -0800, Alistair Francis wrote:
> > > ...
> > > +TUNE_CCARGS_riscv64 .= "${@bb.utils.contains('TUNE_FEATURES',
> > > 'riscv64-f', ' -mabi=lp64d', ' -mabi=lp64', d)}"
> > > +TUNE_CCARGS_riscv32 .= "${@bb.utils.contains('TUNE_FEATURES',
> > > 'riscv32-f', ' -mabi=ilp32f', ' -mabi=ilp32', d)}"
> > > ...
> >
> > That looks wrong, what would you put in TUNE_FEATURES
> > for -mabi=lp64f when -mabi=lp64d is called riscv64-f?
>
> I am just going to add riscv32nf and riscv64nf. This will specify
> -mabi=ilp32 and -mabi=lp64 accordingly. I won't change the default
> riscv32 and riscv64. We can then deal with the single and double float
> at a later point.
>
> >
> > Also note that this is only the floating point calling convention,
> > whether the compiler emits floating point instructions is defined
> > by -march.
>
> -march is another can of worms that I was trying to avoid. I don't have
> a good way of handling the ISA strings at the moment without some crazy
> number of tune options.


We need to handle that but I think that should be in meta-riscv since I
think for Linux we should just stick to rv64gc ABI and something cross
distro agreed upon abi for riscv32 and bare metal is another story that’s
where probably we need to address the ABIs

>
>
> >
> > It would be good if this would start with a plan how to handle
> > all possible combination of RISC-V ISA extensions, ideally better
> > than the arm mess.
>
> Agreed. I am just going to change this to add a no float option as that
> fixes a large number of 32-bit link failures (seen in U-Boot, OpenSBI
> and SDKs) and we can re-evaluate a longer term march fix.


This is fine to start with for now


>
> Alistair
>
> >
> > cu
> > Adrian
> >
> --
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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-06 Thread Alistair Francis
On Thu, 2019-11-07 at 00:12 +0200, Adrian Bunk wrote:
> On Wed, Nov 06, 2019 at 10:18:18AM -0800, Alistair Francis wrote:
> > ...
> > +TUNE_CCARGS_riscv64 .= "${@bb.utils.contains('TUNE_FEATURES',
> > 'riscv64-f', ' -mabi=lp64d', ' -mabi=lp64', d)}"
> > +TUNE_CCARGS_riscv32 .= "${@bb.utils.contains('TUNE_FEATURES',
> > 'riscv32-f', ' -mabi=ilp32f', ' -mabi=ilp32', d)}"
> > ...
> 
> That looks wrong, what would you put in TUNE_FEATURES
> for -mabi=lp64f when -mabi=lp64d is called riscv64-f?

I am just going to add riscv32nf and riscv64nf. This will specify
-mabi=ilp32 and -mabi=lp64 accordingly. I won't change the default
riscv32 and riscv64. We can then deal with the single and double float
at a later point.

> 
> Also note that this is only the floating point calling convention,
> whether the compiler emits floating point instructions is defined
> by -march.

-march is another can of worms that I was trying to avoid. I don't have
a good way of handling the ISA strings at the moment without some crazy
number of tune options.

> 
> It would be good if this would start with a plan how to handle
> all possible combination of RISC-V ISA extensions, ideally better
> than the arm mess.

Agreed. I am just going to change this to add a no float option as that
fixes a large number of 32-bit link failures (seen in U-Boot, OpenSBI
and SDKs) and we can re-evaluate a longer term march fix.

Alistair

> 
> cu
> Adrian
> 
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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-06 Thread Alistair Francis
On Wed, 2019-11-06 at 14:18 -0800, Khem Raj wrote:
> On Wed, Nov 6, 2019 at 1:52 PM Alistair Francis
>  wrote:
> > On Wed, 2019-11-06 at 13:49 -0800, Khem Raj wrote:
> > > On Wed, Nov 6, 2019 at 1:34 PM Alistair Francis
> > >  wrote:
> > > > On Wed, 2019-11-06 at 12:54 -0800, Khem Raj wrote:
> > > > > On Wed, Nov 6, 2019 at 12:37 PM Alistair Francis
> > > > >  wrote:
> > > > > > Signed-off-by: Alistair Francis 
> > > > > > ---
> > > > > >  meta/conf/machine/include/riscv/arch-riscv.inc |  3 ++-
> > > > > >  meta/conf/machine/include/riscv/tune-riscv.inc | 17
> > > > > > +++--
> > > > > >  2 files changed, 17 insertions(+), 3 deletions(-)
> > > > > > 
> > > > > > diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc
> > > > > > b/meta/conf/machine/include/riscv/arch-riscv.inc
> > > > > > index f3edcc39f7..6737545e00 100644
> > > > > > --- a/meta/conf/machine/include/riscv/arch-riscv.inc
> > > > > > +++ b/meta/conf/machine/include/riscv/arch-riscv.inc
> > > > > > @@ -4,7 +4,8 @@ DEFAULTTUNE ?= "riscv64"
> > > > > > 
> > > > > >  TUNE_ARCH = "${TUNE_ARCH_tune-${DEFAULTTUNE}}"
> > > > > >  TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}"
> > > > > > -TUNE_CCARGS .= ""
> > > > > > +TUNE_CCARGS_riscv64 .= "${@bb.utils.contains('TUNE_FEATURE
> > > > > > S',
> > > > > > 'riscv64-f', ' -mabi=lp64d', ' -mabi=lp64', d)}"
> > > > > > +TUNE_CCARGS_riscv32 .= "${@bb.utils.contains('TUNE_FEATURE
> > > > > > S',
> > > > > > 'riscv32-f', ' -mabi=ilp32f', ' -mabi=ilp32', d)}"
> > > > > > 
> > > > > >  # QEMU usermode fails with invalid instruction error (For
> > > > > > riscv32)
> > > > > >  MACHINE_FEATURES_BACKFILL_CONSIDERED_append = "
> > > > > > ${@bb.utils.contains('TUNE_FEATURES', 'riscv32', ' qemu-
> > > > > > usermode',
> > > > > > '', d)}"
> > > > > > diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc
> > > > > > b/meta/conf/machine/include/riscv/tune-riscv.inc
> > > > > > index 25d0463492..631653f2a2 100644
> > > > > > --- a/meta/conf/machine/include/riscv/tune-riscv.inc
> > > > > > +++ b/meta/conf/machine/include/riscv/tune-riscv.inc
> > > > > > @@ -1,12 +1,26 @@
> > > > > >  require conf/machine/include/riscv/arch-riscv.inc
> > > > > > 
> > > > > >  TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
> > > > > > +TUNEVALID[riscv64-f] = "Enable 64-bit RISC-V optimizations
> > > > > > with
> > > > > > hard float"
> > > > > >  TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
> > > > > > +TUNEVALID[riscv32-f] = "Enable 32-bit RISC-V optimizations
> > > > > > with
> > > > > > hard float"
> > > > > > 
> > > > > >  TUNEVALID[bigendian] = "Big endian mode"
> > > > > > 
> > > > > > -AVAILTUNES += "riscv64 riscv32"
> > > > > > +AVAILTUNES += "riscv64 riscv64-f riscv32 riscv32-f"
> > > > > > 
> > > > > > +# Hard float
> > > > > > +TUNE_FEATURES_tune-riscv64-f = "${TUNE_FEATURES_tune-
> > > > > > riscv64}
> > > > > > riscv64-f"
> > > > > > +TUNE_ARCH_tune-riscv64-f = "riscv64"
> > > > > > +TUNE_PKGARCH_tune-riscv64-f = "riscv64"
> > > > > > +PACKAGE_EXTRA_ARCHS_tune-riscv64-f = "riscv64"
> > > > > > +
> > > > > > +TUNE_FEATURES_tune-riscv32-f = "${TUNE_FEATURES_tune-
> > > > > > riscv32}
> > > > > > riscv32-f"
> > > > > > +TUNE_ARCH_tune-riscv32-f = "riscv32"
> > > > > > +TUNE_PKGARCH_tune-riscv32-f = "riscv32"
> > > > > > +PACKAGE_EXTRA_ARCHS_tune-riscv32-f = "riscv32"
> > > > > > +
> > > > > > +# Soft float
> > > > > >  TUNE_FEATURES_tune-riscv64 = "riscv64"
> > > > > >  TUNE_ARCH_tune-riscv64 = "riscv64"
> > > > > >  TUNE_PKGARCH_tune-riscv64 = "riscv64"
> > > > > > @@ -16,4 +30,3 @@ TUNE_FEATURES_tune-riscv32 = "riscv32"
> > > > > >  TUNE_ARCH_tune-riscv32 = "riscv32"
> > > > > >  TUNE_PKGARCH_tune-riscv32 = "riscv32"
> > > > > >  PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32"
> > > > > > -
> > > > > 
> > > > >  its better to add riscv64sf and keep existing tunes as it
> > > > > is.
> > > > > since
> > > > > sf is going to be rare
> > > > > compared to rv64gc
> > > > 
> > > > Ok, these are the tunes I have now:
> > > > riscv64 riscv64sf riscv32 riscv32hf
> > > 
> > > what would riscv32hf be ?
> > 
> > RISC-V 32-bit hard float. It sets: -mabi=ilp32f
> > 
> > It currently isn't used, but it could be in the future.
> > 
> 
> hmmm we could also use sf = single float df=double float
> nf=soft(no) float where exceptions are to be indicated and keep
> riscv64 and riscv32 to indicate default ( common ) ABIs

Ok, how about this.

I am just going to add riscv32nf and riscv64nf. This will specify
-mabi=ilp32 and -mabi=lp64 accordingly. I won't change the default
riscv32 and riscv64. We can then deal with the single and double float
at a later point.

Alistair

> 
> > Alistair
> > 
> > > > Alistair
> > > > 
> > > > > > --
> > > > > > 2.23.0
> > > > > > 
> > > > > > --
> > > > > > ___
> > > > > > Openembedded-core mailing list
> > > > > > Openembedded-core@lists.openembedded.org
> > > > > > 

Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-06 Thread Adrian Bunk
On Wed, Nov 06, 2019 at 10:18:18AM -0800, Alistair Francis wrote:
>...
> +TUNE_CCARGS_riscv64 .= "${@bb.utils.contains('TUNE_FEATURES', 'riscv64-f', ' 
> -mabi=lp64d', ' -mabi=lp64', d)}"
> +TUNE_CCARGS_riscv32 .= "${@bb.utils.contains('TUNE_FEATURES', 'riscv32-f', ' 
> -mabi=ilp32f', ' -mabi=ilp32', d)}"
>...

That looks wrong, what would you put in TUNE_FEATURES
for -mabi=lp64f when -mabi=lp64d is called riscv64-f?

Also note that this is only the floating point calling convention,
whether the compiler emits floating point instructions is defined
by -march.

It would be good if this would start with a plan how to handle
all possible combination of RISC-V ISA extensions, ideally better
than the arm mess.

cu
Adrian

-- 

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of the darkness. There had been need of rain for many days.
   "Only a promise," Lao Er said.
   Pearl S. Buck - Dragon Seed

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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-06 Thread Khem Raj
On Wed, Nov 6, 2019 at 1:52 PM Alistair Francis
 wrote:
>
> On Wed, 2019-11-06 at 13:49 -0800, Khem Raj wrote:
> > On Wed, Nov 6, 2019 at 1:34 PM Alistair Francis
> >  wrote:
> > > On Wed, 2019-11-06 at 12:54 -0800, Khem Raj wrote:
> > > > On Wed, Nov 6, 2019 at 12:37 PM Alistair Francis
> > > >  wrote:
> > > > > Signed-off-by: Alistair Francis 
> > > > > ---
> > > > >  meta/conf/machine/include/riscv/arch-riscv.inc |  3 ++-
> > > > >  meta/conf/machine/include/riscv/tune-riscv.inc | 17
> > > > > +++--
> > > > >  2 files changed, 17 insertions(+), 3 deletions(-)
> > > > >
> > > > > diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc
> > > > > b/meta/conf/machine/include/riscv/arch-riscv.inc
> > > > > index f3edcc39f7..6737545e00 100644
> > > > > --- a/meta/conf/machine/include/riscv/arch-riscv.inc
> > > > > +++ b/meta/conf/machine/include/riscv/arch-riscv.inc
> > > > > @@ -4,7 +4,8 @@ DEFAULTTUNE ?= "riscv64"
> > > > >
> > > > >  TUNE_ARCH = "${TUNE_ARCH_tune-${DEFAULTTUNE}}"
> > > > >  TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}"
> > > > > -TUNE_CCARGS .= ""
> > > > > +TUNE_CCARGS_riscv64 .= "${@bb.utils.contains('TUNE_FEATURES',
> > > > > 'riscv64-f', ' -mabi=lp64d', ' -mabi=lp64', d)}"
> > > > > +TUNE_CCARGS_riscv32 .= "${@bb.utils.contains('TUNE_FEATURES',
> > > > > 'riscv32-f', ' -mabi=ilp32f', ' -mabi=ilp32', d)}"
> > > > >
> > > > >  # QEMU usermode fails with invalid instruction error (For
> > > > > riscv32)
> > > > >  MACHINE_FEATURES_BACKFILL_CONSIDERED_append = "
> > > > > ${@bb.utils.contains('TUNE_FEATURES', 'riscv32', ' qemu-
> > > > > usermode',
> > > > > '', d)}"
> > > > > diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc
> > > > > b/meta/conf/machine/include/riscv/tune-riscv.inc
> > > > > index 25d0463492..631653f2a2 100644
> > > > > --- a/meta/conf/machine/include/riscv/tune-riscv.inc
> > > > > +++ b/meta/conf/machine/include/riscv/tune-riscv.inc
> > > > > @@ -1,12 +1,26 @@
> > > > >  require conf/machine/include/riscv/arch-riscv.inc
> > > > >
> > > > >  TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
> > > > > +TUNEVALID[riscv64-f] = "Enable 64-bit RISC-V optimizations
> > > > > with
> > > > > hard float"
> > > > >  TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
> > > > > +TUNEVALID[riscv32-f] = "Enable 32-bit RISC-V optimizations
> > > > > with
> > > > > hard float"
> > > > >
> > > > >  TUNEVALID[bigendian] = "Big endian mode"
> > > > >
> > > > > -AVAILTUNES += "riscv64 riscv32"
> > > > > +AVAILTUNES += "riscv64 riscv64-f riscv32 riscv32-f"
> > > > >
> > > > > +# Hard float
> > > > > +TUNE_FEATURES_tune-riscv64-f = "${TUNE_FEATURES_tune-riscv64}
> > > > > riscv64-f"
> > > > > +TUNE_ARCH_tune-riscv64-f = "riscv64"
> > > > > +TUNE_PKGARCH_tune-riscv64-f = "riscv64"
> > > > > +PACKAGE_EXTRA_ARCHS_tune-riscv64-f = "riscv64"
> > > > > +
> > > > > +TUNE_FEATURES_tune-riscv32-f = "${TUNE_FEATURES_tune-riscv32}
> > > > > riscv32-f"
> > > > > +TUNE_ARCH_tune-riscv32-f = "riscv32"
> > > > > +TUNE_PKGARCH_tune-riscv32-f = "riscv32"
> > > > > +PACKAGE_EXTRA_ARCHS_tune-riscv32-f = "riscv32"
> > > > > +
> > > > > +# Soft float
> > > > >  TUNE_FEATURES_tune-riscv64 = "riscv64"
> > > > >  TUNE_ARCH_tune-riscv64 = "riscv64"
> > > > >  TUNE_PKGARCH_tune-riscv64 = "riscv64"
> > > > > @@ -16,4 +30,3 @@ TUNE_FEATURES_tune-riscv32 = "riscv32"
> > > > >  TUNE_ARCH_tune-riscv32 = "riscv32"
> > > > >  TUNE_PKGARCH_tune-riscv32 = "riscv32"
> > > > >  PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32"
> > > > > -
> > > >
> > > >  its better to add riscv64sf and keep existing tunes as it is.
> > > > since
> > > > sf is going to be rare
> > > > compared to rv64gc
> > >
> > > Ok, these are the tunes I have now:
> > > riscv64 riscv64sf riscv32 riscv32hf
> >
> > what would riscv32hf be ?
>
> RISC-V 32-bit hard float. It sets: -mabi=ilp32f
>
> It currently isn't used, but it could be in the future.
>

hmmm we could also use sf = single float df=double float
nf=soft(no) float where exceptions are to be indicated and keep
riscv64 and riscv32 to indicate default ( common ) ABIs

> Alistair
>
> >
> > > Alistair
> > >
> > > > > --
> > > > > 2.23.0
> > > > >
> > > > > --
> > > > > ___
> > > > > Openembedded-core mailing list
> > > > > Openembedded-core@lists.openembedded.org
> > > > > http://lists.openembedded.org/mailman/listinfo/openembedded-core
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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-06 Thread Khem Raj
On Wed, Nov 6, 2019 at 1:34 PM Alistair Francis
 wrote:
>
> On Wed, 2019-11-06 at 12:54 -0800, Khem Raj wrote:
> > On Wed, Nov 6, 2019 at 12:37 PM Alistair Francis
> >  wrote:
> > > Signed-off-by: Alistair Francis 
> > > ---
> > >  meta/conf/machine/include/riscv/arch-riscv.inc |  3 ++-
> > >  meta/conf/machine/include/riscv/tune-riscv.inc | 17
> > > +++--
> > >  2 files changed, 17 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc
> > > b/meta/conf/machine/include/riscv/arch-riscv.inc
> > > index f3edcc39f7..6737545e00 100644
> > > --- a/meta/conf/machine/include/riscv/arch-riscv.inc
> > > +++ b/meta/conf/machine/include/riscv/arch-riscv.inc
> > > @@ -4,7 +4,8 @@ DEFAULTTUNE ?= "riscv64"
> > >
> > >  TUNE_ARCH = "${TUNE_ARCH_tune-${DEFAULTTUNE}}"
> > >  TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}"
> > > -TUNE_CCARGS .= ""
> > > +TUNE_CCARGS_riscv64 .= "${@bb.utils.contains('TUNE_FEATURES',
> > > 'riscv64-f', ' -mabi=lp64d', ' -mabi=lp64', d)}"
> > > +TUNE_CCARGS_riscv32 .= "${@bb.utils.contains('TUNE_FEATURES',
> > > 'riscv32-f', ' -mabi=ilp32f', ' -mabi=ilp32', d)}"
> > >
> > >  # QEMU usermode fails with invalid instruction error (For riscv32)
> > >  MACHINE_FEATURES_BACKFILL_CONSIDERED_append = "
> > > ${@bb.utils.contains('TUNE_FEATURES', 'riscv32', ' qemu-usermode',
> > > '', d)}"
> > > diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc
> > > b/meta/conf/machine/include/riscv/tune-riscv.inc
> > > index 25d0463492..631653f2a2 100644
> > > --- a/meta/conf/machine/include/riscv/tune-riscv.inc
> > > +++ b/meta/conf/machine/include/riscv/tune-riscv.inc
> > > @@ -1,12 +1,26 @@
> > >  require conf/machine/include/riscv/arch-riscv.inc
> > >
> > >  TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
> > > +TUNEVALID[riscv64-f] = "Enable 64-bit RISC-V optimizations with
> > > hard float"
> > >  TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
> > > +TUNEVALID[riscv32-f] = "Enable 32-bit RISC-V optimizations with
> > > hard float"
> > >
> > >  TUNEVALID[bigendian] = "Big endian mode"
> > >
> > > -AVAILTUNES += "riscv64 riscv32"
> > > +AVAILTUNES += "riscv64 riscv64-f riscv32 riscv32-f"
> > >
> > > +# Hard float
> > > +TUNE_FEATURES_tune-riscv64-f = "${TUNE_FEATURES_tune-riscv64}
> > > riscv64-f"
> > > +TUNE_ARCH_tune-riscv64-f = "riscv64"
> > > +TUNE_PKGARCH_tune-riscv64-f = "riscv64"
> > > +PACKAGE_EXTRA_ARCHS_tune-riscv64-f = "riscv64"
> > > +
> > > +TUNE_FEATURES_tune-riscv32-f = "${TUNE_FEATURES_tune-riscv32}
> > > riscv32-f"
> > > +TUNE_ARCH_tune-riscv32-f = "riscv32"
> > > +TUNE_PKGARCH_tune-riscv32-f = "riscv32"
> > > +PACKAGE_EXTRA_ARCHS_tune-riscv32-f = "riscv32"
> > > +
> > > +# Soft float
> > >  TUNE_FEATURES_tune-riscv64 = "riscv64"
> > >  TUNE_ARCH_tune-riscv64 = "riscv64"
> > >  TUNE_PKGARCH_tune-riscv64 = "riscv64"
> > > @@ -16,4 +30,3 @@ TUNE_FEATURES_tune-riscv32 = "riscv32"
> > >  TUNE_ARCH_tune-riscv32 = "riscv32"
> > >  TUNE_PKGARCH_tune-riscv32 = "riscv32"
> > >  PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32"
> > > -
> >
> >  its better to add riscv64sf and keep existing tunes as it is. since
> > sf is going to be rare
> > compared to rv64gc
>
> Ok, these are the tunes I have now:
> riscv64 riscv64sf riscv32 riscv32hf

what would riscv32hf be ?

>
> Alistair
>
> >
> > > --
> > > 2.23.0
> > >
> > > --
> > > ___
> > > Openembedded-core mailing list
> > > Openembedded-core@lists.openembedded.org
> > > http://lists.openembedded.org/mailman/listinfo/openembedded-core
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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-06 Thread Alistair Francis
On Wed, 2019-11-06 at 13:49 -0800, Khem Raj wrote:
> On Wed, Nov 6, 2019 at 1:34 PM Alistair Francis
>  wrote:
> > On Wed, 2019-11-06 at 12:54 -0800, Khem Raj wrote:
> > > On Wed, Nov 6, 2019 at 12:37 PM Alistair Francis
> > >  wrote:
> > > > Signed-off-by: Alistair Francis 
> > > > ---
> > > >  meta/conf/machine/include/riscv/arch-riscv.inc |  3 ++-
> > > >  meta/conf/machine/include/riscv/tune-riscv.inc | 17
> > > > +++--
> > > >  2 files changed, 17 insertions(+), 3 deletions(-)
> > > > 
> > > > diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc
> > > > b/meta/conf/machine/include/riscv/arch-riscv.inc
> > > > index f3edcc39f7..6737545e00 100644
> > > > --- a/meta/conf/machine/include/riscv/arch-riscv.inc
> > > > +++ b/meta/conf/machine/include/riscv/arch-riscv.inc
> > > > @@ -4,7 +4,8 @@ DEFAULTTUNE ?= "riscv64"
> > > > 
> > > >  TUNE_ARCH = "${TUNE_ARCH_tune-${DEFAULTTUNE}}"
> > > >  TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}"
> > > > -TUNE_CCARGS .= ""
> > > > +TUNE_CCARGS_riscv64 .= "${@bb.utils.contains('TUNE_FEATURES',
> > > > 'riscv64-f', ' -mabi=lp64d', ' -mabi=lp64', d)}"
> > > > +TUNE_CCARGS_riscv32 .= "${@bb.utils.contains('TUNE_FEATURES',
> > > > 'riscv32-f', ' -mabi=ilp32f', ' -mabi=ilp32', d)}"
> > > > 
> > > >  # QEMU usermode fails with invalid instruction error (For
> > > > riscv32)
> > > >  MACHINE_FEATURES_BACKFILL_CONSIDERED_append = "
> > > > ${@bb.utils.contains('TUNE_FEATURES', 'riscv32', ' qemu-
> > > > usermode',
> > > > '', d)}"
> > > > diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc
> > > > b/meta/conf/machine/include/riscv/tune-riscv.inc
> > > > index 25d0463492..631653f2a2 100644
> > > > --- a/meta/conf/machine/include/riscv/tune-riscv.inc
> > > > +++ b/meta/conf/machine/include/riscv/tune-riscv.inc
> > > > @@ -1,12 +1,26 @@
> > > >  require conf/machine/include/riscv/arch-riscv.inc
> > > > 
> > > >  TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
> > > > +TUNEVALID[riscv64-f] = "Enable 64-bit RISC-V optimizations
> > > > with
> > > > hard float"
> > > >  TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
> > > > +TUNEVALID[riscv32-f] = "Enable 32-bit RISC-V optimizations
> > > > with
> > > > hard float"
> > > > 
> > > >  TUNEVALID[bigendian] = "Big endian mode"
> > > > 
> > > > -AVAILTUNES += "riscv64 riscv32"
> > > > +AVAILTUNES += "riscv64 riscv64-f riscv32 riscv32-f"
> > > > 
> > > > +# Hard float
> > > > +TUNE_FEATURES_tune-riscv64-f = "${TUNE_FEATURES_tune-riscv64}
> > > > riscv64-f"
> > > > +TUNE_ARCH_tune-riscv64-f = "riscv64"
> > > > +TUNE_PKGARCH_tune-riscv64-f = "riscv64"
> > > > +PACKAGE_EXTRA_ARCHS_tune-riscv64-f = "riscv64"
> > > > +
> > > > +TUNE_FEATURES_tune-riscv32-f = "${TUNE_FEATURES_tune-riscv32}
> > > > riscv32-f"
> > > > +TUNE_ARCH_tune-riscv32-f = "riscv32"
> > > > +TUNE_PKGARCH_tune-riscv32-f = "riscv32"
> > > > +PACKAGE_EXTRA_ARCHS_tune-riscv32-f = "riscv32"
> > > > +
> > > > +# Soft float
> > > >  TUNE_FEATURES_tune-riscv64 = "riscv64"
> > > >  TUNE_ARCH_tune-riscv64 = "riscv64"
> > > >  TUNE_PKGARCH_tune-riscv64 = "riscv64"
> > > > @@ -16,4 +30,3 @@ TUNE_FEATURES_tune-riscv32 = "riscv32"
> > > >  TUNE_ARCH_tune-riscv32 = "riscv32"
> > > >  TUNE_PKGARCH_tune-riscv32 = "riscv32"
> > > >  PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32"
> > > > -
> > > 
> > >  its better to add riscv64sf and keep existing tunes as it is.
> > > since
> > > sf is going to be rare
> > > compared to rv64gc
> > 
> > Ok, these are the tunes I have now:
> > riscv64 riscv64sf riscv32 riscv32hf
> 
> what would riscv32hf be ?

RISC-V 32-bit hard float. It sets: -mabi=ilp32f

It currently isn't used, but it could be in the future.

Alistair

> 
> > Alistair
> > 
> > > > --
> > > > 2.23.0
> > > > 
> > > > --
> > > > ___
> > > > Openembedded-core mailing list
> > > > Openembedded-core@lists.openembedded.org
> > > > http://lists.openembedded.org/mailman/listinfo/openembedded-core
-- 
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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-06 Thread Alistair Francis
On Wed, 2019-11-06 at 12:54 -0800, Khem Raj wrote:
> On Wed, Nov 6, 2019 at 12:37 PM Alistair Francis
>  wrote:
> > Signed-off-by: Alistair Francis 
> > ---
> >  meta/conf/machine/include/riscv/arch-riscv.inc |  3 ++-
> >  meta/conf/machine/include/riscv/tune-riscv.inc | 17
> > +++--
> >  2 files changed, 17 insertions(+), 3 deletions(-)
> > 
> > diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc
> > b/meta/conf/machine/include/riscv/arch-riscv.inc
> > index f3edcc39f7..6737545e00 100644
> > --- a/meta/conf/machine/include/riscv/arch-riscv.inc
> > +++ b/meta/conf/machine/include/riscv/arch-riscv.inc
> > @@ -4,7 +4,8 @@ DEFAULTTUNE ?= "riscv64"
> > 
> >  TUNE_ARCH = "${TUNE_ARCH_tune-${DEFAULTTUNE}}"
> >  TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}"
> > -TUNE_CCARGS .= ""
> > +TUNE_CCARGS_riscv64 .= "${@bb.utils.contains('TUNE_FEATURES',
> > 'riscv64-f', ' -mabi=lp64d', ' -mabi=lp64', d)}"
> > +TUNE_CCARGS_riscv32 .= "${@bb.utils.contains('TUNE_FEATURES',
> > 'riscv32-f', ' -mabi=ilp32f', ' -mabi=ilp32', d)}"
> > 
> >  # QEMU usermode fails with invalid instruction error (For riscv32)
> >  MACHINE_FEATURES_BACKFILL_CONSIDERED_append = "
> > ${@bb.utils.contains('TUNE_FEATURES', 'riscv32', ' qemu-usermode',
> > '', d)}"
> > diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc
> > b/meta/conf/machine/include/riscv/tune-riscv.inc
> > index 25d0463492..631653f2a2 100644
> > --- a/meta/conf/machine/include/riscv/tune-riscv.inc
> > +++ b/meta/conf/machine/include/riscv/tune-riscv.inc
> > @@ -1,12 +1,26 @@
> >  require conf/machine/include/riscv/arch-riscv.inc
> > 
> >  TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
> > +TUNEVALID[riscv64-f] = "Enable 64-bit RISC-V optimizations with
> > hard float"
> >  TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
> > +TUNEVALID[riscv32-f] = "Enable 32-bit RISC-V optimizations with
> > hard float"
> > 
> >  TUNEVALID[bigendian] = "Big endian mode"
> > 
> > -AVAILTUNES += "riscv64 riscv32"
> > +AVAILTUNES += "riscv64 riscv64-f riscv32 riscv32-f"
> > 
> > +# Hard float
> > +TUNE_FEATURES_tune-riscv64-f = "${TUNE_FEATURES_tune-riscv64}
> > riscv64-f"
> > +TUNE_ARCH_tune-riscv64-f = "riscv64"
> > +TUNE_PKGARCH_tune-riscv64-f = "riscv64"
> > +PACKAGE_EXTRA_ARCHS_tune-riscv64-f = "riscv64"
> > +
> > +TUNE_FEATURES_tune-riscv32-f = "${TUNE_FEATURES_tune-riscv32}
> > riscv32-f"
> > +TUNE_ARCH_tune-riscv32-f = "riscv32"
> > +TUNE_PKGARCH_tune-riscv32-f = "riscv32"
> > +PACKAGE_EXTRA_ARCHS_tune-riscv32-f = "riscv32"
> > +
> > +# Soft float
> >  TUNE_FEATURES_tune-riscv64 = "riscv64"
> >  TUNE_ARCH_tune-riscv64 = "riscv64"
> >  TUNE_PKGARCH_tune-riscv64 = "riscv64"
> > @@ -16,4 +30,3 @@ TUNE_FEATURES_tune-riscv32 = "riscv32"
> >  TUNE_ARCH_tune-riscv32 = "riscv32"
> >  TUNE_PKGARCH_tune-riscv32 = "riscv32"
> >  PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32"
> > -
> 
>  its better to add riscv64sf and keep existing tunes as it is. since
> sf is going to be rare
> compared to rv64gc

Ok, these are the tunes I have now:
riscv64 riscv64sf riscv32 riscv32hf

Alistair

> 
> > --
> > 2.23.0
> > 
> > --
> > ___
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> > Openembedded-core@lists.openembedded.org
> > http://lists.openembedded.org/mailman/listinfo/openembedded-core
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Re: [OE-core] [PATCH 1/2] tune-riscv: Add support for hard and soft float

2019-11-06 Thread Khem Raj
On Wed, Nov 6, 2019 at 12:37 PM Alistair Francis
 wrote:
>
> Signed-off-by: Alistair Francis 
> ---
>  meta/conf/machine/include/riscv/arch-riscv.inc |  3 ++-
>  meta/conf/machine/include/riscv/tune-riscv.inc | 17 +++--
>  2 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc 
> b/meta/conf/machine/include/riscv/arch-riscv.inc
> index f3edcc39f7..6737545e00 100644
> --- a/meta/conf/machine/include/riscv/arch-riscv.inc
> +++ b/meta/conf/machine/include/riscv/arch-riscv.inc
> @@ -4,7 +4,8 @@ DEFAULTTUNE ?= "riscv64"
>
>  TUNE_ARCH = "${TUNE_ARCH_tune-${DEFAULTTUNE}}"
>  TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}"
> -TUNE_CCARGS .= ""
> +TUNE_CCARGS_riscv64 .= "${@bb.utils.contains('TUNE_FEATURES', 'riscv64-f', ' 
> -mabi=lp64d', ' -mabi=lp64', d)}"
> +TUNE_CCARGS_riscv32 .= "${@bb.utils.contains('TUNE_FEATURES', 'riscv32-f', ' 
> -mabi=ilp32f', ' -mabi=ilp32', d)}"
>
>  # QEMU usermode fails with invalid instruction error (For riscv32)
>  MACHINE_FEATURES_BACKFILL_CONSIDERED_append = 
> "${@bb.utils.contains('TUNE_FEATURES', 'riscv32', ' qemu-usermode', '', d)}"
> diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc 
> b/meta/conf/machine/include/riscv/tune-riscv.inc
> index 25d0463492..631653f2a2 100644
> --- a/meta/conf/machine/include/riscv/tune-riscv.inc
> +++ b/meta/conf/machine/include/riscv/tune-riscv.inc
> @@ -1,12 +1,26 @@
>  require conf/machine/include/riscv/arch-riscv.inc
>
>  TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
> +TUNEVALID[riscv64-f] = "Enable 64-bit RISC-V optimizations with hard float"
>  TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
> +TUNEVALID[riscv32-f] = "Enable 32-bit RISC-V optimizations with hard float"
>
>  TUNEVALID[bigendian] = "Big endian mode"
>
> -AVAILTUNES += "riscv64 riscv32"
> +AVAILTUNES += "riscv64 riscv64-f riscv32 riscv32-f"
>
> +# Hard float
> +TUNE_FEATURES_tune-riscv64-f = "${TUNE_FEATURES_tune-riscv64} riscv64-f"
> +TUNE_ARCH_tune-riscv64-f = "riscv64"
> +TUNE_PKGARCH_tune-riscv64-f = "riscv64"
> +PACKAGE_EXTRA_ARCHS_tune-riscv64-f = "riscv64"
> +
> +TUNE_FEATURES_tune-riscv32-f = "${TUNE_FEATURES_tune-riscv32} riscv32-f"
> +TUNE_ARCH_tune-riscv32-f = "riscv32"
> +TUNE_PKGARCH_tune-riscv32-f = "riscv32"
> +PACKAGE_EXTRA_ARCHS_tune-riscv32-f = "riscv32"
> +
> +# Soft float
>  TUNE_FEATURES_tune-riscv64 = "riscv64"
>  TUNE_ARCH_tune-riscv64 = "riscv64"
>  TUNE_PKGARCH_tune-riscv64 = "riscv64"
> @@ -16,4 +30,3 @@ TUNE_FEATURES_tune-riscv32 = "riscv32"
>  TUNE_ARCH_tune-riscv32 = "riscv32"
>  TUNE_PKGARCH_tune-riscv32 = "riscv32"
>  PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32"
> -

 its better to add riscv64sf and keep existing tunes as it is. since
sf is going to be rare
compared to rv64gc

> --
> 2.23.0
>
> --
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