Hi,
thanks for your patch and your work on OpenOCD.
Could it be possible for you to push your patch on OpenOCD gerrit?
The relevant information to do it are in HACKING file in the source code,
and also online in
https://openocd.org/doc-release/doxygen/patchguide.html
I also see a few other inter
Hi,
thanks for your reply.
My patch only solves this kind of problem when manipulating flash.
Maybe there are similar problems in other locations inside OpenOCD, maybe we
can work it out together.
Best Regards
YanWen Wang
发自我的企业微信
--回复的邮件信息--
Example SOC: https://www.nordicsemi.com/Products/nRF54H20 - This is with
combination of ARM and RISCV core on an SOC.
CH32V seems to be a RISCV based SOC only.
For SOC having combination of ARM and RISCV or any other peripheral connected
on APB bus, ARM being a primary debug chip is accessible
This is an automated email from Gerrit.
"ahmed BOUDJELIDA " just uploaded a new patch set
to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8079
-- gerrit
commit 2530c12b7e0d4f0238760f67d88f1eea5ed0f04f
Author: Ahmed BOUDJELIDA
Date: Mon Jan 15 15:45:49 2024 +0100
I believe sending the ABORT command via JTAG is actually pretty simple. I've
been looking at the SoC-400 TRM and according to the table on this page
https://developer.arm.com/documentation/ddi0480/g/Programmers-Model/DAP-register-summary/Debug-port-register-summary?lang=en
ABORT should be as sim
