Example SOC: https://www.nordicsemi.com/Products/nRF54H20 - This is with combination of ARM and RISCV core on an SOC. CH32V seems to be a RISCV based SOC only.
For SOC having combination of ARM and RISCV or any other peripheral connected on APB bus, ARM being a primary debug chip is accessible via DAP and debug can be done/supported using Openocd but is there any way to select a peripheral having its own debugbase connected on APB-AP ? I came across interesting old ticket whre some conversation has happened for peripherals connected on APB port https://sourceforge.net/p/openocd/mailman/openocd-devel/thread/n2qvvu$m6n$1...@ger.gmane.org/ --- **[tickets:#378] SWD support for RISCV artchitecture** **Status:** new **Milestone:** 0.10.0 **Labels:** openocd **Created:** Wed Dec 28, 2022 07:00 AM UTC by Ashi Gupta **Last Updated:** Wed Jan 10, 2024 01:32 PM UTC **Owner:** nobody Hi, I want to know if SWD debug support has been added for RISCV architecture in openocd ? So far i know that JTAG support is only available. If not any plans in doing so ? --- Sent from sourceforge.net because openocd-devel@lists.sourceforge.net is subscribed to https://sourceforge.net/p/openocd/tickets/ To unsubscribe from further messages, a project admin can change settings at https://sourceforge.net/p/openocd/admin/tickets/options. Or, if this is a mailing list, you can unsubscribe from the mailing list.
