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commit 6686f696a7b504b0673979a54a69a6e5bfae608d
Author: Antonio Borneo
Date: Sun Jan 28 14:58:46 2024 +0100
Hi all,
There is a hardware debug architecture as the image shown:
So I want to know how openocd can support this debug architecture?
Thanks!
0ADD7996@43923268.8B62B665.png
Description: Binary data
> I have came across custom SOCs where there is a single ARM Coresight DAP and
> a riscv processor connected on APB bus on a particular APB port.
> Example SOC: https://www.nordicsemi.com/Products/nRF54H20 - This is with
> combination of ARM and RISCV core on an SOC.
Ashi, does the first
On Thu, Jun 30, 2022 at 6:22 PM Tim Newsome wrote:
> On Wed, Jun 29, 2022 at 1:46 PM Antonio Borneo
> wrote:
>
>> On Wed, Jun 29, 2022 at 9:48 PM Tim Newsome wrote:
>> >
>> > On Tue, Jun 28, 2022 at 3:09 PM Antonio Borneo <
>> borneo.anto...@gmail.com> wrote:
>> >>
>> >> Definitively odd! The
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commit 42d6e1b9644e6436d252652e22b1cbf4256e236e
Author: Sevan Janiyan
Date: Sun Jan 28 20:34:41 2024 +
> I haven't check if the RISC-V fork already has merged a JTAG-AP
> implementation.
FWIW, I'm pretty sure that it hasn't.
* https://github.com/search?q=repo%3Ariscv%2Friscv-openocd%20jtag-ap=code
* https://github.com/search?q=repo%3Ariscv%2Friscv-openocd%20jtag_ap=code
*
I did some investigation on the CH32V series. It seems that they have their own
custom protocol completely unrelated to ARM SWD. I have seen it referred to as
RVSWD. To complicate things even further, their CH32V003 uses a different
single transport protocol.
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**[tickets:#378] SWD support
