> I have came across custom SOCs where there is a single ARM Coresight DAP and > a riscv processor connected on APB bus on a particular APB port.
> Example SOC: https://www.nordicsemi.com/Products/nRF54H20 - This is with > combination of ARM and RISCV core on an SOC. Ashi, does the first statement reference the same SoC like the second one? nRF have not yet released any product specification about 54 series. Do you know some details? --- **[tickets:#378] SWD support for RISCV artchitecture** **Status:** new **Milestone:** 0.10.0 **Labels:** openocd **Created:** Wed Dec 28, 2022 07:00 AM UTC by Ashi Gupta **Last Updated:** Tue Jan 16, 2024 02:21 PM UTC **Owner:** nobody Hi, I want to know if SWD debug support has been added for RISCV architecture in openocd ? So far i know that JTAG support is only available. If not any plans in doing so ? --- Sent from sourceforge.net because openocd-devel@lists.sourceforge.net is subscribed to https://sourceforge.net/p/openocd/tickets/ To unsubscribe from further messages, a project admin can change settings at https://sourceforge.net/p/openocd/admin/tickets/options. Or, if this is a mailing list, you can unsubscribe from the mailing list.
