Hi!
Changing the reset config to separate, and the script to use reset
halt worked, now every programming works!
Here's my output. http://sem.sch.bme.hu/~akos/output.txt It was
created using reset_config trst_pulls_srst and reset run.
If it is any help I can send the output using the fixed
Akos Vandra wrote:
1. (in reply to freddie choppin)
As far as I understand, reset halt is not supported on my target
because srst pulls trst.
Note that this was set incorrectly for the lpc17xx chip. Double check
if the setting in openocd really actually matches your hardware. You
need to
I know what TRST is, but not SRST. Would it be the normal chip reset?
Ákos
On 20 October 2011 11:12, Peter Stuge pe...@stuge.se wrote:
Akos Vandra wrote:
1. (in reply to freddie choppin)
As far as I understand, reset halt is not supported on my target
because srst pulls trst.
Note that
Akos Vandra wrote:
I know what TRST is, but not SRST. Would it be the normal chip
reset?
Right, system reset.
//Peter
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W dniu 2011-10-19 14:14:11 użytkownik Akos Vandra axo...@gmail.com napisał:
#lpcfixchecksum takes only binary files, so
#make a binary file from the elf, and fix the checksum.
arm-eabi-objcopy -O binary $FILE tmp.bin
lpcfixchecksum tmp.bin
On LPC2xxx you can use elf, hex of bin - no need to
Hi guys!
I am trying to program an lpc1768 device using an oocdlink
(Ft2232-based) programmer.
Only every other programming works, which is very strange.
After the first programming, the uC seems to be in a lockup state.
After second programming, it always works as a charm.
I'm pretty much
On Wed, Oct 19, 2011 at 2:23 PM, freddie_chopin freddie_cho...@op.plwrote:
W dniu 2011-10-19 14:14:11 użytkownik Akos Vandra axo...@gmail.com
napisał:
#lpcfixchecksum takes only binary files, so
#make a binary file from the elf, and fix the checksum.
arm-eabi-objcopy -O binary $FILE
Andreas Fritiofson wrote:
But what is the mwb 0x400FC040 0x01 doing?
MEMMAP
Bit 0 MAP Reset value 0
0 Boot mode. A portion of the Boot ROM is mapped to address 0.
1 User mode. The on-chip Flash memory is mapped to address 0.
6. Debug memory re-mapping
-
Following chip reset, a portion of the
