Do not reset the RTL930x SerDes on link changes, instead set up
the SDS with internal PHYs for the SFP+ ports only.
This fixes the 8 1GBit ports on the Zyxel XGS1250 which
do not work without this patch.
Tested-by: Stijn Segers
Signed-off-by: Birger Koblitz
---
v2: A different patch
This fixes a bug where frames sent to the switch itself were
flooded to all ports unless the MAC address of the CPU-port
was learned otherwise.
Tested-by: Wenli Looi
Tested-by: Bjørn Mork
Signed-off-by: Birger Koblitz
---
This was previously sent as a patch with a wrong subject
"[
Thanks a lot Sander, helpful and efficient!
Cheers,
Birger
On 11.05.22 22:26, Sander Vanheule wrote:
> Hi Birger,
>
> On Sun, 2022-05-08 at 16:53 +0200, Birger Koblitz wrote:
>> Hi,
>>
>> On 08.05.22 13:11, Sander Vanheule wrote:
>>> Hi,
>>>
&
Hi,
the TLS certificate expired on the forum
Valid: Not After Thu, 12 May 2022 04:05:04 GMT
Cheers,
Birger
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Hi,
has anyone tested that??? This does not make sense at all, there is no LED
disable
in the LED_GLB_CTRL register. Instead one needs to use
RTL9310_MAC_L2_GLOBAL_CTRL2
The following works nicely on the XS1930 and Edgecore:
pinmux: pinmux@1b001358 {
compatible =
Hi,
On 07.06.22 11:10, Sander Vanheule wrote:
> On Tue, 2022-06-07 at 10:24 +0200, Birger Koblitz wrote:
>> Hi,
>>
>> at least for the RTL931x, removing the rtl931x_setup() is not a good idea as
>> the WDT reset does
>> not work for that architecture.
>&
Hi,
On 07.06.22 11:04, Sander Vanheule wrote:
> On Tue, 2022-06-07 at 10:15 +0200, Birger Koblitz wrote:
>> Hi,
>>
>> has anyone tested that???
>
> I don't have any 931x hardware, but it is based on what you put into setup.c.
What is in the setup.c makes the System L
Hi,
at least for the RTL931x, removing the rtl931x_setup() is not a good idea as
the WDT reset does not work for that architecture.
The only way to get a working reset is via registering a reset handler:
static void __init rtl931x_setup(void)
{
pr_info("Registering _machine_restart\n");
Hi,
On 19.06.22 10:56, Sander Vanheule wrote:
> - h->cpu_tag[1] = h->cpu_tag[2] = 0;
> - if (prio >= 0)
> - h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority
> Queue
> + h->cpu_tag[1] = 0;
> + /* Enable (AS_QID) and set Priority Queue (QID) */
> +
On 19/06/2022 13:46, Sander Vanheule wrote:
Priority values passed to the egress (TX) frame header initialiser are
invalid when smaller than 0, and should not be assigned to the frame.
Queue assignment is then left to the switch core logic.
Current code for RTL83xx forces the passed priority
Hi Arinc,
very well spotted! If I could make a suggestion, the RTL93xx tag generation
functions have the opposite problem, i.e. rtl930x_decode_tag() and
rtl931x_decode_tag() do not do the check for the destination port being >= 0,
i.e. defined and the packet not being a broadcast packet.
So I
Hi Arinc,
yes, this would be what I suggest.
Cheers,
Birger
On 13.06.22 13:32, Arinc UNAL (Xeront) wrote:
> Hey Birger,
>
> On 09/06/2022 14:30, Birger Koblitz wrote:
>> Hi Arinc,
>>
>> very well spotted! If I could make a suggestion, the RTL93xx tag generation
>
Hi,
dest_port -1 means flood all ports with a broadcast packet in the tx routine,
the tag functions can only be called with dest_port >= 0, however.
In the case of broadcast packets there should not be a CPU-tag with a
destination port,
or all bits in the destination port mask would need to be
Hi,
On 7/16/22 21:31, Sander Vanheule wrote:
On Sat, 2022-07-16 at 21:09 +0200, Sander Vanheule wrote:
This RFC series introduces a new MFD device for the switch core found
in the Realtek SoCs. Currently only an implementation is provided for
RTL8380, but it written with the register structure
Hi,
On 7/17/22 11:55, Paul Fertser wrote:
On Sat, Jul 16, 2022 at 11:32:52PM -0300, Luiz Angelo Daros de Luca wrote:
It uses SOC := rtl8380 while all existing dgs-1210 F1 variants use
rtl8382 (except for the pending -52 variant). The commit didn't
mention why that happened.
It's just
Hi Sander,
On 7/17/22 15:37, Sander Vanheule wrote:
On Sat, 2022-07-16 at 23:09 +0200, Birger Koblitz wrote:
Hi,
On 7/16/22 21:31, Sander Vanheule wrote:
On Sat, 2022-07-16 at 21:09 +0200, Sander Vanheule wrote:
This RFC series introduces a new MFD device for the switch core found
On 7/23/22 22:53, Jan Hoffmann wrote:
Don't use udelay to allow other kernel tasks to execute if the kernel
has been built without preemption. Also determine the timeout based on
jiffies instead of loop iterations.
Tested on a D-Link DGS-1210-16.
On 7/23/22 22:53, Jan Hoffmann wrote:
Probe the SFP module during PHY initialization and implement
insertion/removal handlers to automatically configure the media type
of the respective port.
Tested on a D-Link DGS-1210-16, which however needs updated .dts to make
use of this feature.
On 7/23/22 22:53, Jan Hoffmann wrote:
Move RTL8214FC power configuration to newly created suspend and resume
methods. A media change now only results in power configuration if the
PHY is not suspended, to avoid powering up a port when the interface is
currently not up.
While at it, remove the
Hi,
On 08.05.22 13:11, Sander Vanheule wrote:
> Hi,
>
> Sorry I didn't get back to this any sooner.
>
> On Wed, 2022-04-27 at 20:16 +0200, Birger Koblitz wrote:
>> Hi,
> It's still not clear to me what issue or issues you are fixing exactly with
> this patch,
> an
, Sander Vanheule wrote:
> Hi Birger,
>
> On Sun, 2022-04-24 at 22:01 +0200, Birger Koblitz wrote:
>> Do not reset the RTL930x SerDes on link changes, instead set up
>> the SDS with internal PHYs for the SFP+ ports only.
>> This fixes the 8 1GBit ports on the Zyxel X
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