On Wednesday, March 10, 2021 at 12:57:01 AM UTC+2 jwkoz...@gmail.com wrote:
> Thanks for the patch. Let me find some time to properly review the
> changes. It is highly valuable to have some automated tests of DAX window
> functionality.
>
> How confident are you that your changes to the
Hi,
In the last couple of days, I have been troubleshooting the scenarios when
some unit test would hang when running on QEMU in TCG mode. I have opened
an issue with extensive details and some findings
- https://github.com/cloudius-systems/osv/issues/1127. My running theory is
that we may
During early boot, we don't have a good way to map the UART page as
Device-nGnRnE memory. I'm testing this on a hypervisor that maps the UART page
as Device-GRE memory in the 2nd stage translation table. The OSv early page
tables map everything as normal memory in stage 1. As a result, there will
Parses the Cadence UART base address and IRQ.
Signed-off-by: Stewart Hildebrand
---
arch/aarch64/arch-dtb.cc | 40
arch/aarch64/arch-dtb.hh | 8
2 files changed, 48 insertions(+)
diff --git a/arch/aarch64/arch-dtb.cc b/arch/aarch64/arch-dtb.cc
Add runtime map for Cadence UART
Signed-off-by: Stewart Hildebrand
---
arch/aarch64/arch-setup.cc| 17 +
arch/aarch64/early-console.hh | 2 ++
2 files changed, 19 insertions(+)
diff --git a/arch/aarch64/arch-setup.cc b/arch/aarch64/arch-setup.cc
index e22b4ea4..fd2103b7
The irq bits need to be cleared after reading the fifo register, so the fifo
register needs to be read from interrupt context. Therefore, I introduced
the variables _input_ready and _uart_fifo to store the RX character during the
interrupt handler to be retrieved by the service thread later.
The
This work is part of an effort to port OSv to LynxSecure hypervisor. I've
tested this running on LynxSecure with the UART passed through, both on real
hardware (ZCU102) and the Xilinx qemu model of the ZCU102 with emulated Cadence
UART. I also did a test on qemu-system-aarch64 (without Cadence
