This work is part of an effort to port OSv to LynxSecure hypervisor. I've tested this running on LynxSecure with the UART passed through, both on real hardware (ZCU102) and the Xilinx qemu model of the ZCU102 with emulated Cadence UART. I also did a test on qemu-system-aarch64 (without Cadence UART) to ensure it doesn't break backward compatibility.
Stewart Hildebrand (4): Introduce Cadence UART driver Cadence: add device tree parsing function Cadence: initialize from device tree Cadence: add barrier Makefile | 1 + arch/aarch64/arch-dtb.cc | 40 +++++++++ arch/aarch64/arch-dtb.hh | 8 ++ arch/aarch64/arch-setup.cc | 17 ++++ arch/aarch64/early-console.hh | 2 + drivers/cadence-uart.cc | 148 ++++++++++++++++++++++++++++++++++ drivers/cadence-uart.hh | 45 +++++++++++ 7 files changed, 261 insertions(+) create mode 100644 drivers/cadence-uart.cc create mode 100644 drivers/cadence-uart.hh -- 2.30.2 -- You received this message because you are subscribed to the Google Groups "OSv Development" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/osv-dev/20210311171431.31417-1-stewart.hildebrand%40dornerworks.com.
