On AMD processors, we need to allocate a data structure per Northbridge
to handle certain events.
On CPU initialization, we need to query the Northbridge id and check
whether the structure is already allocated or not. We use the
amd_get_nb_id() function to r
When perf stat -p pid is used, the events must be enabled
immediately as there is no exec and thus no enable_on_exec.
Signed-off-by: Stephane Eranian
--
builtin-stat.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tools/perf/builtin-stat.c
Hi,
I was planning to use IBS (Instruction-based sampling) on an Opteron
cluster that we have in our University. And had some questions about
setting it up.
The cluster has a collection of dual core and quad core Opteron
processors. Model types are:
Dual Core AMD Opteron(tm) Processor 180
Quad-Co
Hello Ram --
Instruction-Based Sampling (BS) is supported on AMD Family 10h
processors (both Phenom(tm) and Opteron(tm)).
An AMD Opteron 180 is a so-called "K8" processor and
pre-dates AMD Family 10h. So, The AMD Opteron 180's do
not support IBS, I'm sorry to say.
The AMD Opteron 2354 is a Famil
If reserve_pmc_hardware() succeeds but reserve_ds_buffers()
fails, then we need to release_pmc_hardware. It won't be done
by the destroy() callback because we return before setting it
in case of error.
Signed-off-by: Stephane Eranian
--
perf_event.c |
Hi Paul,
That sounds promising to me. If I understand right, your reply means
that the necessary architecture support is available on 2354, although
the IBS samples may be biased and little inaccurate.
It would be great if someone can also educate me about the kernel
patch required for my configur
On Wed, 2010-03-17 at 10:40 +0200, Stephane Eranian wrote:
> On AMD processors, we need to allocate a data structure per Northbridge
> to handle certain events.
>
> On CPU initialization, we need to query the Northbridge id and check
> whether the structure is already alloc
On Thu, Mar 18, 2010 at 12:47 AM, Peter Zijlstra wrote:
> On Wed, 2010-03-17 at 10:40 +0200, Stephane Eranian wrote:
>> On AMD processors, we need to allocate a data structure per Northbridge
>> to handle certain events.
>>
>> On CPU initialization, we need to query the Northbrid
Hi Paul,
So Barcelona doesn't support dispatched op mode. From which version of
processors, it supports this mode?
Thanks,
Xu
- Original Message -
From: "Drongowski, Paul"
To: "Ramachandra CN" ;
Sent: Wednesday, March 17, 2010 4:11 PM
Subject: Re: [perfmon2] IBS on Opteron
> Hello
> >
> > Do you mean that even though I exclude kernel level events (
> exclude_kernel
> > = 1) the interrupt handler portion of the events are counted? Could you
> > briefly explain what kind of interruptions destroy determinism?
>
> There are several things you could do to try and narrow down a c
Thank you very much. It is really nice piece of work and very helpful.
BTW, I have a question on this work. Did you include OS instructions (kernel
mode) in your measurement?
In section 3, you mention that you enabled counting the OS. Does that mean
kernel mode counting?
Heechul
On Fri, Mar 12,
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