[perfmon2] Question about IBS op with dispatch mode

2011-03-16 Thread Besar Wicaksono
Hello, I am experimenting with IBS on AMD Shanghai processor. Currently my code is based on the IBS example in libpfm3.9. I only capture the load operation, and play with the sampling period. When using small sampling period, the number of captured data is larger, but the distribution is not ver

[perfmon2] Question about event "BRANCH_INSTRUCTIONS_RETIRED" on x86 machine

2011-03-16 Thread 陳韋任
Hi, all I do not sure some events description and their result. Take event "BRANCH_INSTRUCTIONS_RETIRED" for example. `showevtinfo` says this event counts the retirement of the last micro-op of a branch instruction. When I sample an application with event "BRANCH_INSTRUCTIONS_RETIRED", I will

Re: [perfmon2] Question about event "BRANCH_INSTRUCTIONS_RETIRED" on x86 machine

2011-03-16 Thread stephane eranian
Hi, What you're observing is a known side effect of interrupt-based sampling. There is skid. Let me explain. What the kernel captures is the address of the instruction at the time of the PMU interrupt. That instruction may be far away from the instruction that cause the counter to overflow, i.e.,

Re: [perfmon2] I can't run pfmon

2011-03-16 Thread Easley
Is there any more informations about 'perf' ? I learn perfmon2, because of I want to get the event of cpu by myself. I have developed a tool which need this event, so I must to write these codes by myself. Sometimes you mustn't update the kernel due to the system used to production line. The

Re: [perfmon2] I can't run pfmon

2011-03-16 Thread Corey Ashford
On 03/16/2011 07:35 AM, Easley wrote: > Is there any more informations about 'perf' ? I learn perfmon2, because of I > want to get the event of cpu by myself. > I have developed a tool which need this event, so I must to write these codes > by myself. > Sometimes you mustn't update the kernel du

Re: [perfmon2] Question about event "BRANCH_INSTRUCTIONS_RETIRED" on x86 machine

2011-03-16 Thread 陳韋任
Hi, Stephane > The PMU takes some variable amount of time to interrupt after an overflow. > During that time, execution continues. So the skid has nothing to do with "micro-op"? > This "imprecision" cannot be corrected by software but only thru hardware. > That's why you have Intel PEBS, for

Re: [perfmon2] Question about event "BRANCH_INSTRUCTIONS_RETIRED" on x86 machine

2011-03-16 Thread 陳韋任
Hi, > In summary, except for cycles you should do not expect profiles to point at > instructions that generated the occurrences of the sampling event. Even "instructions" event has the skid? Regards, chenwj -- Wei-Ren Chen (陳韋任) Parallel Processing Lab, Institute of Information Science, Acad

Re: [perfmon2] Question about event "BRANCH_INSTRUCTIONS_RETIRED" on x86 machine

2011-03-16 Thread Arun Sharma
On Wed, Mar 16, 2011 at 7:07 PM, 陳韋任 wrote: >  You mean PEBS makes the skid disappered? Does `perf` or libpfm4 support this? > The example I showed was ran on a x86 machine, it seems `perf` does not use > PEBS > feature. > It depends on the suffix. Try perf record -e branch-misses:p PEBS is kn

[perfmon2] How does take use of EventName and UnitMask?

2011-03-16 Thread Easley
EventName(2CH) UnitMask(07H) UNC_QMC_NORMAL_READS.ANY Counts the number of Quickpath Memory Controller medium and low priority read requests. The QMC normal read occupancy divided by this count provides the average QMC read latency. - EventName(2FH) UnitMask(07H) UNC_Q

Re: [perfmon2] How does take use of EventName and UnitMask?

2011-03-16 Thread 陳韋任
Hi, > How does I take use of EventName and UnitMask to get UNC_QMC_NORMAL_READS.ANY > or UNC_QMC_WRITES.FULL.ANY evnets? And Which are these 2 events control bits? I guess you are using pfmon, try "-e UNC_QMC_NORMAL_READS:ANY". Regards, chenwj -- Wei-Ren Chen (陳韋任) Parallel Processing Lab,