Hi,
Ok, I found a bug in the Makefile which caused the SPARC detection
to fail. Please pull the source code again and retry.
Thanks.
On Sat, Mar 19, 2011 at 4:08 AM, 陳韋任 wrote:
> Hi,
>
> The attachment is the SPARC's /proc/cpuinfo.
>
> Regards,
> chenwj
>
> --
> Wei-Ren Chen (陳韋任)
> Parallel
Arun,
I have pushed a patch that enables uncore support in libpfm4.
This is based on Lin's patch. It takes care of the priv level issue.
On Thu, Mar 17, 2011 at 10:03 PM, Arun Sharma wrote:
> On Thu, Mar 17, 2011 at 8:43 AM, Arun Sharma wrote:
>>
>> Stephane has disabled the uncore event suppo
The following patch solves the problems introduced by Robert's
commit 41bf498 and reported by Arun Sharma. This commit gets rid
of the base + index notation for reading and writing PMU msrs.
The problem is that for fixed counters, the new calculation for the
base did not take into account the fix
Hi,
Development of libpfm3 and perfmon has been stopped two years ago.
You are encouraged to use perf and perf_events from now on.
On Fri, Mar 11, 2011 at 2:51 AM, 陳韋任 wrote:
> Hi,
>
>> Sorry for the last reply, I accidentally hit the send button. I think it
>> needs to be 1 to 1. When we use
Besar,
On Wed, Mar 16, 2011 at 8:56 AM, Besar Wicaksono wrote:
> Hello,
> I am experimenting with IBS on AMD Shanghai processor.
> Currently my code is based on the IBS example in libpfm3.9. I only capture
> the load operation, and play with the sampling period.
> When using small sampling period
Hi,
On Fri, Mar 18, 2011 at 8:55 AM, 陳韋任 wrote:
> Hi, all
>
> I am interested in the LBR (Last Branch Record), and
> I saw perfmon supports LBR for Intel Core i7.
>
Yes, it does on select processors.
> http://perfmon2.sourceforge.net/pfmon_intel_corei7.html
>
> How the LBR is used in perfmon?
Hi,
`showevtinfo` now is able to detect niagara2. Thanks.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Parallel Processing Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
--
