Why would a software machine closely emulating CISC architecture
be expected to execute as efficiently on RISC and CISC machines?
Does it make any sense to create a low-level machine modeled on
one-architecture instead of a high-level architecture which can
flexibly optimize to either
On Mon, Dec 03, 2001 at 08:31:00AM -0800, Terrence Brannon wrote:
Also, I thought Parrot was not stack-based If that is the case
then why does Overview.pod say this:
Registers will be stored in register frames, which can be pushed and
popped onto the register stack. For instance, a
Terrence Brannon:
# Why would a software machine closely emulating CISC architecture
# be expected to execute as efficiently on RISC and CISC machines?
We're not necessarily expecting it to run as efficiently. We're just
expecting it to run efficiently enough.
# Does it make any sense to
At 08:31 AM 12/3/2001 -0800, Terrence Brannon wrote:
Why would a software machine closely emulating CISC architecture be
expected to execute as efficiently on RISC and CISC machines?
Because it means that the machine doesn't do that much work itself, passing
most of the work off to the opcode
