Does anyone know if it is possible (or how to) set a design rule to
check between the overlay and the soldermask layers? If you place a
designator over a pad or via then it does not appear correctly on the
finished PCB. I have simplified the solution to check the reference
designators versus the [inverted] soldermask of the same side and make
sure they don't overlap. I was hoping to automate the process with a
design rule. Any ideas?
Anthony Whitesell
Out of luck I think - there is no possibility using the current set of
design rules (from memory). I was asked about this some time ago and
spent a little time looking at it but I can't even remember where we got
to. I know I am still doing it with a visual check so I guess I did not
work out a better way.
I would certainly like a better solution. A server could be written to
do the check but there is absolutely no incentive in writing such
servers unless you have lots of free time or your company will pay you
to do it.
There may be some combination layer colours and Transparent layer
colouring that would show up violations clearly but this does not do
much for mis-registration (there is no clearance parameter).
I know that some of the CAM packages can do an overlay/silkscreen cut to
prevent text on pads but I do not know if Camtastic has such a checking
function.
A design rule would be nice.
Ian Wilson
I do not know if any of the higher priced packages accomplish this check.
I do know that even Allegro's Autosilk function does not correctly or
always prevent text on pads. Valor does check for these violations,
though it may not be an economical solution.
Cheers!
Drew (Andrew W. Riley III)
In a past job, I used the AD2.0 version of PCAD (a DOS version of that
application), and that provided a configurable DRC capability (albiet not in
Protel's on-line form). Although I never tried it at the time, it is not
totally out of the question that its DRC feature might have been
configurable to have checked for overlaps between items on silkscreen layers
and items on soldermask layers (on the same side of the PCB). (Simon Peacock
(or anyone else), can you comment on this?)
Like Ian Wilson, I have also contemplated the possibility of creating an
addon server incorporating a process which could check for such overlaps.
Although I have yet to have written any associated code, it is my belief
that, for the most part, such a process could be created, but my gut feeling
is that text objects (strings) probably would be problematic to some extent.
(I have designed various PCBs in which the bounding rectangle of a string
encompasses the area occupied by a via, but the actual text itself still
misses the area occupied by the via.)
I have already released some other processes within addon servers on a
freeware basis, but to create this process would impose demands upon my
time which would prevent me from releasing it any time soon.
Other postings to this forum suggest that Phoenix (the name currently
assigned to the next version of Protel) is currently undergoing beta
testing. I am not a beta tester for this myself, but it is not totally out
the question that Phoenix could incorporate this feature; although it has
been a while since the issue was last raised on this forum, various
correspondents have still previously commented on this feature and requested
it from time to time. So wait and see what is provided in any public
prerelease and/or trial versions of this...
My way of checking for overlaps is by visual inspection, both from the
Protel PCB file itself, and from the Gerber files produced from that (while
using a Gerber file viewer, such as Graphicode's GC-Prevue freeware
application). In the absense of any automated checking feature, that is
about the only way to do it, but I certainly concur on the merits of having
automated checking provided for this.
Regards,
Geoff Harland.
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