[PEDA] P99SE Annotate component sorting order.
Hi all, this is an issue that I am sure has been around a while. On this design I am working it has just become too much for me to accept, is there something I am missing or a work around? Trying to annotate a two page schematic it keeps pre-sorting and ordering it's annotate based on the part type information. It is not simply using the part type information for matching purposes, it is doing matched part type designator assignments first. For example, here is what I am seeing. I have a bunch of resistors on page two of the schematic. They are being numbered R38, R39, R40, R42, etc. sorted according to the specified annotate pattern. Then the next resistor may be R15. A short number of resistors follow the original number pattern R43, R44, R45. Then I get another one R16! The part type data of the R16 is the same as R15 and is different than all the other mentioned resistors. On the same page I noted some resistors of the same value/part type information that were numbered R17 R18 even though the other resistors around them are numbered in the 50s. What P99SE is doing is annotating according to the specified pattern only when it finds a part type that was not previously matched by the part type. Parts with matching part types get annotated in the order that the first component of that value was found on the first page of the schematic, then it purposely searches out parts with the same part type to annotate next in sequence even across other schematic pages. On my configuration for annotating I do have the Group parts together if matched by: set to part type. However this is only for grouping multipart symbols, is it not? Matching multiple parts from a single package? Or am I carrying old baggage from OrCAD or other packages, the Help file agrees with me though? Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Protel99SE and Specctra v7.1
Hello All, Has anyone used Protel99SE with Specctra v7.1? Are there any issues, major problems with this combination? Thanks, Loc Tran * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P99SE Annotate component sorting order.
Brad, The following may meander a little from the basic problem you are describing, but I think it is nonetheless directly relevant, and actually address the problem in an indirect way. It sounds like Protel suffers from the same problem that many, if not most, of these EDA software systems do, in that, the manner in which the internal databases store information is in most cases what I call Entry Order Driven, that is, that the first part entered in the design stays at the top of the database list (and any subsequent parts of the same type may (or may not) get put up there with it), and that all connections are put in their own little database list in the order in which they were entered, etc., etc., etc., and that all of these entries in all of the different internal databases never loose their original position in the internal database list, or are moved from their original Entry Order, unless possibly it is to sort them by some other parameter that is totally unrelated to the actual electrical design, such as the part number of the devices, or the footprint type of the devices, or the physical length of the actual connection line on the physical schematic, etc., etc., etc., which is again, totally unrelated to the electrical function of the schematic. This is why most Auto Placement schemes do not work, since they too are Entry Order Driven, and internally work off of the same Entry Order internal database lists, which cause them to do stupid things like place all of the pull up resistors of the same value first because the first part that the engineer put in the original schematic was a pull up resistor of that vakue, which he subsequently copied all over the schematic, an hence caused to be at the top of the Entry Order List. This same problem appears in net numbering, in that many times the nets are numbered and processed and laid out in the same Entry Order that they were originally entered into the internal database, which is why Priorities get all screwed up in Routing the Board, because the basic Entry Order will never change. Of course you can cause several subsequent Sorts of these internal databases, when you do things like assign certain parts or nets to certain Classes, or certain areas or sheets of a schematic to certain Rooms, or assign a certain Width to a certain net, of place certain parts on a specific side of the Board, all of which break down the original Entry Order internal database lists to even more Entry Order database lists, but which nonetheless still somehow never seem to loose their Entry Order. Of course the Protel software further alters these Entry Order Lists into yet again different Entry Order Lists, and yet in some senses, certain things within these internal databases will never loose their Entry Order. Years ago I found out that Dasix (which was originally Cadnetix, and then became InterGraph, and then became VeryBest, and is now Mentor Expidition) Compiled (Linked) its Hierarchical Schematic Pages or Sheets based on the physical order in which it encountered the actual subdirectory of each Sheet on the physical disk drive, and that if you edited a Sheet for any reason, such as changing a netname, that it created a new copy of the Sheet, which really meant creating a new subdirectory on the physical hard drive, usually at the end of the available disk space, and only when you finished editing the new Sheet did you actually end up deleting the old copy (or previous backup) of the old Sheet, thereby deleting its corresponding subdirectory, and freeing up a physical slot on the hard drive (and its directory) so that you could further sort and scramble the physical location of the next Sheet that you edited. Today, virtually everything that you look at in terms of a listing of files on your computer, is Sorted, either alphabetically or by some other parameter such as file type or something else, before it is listed on your display and actually presented to you (even the LS command in Unix or Linex sorts the directory before it is displayed). The one possible exception to this is a directory listing (the dir command) in MSDOS (or the Command Prompt on some newer versions of Windows), which will present files in an unsorted manner in which they are physically located (listed) in the actual directory (or subdirectory) on the actual hard disk. If you look at this type of list you will begin to understand the scope of this problem Thus in Dasix, every time that you edited a schematic Sheet in your design, and then re-Compiled (re-Linked) your entire design, you got a completely different netlist, because it physically encountered each Sheet's subdirectory in a new and different location or physical Entry Order on the hard disk as it was Compiling (Linking). This may sound dumb, and even stupid, and in fact it really is, but that is the way that these simple and stupid software systems work at the bottom level of their software designs. Back in about 1988 or 89 I
Re: [PEDA] Components tombstoning After reflow.
Title: RE: [PEDA] Components tombstoning After reflow. Subject: RE: [PEDA] Components tombstoning After reflow. Dear Brad, Lan others, Thank you very much for yours kindly respond and instructions. Since the assembly house is in another city, I could not get the exact information about this issue, Please allow me to forward your instructions to them to try and analyze. Meanwhile, they also mentioned the soldmask open on the pads which connect to copper plane, I set the slodmask override to 3mil on normal pads, So, according to my polygon connect style, The actual pad size on the copper plane will be large than the design size (3mil each side), Thus, a component with two different size pads, maybe this will cause tombstoning after reflow, So I reduce the soldmask open size as same as the pad size (override size = 0, just those pads connect to copper plane). I wonder if this is helpful. Currently, the component size is 0402, yes, we used to use 0603 or large parts and no tombstoning occur. We found this issue most recently, but we had changed the component size for a span seldom found tomdstoning. I also notice two RF module samples, one with components on both side, one with single side components, The bottom layout of the one with both side components is same as the the one with single side component, After reflow, the single-side-component module no tombstoning , The double-side-components module with many tombstoning on the bottom side (The top side contains 4 BGA ICs, it is to say the bottom side components go through the reflow twice. ) , I will try to change my habit in next design, but I wonder if the polygon connect style is really critical, and does anyone else have got experiences on this? Thanks again! Best regards, Luo. -Original Message- From: Brad Velander [mailto:[EMAIL PROTECTED]] Sent: Tuesday, March 04, 2003 1:22 AM To: Protel EDA Forum Subject: Re: [PEDA] Components stand After reflow. Luo, the problem you are experiencing is called tombstoning in English. Tombstoning typically occurs because of incorrect component pad geometries, solder volumes or reflow heat profiles. It can be effected by your polygon connections but as you state it is not the only reason as not all polygon connects do it and some components that are not connected to polygons also do it. The cause of tombstoning is varied but typically it occurs because the viscosity of the molten solderpaste at one end of the component is greater than the viscosity of the molten solder paste at the other end of the component or it has melted prior to the other end melting. Sometimes this is because one end of the component reaches the solder melt point faster than the other end (which end hits the heat first?), usually the end that is attached to the solderpad reached melting temperature prior to the other end (the one stuck up in the air). You will need to work with the assembly facility to determine the cause of this tombstoning, there are many possible reasons and they are not all board design related. One simple test, try putting the boards through the reflow oven in a different orientation, 90 degrees clockwise or 90 degrees counter-clockwise. There is a preferred orientation for most boards, at least if they are properly laid out in the first place, not just willy-nilly on component orientation. The bias should see the heat profile sweeping across both ends of chip components, down both sides of SOIC components simultaneously rather than one end and then the other (one side and then the other for SOIC parts). My money would be on the assembly line running a quick temperature ramp-up, or they are just not adequately preheating before the components hit the main reflow temperature phase. This is probably resulting in the leading edge solder melting prior to the trailing edge solder on small chip components. What size are your components, 0402 (or even 0201)? Lots of people running 0603 or larger parts, then changing to 0402 or 0201 have problems with tombstoning where they had no prior problems with the larger parts. Do you have much history running these components through this assembly line? Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Sunday, March 02, 2003 6:36 PM To: Protel EDA Forum Subject: [PEDA] Components stand After reflow. Dear All, I always set the polygon connect to pads directly, and it always work fine. But now, we found there are components stand after reflow, some contain pads connect to polygon, some not. I wonder if this is caused by the polygon connet style or any other reason. So my question is: 1, what are the key points to cause components stand after reflow? 2, When will components-stand always occur during reflow
